arch/x86/include/asm/irq_vectors.h

   1 #ifndef _ASM_X86_IRQ_VECTORS_H
   2 #define _ASM_X86_IRQ_VECTORS_H
   3
   4 /*
   5  * Linux IRQ vector layout.
   6  *
   7  * There are 256 IDT entries (per CPU - each entry is 8 bytes) which can
   8  * be defined by Linux. They are used as a jump table by the CPU when a
   9  * given vector is triggered - by a CPU-external, CPU-internal or
  10  * software-triggered event.
  11  *
  12  * Linux sets the kernel code address each entry jumps to early during
  13  * bootup, and never changes them. This is the general layout of the
  14  * IDT entries:
  15  *
  16  *  Vectors   0 ...  31 : system traps and exceptions - hardcoded events
  17  *  Vectors  32 ... 127 : device interrupts
  18  *  Vector  128         : legacy int80 syscall interface
  19  *  Vectors 129 ... 237 : device interrupts
  20  *  Vectors 238 ... 255 : special interrupts
  21  *
  22  * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table.
  23  *
  24  * This file enumerates the exact layout of them:
  25  */
  26
  27 #define NMI_VECTOR                      0x02
  28
  29 /*
  30  * IDT vectors usable for external interrupt sources start
  31  * at 0x20:
  32  */
  33 #define FIRST_EXTERNAL_VECTOR           0x20
  34
  35 #ifdef CONFIG_X86_32
  36 # define SYSCALL_VECTOR                 0x80
  37 # define IA32_SYSCALL_VECTOR            0x80
  38 #else
  39 # define IA32_SYSCALL_VECTOR            0x80
  40 #endif
  41
  42 /*
  43  * Reserve the lowest usable priority level 0x20 - 0x2f for triggering
  44  * cleanup after irq migration.
  45  */
  46 #define IRQ_MOVE_CLEANUP_VECTOR         FIRST_EXTERNAL_VECTOR
  47
  48 /*
  49  * Vectors 0x30-0x3f are used for ISA interrupts.
  50  */
  51 #define IRQ0_VECTOR                     (FIRST_EXTERNAL_VECTOR + 0x10)
  52
  53 #define IRQ1_VECTOR                     (IRQ0_VECTOR +  1)
  54 #define IRQ2_VECTOR                     (IRQ0_VECTOR +  2)
  55 #define IRQ3_VECTOR                     (IRQ0_VECTOR +  3)
  56 #define IRQ4_VECTOR                     (IRQ0_VECTOR +  4)
  57 #define IRQ5_VECTOR                     (IRQ0_VECTOR +  5)
  58 #define IRQ6_VECTOR                     (IRQ0_VECTOR +  6)
  59 #define IRQ7_VECTOR                     (IRQ0_VECTOR +  7)
  60 #define IRQ8_VECTOR                     (IRQ0_VECTOR +  8)
  61 #define IRQ9_VECTOR                     (IRQ0_VECTOR +  9)
  62 #define IRQ10_VECTOR                    (IRQ0_VECTOR + 10)
  63 #define IRQ11_VECTOR                    (IRQ0_VECTOR + 11)
  64 #define IRQ12_VECTOR                    (IRQ0_VECTOR + 12)
  65 #define IRQ13_VECTOR                    (IRQ0_VECTOR + 13)
  66 #define IRQ14_VECTOR                    (IRQ0_VECTOR + 14)
  67 #define IRQ15_VECTOR                    (IRQ0_VECTOR + 15)
  68
  69 /*
  70  * Special IRQ vectors used by the SMP architecture, 0xf0-0xff
  71  *
  72  *  some of the following vectors are 'rare', they are merged
  73  *  into a single vector (CALL_FUNCTION_VECTOR) to save vector space.
  74  *  TLB, reschedule and local APIC vectors are performance-critical.
  75  */
  76
  77 #define SPURIOUS_APIC_VECTOR            0xff
  78 /*
  79  * Sanity check
  80  */
  81 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
  82 # error SPURIOUS_APIC_VECTOR definition error
  83 #endif
  84
  85 #define ERROR_APIC_VECTOR               0xfe
  86 #define RESCHEDULE_VECTOR               0xfd
  87 #define CALL_FUNCTION_VECTOR            0xfc
  88 #define CALL_FUNCTION_SINGLE_VECTOR     0xfb
  89 #define THERMAL_APIC_VECTOR             0xfa
  90 #define THRESHOLD_APIC_VECTOR           0xf9
  91 #define REBOOT_VECTOR                   0xf8
  92
  93 /* f0-f7 used for spreading out TLB flushes: */
  94 #define INVALIDATE_TLB_VECTOR_END       0xf7
  95 #define INVALIDATE_TLB_VECTOR_START     0xf0
  96 #define NUM_INVALIDATE_TLB_VECTORS         8
  97
  98 /*
  99  * Local APIC timer IRQ vector is on a different priority level,
 100  * to work around the 'lost local interrupt if more than 2 IRQ
 101  * sources per level' errata.
 102  */
 103 #define LOCAL_TIMER_VECTOR              0xef
 104
 105 /*
 106  * Performance monitoring interrupt vector:
 107  */
 108 #define LOCAL_PERF_VECTOR               0xee
 109
 110 /*
 111  * Generic system vector for platform specific use
 112  */
 113 #define GENERIC_INTERRUPT_VECTOR        0xed
 114
 115 #define UV_BAU_MESSAGE                  0xec
 116
 117 /*
 118  * Self IPI vector for machine checks
 119  */
 120 #define MCE_SELF_VECTOR                 0xeb
 121
 122 /*
 123  * First APIC vector available to drivers: (vectors 0x30-0xee) we
 124  * start at 0x31(0x41) to spread out vectors evenly between priority
 125  * levels. (0x80 is the syscall vector)
 126  */
 127 #define FIRST_DEVICE_VECTOR             (IRQ15_VECTOR + 2)
 128
 129 #define NR_VECTORS                       256
 130
 131 #define FPU_IRQ                           13
 132
 133 #define FIRST_VM86_IRQ                     3
 134 #define LAST_VM86_IRQ                     15
 135
 136 #ifndef __ASSEMBLY__
 137 static inline int invalid_vm86_irq(int irq)
 138 {
 139         return irq < FIRST_VM86_IRQ || irq > LAST_VM86_IRQ;
 140 }
 141 #endif
 142
 143 /*
 144  * Size the maximum number of interrupts.
 145  *
 146  * If the irq_desc[] array has a sparse layout, we can size things
 147  * generously - it scales up linearly with the maximum number of CPUs,
 148  * and the maximum number of IO-APICs, whichever is higher.
 149  *
 150  * In other cases we size more conservatively, to not create too large
 151  * static arrays.
 152  */
 153
 154 #define NR_IRQS_LEGACY                    16
 155
 156 #define CPU_VECTOR_LIMIT                (  8 * NR_CPUS      )
 157 #define IO_APIC_VECTOR_LIMIT            ( 32 * MAX_IO_APICS )
 158
 159 #ifdef CONFIG_X86_IO_APIC
 160 # ifdef CONFIG_SPARSE_IRQ
 161 #  define NR_IRQS                                       \
 162         (CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ?      \
 163                 (NR_VECTORS + CPU_VECTOR_LIMIT)  :      \
 164                 (NR_VECTORS + IO_APIC_VECTOR_LIMIT))
 165 # else
 166 #  if NR_CPUS < MAX_IO_APICS
 167 #   define NR_IRQS                      (NR_VECTORS + 4*CPU_VECTOR_LIMIT)
 168 #  else
 169 #   define NR_IRQS                      (NR_VECTORS + IO_APIC_VECTOR_LIMIT)
 170 #  endif
 171 # endif
 172 #else /* !CONFIG_X86_IO_APIC: */
 173 # define NR_IRQS                        NR_IRQS_LEGACY
 174 #endif
 175
 176 #endif /* _ASM_X86_IRQ_VECTORS_H */