2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,2005,2006,2007,2008 NVIDIA Corporation
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 * We suspect that on some hardware no TX done interrupts are generated.
34 * This means recovery from netif_stop_queue only happens if the hw timer
35 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37 * If your hardware reliably generates tx done interrupts, then you can remove
38 * DEV_NEED_TIMERIRQ from the driver_data flags.
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic.
42 #define FORCEDETH_VERSION "0.61"
43 #define DRV_NAME "forcedeth"
45 #include <linux/module.h>
46 #include <linux/types.h>
47 #include <linux/pci.h>
48 #include <linux/interrupt.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/delay.h>
52 #include <linux/spinlock.h>
53 #include <linux/ethtool.h>
54 #include <linux/timer.h>
55 #include <linux/skbuff.h>
56 #include <linux/mii.h>
57 #include <linux/random.h>
58 #include <linux/init.h>
59 #include <linux/if_vlan.h>
60 #include <linux/dma-mapping.h>
64 #include <asm/uaccess.h>
65 #include <asm/system.h>
68 #define dprintk printk
70 #define dprintk(x...) do { } while (0)
73 #define TX_WORK_PER_LOOP 64
74 #define RX_WORK_PER_LOOP 64
80 #define DEV_NEED_TIMERIRQ 0x00001 /* set the timer irq flag in the irq mask */
81 #define DEV_NEED_LINKTIMER 0x00002 /* poll link settings. Relies on the timer irq */
82 #define DEV_HAS_LARGEDESC 0x00004 /* device supports jumbo frames and needs packet format 2 */
83 #define DEV_HAS_HIGH_DMA 0x00008 /* device supports 64bit dma */
84 #define DEV_HAS_CHECKSUM 0x00010 /* device supports tx and rx checksum offloads */
85 #define DEV_HAS_VLAN 0x00020 /* device supports vlan tagging and striping */
86 #define DEV_HAS_MSI 0x00040 /* device supports MSI */
87 #define DEV_HAS_MSI_X 0x00080 /* device supports MSI-X */
88 #define DEV_HAS_POWER_CNTRL 0x00100 /* device supports power savings */
89 #define DEV_HAS_STATISTICS_V1 0x00200 /* device supports hw statistics version 1 */
90 #define DEV_HAS_STATISTICS_V2 0x00400 /* device supports hw statistics version 2 */
91 #define DEV_HAS_TEST_EXTENDED 0x00800 /* device supports extended diagnostic test */
92 #define DEV_HAS_MGMT_UNIT 0x01000 /* device supports management unit */
93 #define DEV_HAS_CORRECT_MACADDR 0x02000 /* device supports correct mac address order */
94 #define DEV_HAS_COLLISION_FIX 0x04000 /* device supports tx collision fix */
95 #define DEV_HAS_PAUSEFRAME_TX_V1 0x08000 /* device supports tx pause frames version 1 */
96 #define DEV_HAS_PAUSEFRAME_TX_V2 0x10000 /* device supports tx pause frames version 2 */
97 #define DEV_HAS_PAUSEFRAME_TX_V3 0x20000 /* device supports tx pause frames version 3 */
98 #define DEV_NEED_TX_LIMIT 0x40000 /* device needs to limit tx */
99 #define DEV_HAS_GEAR_MODE 0x80000 /* device supports gear mode */
102 NvRegIrqStatus
= 0x000,
103 #define NVREG_IRQSTAT_MIIEVENT 0x040
104 #define NVREG_IRQSTAT_MASK 0x81ff
105 NvRegIrqMask
= 0x004,
106 #define NVREG_IRQ_RX_ERROR 0x0001
107 #define NVREG_IRQ_RX 0x0002
108 #define NVREG_IRQ_RX_NOBUF 0x0004
109 #define NVREG_IRQ_TX_ERR 0x0008
110 #define NVREG_IRQ_TX_OK 0x0010
111 #define NVREG_IRQ_TIMER 0x0020
112 #define NVREG_IRQ_LINK 0x0040
113 #define NVREG_IRQ_RX_FORCED 0x0080
114 #define NVREG_IRQ_TX_FORCED 0x0100
115 #define NVREG_IRQ_RECOVER_ERROR 0x8000
116 #define NVREG_IRQMASK_THROUGHPUT 0x00df
117 #define NVREG_IRQMASK_CPU 0x0060
118 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
119 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
120 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
122 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
123 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
124 NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
126 NvRegUnknownSetupReg6
= 0x008,
127 #define NVREG_UNKSETUP6_VAL 3
130 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
131 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
133 NvRegPollingInterval
= 0x00c,
134 #define NVREG_POLL_DEFAULT_THROUGHPUT 970 /* backup tx cleanup if loop max reached */
135 #define NVREG_POLL_DEFAULT_CPU 13
136 NvRegMSIMap0
= 0x020,
137 NvRegMSIMap1
= 0x024,
138 NvRegMSIIrqMask
= 0x030,
139 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
141 #define NVREG_MISC1_PAUSE_TX 0x01
142 #define NVREG_MISC1_HD 0x02
143 #define NVREG_MISC1_FORCE 0x3b0f3c
145 NvRegMacReset
= 0x34,
146 #define NVREG_MAC_RESET_ASSERT 0x0F3
147 NvRegTransmitterControl
= 0x084,
148 #define NVREG_XMITCTL_START 0x01
149 #define NVREG_XMITCTL_MGMT_ST 0x40000000
150 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
151 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
152 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
153 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
154 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
155 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
156 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
157 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
158 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
159 NvRegTransmitterStatus
= 0x088,
160 #define NVREG_XMITSTAT_BUSY 0x01
162 NvRegPacketFilterFlags
= 0x8c,
163 #define NVREG_PFF_PAUSE_RX 0x08
164 #define NVREG_PFF_ALWAYS 0x7F0000
165 #define NVREG_PFF_PROMISC 0x80
166 #define NVREG_PFF_MYADDR 0x20
167 #define NVREG_PFF_LOOPBACK 0x10
169 NvRegOffloadConfig
= 0x90,
170 #define NVREG_OFFLOAD_HOMEPHY 0x601
171 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
172 NvRegReceiverControl
= 0x094,
173 #define NVREG_RCVCTL_START 0x01
174 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
175 NvRegReceiverStatus
= 0x98,
176 #define NVREG_RCVSTAT_BUSY 0x01
178 NvRegSlotTime
= 0x9c,
179 #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
180 #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
181 #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
182 #define NVREG_SLOTTIME_HALF 0x0000ff00
183 #define NVREG_SLOTTIME_DEFAULT 0x00007f00
184 #define NVREG_SLOTTIME_MASK 0x000000ff
186 NvRegTxDeferral
= 0xA0,
187 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
188 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
189 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
190 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
191 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
192 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
193 NvRegRxDeferral
= 0xA4,
194 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
195 NvRegMacAddrA
= 0xA8,
196 NvRegMacAddrB
= 0xAC,
197 NvRegMulticastAddrA
= 0xB0,
198 #define NVREG_MCASTADDRA_FORCE 0x01
199 NvRegMulticastAddrB
= 0xB4,
200 NvRegMulticastMaskA
= 0xB8,
201 #define NVREG_MCASTMASKA_NONE 0xffffffff
202 NvRegMulticastMaskB
= 0xBC,
203 #define NVREG_MCASTMASKB_NONE 0xffff
205 NvRegPhyInterface
= 0xC0,
206 #define PHY_RGMII 0x10000000
207 NvRegBackOffControl
= 0xC4,
208 #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
209 #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
210 #define NVREG_BKOFFCTRL_SELECT 24
211 #define NVREG_BKOFFCTRL_GEAR 12
213 NvRegTxRingPhysAddr
= 0x100,
214 NvRegRxRingPhysAddr
= 0x104,
215 NvRegRingSizes
= 0x108,
216 #define NVREG_RINGSZ_TXSHIFT 0
217 #define NVREG_RINGSZ_RXSHIFT 16
218 NvRegTransmitPoll
= 0x10c,
219 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
220 NvRegLinkSpeed
= 0x110,
221 #define NVREG_LINKSPEED_FORCE 0x10000
222 #define NVREG_LINKSPEED_10 1000
223 #define NVREG_LINKSPEED_100 100
224 #define NVREG_LINKSPEED_1000 50
225 #define NVREG_LINKSPEED_MASK (0xFFF)
226 NvRegUnknownSetupReg5
= 0x130,
227 #define NVREG_UNKSETUP5_BIT31 (1<<31)
228 NvRegTxWatermark
= 0x13c,
229 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
230 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
231 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
232 NvRegTxRxControl
= 0x144,
233 #define NVREG_TXRXCTL_KICK 0x0001
234 #define NVREG_TXRXCTL_BIT1 0x0002
235 #define NVREG_TXRXCTL_BIT2 0x0004
236 #define NVREG_TXRXCTL_IDLE 0x0008
237 #define NVREG_TXRXCTL_RESET 0x0010
238 #define NVREG_TXRXCTL_RXCHECK 0x0400
239 #define NVREG_TXRXCTL_DESC_1 0
240 #define NVREG_TXRXCTL_DESC_2 0x002100
241 #define NVREG_TXRXCTL_DESC_3 0xc02200
242 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
243 #define NVREG_TXRXCTL_VLANINS 0x00080
244 NvRegTxRingPhysAddrHigh
= 0x148,
245 NvRegRxRingPhysAddrHigh
= 0x14C,
246 NvRegTxPauseFrame
= 0x170,
247 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
248 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
249 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
250 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
251 NvRegMIIStatus
= 0x180,
252 #define NVREG_MIISTAT_ERROR 0x0001
253 #define NVREG_MIISTAT_LINKCHANGE 0x0008
254 #define NVREG_MIISTAT_MASK_RW 0x0007
255 #define NVREG_MIISTAT_MASK_ALL 0x000f
256 NvRegMIIMask
= 0x184,
257 #define NVREG_MII_LINKCHANGE 0x0008
259 NvRegAdapterControl
= 0x188,
260 #define NVREG_ADAPTCTL_START 0x02
261 #define NVREG_ADAPTCTL_LINKUP 0x04
262 #define NVREG_ADAPTCTL_PHYVALID 0x40000
263 #define NVREG_ADAPTCTL_RUNNING 0x100000
264 #define NVREG_ADAPTCTL_PHYSHIFT 24
265 NvRegMIISpeed
= 0x18c,
266 #define NVREG_MIISPEED_BIT8 (1<<8)
267 #define NVREG_MIIDELAY 5
268 NvRegMIIControl
= 0x190,
269 #define NVREG_MIICTL_INUSE 0x08000
270 #define NVREG_MIICTL_WRITE 0x00400
271 #define NVREG_MIICTL_ADDRSHIFT 5
272 NvRegMIIData
= 0x194,
273 NvRegWakeUpFlags
= 0x200,
274 #define NVREG_WAKEUPFLAGS_VAL 0x7770
275 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
276 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
277 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
278 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
279 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
280 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
281 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
282 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
283 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
284 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
286 NvRegPatternCRC
= 0x204,
287 NvRegPatternMask
= 0x208,
288 NvRegPowerCap
= 0x268,
289 #define NVREG_POWERCAP_D3SUPP (1<<30)
290 #define NVREG_POWERCAP_D2SUPP (1<<26)
291 #define NVREG_POWERCAP_D1SUPP (1<<25)
292 NvRegPowerState
= 0x26c,
293 #define NVREG_POWERSTATE_POWEREDUP 0x8000
294 #define NVREG_POWERSTATE_VALID 0x0100
295 #define NVREG_POWERSTATE_MASK 0x0003
296 #define NVREG_POWERSTATE_D0 0x0000
297 #define NVREG_POWERSTATE_D1 0x0001
298 #define NVREG_POWERSTATE_D2 0x0002
299 #define NVREG_POWERSTATE_D3 0x0003
301 NvRegTxZeroReXmt
= 0x284,
302 NvRegTxOneReXmt
= 0x288,
303 NvRegTxManyReXmt
= 0x28c,
304 NvRegTxLateCol
= 0x290,
305 NvRegTxUnderflow
= 0x294,
306 NvRegTxLossCarrier
= 0x298,
307 NvRegTxExcessDef
= 0x29c,
308 NvRegTxRetryErr
= 0x2a0,
309 NvRegRxFrameErr
= 0x2a4,
310 NvRegRxExtraByte
= 0x2a8,
311 NvRegRxLateCol
= 0x2ac,
313 NvRegRxFrameTooLong
= 0x2b4,
314 NvRegRxOverflow
= 0x2b8,
315 NvRegRxFCSErr
= 0x2bc,
316 NvRegRxFrameAlignErr
= 0x2c0,
317 NvRegRxLenErr
= 0x2c4,
318 NvRegRxUnicast
= 0x2c8,
319 NvRegRxMulticast
= 0x2cc,
320 NvRegRxBroadcast
= 0x2d0,
322 NvRegTxFrame
= 0x2d8,
324 NvRegTxPause
= 0x2e0,
325 NvRegRxPause
= 0x2e4,
326 NvRegRxDropFrame
= 0x2e8,
327 NvRegVlanControl
= 0x300,
328 #define NVREG_VLANCONTROL_ENABLE 0x2000
329 NvRegMSIXMap0
= 0x3e0,
330 NvRegMSIXMap1
= 0x3e4,
331 NvRegMSIXIrqStatus
= 0x3f0,
333 NvRegPowerState2
= 0x600,
334 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
335 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
338 /* Big endian: should work, but is untested */
344 struct ring_desc_ex
{
352 struct ring_desc
* orig
;
353 struct ring_desc_ex
* ex
;
356 #define FLAG_MASK_V1 0xffff0000
357 #define FLAG_MASK_V2 0xffffc000
358 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
359 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
361 #define NV_TX_LASTPACKET (1<<16)
362 #define NV_TX_RETRYERROR (1<<19)
363 #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
364 #define NV_TX_FORCED_INTERRUPT (1<<24)
365 #define NV_TX_DEFERRED (1<<26)
366 #define NV_TX_CARRIERLOST (1<<27)
367 #define NV_TX_LATECOLLISION (1<<28)
368 #define NV_TX_UNDERFLOW (1<<29)
369 #define NV_TX_ERROR (1<<30)
370 #define NV_TX_VALID (1<<31)
372 #define NV_TX2_LASTPACKET (1<<29)
373 #define NV_TX2_RETRYERROR (1<<18)
374 #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
375 #define NV_TX2_FORCED_INTERRUPT (1<<30)
376 #define NV_TX2_DEFERRED (1<<25)
377 #define NV_TX2_CARRIERLOST (1<<26)
378 #define NV_TX2_LATECOLLISION (1<<27)
379 #define NV_TX2_UNDERFLOW (1<<28)
380 /* error and valid are the same for both */
381 #define NV_TX2_ERROR (1<<30)
382 #define NV_TX2_VALID (1<<31)
383 #define NV_TX2_TSO (1<<28)
384 #define NV_TX2_TSO_SHIFT 14
385 #define NV_TX2_TSO_MAX_SHIFT 14
386 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
387 #define NV_TX2_CHECKSUM_L3 (1<<27)
388 #define NV_TX2_CHECKSUM_L4 (1<<26)
390 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
392 #define NV_RX_DESCRIPTORVALID (1<<16)
393 #define NV_RX_MISSEDFRAME (1<<17)
394 #define NV_RX_SUBSTRACT1 (1<<18)
395 #define NV_RX_ERROR1 (1<<23)
396 #define NV_RX_ERROR2 (1<<24)
397 #define NV_RX_ERROR3 (1<<25)
398 #define NV_RX_ERROR4 (1<<26)
399 #define NV_RX_CRCERR (1<<27)
400 #define NV_RX_OVERFLOW (1<<28)
401 #define NV_RX_FRAMINGERR (1<<29)
402 #define NV_RX_ERROR (1<<30)
403 #define NV_RX_AVAIL (1<<31)
405 #define NV_RX2_CHECKSUMMASK (0x1C000000)
406 #define NV_RX2_CHECKSUM_IP (0x10000000)
407 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
408 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
409 #define NV_RX2_DESCRIPTORVALID (1<<29)
410 #define NV_RX2_SUBSTRACT1 (1<<25)
411 #define NV_RX2_ERROR1 (1<<18)
412 #define NV_RX2_ERROR2 (1<<19)
413 #define NV_RX2_ERROR3 (1<<20)
414 #define NV_RX2_ERROR4 (1<<21)
415 #define NV_RX2_CRCERR (1<<22)
416 #define NV_RX2_OVERFLOW (1<<23)
417 #define NV_RX2_FRAMINGERR (1<<24)
418 /* error and avail are the same for both */
419 #define NV_RX2_ERROR (1<<30)
420 #define NV_RX2_AVAIL (1<<31)
422 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
423 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
425 /* Miscelaneous hardware related defines: */
426 #define NV_PCI_REGSZ_VER1 0x270
427 #define NV_PCI_REGSZ_VER2 0x2d4
428 #define NV_PCI_REGSZ_VER3 0x604
429 #define NV_PCI_REGSZ_MAX 0x604
431 /* various timeout delays: all in usec */
432 #define NV_TXRX_RESET_DELAY 4
433 #define NV_TXSTOP_DELAY1 10
434 #define NV_TXSTOP_DELAY1MAX 500000
435 #define NV_TXSTOP_DELAY2 100
436 #define NV_RXSTOP_DELAY1 10
437 #define NV_RXSTOP_DELAY1MAX 500000
438 #define NV_RXSTOP_DELAY2 100
439 #define NV_SETUP5_DELAY 5
440 #define NV_SETUP5_DELAYMAX 50000
441 #define NV_POWERUP_DELAY 5
442 #define NV_POWERUP_DELAYMAX 5000
443 #define NV_MIIBUSY_DELAY 50
444 #define NV_MIIPHY_DELAY 10
445 #define NV_MIIPHY_DELAYMAX 10000
446 #define NV_MAC_RESET_DELAY 64
448 #define NV_WAKEUPPATTERNS 5
449 #define NV_WAKEUPMASKENTRIES 4
451 /* General driver defaults */
452 #define NV_WATCHDOG_TIMEO (5*HZ)
454 #define RX_RING_DEFAULT 128
455 #define TX_RING_DEFAULT 256
456 #define RX_RING_MIN 128
457 #define TX_RING_MIN 64
458 #define RING_MAX_DESC_VER_1 1024
459 #define RING_MAX_DESC_VER_2_3 16384
461 /* rx/tx mac addr + type + vlan + align + slack*/
462 #define NV_RX_HEADERS (64)
463 /* even more slack. */
464 #define NV_RX_ALLOC_PAD (64)
466 /* maximum mtu size */
467 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
468 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
470 #define OOM_REFILL (1+HZ/20)
471 #define POLL_WAIT (1+HZ/100)
472 #define LINK_TIMEOUT (3*HZ)
473 #define STATS_INTERVAL (10*HZ)
477 * The nic supports three different descriptor types:
478 * - DESC_VER_1: Original
479 * - DESC_VER_2: support for jumbo frames.
480 * - DESC_VER_3: 64-bit format.
487 #define PHY_OUI_MARVELL 0x5043
488 #define PHY_OUI_CICADA 0x03f1
489 #define PHY_OUI_VITESSE 0x01c1
490 #define PHY_OUI_REALTEK 0x0732
491 #define PHY_OUI_REALTEK2 0x0020
492 #define PHYID1_OUI_MASK 0x03ff
493 #define PHYID1_OUI_SHFT 6
494 #define PHYID2_OUI_MASK 0xfc00
495 #define PHYID2_OUI_SHFT 10
496 #define PHYID2_MODEL_MASK 0x03f0
497 #define PHY_MODEL_REALTEK_8211 0x0110
498 #define PHY_REV_MASK 0x0001
499 #define PHY_REV_REALTEK_8211B 0x0000
500 #define PHY_REV_REALTEK_8211C 0x0001
501 #define PHY_MODEL_REALTEK_8201 0x0200
502 #define PHY_MODEL_MARVELL_E3016 0x0220
503 #define PHY_MARVELL_E3016_INITMASK 0x0300
504 #define PHY_CICADA_INIT1 0x0f000
505 #define PHY_CICADA_INIT2 0x0e00
506 #define PHY_CICADA_INIT3 0x01000
507 #define PHY_CICADA_INIT4 0x0200
508 #define PHY_CICADA_INIT5 0x0004
509 #define PHY_CICADA_INIT6 0x02000
510 #define PHY_VITESSE_INIT_REG1 0x1f
511 #define PHY_VITESSE_INIT_REG2 0x10
512 #define PHY_VITESSE_INIT_REG3 0x11
513 #define PHY_VITESSE_INIT_REG4 0x12
514 #define PHY_VITESSE_INIT_MSK1 0xc
515 #define PHY_VITESSE_INIT_MSK2 0x0180
516 #define PHY_VITESSE_INIT1 0x52b5
517 #define PHY_VITESSE_INIT2 0xaf8a
518 #define PHY_VITESSE_INIT3 0x8
519 #define PHY_VITESSE_INIT4 0x8f8a
520 #define PHY_VITESSE_INIT5 0xaf86
521 #define PHY_VITESSE_INIT6 0x8f86
522 #define PHY_VITESSE_INIT7 0xaf82
523 #define PHY_VITESSE_INIT8 0x0100
524 #define PHY_VITESSE_INIT9 0x8f82
525 #define PHY_VITESSE_INIT10 0x0
526 #define PHY_REALTEK_INIT_REG1 0x1f
527 #define PHY_REALTEK_INIT_REG2 0x19
528 #define PHY_REALTEK_INIT_REG3 0x13
529 #define PHY_REALTEK_INIT_REG4 0x14
530 #define PHY_REALTEK_INIT_REG5 0x18
531 #define PHY_REALTEK_INIT_REG6 0x11
532 #define PHY_REALTEK_INIT1 0x0000
533 #define PHY_REALTEK_INIT2 0x8e00
534 #define PHY_REALTEK_INIT3 0x0001
535 #define PHY_REALTEK_INIT4 0xad17
536 #define PHY_REALTEK_INIT5 0xfb54
537 #define PHY_REALTEK_INIT6 0xf5c7
538 #define PHY_REALTEK_INIT7 0x1000
539 #define PHY_REALTEK_INIT8 0x0003
540 #define PHY_REALTEK_INIT_MSK1 0x0003
542 #define PHY_GIGABIT 0x0100
544 #define PHY_TIMEOUT 0x1
545 #define PHY_ERROR 0x2
549 #define PHY_HALF 0x100
551 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
552 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
553 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
554 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
555 #define NV_PAUSEFRAME_RX_REQ 0x0010
556 #define NV_PAUSEFRAME_TX_REQ 0x0020
557 #define NV_PAUSEFRAME_AUTONEG 0x0040
559 /* MSI/MSI-X defines */
560 #define NV_MSI_X_MAX_VECTORS 8
561 #define NV_MSI_X_VECTORS_MASK 0x000f
562 #define NV_MSI_CAPABLE 0x0010
563 #define NV_MSI_X_CAPABLE 0x0020
564 #define NV_MSI_ENABLED 0x0040
565 #define NV_MSI_X_ENABLED 0x0080
567 #define NV_MSI_X_VECTOR_ALL 0x0
568 #define NV_MSI_X_VECTOR_RX 0x0
569 #define NV_MSI_X_VECTOR_TX 0x1
570 #define NV_MSI_X_VECTOR_OTHER 0x2
572 #define NV_RESTART_TX 0x1
573 #define NV_RESTART_RX 0x2
575 #define NV_TX_LIMIT_COUNT 16
578 struct nv_ethtool_str
{
579 char name
[ETH_GSTRING_LEN
];
582 static const struct nv_ethtool_str nv_estats_str
[] = {
587 { "tx_late_collision" },
588 { "tx_fifo_errors" },
589 { "tx_carrier_errors" },
590 { "tx_excess_deferral" },
591 { "tx_retry_error" },
592 { "rx_frame_error" },
594 { "rx_late_collision" },
596 { "rx_frame_too_long" },
597 { "rx_over_errors" },
599 { "rx_frame_align_error" },
600 { "rx_length_error" },
605 { "rx_errors_total" },
606 { "tx_errors_total" },
608 /* version 2 stats */
617 struct nv_ethtool_stats
{
622 u64 tx_late_collision
;
624 u64 tx_carrier_errors
;
625 u64 tx_excess_deferral
;
629 u64 rx_late_collision
;
631 u64 rx_frame_too_long
;
634 u64 rx_frame_align_error
;
643 /* version 2 stats */
652 #define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
653 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
656 #define NV_TEST_COUNT_BASE 3
657 #define NV_TEST_COUNT_EXTENDED 4
659 static const struct nv_ethtool_str nv_etests_str
[] = {
660 { "link (online/offline)" },
661 { "register (offline) " },
662 { "interrupt (offline) " },
663 { "loopback (offline) " }
666 struct register_test
{
671 static const struct register_test nv_registers_test
[] = {
672 { NvRegUnknownSetupReg6
, 0x01 },
673 { NvRegMisc1
, 0x03c },
674 { NvRegOffloadConfig
, 0x03ff },
675 { NvRegMulticastAddrA
, 0xffffffff },
676 { NvRegTxWatermark
, 0x0ff },
677 { NvRegWakeUpFlags
, 0x07777 },
684 unsigned int dma_len
;
685 struct ring_desc_ex
*first_tx_desc
;
686 struct nv_skb_map
*next_tx_ctx
;
691 * All hardware access under dev->priv->lock, except the performance
693 * - rx is (pseudo-) lockless: it relies on the single-threading provided
694 * by the arch code for interrupts.
695 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
696 * needs dev->priv->lock :-(
697 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
700 /* in dev: base, irq */
704 struct net_device
*dev
;
705 struct napi_struct napi
;
708 * Locking: spin_lock(&np->lock); */
709 struct nv_ethtool_stats estats
;
717 unsigned int phy_oui
;
718 unsigned int phy_model
;
719 unsigned int phy_rev
;
724 /* General data: RO fields */
725 dma_addr_t ring_addr
;
726 struct pci_dev
*pci_dev
;
740 /* rx specific fields.
741 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
743 union ring_type get_rx
, put_rx
, first_rx
, last_rx
;
744 struct nv_skb_map
*get_rx_ctx
, *put_rx_ctx
;
745 struct nv_skb_map
*first_rx_ctx
, *last_rx_ctx
;
746 struct nv_skb_map
*rx_skb
;
748 union ring_type rx_ring
;
749 unsigned int rx_buf_sz
;
750 unsigned int pkt_limit
;
751 struct timer_list oom_kick
;
752 struct timer_list nic_poll
;
753 struct timer_list stats_poll
;
757 /* media detection workaround.
758 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
761 unsigned long link_timeout
;
763 * tx specific fields.
765 union ring_type get_tx
, put_tx
, first_tx
, last_tx
;
766 struct nv_skb_map
*get_tx_ctx
, *put_tx_ctx
;
767 struct nv_skb_map
*first_tx_ctx
, *last_tx_ctx
;
768 struct nv_skb_map
*tx_skb
;
770 union ring_type tx_ring
;
774 u32 tx_pkts_in_progress
;
775 struct nv_skb_map
*tx_change_owner
;
776 struct nv_skb_map
*tx_end_flip
;
780 struct vlan_group
*vlangrp
;
782 /* msi/msi-x fields */
784 struct msix_entry msi_x_entry
[NV_MSI_X_MAX_VECTORS
];
789 /* power saved state */
790 u32 saved_config_space
[NV_PCI_REGSZ_MAX
/4];
794 * Maximum number of loops until we assume that a bit in the irq mask
795 * is stuck. Overridable with module param.
797 static int max_interrupt_work
= 5;
800 * Optimization can be either throuput mode or cpu mode
802 * Throughput Mode: Every tx and rx packet will generate an interrupt.
803 * CPU Mode: Interrupts are controlled by a timer.
806 NV_OPTIMIZATION_MODE_THROUGHPUT
,
807 NV_OPTIMIZATION_MODE_CPU
809 static int optimization_mode
= NV_OPTIMIZATION_MODE_THROUGHPUT
;
812 * Poll interval for timer irq
814 * This interval determines how frequent an interrupt is generated.
815 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
816 * Min = 0, and Max = 65535
818 static int poll_interval
= -1;
827 static int msi
= NV_MSI_INT_ENABLED
;
833 NV_MSIX_INT_DISABLED
,
836 static int msix
= NV_MSIX_INT_DISABLED
;
842 NV_DMA_64BIT_DISABLED
,
845 static int dma_64bit
= NV_DMA_64BIT_ENABLED
;
848 * Crossover Detection
849 * Realtek 8201 phy + some OEM boards do not work properly.
852 NV_CROSSOVER_DETECTION_DISABLED
,
853 NV_CROSSOVER_DETECTION_ENABLED
855 static int phy_cross
= NV_CROSSOVER_DETECTION_DISABLED
;
857 static inline struct fe_priv
*get_nvpriv(struct net_device
*dev
)
859 return netdev_priv(dev
);
862 static inline u8 __iomem
*get_hwbase(struct net_device
*dev
)
864 return ((struct fe_priv
*)netdev_priv(dev
))->base
;
867 static inline void pci_push(u8 __iomem
*base
)
869 /* force out pending posted writes */
873 static inline u32
nv_descr_getlength(struct ring_desc
*prd
, u32 v
)
875 return le32_to_cpu(prd
->flaglen
)
876 & ((v
== DESC_VER_1
) ? LEN_MASK_V1
: LEN_MASK_V2
);
879 static inline u32
nv_descr_getlength_ex(struct ring_desc_ex
*prd
, u32 v
)
881 return le32_to_cpu(prd
->flaglen
) & LEN_MASK_V2
;
884 static bool nv_optimized(struct fe_priv
*np
)
886 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
891 static int reg_delay(struct net_device
*dev
, int offset
, u32 mask
, u32 target
,
892 int delay
, int delaymax
, const char *msg
)
894 u8 __iomem
*base
= get_hwbase(dev
);
905 } while ((readl(base
+ offset
) & mask
) != target
);
909 #define NV_SETUP_RX_RING 0x01
910 #define NV_SETUP_TX_RING 0x02
912 static inline u32
dma_low(dma_addr_t addr
)
917 static inline u32
dma_high(dma_addr_t addr
)
919 return addr
>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
922 static void setup_hw_rings(struct net_device
*dev
, int rxtx_flags
)
924 struct fe_priv
*np
= get_nvpriv(dev
);
925 u8 __iomem
*base
= get_hwbase(dev
);
927 if (!nv_optimized(np
)) {
928 if (rxtx_flags
& NV_SETUP_RX_RING
) {
929 writel(dma_low(np
->ring_addr
), base
+ NvRegRxRingPhysAddr
);
931 if (rxtx_flags
& NV_SETUP_TX_RING
) {
932 writel(dma_low(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc
)), base
+ NvRegTxRingPhysAddr
);
935 if (rxtx_flags
& NV_SETUP_RX_RING
) {
936 writel(dma_low(np
->ring_addr
), base
+ NvRegRxRingPhysAddr
);
937 writel(dma_high(np
->ring_addr
), base
+ NvRegRxRingPhysAddrHigh
);
939 if (rxtx_flags
& NV_SETUP_TX_RING
) {
940 writel(dma_low(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc_ex
)), base
+ NvRegTxRingPhysAddr
);
941 writel(dma_high(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc_ex
)), base
+ NvRegTxRingPhysAddrHigh
);
946 static void free_rings(struct net_device
*dev
)
948 struct fe_priv
*np
= get_nvpriv(dev
);
950 if (!nv_optimized(np
)) {
951 if (np
->rx_ring
.orig
)
952 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
953 np
->rx_ring
.orig
, np
->ring_addr
);
956 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc_ex
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
957 np
->rx_ring
.ex
, np
->ring_addr
);
965 static int using_multi_irqs(struct net_device
*dev
)
967 struct fe_priv
*np
= get_nvpriv(dev
);
969 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
) ||
970 ((np
->msi_flags
& NV_MSI_X_ENABLED
) &&
971 ((np
->msi_flags
& NV_MSI_X_VECTORS_MASK
) == 0x1)))
977 static void nv_enable_irq(struct net_device
*dev
)
979 struct fe_priv
*np
= get_nvpriv(dev
);
981 if (!using_multi_irqs(dev
)) {
982 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
983 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
985 enable_irq(np
->pci_dev
->irq
);
987 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
988 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
989 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
993 static void nv_disable_irq(struct net_device
*dev
)
995 struct fe_priv
*np
= get_nvpriv(dev
);
997 if (!using_multi_irqs(dev
)) {
998 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
999 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1001 disable_irq(np
->pci_dev
->irq
);
1003 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1004 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
1005 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
1009 /* In MSIX mode, a write to irqmask behaves as XOR */
1010 static void nv_enable_hw_interrupts(struct net_device
*dev
, u32 mask
)
1012 u8 __iomem
*base
= get_hwbase(dev
);
1014 writel(mask
, base
+ NvRegIrqMask
);
1017 static void nv_disable_hw_interrupts(struct net_device
*dev
, u32 mask
)
1019 struct fe_priv
*np
= get_nvpriv(dev
);
1020 u8 __iomem
*base
= get_hwbase(dev
);
1022 if (np
->msi_flags
& NV_MSI_X_ENABLED
) {
1023 writel(mask
, base
+ NvRegIrqMask
);
1025 if (np
->msi_flags
& NV_MSI_ENABLED
)
1026 writel(0, base
+ NvRegMSIIrqMask
);
1027 writel(0, base
+ NvRegIrqMask
);
1031 #define MII_READ (-1)
1032 /* mii_rw: read/write a register on the PHY.
1034 * Caller must guarantee serialization
1036 static int mii_rw(struct net_device
*dev
, int addr
, int miireg
, int value
)
1038 u8 __iomem
*base
= get_hwbase(dev
);
1042 writel(NVREG_MIISTAT_MASK_RW
, base
+ NvRegMIIStatus
);
1044 reg
= readl(base
+ NvRegMIIControl
);
1045 if (reg
& NVREG_MIICTL_INUSE
) {
1046 writel(NVREG_MIICTL_INUSE
, base
+ NvRegMIIControl
);
1047 udelay(NV_MIIBUSY_DELAY
);
1050 reg
= (addr
<< NVREG_MIICTL_ADDRSHIFT
) | miireg
;
1051 if (value
!= MII_READ
) {
1052 writel(value
, base
+ NvRegMIIData
);
1053 reg
|= NVREG_MIICTL_WRITE
;
1055 writel(reg
, base
+ NvRegMIIControl
);
1057 if (reg_delay(dev
, NvRegMIIControl
, NVREG_MIICTL_INUSE
, 0,
1058 NV_MIIPHY_DELAY
, NV_MIIPHY_DELAYMAX
, NULL
)) {
1059 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d timed out.\n",
1060 dev
->name
, miireg
, addr
);
1062 } else if (value
!= MII_READ
) {
1063 /* it was a write operation - fewer failures are detectable */
1064 dprintk(KERN_DEBUG
"%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1065 dev
->name
, value
, miireg
, addr
);
1067 } else if (readl(base
+ NvRegMIIStatus
) & NVREG_MIISTAT_ERROR
) {
1068 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d failed.\n",
1069 dev
->name
, miireg
, addr
);
1072 retval
= readl(base
+ NvRegMIIData
);
1073 dprintk(KERN_DEBUG
"%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1074 dev
->name
, miireg
, addr
, retval
);
1080 static int phy_reset(struct net_device
*dev
, u32 bmcr_setup
)
1082 struct fe_priv
*np
= netdev_priv(dev
);
1084 unsigned int tries
= 0;
1086 miicontrol
= BMCR_RESET
| bmcr_setup
;
1087 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, miicontrol
)) {
1091 /* wait for 500ms */
1094 /* must wait till reset is deasserted */
1095 while (miicontrol
& BMCR_RESET
) {
1097 miicontrol
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1098 /* FIXME: 100 tries seem excessive */
1105 static int phy_init(struct net_device
*dev
)
1107 struct fe_priv
*np
= get_nvpriv(dev
);
1108 u8 __iomem
*base
= get_hwbase(dev
);
1109 u32 phyinterface
, phy_reserved
, mii_status
, mii_control
, mii_control_1000
,reg
;
1111 /* phy errata for E3016 phy */
1112 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
1113 reg
= mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, MII_READ
);
1114 reg
&= ~PHY_MARVELL_E3016_INITMASK
;
1115 if (mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, reg
)) {
1116 printk(KERN_INFO
"%s: phy write to errata reg failed.\n", pci_name(np
->pci_dev
));
1120 if (np
->phy_oui
== PHY_OUI_REALTEK
) {
1121 if (np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1122 np
->phy_rev
== PHY_REV_REALTEK_8211B
) {
1123 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1124 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1127 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, PHY_REALTEK_INIT2
)) {
1128 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1131 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
)) {
1132 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1135 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG3
, PHY_REALTEK_INIT4
)) {
1136 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1139 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG4
, PHY_REALTEK_INIT5
)) {
1140 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1143 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG5
, PHY_REALTEK_INIT6
)) {
1144 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1147 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1148 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1152 if (np
->phy_model
== PHY_MODEL_REALTEK_8201
) {
1153 if (np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_32
||
1154 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_33
||
1155 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_34
||
1156 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_35
||
1157 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_36
||
1158 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_37
||
1159 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_38
||
1160 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_39
) {
1161 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, MII_READ
);
1162 phy_reserved
|= PHY_REALTEK_INIT7
;
1163 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, phy_reserved
)) {
1164 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1171 /* set advertise register */
1172 reg
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
1173 reg
|= (ADVERTISE_10HALF
|ADVERTISE_10FULL
|ADVERTISE_100HALF
|ADVERTISE_100FULL
|ADVERTISE_PAUSE_ASYM
|ADVERTISE_PAUSE_CAP
);
1174 if (mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, reg
)) {
1175 printk(KERN_INFO
"%s: phy write to advertise failed.\n", pci_name(np
->pci_dev
));
1179 /* get phy interface type */
1180 phyinterface
= readl(base
+ NvRegPhyInterface
);
1182 /* see if gigabit phy */
1183 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
1184 if (mii_status
& PHY_GIGABIT
) {
1185 np
->gigabit
= PHY_GIGABIT
;
1186 mii_control_1000
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
1187 mii_control_1000
&= ~ADVERTISE_1000HALF
;
1188 if (phyinterface
& PHY_RGMII
)
1189 mii_control_1000
|= ADVERTISE_1000FULL
;
1191 mii_control_1000
&= ~ADVERTISE_1000FULL
;
1193 if (mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, mii_control_1000
)) {
1194 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1201 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1202 mii_control
|= BMCR_ANENABLE
;
1205 * (certain phys need bmcr to be setup with reset)
1207 if (phy_reset(dev
, mii_control
)) {
1208 printk(KERN_INFO
"%s: phy reset failed\n", pci_name(np
->pci_dev
));
1212 /* phy vendor specific configuration */
1213 if ((np
->phy_oui
== PHY_OUI_CICADA
) && (phyinterface
& PHY_RGMII
) ) {
1214 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_RESV1
, MII_READ
);
1215 phy_reserved
&= ~(PHY_CICADA_INIT1
| PHY_CICADA_INIT2
);
1216 phy_reserved
|= (PHY_CICADA_INIT3
| PHY_CICADA_INIT4
);
1217 if (mii_rw(dev
, np
->phyaddr
, MII_RESV1
, phy_reserved
)) {
1218 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1221 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, MII_READ
);
1222 phy_reserved
|= PHY_CICADA_INIT5
;
1223 if (mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, phy_reserved
)) {
1224 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1228 if (np
->phy_oui
== PHY_OUI_CICADA
) {
1229 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, MII_READ
);
1230 phy_reserved
|= PHY_CICADA_INIT6
;
1231 if (mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, phy_reserved
)) {
1232 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1236 if (np
->phy_oui
== PHY_OUI_VITESSE
) {
1237 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG1
, PHY_VITESSE_INIT1
)) {
1238 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1241 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT2
)) {
1242 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1245 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, MII_READ
);
1246 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, phy_reserved
)) {
1247 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1250 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, MII_READ
);
1251 phy_reserved
&= ~PHY_VITESSE_INIT_MSK1
;
1252 phy_reserved
|= PHY_VITESSE_INIT3
;
1253 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, phy_reserved
)) {
1254 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1257 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT4
)) {
1258 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1261 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT5
)) {
1262 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1265 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, MII_READ
);
1266 phy_reserved
&= ~PHY_VITESSE_INIT_MSK1
;
1267 phy_reserved
|= PHY_VITESSE_INIT3
;
1268 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, phy_reserved
)) {
1269 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1272 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, MII_READ
);
1273 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, phy_reserved
)) {
1274 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1277 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT6
)) {
1278 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1281 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT7
)) {
1282 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1285 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, MII_READ
);
1286 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, phy_reserved
)) {
1287 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1290 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, MII_READ
);
1291 phy_reserved
&= ~PHY_VITESSE_INIT_MSK2
;
1292 phy_reserved
|= PHY_VITESSE_INIT8
;
1293 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, phy_reserved
)) {
1294 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1297 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT9
)) {
1298 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1301 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG1
, PHY_VITESSE_INIT10
)) {
1302 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1306 if (np
->phy_oui
== PHY_OUI_REALTEK
) {
1307 if (np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1308 np
->phy_rev
== PHY_REV_REALTEK_8211B
) {
1309 /* reset could have cleared these out, set them back */
1310 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1311 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1314 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, PHY_REALTEK_INIT2
)) {
1315 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1318 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
)) {
1319 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1322 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG3
, PHY_REALTEK_INIT4
)) {
1323 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1326 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG4
, PHY_REALTEK_INIT5
)) {
1327 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1330 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG5
, PHY_REALTEK_INIT6
)) {
1331 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1334 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1335 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1339 if (np
->phy_model
== PHY_MODEL_REALTEK_8201
) {
1340 if (np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_32
||
1341 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_33
||
1342 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_34
||
1343 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_35
||
1344 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_36
||
1345 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_37
||
1346 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_38
||
1347 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_39
) {
1348 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, MII_READ
);
1349 phy_reserved
|= PHY_REALTEK_INIT7
;
1350 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, phy_reserved
)) {
1351 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1355 if (phy_cross
== NV_CROSSOVER_DETECTION_DISABLED
) {
1356 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
)) {
1357 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1360 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, MII_READ
);
1361 phy_reserved
&= ~PHY_REALTEK_INIT_MSK1
;
1362 phy_reserved
|= PHY_REALTEK_INIT3
;
1363 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, phy_reserved
)) {
1364 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1367 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1368 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1375 /* some phys clear out pause advertisment on reset, set it back */
1376 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, reg
);
1378 /* restart auto negotiation */
1379 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1380 mii_control
|= (BMCR_ANRESTART
| BMCR_ANENABLE
);
1381 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
)) {
1388 static void nv_start_rx(struct net_device
*dev
)
1390 struct fe_priv
*np
= netdev_priv(dev
);
1391 u8 __iomem
*base
= get_hwbase(dev
);
1392 u32 rx_ctrl
= readl(base
+ NvRegReceiverControl
);
1394 dprintk(KERN_DEBUG
"%s: nv_start_rx\n", dev
->name
);
1395 /* Already running? Stop it. */
1396 if ((readl(base
+ NvRegReceiverControl
) & NVREG_RCVCTL_START
) && !np
->mac_in_use
) {
1397 rx_ctrl
&= ~NVREG_RCVCTL_START
;
1398 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1401 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
1403 rx_ctrl
|= NVREG_RCVCTL_START
;
1405 rx_ctrl
&= ~NVREG_RCVCTL_RX_PATH_EN
;
1406 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1407 dprintk(KERN_DEBUG
"%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1408 dev
->name
, np
->duplex
, np
->linkspeed
);
1412 static void nv_stop_rx(struct net_device
*dev
)
1414 struct fe_priv
*np
= netdev_priv(dev
);
1415 u8 __iomem
*base
= get_hwbase(dev
);
1416 u32 rx_ctrl
= readl(base
+ NvRegReceiverControl
);
1418 dprintk(KERN_DEBUG
"%s: nv_stop_rx\n", dev
->name
);
1419 if (!np
->mac_in_use
)
1420 rx_ctrl
&= ~NVREG_RCVCTL_START
;
1422 rx_ctrl
|= NVREG_RCVCTL_RX_PATH_EN
;
1423 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1424 reg_delay(dev
, NvRegReceiverStatus
, NVREG_RCVSTAT_BUSY
, 0,
1425 NV_RXSTOP_DELAY1
, NV_RXSTOP_DELAY1MAX
,
1426 KERN_INFO
"nv_stop_rx: ReceiverStatus remained busy");
1428 udelay(NV_RXSTOP_DELAY2
);
1429 if (!np
->mac_in_use
)
1430 writel(0, base
+ NvRegLinkSpeed
);
1433 static void nv_start_tx(struct net_device
*dev
)
1435 struct fe_priv
*np
= netdev_priv(dev
);
1436 u8 __iomem
*base
= get_hwbase(dev
);
1437 u32 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
1439 dprintk(KERN_DEBUG
"%s: nv_start_tx\n", dev
->name
);
1440 tx_ctrl
|= NVREG_XMITCTL_START
;
1442 tx_ctrl
&= ~NVREG_XMITCTL_TX_PATH_EN
;
1443 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
1447 static void nv_stop_tx(struct net_device
*dev
)
1449 struct fe_priv
*np
= netdev_priv(dev
);
1450 u8 __iomem
*base
= get_hwbase(dev
);
1451 u32 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
1453 dprintk(KERN_DEBUG
"%s: nv_stop_tx\n", dev
->name
);
1454 if (!np
->mac_in_use
)
1455 tx_ctrl
&= ~NVREG_XMITCTL_START
;
1457 tx_ctrl
|= NVREG_XMITCTL_TX_PATH_EN
;
1458 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
1459 reg_delay(dev
, NvRegTransmitterStatus
, NVREG_XMITSTAT_BUSY
, 0,
1460 NV_TXSTOP_DELAY1
, NV_TXSTOP_DELAY1MAX
,
1461 KERN_INFO
"nv_stop_tx: TransmitterStatus remained busy");
1463 udelay(NV_TXSTOP_DELAY2
);
1464 if (!np
->mac_in_use
)
1465 writel(readl(base
+ NvRegTransmitPoll
) & NVREG_TRANSMITPOLL_MAC_ADDR_REV
,
1466 base
+ NvRegTransmitPoll
);
1469 static void nv_start_rxtx(struct net_device
*dev
)
1475 static void nv_stop_rxtx(struct net_device
*dev
)
1481 static void nv_txrx_reset(struct net_device
*dev
)
1483 struct fe_priv
*np
= netdev_priv(dev
);
1484 u8 __iomem
*base
= get_hwbase(dev
);
1486 dprintk(KERN_DEBUG
"%s: nv_txrx_reset\n", dev
->name
);
1487 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1489 udelay(NV_TXRX_RESET_DELAY
);
1490 writel(NVREG_TXRXCTL_BIT2
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1494 static void nv_mac_reset(struct net_device
*dev
)
1496 struct fe_priv
*np
= netdev_priv(dev
);
1497 u8 __iomem
*base
= get_hwbase(dev
);
1498 u32 temp1
, temp2
, temp3
;
1500 dprintk(KERN_DEBUG
"%s: nv_mac_reset\n", dev
->name
);
1502 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1505 /* save registers since they will be cleared on reset */
1506 temp1
= readl(base
+ NvRegMacAddrA
);
1507 temp2
= readl(base
+ NvRegMacAddrB
);
1508 temp3
= readl(base
+ NvRegTransmitPoll
);
1510 writel(NVREG_MAC_RESET_ASSERT
, base
+ NvRegMacReset
);
1512 udelay(NV_MAC_RESET_DELAY
);
1513 writel(0, base
+ NvRegMacReset
);
1515 udelay(NV_MAC_RESET_DELAY
);
1517 /* restore saved registers */
1518 writel(temp1
, base
+ NvRegMacAddrA
);
1519 writel(temp2
, base
+ NvRegMacAddrB
);
1520 writel(temp3
, base
+ NvRegTransmitPoll
);
1522 writel(NVREG_TXRXCTL_BIT2
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1526 static void nv_get_hw_stats(struct net_device
*dev
)
1528 struct fe_priv
*np
= netdev_priv(dev
);
1529 u8 __iomem
*base
= get_hwbase(dev
);
1531 np
->estats
.tx_bytes
+= readl(base
+ NvRegTxCnt
);
1532 np
->estats
.tx_zero_rexmt
+= readl(base
+ NvRegTxZeroReXmt
);
1533 np
->estats
.tx_one_rexmt
+= readl(base
+ NvRegTxOneReXmt
);
1534 np
->estats
.tx_many_rexmt
+= readl(base
+ NvRegTxManyReXmt
);
1535 np
->estats
.tx_late_collision
+= readl(base
+ NvRegTxLateCol
);
1536 np
->estats
.tx_fifo_errors
+= readl(base
+ NvRegTxUnderflow
);
1537 np
->estats
.tx_carrier_errors
+= readl(base
+ NvRegTxLossCarrier
);
1538 np
->estats
.tx_excess_deferral
+= readl(base
+ NvRegTxExcessDef
);
1539 np
->estats
.tx_retry_error
+= readl(base
+ NvRegTxRetryErr
);
1540 np
->estats
.rx_frame_error
+= readl(base
+ NvRegRxFrameErr
);
1541 np
->estats
.rx_extra_byte
+= readl(base
+ NvRegRxExtraByte
);
1542 np
->estats
.rx_late_collision
+= readl(base
+ NvRegRxLateCol
);
1543 np
->estats
.rx_runt
+= readl(base
+ NvRegRxRunt
);
1544 np
->estats
.rx_frame_too_long
+= readl(base
+ NvRegRxFrameTooLong
);
1545 np
->estats
.rx_over_errors
+= readl(base
+ NvRegRxOverflow
);
1546 np
->estats
.rx_crc_errors
+= readl(base
+ NvRegRxFCSErr
);
1547 np
->estats
.rx_frame_align_error
+= readl(base
+ NvRegRxFrameAlignErr
);
1548 np
->estats
.rx_length_error
+= readl(base
+ NvRegRxLenErr
);
1549 np
->estats
.rx_unicast
+= readl(base
+ NvRegRxUnicast
);
1550 np
->estats
.rx_multicast
+= readl(base
+ NvRegRxMulticast
);
1551 np
->estats
.rx_broadcast
+= readl(base
+ NvRegRxBroadcast
);
1552 np
->estats
.rx_packets
=
1553 np
->estats
.rx_unicast
+
1554 np
->estats
.rx_multicast
+
1555 np
->estats
.rx_broadcast
;
1556 np
->estats
.rx_errors_total
=
1557 np
->estats
.rx_crc_errors
+
1558 np
->estats
.rx_over_errors
+
1559 np
->estats
.rx_frame_error
+
1560 (np
->estats
.rx_frame_align_error
- np
->estats
.rx_extra_byte
) +
1561 np
->estats
.rx_late_collision
+
1562 np
->estats
.rx_runt
+
1563 np
->estats
.rx_frame_too_long
;
1564 np
->estats
.tx_errors_total
=
1565 np
->estats
.tx_late_collision
+
1566 np
->estats
.tx_fifo_errors
+
1567 np
->estats
.tx_carrier_errors
+
1568 np
->estats
.tx_excess_deferral
+
1569 np
->estats
.tx_retry_error
;
1571 if (np
->driver_data
& DEV_HAS_STATISTICS_V2
) {
1572 np
->estats
.tx_deferral
+= readl(base
+ NvRegTxDef
);
1573 np
->estats
.tx_packets
+= readl(base
+ NvRegTxFrame
);
1574 np
->estats
.rx_bytes
+= readl(base
+ NvRegRxCnt
);
1575 np
->estats
.tx_pause
+= readl(base
+ NvRegTxPause
);
1576 np
->estats
.rx_pause
+= readl(base
+ NvRegRxPause
);
1577 np
->estats
.rx_drop_frame
+= readl(base
+ NvRegRxDropFrame
);
1582 * nv_get_stats: dev->get_stats function
1583 * Get latest stats value from the nic.
1584 * Called with read_lock(&dev_base_lock) held for read -
1585 * only synchronized against unregister_netdevice.
1587 static struct net_device_stats
*nv_get_stats(struct net_device
*dev
)
1589 struct fe_priv
*np
= netdev_priv(dev
);
1591 /* If the nic supports hw counters then retrieve latest values */
1592 if (np
->driver_data
& (DEV_HAS_STATISTICS_V1
|DEV_HAS_STATISTICS_V2
)) {
1593 nv_get_hw_stats(dev
);
1595 /* copy to net_device stats */
1596 dev
->stats
.tx_bytes
= np
->estats
.tx_bytes
;
1597 dev
->stats
.tx_fifo_errors
= np
->estats
.tx_fifo_errors
;
1598 dev
->stats
.tx_carrier_errors
= np
->estats
.tx_carrier_errors
;
1599 dev
->stats
.rx_crc_errors
= np
->estats
.rx_crc_errors
;
1600 dev
->stats
.rx_over_errors
= np
->estats
.rx_over_errors
;
1601 dev
->stats
.rx_errors
= np
->estats
.rx_errors_total
;
1602 dev
->stats
.tx_errors
= np
->estats
.tx_errors_total
;
1609 * nv_alloc_rx: fill rx ring entries.
1610 * Return 1 if the allocations for the skbs failed and the
1611 * rx engine is without Available descriptors
1613 static int nv_alloc_rx(struct net_device
*dev
)
1615 struct fe_priv
*np
= netdev_priv(dev
);
1616 struct ring_desc
* less_rx
;
1618 less_rx
= np
->get_rx
.orig
;
1619 if (less_rx
-- == np
->first_rx
.orig
)
1620 less_rx
= np
->last_rx
.orig
;
1622 while (np
->put_rx
.orig
!= less_rx
) {
1623 struct sk_buff
*skb
= dev_alloc_skb(np
->rx_buf_sz
+ NV_RX_ALLOC_PAD
);
1625 np
->put_rx_ctx
->skb
= skb
;
1626 np
->put_rx_ctx
->dma
= pci_map_single(np
->pci_dev
,
1629 PCI_DMA_FROMDEVICE
);
1630 np
->put_rx_ctx
->dma_len
= skb_tailroom(skb
);
1631 np
->put_rx
.orig
->buf
= cpu_to_le32(np
->put_rx_ctx
->dma
);
1633 np
->put_rx
.orig
->flaglen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX_AVAIL
);
1634 if (unlikely(np
->put_rx
.orig
++ == np
->last_rx
.orig
))
1635 np
->put_rx
.orig
= np
->first_rx
.orig
;
1636 if (unlikely(np
->put_rx_ctx
++ == np
->last_rx_ctx
))
1637 np
->put_rx_ctx
= np
->first_rx_ctx
;
1645 static int nv_alloc_rx_optimized(struct net_device
*dev
)
1647 struct fe_priv
*np
= netdev_priv(dev
);
1648 struct ring_desc_ex
* less_rx
;
1650 less_rx
= np
->get_rx
.ex
;
1651 if (less_rx
-- == np
->first_rx
.ex
)
1652 less_rx
= np
->last_rx
.ex
;
1654 while (np
->put_rx
.ex
!= less_rx
) {
1655 struct sk_buff
*skb
= dev_alloc_skb(np
->rx_buf_sz
+ NV_RX_ALLOC_PAD
);
1657 np
->put_rx_ctx
->skb
= skb
;
1658 np
->put_rx_ctx
->dma
= pci_map_single(np
->pci_dev
,
1661 PCI_DMA_FROMDEVICE
);
1662 np
->put_rx_ctx
->dma_len
= skb_tailroom(skb
);
1663 np
->put_rx
.ex
->bufhigh
= cpu_to_le32(dma_high(np
->put_rx_ctx
->dma
));
1664 np
->put_rx
.ex
->buflow
= cpu_to_le32(dma_low(np
->put_rx_ctx
->dma
));
1666 np
->put_rx
.ex
->flaglen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX2_AVAIL
);
1667 if (unlikely(np
->put_rx
.ex
++ == np
->last_rx
.ex
))
1668 np
->put_rx
.ex
= np
->first_rx
.ex
;
1669 if (unlikely(np
->put_rx_ctx
++ == np
->last_rx_ctx
))
1670 np
->put_rx_ctx
= np
->first_rx_ctx
;
1678 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1679 #ifdef CONFIG_FORCEDETH_NAPI
1680 static void nv_do_rx_refill(unsigned long data
)
1682 struct net_device
*dev
= (struct net_device
*) data
;
1683 struct fe_priv
*np
= netdev_priv(dev
);
1685 /* Just reschedule NAPI rx processing */
1686 netif_rx_schedule(dev
, &np
->napi
);
1689 static void nv_do_rx_refill(unsigned long data
)
1691 struct net_device
*dev
= (struct net_device
*) data
;
1692 struct fe_priv
*np
= netdev_priv(dev
);
1695 if (!using_multi_irqs(dev
)) {
1696 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1697 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1699 disable_irq(np
->pci_dev
->irq
);
1701 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1703 if (!nv_optimized(np
))
1704 retcode
= nv_alloc_rx(dev
);
1706 retcode
= nv_alloc_rx_optimized(dev
);
1708 spin_lock_irq(&np
->lock
);
1709 if (!np
->in_shutdown
)
1710 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
1711 spin_unlock_irq(&np
->lock
);
1713 if (!using_multi_irqs(dev
)) {
1714 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1715 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1717 enable_irq(np
->pci_dev
->irq
);
1719 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1724 static void nv_init_rx(struct net_device
*dev
)
1726 struct fe_priv
*np
= netdev_priv(dev
);
1729 np
->get_rx
= np
->put_rx
= np
->first_rx
= np
->rx_ring
;
1731 if (!nv_optimized(np
))
1732 np
->last_rx
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
-1];
1734 np
->last_rx
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
-1];
1735 np
->get_rx_ctx
= np
->put_rx_ctx
= np
->first_rx_ctx
= np
->rx_skb
;
1736 np
->last_rx_ctx
= &np
->rx_skb
[np
->rx_ring_size
-1];
1738 for (i
= 0; i
< np
->rx_ring_size
; i
++) {
1739 if (!nv_optimized(np
)) {
1740 np
->rx_ring
.orig
[i
].flaglen
= 0;
1741 np
->rx_ring
.orig
[i
].buf
= 0;
1743 np
->rx_ring
.ex
[i
].flaglen
= 0;
1744 np
->rx_ring
.ex
[i
].txvlan
= 0;
1745 np
->rx_ring
.ex
[i
].bufhigh
= 0;
1746 np
->rx_ring
.ex
[i
].buflow
= 0;
1748 np
->rx_skb
[i
].skb
= NULL
;
1749 np
->rx_skb
[i
].dma
= 0;
1753 static void nv_init_tx(struct net_device
*dev
)
1755 struct fe_priv
*np
= netdev_priv(dev
);
1758 np
->get_tx
= np
->put_tx
= np
->first_tx
= np
->tx_ring
;
1760 if (!nv_optimized(np
))
1761 np
->last_tx
.orig
= &np
->tx_ring
.orig
[np
->tx_ring_size
-1];
1763 np
->last_tx
.ex
= &np
->tx_ring
.ex
[np
->tx_ring_size
-1];
1764 np
->get_tx_ctx
= np
->put_tx_ctx
= np
->first_tx_ctx
= np
->tx_skb
;
1765 np
->last_tx_ctx
= &np
->tx_skb
[np
->tx_ring_size
-1];
1766 np
->tx_pkts_in_progress
= 0;
1767 np
->tx_change_owner
= NULL
;
1768 np
->tx_end_flip
= NULL
;
1770 for (i
= 0; i
< np
->tx_ring_size
; i
++) {
1771 if (!nv_optimized(np
)) {
1772 np
->tx_ring
.orig
[i
].flaglen
= 0;
1773 np
->tx_ring
.orig
[i
].buf
= 0;
1775 np
->tx_ring
.ex
[i
].flaglen
= 0;
1776 np
->tx_ring
.ex
[i
].txvlan
= 0;
1777 np
->tx_ring
.ex
[i
].bufhigh
= 0;
1778 np
->tx_ring
.ex
[i
].buflow
= 0;
1780 np
->tx_skb
[i
].skb
= NULL
;
1781 np
->tx_skb
[i
].dma
= 0;
1782 np
->tx_skb
[i
].dma_len
= 0;
1783 np
->tx_skb
[i
].first_tx_desc
= NULL
;
1784 np
->tx_skb
[i
].next_tx_ctx
= NULL
;
1788 static int nv_init_ring(struct net_device
*dev
)
1790 struct fe_priv
*np
= netdev_priv(dev
);
1795 if (!nv_optimized(np
))
1796 return nv_alloc_rx(dev
);
1798 return nv_alloc_rx_optimized(dev
);
1801 static int nv_release_txskb(struct net_device
*dev
, struct nv_skb_map
* tx_skb
)
1803 struct fe_priv
*np
= netdev_priv(dev
);
1806 pci_unmap_page(np
->pci_dev
, tx_skb
->dma
,
1812 dev_kfree_skb_any(tx_skb
->skb
);
1820 static void nv_drain_tx(struct net_device
*dev
)
1822 struct fe_priv
*np
= netdev_priv(dev
);
1825 for (i
= 0; i
< np
->tx_ring_size
; i
++) {
1826 if (!nv_optimized(np
)) {
1827 np
->tx_ring
.orig
[i
].flaglen
= 0;
1828 np
->tx_ring
.orig
[i
].buf
= 0;
1830 np
->tx_ring
.ex
[i
].flaglen
= 0;
1831 np
->tx_ring
.ex
[i
].txvlan
= 0;
1832 np
->tx_ring
.ex
[i
].bufhigh
= 0;
1833 np
->tx_ring
.ex
[i
].buflow
= 0;
1835 if (nv_release_txskb(dev
, &np
->tx_skb
[i
]))
1836 dev
->stats
.tx_dropped
++;
1837 np
->tx_skb
[i
].dma
= 0;
1838 np
->tx_skb
[i
].dma_len
= 0;
1839 np
->tx_skb
[i
].first_tx_desc
= NULL
;
1840 np
->tx_skb
[i
].next_tx_ctx
= NULL
;
1842 np
->tx_pkts_in_progress
= 0;
1843 np
->tx_change_owner
= NULL
;
1844 np
->tx_end_flip
= NULL
;
1847 static void nv_drain_rx(struct net_device
*dev
)
1849 struct fe_priv
*np
= netdev_priv(dev
);
1852 for (i
= 0; i
< np
->rx_ring_size
; i
++) {
1853 if (!nv_optimized(np
)) {
1854 np
->rx_ring
.orig
[i
].flaglen
= 0;
1855 np
->rx_ring
.orig
[i
].buf
= 0;
1857 np
->rx_ring
.ex
[i
].flaglen
= 0;
1858 np
->rx_ring
.ex
[i
].txvlan
= 0;
1859 np
->rx_ring
.ex
[i
].bufhigh
= 0;
1860 np
->rx_ring
.ex
[i
].buflow
= 0;
1863 if (np
->rx_skb
[i
].skb
) {
1864 pci_unmap_single(np
->pci_dev
, np
->rx_skb
[i
].dma
,
1865 (skb_end_pointer(np
->rx_skb
[i
].skb
) -
1866 np
->rx_skb
[i
].skb
->data
),
1867 PCI_DMA_FROMDEVICE
);
1868 dev_kfree_skb(np
->rx_skb
[i
].skb
);
1869 np
->rx_skb
[i
].skb
= NULL
;
1874 static void nv_drain_rxtx(struct net_device
*dev
)
1880 static inline u32
nv_get_empty_tx_slots(struct fe_priv
*np
)
1882 return (u32
)(np
->tx_ring_size
- ((np
->tx_ring_size
+ (np
->put_tx_ctx
- np
->get_tx_ctx
)) % np
->tx_ring_size
));
1885 static void nv_legacybackoff_reseed(struct net_device
*dev
)
1887 u8 __iomem
*base
= get_hwbase(dev
);
1892 reg
= readl(base
+ NvRegSlotTime
) & ~NVREG_SLOTTIME_MASK
;
1893 get_random_bytes(&low
, sizeof(low
));
1894 reg
|= low
& NVREG_SLOTTIME_MASK
;
1896 /* Need to stop tx before change takes effect.
1897 * Caller has already gained np->lock.
1899 tx_status
= readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_START
;
1903 writel(reg
, base
+ NvRegSlotTime
);
1909 /* Gear Backoff Seeds */
1910 #define BACKOFF_SEEDSET_ROWS 8
1911 #define BACKOFF_SEEDSET_LFSRS 15
1913 /* Known Good seed sets */
1914 static const u32 main_seedset
[BACKOFF_SEEDSET_ROWS
][BACKOFF_SEEDSET_LFSRS
] = {
1915 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
1916 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
1917 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
1918 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
1919 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
1920 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
1921 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
1922 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
1924 static const u32 gear_seedset
[BACKOFF_SEEDSET_ROWS
][BACKOFF_SEEDSET_LFSRS
] = {
1925 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
1926 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1927 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
1928 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
1929 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
1930 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1931 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1932 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
1934 static void nv_gear_backoff_reseed(struct net_device
*dev
)
1936 u8 __iomem
*base
= get_hwbase(dev
);
1937 u32 miniseed1
, miniseed2
, miniseed2_reversed
, miniseed3
, miniseed3_reversed
;
1938 u32 temp
, seedset
, combinedSeed
;
1941 /* Setup seed for free running LFSR */
1942 /* We are going to read the time stamp counter 3 times
1943 and swizzle bits around to increase randomness */
1944 get_random_bytes(&miniseed1
, sizeof(miniseed1
));
1945 miniseed1
&= 0x0fff;
1949 get_random_bytes(&miniseed2
, sizeof(miniseed2
));
1950 miniseed2
&= 0x0fff;
1953 miniseed2_reversed
=
1954 ((miniseed2
& 0xF00) >> 8) |
1955 (miniseed2
& 0x0F0) |
1956 ((miniseed2
& 0x00F) << 8);
1958 get_random_bytes(&miniseed3
, sizeof(miniseed3
));
1959 miniseed3
&= 0x0fff;
1962 miniseed3_reversed
=
1963 ((miniseed3
& 0xF00) >> 8) |
1964 (miniseed3
& 0x0F0) |
1965 ((miniseed3
& 0x00F) << 8);
1967 combinedSeed
= ((miniseed1
^ miniseed2_reversed
) << 12) |
1968 (miniseed2
^ miniseed3_reversed
);
1970 /* Seeds can not be zero */
1971 if ((combinedSeed
& NVREG_BKOFFCTRL_SEED_MASK
) == 0)
1972 combinedSeed
|= 0x08;
1973 if ((combinedSeed
& (NVREG_BKOFFCTRL_SEED_MASK
<< NVREG_BKOFFCTRL_GEAR
)) == 0)
1974 combinedSeed
|= 0x8000;
1976 /* No need to disable tx here */
1977 temp
= NVREG_BKOFFCTRL_DEFAULT
| (0 << NVREG_BKOFFCTRL_SELECT
);
1978 temp
|= combinedSeed
& NVREG_BKOFFCTRL_SEED_MASK
;
1979 temp
|= combinedSeed
>> NVREG_BKOFFCTRL_GEAR
;
1980 writel(temp
,base
+ NvRegBackOffControl
);
1982 /* Setup seeds for all gear LFSRs. */
1983 get_random_bytes(&seedset
, sizeof(seedset
));
1984 seedset
= seedset
% BACKOFF_SEEDSET_ROWS
;
1985 for (i
= 1; i
<= BACKOFF_SEEDSET_LFSRS
; i
++)
1987 temp
= NVREG_BKOFFCTRL_DEFAULT
| (i
<< NVREG_BKOFFCTRL_SELECT
);
1988 temp
|= main_seedset
[seedset
][i
-1] & 0x3ff;
1989 temp
|= ((gear_seedset
[seedset
][i
-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR
);
1990 writel(temp
, base
+ NvRegBackOffControl
);
1995 * nv_start_xmit: dev->hard_start_xmit function
1996 * Called with netif_tx_lock held.
1998 static int nv_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2000 struct fe_priv
*np
= netdev_priv(dev
);
2002 u32 tx_flags_extra
= (np
->desc_ver
== DESC_VER_1
? NV_TX_LASTPACKET
: NV_TX2_LASTPACKET
);
2003 unsigned int fragments
= skb_shinfo(skb
)->nr_frags
;
2007 u32 size
= skb
->len
-skb
->data_len
;
2008 u32 entries
= (size
>> NV_TX2_TSO_MAX_SHIFT
) + ((size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2010 struct ring_desc
* put_tx
;
2011 struct ring_desc
* start_tx
;
2012 struct ring_desc
* prev_tx
;
2013 struct nv_skb_map
* prev_tx_ctx
;
2014 unsigned long flags
;
2016 /* add fragments to entries count */
2017 for (i
= 0; i
< fragments
; i
++) {
2018 entries
+= (skb_shinfo(skb
)->frags
[i
].size
>> NV_TX2_TSO_MAX_SHIFT
) +
2019 ((skb_shinfo(skb
)->frags
[i
].size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2022 empty_slots
= nv_get_empty_tx_slots(np
);
2023 if (unlikely(empty_slots
<= entries
)) {
2024 spin_lock_irqsave(&np
->lock
, flags
);
2025 netif_stop_queue(dev
);
2027 spin_unlock_irqrestore(&np
->lock
, flags
);
2028 return NETDEV_TX_BUSY
;
2031 start_tx
= put_tx
= np
->put_tx
.orig
;
2033 /* setup the header buffer */
2036 prev_tx_ctx
= np
->put_tx_ctx
;
2037 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2038 np
->put_tx_ctx
->dma
= pci_map_single(np
->pci_dev
, skb
->data
+ offset
, bcnt
,
2040 np
->put_tx_ctx
->dma_len
= bcnt
;
2041 put_tx
->buf
= cpu_to_le32(np
->put_tx_ctx
->dma
);
2042 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2044 tx_flags
= np
->tx_flags
;
2047 if (unlikely(put_tx
++ == np
->last_tx
.orig
))
2048 put_tx
= np
->first_tx
.orig
;
2049 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2050 np
->put_tx_ctx
= np
->first_tx_ctx
;
2053 /* setup the fragments */
2054 for (i
= 0; i
< fragments
; i
++) {
2055 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2056 u32 size
= frag
->size
;
2061 prev_tx_ctx
= np
->put_tx_ctx
;
2062 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2063 np
->put_tx_ctx
->dma
= pci_map_page(np
->pci_dev
, frag
->page
, frag
->page_offset
+offset
, bcnt
,
2065 np
->put_tx_ctx
->dma_len
= bcnt
;
2066 put_tx
->buf
= cpu_to_le32(np
->put_tx_ctx
->dma
);
2067 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2071 if (unlikely(put_tx
++ == np
->last_tx
.orig
))
2072 put_tx
= np
->first_tx
.orig
;
2073 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2074 np
->put_tx_ctx
= np
->first_tx_ctx
;
2078 /* set last fragment flag */
2079 prev_tx
->flaglen
|= cpu_to_le32(tx_flags_extra
);
2081 /* save skb in this slot's context area */
2082 prev_tx_ctx
->skb
= skb
;
2084 if (skb_is_gso(skb
))
2085 tx_flags_extra
= NV_TX2_TSO
| (skb_shinfo(skb
)->gso_size
<< NV_TX2_TSO_SHIFT
);
2087 tx_flags_extra
= skb
->ip_summed
== CHECKSUM_PARTIAL
?
2088 NV_TX2_CHECKSUM_L3
| NV_TX2_CHECKSUM_L4
: 0;
2090 spin_lock_irqsave(&np
->lock
, flags
);
2093 start_tx
->flaglen
|= cpu_to_le32(tx_flags
| tx_flags_extra
);
2094 np
->put_tx
.orig
= put_tx
;
2096 spin_unlock_irqrestore(&np
->lock
, flags
);
2098 dprintk(KERN_DEBUG
"%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2099 dev
->name
, entries
, tx_flags_extra
);
2102 for (j
=0; j
<64; j
++) {
2104 dprintk("\n%03x:", j
);
2105 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
2110 dev
->trans_start
= jiffies
;
2111 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2112 return NETDEV_TX_OK
;
2115 static int nv_start_xmit_optimized(struct sk_buff
*skb
, struct net_device
*dev
)
2117 struct fe_priv
*np
= netdev_priv(dev
);
2120 unsigned int fragments
= skb_shinfo(skb
)->nr_frags
;
2124 u32 size
= skb
->len
-skb
->data_len
;
2125 u32 entries
= (size
>> NV_TX2_TSO_MAX_SHIFT
) + ((size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2127 struct ring_desc_ex
* put_tx
;
2128 struct ring_desc_ex
* start_tx
;
2129 struct ring_desc_ex
* prev_tx
;
2130 struct nv_skb_map
* prev_tx_ctx
;
2131 struct nv_skb_map
* start_tx_ctx
;
2132 unsigned long flags
;
2134 /* add fragments to entries count */
2135 for (i
= 0; i
< fragments
; i
++) {
2136 entries
+= (skb_shinfo(skb
)->frags
[i
].size
>> NV_TX2_TSO_MAX_SHIFT
) +
2137 ((skb_shinfo(skb
)->frags
[i
].size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2140 empty_slots
= nv_get_empty_tx_slots(np
);
2141 if (unlikely(empty_slots
<= entries
)) {
2142 spin_lock_irqsave(&np
->lock
, flags
);
2143 netif_stop_queue(dev
);
2145 spin_unlock_irqrestore(&np
->lock
, flags
);
2146 return NETDEV_TX_BUSY
;
2149 start_tx
= put_tx
= np
->put_tx
.ex
;
2150 start_tx_ctx
= np
->put_tx_ctx
;
2152 /* setup the header buffer */
2155 prev_tx_ctx
= np
->put_tx_ctx
;
2156 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2157 np
->put_tx_ctx
->dma
= pci_map_single(np
->pci_dev
, skb
->data
+ offset
, bcnt
,
2159 np
->put_tx_ctx
->dma_len
= bcnt
;
2160 put_tx
->bufhigh
= cpu_to_le32(dma_high(np
->put_tx_ctx
->dma
));
2161 put_tx
->buflow
= cpu_to_le32(dma_low(np
->put_tx_ctx
->dma
));
2162 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2164 tx_flags
= NV_TX2_VALID
;
2167 if (unlikely(put_tx
++ == np
->last_tx
.ex
))
2168 put_tx
= np
->first_tx
.ex
;
2169 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2170 np
->put_tx_ctx
= np
->first_tx_ctx
;
2173 /* setup the fragments */
2174 for (i
= 0; i
< fragments
; i
++) {
2175 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2176 u32 size
= frag
->size
;
2181 prev_tx_ctx
= np
->put_tx_ctx
;
2182 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2183 np
->put_tx_ctx
->dma
= pci_map_page(np
->pci_dev
, frag
->page
, frag
->page_offset
+offset
, bcnt
,
2185 np
->put_tx_ctx
->dma_len
= bcnt
;
2186 put_tx
->bufhigh
= cpu_to_le32(dma_high(np
->put_tx_ctx
->dma
));
2187 put_tx
->buflow
= cpu_to_le32(dma_low(np
->put_tx_ctx
->dma
));
2188 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2192 if (unlikely(put_tx
++ == np
->last_tx
.ex
))
2193 put_tx
= np
->first_tx
.ex
;
2194 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2195 np
->put_tx_ctx
= np
->first_tx_ctx
;
2199 /* set last fragment flag */
2200 prev_tx
->flaglen
|= cpu_to_le32(NV_TX2_LASTPACKET
);
2202 /* save skb in this slot's context area */
2203 prev_tx_ctx
->skb
= skb
;
2205 if (skb_is_gso(skb
))
2206 tx_flags_extra
= NV_TX2_TSO
| (skb_shinfo(skb
)->gso_size
<< NV_TX2_TSO_SHIFT
);
2208 tx_flags_extra
= skb
->ip_summed
== CHECKSUM_PARTIAL
?
2209 NV_TX2_CHECKSUM_L3
| NV_TX2_CHECKSUM_L4
: 0;
2212 if (likely(!np
->vlangrp
)) {
2213 start_tx
->txvlan
= 0;
2215 if (vlan_tx_tag_present(skb
))
2216 start_tx
->txvlan
= cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT
| vlan_tx_tag_get(skb
));
2218 start_tx
->txvlan
= 0;
2221 spin_lock_irqsave(&np
->lock
, flags
);
2224 /* Limit the number of outstanding tx. Setup all fragments, but
2225 * do not set the VALID bit on the first descriptor. Save a pointer
2226 * to that descriptor and also for next skb_map element.
2229 if (np
->tx_pkts_in_progress
== NV_TX_LIMIT_COUNT
) {
2230 if (!np
->tx_change_owner
)
2231 np
->tx_change_owner
= start_tx_ctx
;
2233 /* remove VALID bit */
2234 tx_flags
&= ~NV_TX2_VALID
;
2235 start_tx_ctx
->first_tx_desc
= start_tx
;
2236 start_tx_ctx
->next_tx_ctx
= np
->put_tx_ctx
;
2237 np
->tx_end_flip
= np
->put_tx_ctx
;
2239 np
->tx_pkts_in_progress
++;
2244 start_tx
->flaglen
|= cpu_to_le32(tx_flags
| tx_flags_extra
);
2245 np
->put_tx
.ex
= put_tx
;
2247 spin_unlock_irqrestore(&np
->lock
, flags
);
2249 dprintk(KERN_DEBUG
"%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2250 dev
->name
, entries
, tx_flags_extra
);
2253 for (j
=0; j
<64; j
++) {
2255 dprintk("\n%03x:", j
);
2256 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
2261 dev
->trans_start
= jiffies
;
2262 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2263 return NETDEV_TX_OK
;
2266 static inline void nv_tx_flip_ownership(struct net_device
*dev
)
2268 struct fe_priv
*np
= netdev_priv(dev
);
2270 np
->tx_pkts_in_progress
--;
2271 if (np
->tx_change_owner
) {
2272 np
->tx_change_owner
->first_tx_desc
->flaglen
|=
2273 cpu_to_le32(NV_TX2_VALID
);
2274 np
->tx_pkts_in_progress
++;
2276 np
->tx_change_owner
= np
->tx_change_owner
->next_tx_ctx
;
2277 if (np
->tx_change_owner
== np
->tx_end_flip
)
2278 np
->tx_change_owner
= NULL
;
2280 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2285 * nv_tx_done: check for completed packets, release the skbs.
2287 * Caller must own np->lock.
2289 static void nv_tx_done(struct net_device
*dev
)
2291 struct fe_priv
*np
= netdev_priv(dev
);
2293 struct ring_desc
* orig_get_tx
= np
->get_tx
.orig
;
2295 while ((np
->get_tx
.orig
!= np
->put_tx
.orig
) &&
2296 !((flags
= le32_to_cpu(np
->get_tx
.orig
->flaglen
)) & NV_TX_VALID
)) {
2298 dprintk(KERN_DEBUG
"%s: nv_tx_done: flags 0x%x.\n",
2301 pci_unmap_page(np
->pci_dev
, np
->get_tx_ctx
->dma
,
2302 np
->get_tx_ctx
->dma_len
,
2304 np
->get_tx_ctx
->dma
= 0;
2306 if (np
->desc_ver
== DESC_VER_1
) {
2307 if (flags
& NV_TX_LASTPACKET
) {
2308 if (flags
& NV_TX_ERROR
) {
2309 if (flags
& NV_TX_UNDERFLOW
)
2310 dev
->stats
.tx_fifo_errors
++;
2311 if (flags
& NV_TX_CARRIERLOST
)
2312 dev
->stats
.tx_carrier_errors
++;
2313 if ((flags
& NV_TX_RETRYERROR
) && !(flags
& NV_TX_RETRYCOUNT_MASK
))
2314 nv_legacybackoff_reseed(dev
);
2315 dev
->stats
.tx_errors
++;
2317 dev
->stats
.tx_packets
++;
2318 dev
->stats
.tx_bytes
+= np
->get_tx_ctx
->skb
->len
;
2320 dev_kfree_skb_any(np
->get_tx_ctx
->skb
);
2321 np
->get_tx_ctx
->skb
= NULL
;
2324 if (flags
& NV_TX2_LASTPACKET
) {
2325 if (flags
& NV_TX2_ERROR
) {
2326 if (flags
& NV_TX2_UNDERFLOW
)
2327 dev
->stats
.tx_fifo_errors
++;
2328 if (flags
& NV_TX2_CARRIERLOST
)
2329 dev
->stats
.tx_carrier_errors
++;
2330 if ((flags
& NV_TX2_RETRYERROR
) && !(flags
& NV_TX2_RETRYCOUNT_MASK
))
2331 nv_legacybackoff_reseed(dev
);
2332 dev
->stats
.tx_errors
++;
2334 dev
->stats
.tx_packets
++;
2335 dev
->stats
.tx_bytes
+= np
->get_tx_ctx
->skb
->len
;
2337 dev_kfree_skb_any(np
->get_tx_ctx
->skb
);
2338 np
->get_tx_ctx
->skb
= NULL
;
2341 if (unlikely(np
->get_tx
.orig
++ == np
->last_tx
.orig
))
2342 np
->get_tx
.orig
= np
->first_tx
.orig
;
2343 if (unlikely(np
->get_tx_ctx
++ == np
->last_tx_ctx
))
2344 np
->get_tx_ctx
= np
->first_tx_ctx
;
2346 if (unlikely((np
->tx_stop
== 1) && (np
->get_tx
.orig
!= orig_get_tx
))) {
2348 netif_wake_queue(dev
);
2352 static void nv_tx_done_optimized(struct net_device
*dev
, int limit
)
2354 struct fe_priv
*np
= netdev_priv(dev
);
2356 struct ring_desc_ex
* orig_get_tx
= np
->get_tx
.ex
;
2358 while ((np
->get_tx
.ex
!= np
->put_tx
.ex
) &&
2359 !((flags
= le32_to_cpu(np
->get_tx
.ex
->flaglen
)) & NV_TX_VALID
) &&
2362 dprintk(KERN_DEBUG
"%s: nv_tx_done_optimized: flags 0x%x.\n",
2365 pci_unmap_page(np
->pci_dev
, np
->get_tx_ctx
->dma
,
2366 np
->get_tx_ctx
->dma_len
,
2368 np
->get_tx_ctx
->dma
= 0;
2370 if (flags
& NV_TX2_LASTPACKET
) {
2371 if (!(flags
& NV_TX2_ERROR
))
2372 dev
->stats
.tx_packets
++;
2374 if ((flags
& NV_TX2_RETRYERROR
) && !(flags
& NV_TX2_RETRYCOUNT_MASK
)) {
2375 if (np
->driver_data
& DEV_HAS_GEAR_MODE
)
2376 nv_gear_backoff_reseed(dev
);
2378 nv_legacybackoff_reseed(dev
);
2382 dev_kfree_skb_any(np
->get_tx_ctx
->skb
);
2383 np
->get_tx_ctx
->skb
= NULL
;
2386 nv_tx_flip_ownership(dev
);
2389 if (unlikely(np
->get_tx
.ex
++ == np
->last_tx
.ex
))
2390 np
->get_tx
.ex
= np
->first_tx
.ex
;
2391 if (unlikely(np
->get_tx_ctx
++ == np
->last_tx_ctx
))
2392 np
->get_tx_ctx
= np
->first_tx_ctx
;
2394 if (unlikely((np
->tx_stop
== 1) && (np
->get_tx
.ex
!= orig_get_tx
))) {
2396 netif_wake_queue(dev
);
2401 * nv_tx_timeout: dev->tx_timeout function
2402 * Called with netif_tx_lock held.
2404 static void nv_tx_timeout(struct net_device
*dev
)
2406 struct fe_priv
*np
= netdev_priv(dev
);
2407 u8 __iomem
*base
= get_hwbase(dev
);
2410 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
2411 status
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
2413 status
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
2415 printk(KERN_INFO
"%s: Got tx_timeout. irq: %08x\n", dev
->name
, status
);
2420 printk(KERN_INFO
"%s: Ring at %lx\n",
2421 dev
->name
, (unsigned long)np
->ring_addr
);
2422 printk(KERN_INFO
"%s: Dumping tx registers\n", dev
->name
);
2423 for (i
=0;i
<=np
->register_size
;i
+= 32) {
2424 printk(KERN_INFO
"%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2426 readl(base
+ i
+ 0), readl(base
+ i
+ 4),
2427 readl(base
+ i
+ 8), readl(base
+ i
+ 12),
2428 readl(base
+ i
+ 16), readl(base
+ i
+ 20),
2429 readl(base
+ i
+ 24), readl(base
+ i
+ 28));
2431 printk(KERN_INFO
"%s: Dumping tx ring\n", dev
->name
);
2432 for (i
=0;i
<np
->tx_ring_size
;i
+= 4) {
2433 if (!nv_optimized(np
)) {
2434 printk(KERN_INFO
"%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2436 le32_to_cpu(np
->tx_ring
.orig
[i
].buf
),
2437 le32_to_cpu(np
->tx_ring
.orig
[i
].flaglen
),
2438 le32_to_cpu(np
->tx_ring
.orig
[i
+1].buf
),
2439 le32_to_cpu(np
->tx_ring
.orig
[i
+1].flaglen
),
2440 le32_to_cpu(np
->tx_ring
.orig
[i
+2].buf
),
2441 le32_to_cpu(np
->tx_ring
.orig
[i
+2].flaglen
),
2442 le32_to_cpu(np
->tx_ring
.orig
[i
+3].buf
),
2443 le32_to_cpu(np
->tx_ring
.orig
[i
+3].flaglen
));
2445 printk(KERN_INFO
"%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2447 le32_to_cpu(np
->tx_ring
.ex
[i
].bufhigh
),
2448 le32_to_cpu(np
->tx_ring
.ex
[i
].buflow
),
2449 le32_to_cpu(np
->tx_ring
.ex
[i
].flaglen
),
2450 le32_to_cpu(np
->tx_ring
.ex
[i
+1].bufhigh
),
2451 le32_to_cpu(np
->tx_ring
.ex
[i
+1].buflow
),
2452 le32_to_cpu(np
->tx_ring
.ex
[i
+1].flaglen
),
2453 le32_to_cpu(np
->tx_ring
.ex
[i
+2].bufhigh
),
2454 le32_to_cpu(np
->tx_ring
.ex
[i
+2].buflow
),
2455 le32_to_cpu(np
->tx_ring
.ex
[i
+2].flaglen
),
2456 le32_to_cpu(np
->tx_ring
.ex
[i
+3].bufhigh
),
2457 le32_to_cpu(np
->tx_ring
.ex
[i
+3].buflow
),
2458 le32_to_cpu(np
->tx_ring
.ex
[i
+3].flaglen
));
2463 spin_lock_irq(&np
->lock
);
2465 /* 1) stop tx engine */
2468 /* 2) check that the packets were not sent already: */
2469 if (!nv_optimized(np
))
2472 nv_tx_done_optimized(dev
, np
->tx_ring_size
);
2474 /* 3) if there are dead entries: clear everything */
2475 if (np
->get_tx_ctx
!= np
->put_tx_ctx
) {
2476 printk(KERN_DEBUG
"%s: tx_timeout: dead entries!\n", dev
->name
);
2479 setup_hw_rings(dev
, NV_SETUP_TX_RING
);
2482 netif_wake_queue(dev
);
2484 /* 4) restart tx engine */
2486 spin_unlock_irq(&np
->lock
);
2490 * Called when the nic notices a mismatch between the actual data len on the
2491 * wire and the len indicated in the 802 header
2493 static int nv_getlen(struct net_device
*dev
, void *packet
, int datalen
)
2495 int hdrlen
; /* length of the 802 header */
2496 int protolen
; /* length as stored in the proto field */
2498 /* 1) calculate len according to header */
2499 if ( ((struct vlan_ethhdr
*)packet
)->h_vlan_proto
== htons(ETH_P_8021Q
)) {
2500 protolen
= ntohs( ((struct vlan_ethhdr
*)packet
)->h_vlan_encapsulated_proto
);
2503 protolen
= ntohs( ((struct ethhdr
*)packet
)->h_proto
);
2506 dprintk(KERN_DEBUG
"%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2507 dev
->name
, datalen
, protolen
, hdrlen
);
2508 if (protolen
> ETH_DATA_LEN
)
2509 return datalen
; /* Value in proto field not a len, no checks possible */
2512 /* consistency checks: */
2513 if (datalen
> ETH_ZLEN
) {
2514 if (datalen
>= protolen
) {
2515 /* more data on wire than in 802 header, trim of
2518 dprintk(KERN_DEBUG
"%s: nv_getlen: accepting %d bytes.\n",
2519 dev
->name
, protolen
);
2522 /* less data on wire than mentioned in header.
2523 * Discard the packet.
2525 dprintk(KERN_DEBUG
"%s: nv_getlen: discarding long packet.\n",
2530 /* short packet. Accept only if 802 values are also short */
2531 if (protolen
> ETH_ZLEN
) {
2532 dprintk(KERN_DEBUG
"%s: nv_getlen: discarding short packet.\n",
2536 dprintk(KERN_DEBUG
"%s: nv_getlen: accepting %d bytes.\n",
2537 dev
->name
, datalen
);
2542 static int nv_rx_process(struct net_device
*dev
, int limit
)
2544 struct fe_priv
*np
= netdev_priv(dev
);
2547 struct sk_buff
*skb
;
2550 while((np
->get_rx
.orig
!= np
->put_rx
.orig
) &&
2551 !((flags
= le32_to_cpu(np
->get_rx
.orig
->flaglen
)) & NV_RX_AVAIL
) &&
2552 (rx_work
< limit
)) {
2554 dprintk(KERN_DEBUG
"%s: nv_rx_process: flags 0x%x.\n",
2558 * the packet is for us - immediately tear down the pci mapping.
2559 * TODO: check if a prefetch of the first cacheline improves
2562 pci_unmap_single(np
->pci_dev
, np
->get_rx_ctx
->dma
,
2563 np
->get_rx_ctx
->dma_len
,
2564 PCI_DMA_FROMDEVICE
);
2565 skb
= np
->get_rx_ctx
->skb
;
2566 np
->get_rx_ctx
->skb
= NULL
;
2570 dprintk(KERN_DEBUG
"Dumping packet (flags 0x%x).",flags
);
2571 for (j
=0; j
<64; j
++) {
2573 dprintk("\n%03x:", j
);
2574 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
2578 /* look at what we actually got: */
2579 if (np
->desc_ver
== DESC_VER_1
) {
2580 if (likely(flags
& NV_RX_DESCRIPTORVALID
)) {
2581 len
= flags
& LEN_MASK_V1
;
2582 if (unlikely(flags
& NV_RX_ERROR
)) {
2583 if (flags
& NV_RX_ERROR4
) {
2584 len
= nv_getlen(dev
, skb
->data
, len
);
2586 dev
->stats
.rx_errors
++;
2591 /* framing errors are soft errors */
2592 else if (flags
& NV_RX_FRAMINGERR
) {
2593 if (flags
& NV_RX_SUBSTRACT1
) {
2597 /* the rest are hard errors */
2599 if (flags
& NV_RX_MISSEDFRAME
)
2600 dev
->stats
.rx_missed_errors
++;
2601 if (flags
& NV_RX_CRCERR
)
2602 dev
->stats
.rx_crc_errors
++;
2603 if (flags
& NV_RX_OVERFLOW
)
2604 dev
->stats
.rx_over_errors
++;
2605 dev
->stats
.rx_errors
++;
2615 if (likely(flags
& NV_RX2_DESCRIPTORVALID
)) {
2616 len
= flags
& LEN_MASK_V2
;
2617 if (unlikely(flags
& NV_RX2_ERROR
)) {
2618 if (flags
& NV_RX2_ERROR4
) {
2619 len
= nv_getlen(dev
, skb
->data
, len
);
2621 dev
->stats
.rx_errors
++;
2626 /* framing errors are soft errors */
2627 else if (flags
& NV_RX2_FRAMINGERR
) {
2628 if (flags
& NV_RX2_SUBSTRACT1
) {
2632 /* the rest are hard errors */
2634 if (flags
& NV_RX2_CRCERR
)
2635 dev
->stats
.rx_crc_errors
++;
2636 if (flags
& NV_RX2_OVERFLOW
)
2637 dev
->stats
.rx_over_errors
++;
2638 dev
->stats
.rx_errors
++;
2643 if (((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_TCP
) || /*ip and tcp */
2644 ((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_UDP
)) /*ip and udp */
2645 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2651 /* got a valid packet - forward it to the network core */
2653 skb
->protocol
= eth_type_trans(skb
, dev
);
2654 dprintk(KERN_DEBUG
"%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2655 dev
->name
, len
, skb
->protocol
);
2656 #ifdef CONFIG_FORCEDETH_NAPI
2657 netif_receive_skb(skb
);
2661 dev
->last_rx
= jiffies
;
2662 dev
->stats
.rx_packets
++;
2663 dev
->stats
.rx_bytes
+= len
;
2665 if (unlikely(np
->get_rx
.orig
++ == np
->last_rx
.orig
))
2666 np
->get_rx
.orig
= np
->first_rx
.orig
;
2667 if (unlikely(np
->get_rx_ctx
++ == np
->last_rx_ctx
))
2668 np
->get_rx_ctx
= np
->first_rx_ctx
;
2676 static int nv_rx_process_optimized(struct net_device
*dev
, int limit
)
2678 struct fe_priv
*np
= netdev_priv(dev
);
2682 struct sk_buff
*skb
;
2685 while((np
->get_rx
.ex
!= np
->put_rx
.ex
) &&
2686 !((flags
= le32_to_cpu(np
->get_rx
.ex
->flaglen
)) & NV_RX2_AVAIL
) &&
2687 (rx_work
< limit
)) {
2689 dprintk(KERN_DEBUG
"%s: nv_rx_process_optimized: flags 0x%x.\n",
2693 * the packet is for us - immediately tear down the pci mapping.
2694 * TODO: check if a prefetch of the first cacheline improves
2697 pci_unmap_single(np
->pci_dev
, np
->get_rx_ctx
->dma
,
2698 np
->get_rx_ctx
->dma_len
,
2699 PCI_DMA_FROMDEVICE
);
2700 skb
= np
->get_rx_ctx
->skb
;
2701 np
->get_rx_ctx
->skb
= NULL
;
2705 dprintk(KERN_DEBUG
"Dumping packet (flags 0x%x).",flags
);
2706 for (j
=0; j
<64; j
++) {
2708 dprintk("\n%03x:", j
);
2709 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
2713 /* look at what we actually got: */
2714 if (likely(flags
& NV_RX2_DESCRIPTORVALID
)) {
2715 len
= flags
& LEN_MASK_V2
;
2716 if (unlikely(flags
& NV_RX2_ERROR
)) {
2717 if (flags
& NV_RX2_ERROR4
) {
2718 len
= nv_getlen(dev
, skb
->data
, len
);
2724 /* framing errors are soft errors */
2725 else if (flags
& NV_RX2_FRAMINGERR
) {
2726 if (flags
& NV_RX2_SUBSTRACT1
) {
2730 /* the rest are hard errors */
2737 if (((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_TCP
) || /*ip and tcp */
2738 ((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_UDP
)) /*ip and udp */
2739 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2741 /* got a valid packet - forward it to the network core */
2743 skb
->protocol
= eth_type_trans(skb
, dev
);
2744 prefetch(skb
->data
);
2746 dprintk(KERN_DEBUG
"%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2747 dev
->name
, len
, skb
->protocol
);
2749 if (likely(!np
->vlangrp
)) {
2750 #ifdef CONFIG_FORCEDETH_NAPI
2751 netif_receive_skb(skb
);
2756 vlanflags
= le32_to_cpu(np
->get_rx
.ex
->buflow
);
2757 if (vlanflags
& NV_RX3_VLAN_TAG_PRESENT
) {
2758 #ifdef CONFIG_FORCEDETH_NAPI
2759 vlan_hwaccel_receive_skb(skb
, np
->vlangrp
,
2760 vlanflags
& NV_RX3_VLAN_TAG_MASK
);
2762 vlan_hwaccel_rx(skb
, np
->vlangrp
,
2763 vlanflags
& NV_RX3_VLAN_TAG_MASK
);
2766 #ifdef CONFIG_FORCEDETH_NAPI
2767 netif_receive_skb(skb
);
2774 dev
->last_rx
= jiffies
;
2775 dev
->stats
.rx_packets
++;
2776 dev
->stats
.rx_bytes
+= len
;
2781 if (unlikely(np
->get_rx
.ex
++ == np
->last_rx
.ex
))
2782 np
->get_rx
.ex
= np
->first_rx
.ex
;
2783 if (unlikely(np
->get_rx_ctx
++ == np
->last_rx_ctx
))
2784 np
->get_rx_ctx
= np
->first_rx_ctx
;
2792 static void set_bufsize(struct net_device
*dev
)
2794 struct fe_priv
*np
= netdev_priv(dev
);
2796 if (dev
->mtu
<= ETH_DATA_LEN
)
2797 np
->rx_buf_sz
= ETH_DATA_LEN
+ NV_RX_HEADERS
;
2799 np
->rx_buf_sz
= dev
->mtu
+ NV_RX_HEADERS
;
2803 * nv_change_mtu: dev->change_mtu function
2804 * Called with dev_base_lock held for read.
2806 static int nv_change_mtu(struct net_device
*dev
, int new_mtu
)
2808 struct fe_priv
*np
= netdev_priv(dev
);
2811 if (new_mtu
< 64 || new_mtu
> np
->pkt_limit
)
2817 /* return early if the buffer sizes will not change */
2818 if (old_mtu
<= ETH_DATA_LEN
&& new_mtu
<= ETH_DATA_LEN
)
2820 if (old_mtu
== new_mtu
)
2823 /* synchronized against open : rtnl_lock() held by caller */
2824 if (netif_running(dev
)) {
2825 u8 __iomem
*base
= get_hwbase(dev
);
2827 * It seems that the nic preloads valid ring entries into an
2828 * internal buffer. The procedure for flushing everything is
2829 * guessed, there is probably a simpler approach.
2830 * Changing the MTU is a rare event, it shouldn't matter.
2832 nv_disable_irq(dev
);
2833 netif_tx_lock_bh(dev
);
2834 spin_lock(&np
->lock
);
2838 /* drain rx queue */
2840 /* reinit driver view of the rx queue */
2842 if (nv_init_ring(dev
)) {
2843 if (!np
->in_shutdown
)
2844 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
2846 /* reinit nic view of the rx queue */
2847 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
2848 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
2849 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
2850 base
+ NvRegRingSizes
);
2852 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2855 /* restart rx engine */
2857 spin_unlock(&np
->lock
);
2858 netif_tx_unlock_bh(dev
);
2864 static void nv_copy_mac_to_hw(struct net_device
*dev
)
2866 u8 __iomem
*base
= get_hwbase(dev
);
2869 mac
[0] = (dev
->dev_addr
[0] << 0) + (dev
->dev_addr
[1] << 8) +
2870 (dev
->dev_addr
[2] << 16) + (dev
->dev_addr
[3] << 24);
2871 mac
[1] = (dev
->dev_addr
[4] << 0) + (dev
->dev_addr
[5] << 8);
2873 writel(mac
[0], base
+ NvRegMacAddrA
);
2874 writel(mac
[1], base
+ NvRegMacAddrB
);
2878 * nv_set_mac_address: dev->set_mac_address function
2879 * Called with rtnl_lock() held.
2881 static int nv_set_mac_address(struct net_device
*dev
, void *addr
)
2883 struct fe_priv
*np
= netdev_priv(dev
);
2884 struct sockaddr
*macaddr
= (struct sockaddr
*)addr
;
2886 if (!is_valid_ether_addr(macaddr
->sa_data
))
2887 return -EADDRNOTAVAIL
;
2889 /* synchronized against open : rtnl_lock() held by caller */
2890 memcpy(dev
->dev_addr
, macaddr
->sa_data
, ETH_ALEN
);
2892 if (netif_running(dev
)) {
2893 netif_tx_lock_bh(dev
);
2894 spin_lock_irq(&np
->lock
);
2896 /* stop rx engine */
2899 /* set mac address */
2900 nv_copy_mac_to_hw(dev
);
2902 /* restart rx engine */
2904 spin_unlock_irq(&np
->lock
);
2905 netif_tx_unlock_bh(dev
);
2907 nv_copy_mac_to_hw(dev
);
2913 * nv_set_multicast: dev->set_multicast function
2914 * Called with netif_tx_lock held.
2916 static void nv_set_multicast(struct net_device
*dev
)
2918 struct fe_priv
*np
= netdev_priv(dev
);
2919 u8 __iomem
*base
= get_hwbase(dev
);
2922 u32 pff
= readl(base
+ NvRegPacketFilterFlags
) & NVREG_PFF_PAUSE_RX
;
2924 memset(addr
, 0, sizeof(addr
));
2925 memset(mask
, 0, sizeof(mask
));
2927 if (dev
->flags
& IFF_PROMISC
) {
2928 pff
|= NVREG_PFF_PROMISC
;
2930 pff
|= NVREG_PFF_MYADDR
;
2932 if (dev
->flags
& IFF_ALLMULTI
|| dev
->mc_list
) {
2936 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0xffffffff;
2937 if (dev
->flags
& IFF_ALLMULTI
) {
2938 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0;
2940 struct dev_mc_list
*walk
;
2942 walk
= dev
->mc_list
;
2943 while (walk
!= NULL
) {
2945 a
= le32_to_cpu(*(__le32
*) walk
->dmi_addr
);
2946 b
= le16_to_cpu(*(__le16
*) (&walk
->dmi_addr
[4]));
2954 addr
[0] = alwaysOn
[0];
2955 addr
[1] = alwaysOn
[1];
2956 mask
[0] = alwaysOn
[0] | alwaysOff
[0];
2957 mask
[1] = alwaysOn
[1] | alwaysOff
[1];
2959 mask
[0] = NVREG_MCASTMASKA_NONE
;
2960 mask
[1] = NVREG_MCASTMASKB_NONE
;
2963 addr
[0] |= NVREG_MCASTADDRA_FORCE
;
2964 pff
|= NVREG_PFF_ALWAYS
;
2965 spin_lock_irq(&np
->lock
);
2967 writel(addr
[0], base
+ NvRegMulticastAddrA
);
2968 writel(addr
[1], base
+ NvRegMulticastAddrB
);
2969 writel(mask
[0], base
+ NvRegMulticastMaskA
);
2970 writel(mask
[1], base
+ NvRegMulticastMaskB
);
2971 writel(pff
, base
+ NvRegPacketFilterFlags
);
2972 dprintk(KERN_INFO
"%s: reconfiguration for multicast lists.\n",
2975 spin_unlock_irq(&np
->lock
);
2978 static void nv_update_pause(struct net_device
*dev
, u32 pause_flags
)
2980 struct fe_priv
*np
= netdev_priv(dev
);
2981 u8 __iomem
*base
= get_hwbase(dev
);
2983 np
->pause_flags
&= ~(NV_PAUSEFRAME_TX_ENABLE
| NV_PAUSEFRAME_RX_ENABLE
);
2985 if (np
->pause_flags
& NV_PAUSEFRAME_RX_CAPABLE
) {
2986 u32 pff
= readl(base
+ NvRegPacketFilterFlags
) & ~NVREG_PFF_PAUSE_RX
;
2987 if (pause_flags
& NV_PAUSEFRAME_RX_ENABLE
) {
2988 writel(pff
|NVREG_PFF_PAUSE_RX
, base
+ NvRegPacketFilterFlags
);
2989 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
2991 writel(pff
, base
+ NvRegPacketFilterFlags
);
2994 if (np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
) {
2995 u32 regmisc
= readl(base
+ NvRegMisc1
) & ~NVREG_MISC1_PAUSE_TX
;
2996 if (pause_flags
& NV_PAUSEFRAME_TX_ENABLE
) {
2997 u32 pause_enable
= NVREG_TX_PAUSEFRAME_ENABLE_V1
;
2998 if (np
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V2
)
2999 pause_enable
= NVREG_TX_PAUSEFRAME_ENABLE_V2
;
3000 if (np
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V3
)
3001 pause_enable
= NVREG_TX_PAUSEFRAME_ENABLE_V3
;
3002 writel(pause_enable
, base
+ NvRegTxPauseFrame
);
3003 writel(regmisc
|NVREG_MISC1_PAUSE_TX
, base
+ NvRegMisc1
);
3004 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3006 writel(NVREG_TX_PAUSEFRAME_DISABLE
, base
+ NvRegTxPauseFrame
);
3007 writel(regmisc
, base
+ NvRegMisc1
);
3013 * nv_update_linkspeed: Setup the MAC according to the link partner
3014 * @dev: Network device to be configured
3016 * The function queries the PHY and checks if there is a link partner.
3017 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3018 * set to 10 MBit HD.
3020 * The function returns 0 if there is no link partner and 1 if there is
3021 * a good link partner.
3023 static int nv_update_linkspeed(struct net_device
*dev
)
3025 struct fe_priv
*np
= netdev_priv(dev
);
3026 u8 __iomem
*base
= get_hwbase(dev
);
3029 int adv_lpa
, adv_pause
, lpa_pause
;
3030 int newls
= np
->linkspeed
;
3031 int newdup
= np
->duplex
;
3034 u32 control_1000
, status_1000
, phyreg
, pause_flags
, txreg
;
3038 /* BMSR_LSTATUS is latched, read it twice:
3039 * we want the current value.
3041 mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
3042 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
3044 if (!(mii_status
& BMSR_LSTATUS
)) {
3045 dprintk(KERN_DEBUG
"%s: no link detected by phy - falling back to 10HD.\n",
3047 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3053 if (np
->autoneg
== 0) {
3054 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3055 dev
->name
, np
->fixed_mode
);
3056 if (np
->fixed_mode
& LPA_100FULL
) {
3057 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3059 } else if (np
->fixed_mode
& LPA_100HALF
) {
3060 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3062 } else if (np
->fixed_mode
& LPA_10FULL
) {
3063 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3066 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3072 /* check auto negotiation is complete */
3073 if (!(mii_status
& BMSR_ANEGCOMPLETE
)) {
3074 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3075 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3078 dprintk(KERN_DEBUG
"%s: autoneg not completed - falling back to 10HD.\n", dev
->name
);
3082 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
3083 lpa
= mii_rw(dev
, np
->phyaddr
, MII_LPA
, MII_READ
);
3084 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3085 dev
->name
, adv
, lpa
);
3088 if (np
->gigabit
== PHY_GIGABIT
) {
3089 control_1000
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
3090 status_1000
= mii_rw(dev
, np
->phyaddr
, MII_STAT1000
, MII_READ
);
3092 if ((control_1000
& ADVERTISE_1000FULL
) &&
3093 (status_1000
& LPA_1000FULL
)) {
3094 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: GBit ethernet detected.\n",
3096 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_1000
;
3102 /* FIXME: handle parallel detection properly */
3103 adv_lpa
= lpa
& adv
;
3104 if (adv_lpa
& LPA_100FULL
) {
3105 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3107 } else if (adv_lpa
& LPA_100HALF
) {
3108 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3110 } else if (adv_lpa
& LPA_10FULL
) {
3111 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3113 } else if (adv_lpa
& LPA_10HALF
) {
3114 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3117 dprintk(KERN_DEBUG
"%s: bad ability %04x - falling back to 10HD.\n", dev
->name
, adv_lpa
);
3118 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3123 if (np
->duplex
== newdup
&& np
->linkspeed
== newls
)
3126 dprintk(KERN_INFO
"%s: changing link setting from %d/%d to %d/%d.\n",
3127 dev
->name
, np
->linkspeed
, np
->duplex
, newls
, newdup
);
3129 np
->duplex
= newdup
;
3130 np
->linkspeed
= newls
;
3132 /* The transmitter and receiver must be restarted for safe update */
3133 if (readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_START
) {
3134 txrxFlags
|= NV_RESTART_TX
;
3137 if (readl(base
+ NvRegReceiverControl
) & NVREG_RCVCTL_START
) {
3138 txrxFlags
|= NV_RESTART_RX
;
3142 if (np
->gigabit
== PHY_GIGABIT
) {
3143 phyreg
= readl(base
+ NvRegSlotTime
);
3144 phyreg
&= ~(0x3FF00);
3145 if (((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_10
) ||
3146 ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_100
))
3147 phyreg
|= NVREG_SLOTTIME_10_100_FULL
;
3148 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_1000
)
3149 phyreg
|= NVREG_SLOTTIME_1000_FULL
;
3150 writel(phyreg
, base
+ NvRegSlotTime
);
3153 phyreg
= readl(base
+ NvRegPhyInterface
);
3154 phyreg
&= ~(PHY_HALF
|PHY_100
|PHY_1000
);
3155 if (np
->duplex
== 0)
3157 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_100
)
3159 else if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
3161 writel(phyreg
, base
+ NvRegPhyInterface
);
3163 phy_exp
= mii_rw(dev
, np
->phyaddr
, MII_EXPANSION
, MII_READ
) & EXPANSION_NWAY
; /* autoneg capable */
3164 if (phyreg
& PHY_RGMII
) {
3165 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
) {
3166 txreg
= NVREG_TX_DEFERRAL_RGMII_1000
;
3168 if (!phy_exp
&& !np
->duplex
&& (np
->driver_data
& DEV_HAS_COLLISION_FIX
)) {
3169 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_10
)
3170 txreg
= NVREG_TX_DEFERRAL_RGMII_STRETCH_10
;
3172 txreg
= NVREG_TX_DEFERRAL_RGMII_STRETCH_100
;
3174 txreg
= NVREG_TX_DEFERRAL_RGMII_10_100
;
3178 if (!phy_exp
&& !np
->duplex
&& (np
->driver_data
& DEV_HAS_COLLISION_FIX
))
3179 txreg
= NVREG_TX_DEFERRAL_MII_STRETCH
;
3181 txreg
= NVREG_TX_DEFERRAL_DEFAULT
;
3183 writel(txreg
, base
+ NvRegTxDeferral
);
3185 if (np
->desc_ver
== DESC_VER_1
) {
3186 txreg
= NVREG_TX_WM_DESC1_DEFAULT
;
3188 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
3189 txreg
= NVREG_TX_WM_DESC2_3_1000
;
3191 txreg
= NVREG_TX_WM_DESC2_3_DEFAULT
;
3193 writel(txreg
, base
+ NvRegTxWatermark
);
3195 writel(NVREG_MISC1_FORCE
| ( np
->duplex
? 0 : NVREG_MISC1_HD
),
3198 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
3202 /* setup pause frame */
3203 if (np
->duplex
!= 0) {
3204 if (np
->autoneg
&& np
->pause_flags
& NV_PAUSEFRAME_AUTONEG
) {
3205 adv_pause
= adv
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
3206 lpa_pause
= lpa
& (LPA_PAUSE_CAP
| LPA_PAUSE_ASYM
);
3208 switch (adv_pause
) {
3209 case ADVERTISE_PAUSE_CAP
:
3210 if (lpa_pause
& LPA_PAUSE_CAP
) {
3211 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3212 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
3213 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3216 case ADVERTISE_PAUSE_ASYM
:
3217 if (lpa_pause
== (LPA_PAUSE_CAP
| LPA_PAUSE_ASYM
))
3219 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3222 case ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
:
3223 if (lpa_pause
& LPA_PAUSE_CAP
)
3225 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3226 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
3227 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3229 if (lpa_pause
== LPA_PAUSE_ASYM
)
3231 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3236 pause_flags
= np
->pause_flags
;
3239 nv_update_pause(dev
, pause_flags
);
3241 if (txrxFlags
& NV_RESTART_TX
)
3243 if (txrxFlags
& NV_RESTART_RX
)
3249 static void nv_linkchange(struct net_device
*dev
)
3251 if (nv_update_linkspeed(dev
)) {
3252 if (!netif_carrier_ok(dev
)) {
3253 netif_carrier_on(dev
);
3254 printk(KERN_INFO
"%s: link up.\n", dev
->name
);
3258 if (netif_carrier_ok(dev
)) {
3259 netif_carrier_off(dev
);
3260 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
3266 static void nv_link_irq(struct net_device
*dev
)
3268 u8 __iomem
*base
= get_hwbase(dev
);
3271 miistat
= readl(base
+ NvRegMIIStatus
);
3272 writel(NVREG_MIISTAT_LINKCHANGE
, base
+ NvRegMIIStatus
);
3273 dprintk(KERN_INFO
"%s: link change irq, status 0x%x.\n", dev
->name
, miistat
);
3275 if (miistat
& (NVREG_MIISTAT_LINKCHANGE
))
3277 dprintk(KERN_DEBUG
"%s: link change notification done.\n", dev
->name
);
3280 static void nv_msi_workaround(struct fe_priv
*np
)
3283 /* Need to toggle the msi irq mask within the ethernet device,
3284 * otherwise, future interrupts will not be detected.
3286 if (np
->msi_flags
& NV_MSI_ENABLED
) {
3287 u8 __iomem
*base
= np
->base
;
3289 writel(0, base
+ NvRegMSIIrqMask
);
3290 writel(NVREG_MSI_VECTOR_0_ENABLED
, base
+ NvRegMSIIrqMask
);
3294 static irqreturn_t
nv_nic_irq(int foo
, void *data
)
3296 struct net_device
*dev
= (struct net_device
*) data
;
3297 struct fe_priv
*np
= netdev_priv(dev
);
3298 u8 __iomem
*base
= get_hwbase(dev
);
3302 dprintk(KERN_DEBUG
"%s: nv_nic_irq\n", dev
->name
);
3305 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
3306 events
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
3307 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
3309 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
3310 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
3312 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
3313 if (!(events
& np
->irqmask
))
3316 nv_msi_workaround(np
);
3318 spin_lock(&np
->lock
);
3320 spin_unlock(&np
->lock
);
3322 #ifdef CONFIG_FORCEDETH_NAPI
3323 if (events
& NVREG_IRQ_RX_ALL
) {
3324 netif_rx_schedule(dev
, &np
->napi
);
3326 /* Disable furthur receive irq's */
3327 spin_lock(&np
->lock
);
3328 np
->irqmask
&= ~NVREG_IRQ_RX_ALL
;
3330 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
3331 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
3333 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3334 spin_unlock(&np
->lock
);
3337 if (nv_rx_process(dev
, RX_WORK_PER_LOOP
)) {
3338 if (unlikely(nv_alloc_rx(dev
))) {
3339 spin_lock(&np
->lock
);
3340 if (!np
->in_shutdown
)
3341 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3342 spin_unlock(&np
->lock
);
3346 if (unlikely(events
& NVREG_IRQ_LINK
)) {
3347 spin_lock(&np
->lock
);
3349 spin_unlock(&np
->lock
);
3351 if (unlikely(np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
))) {
3352 spin_lock(&np
->lock
);
3354 spin_unlock(&np
->lock
);
3355 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
3357 if (unlikely(events
& (NVREG_IRQ_TX_ERR
))) {
3358 dprintk(KERN_DEBUG
"%s: received irq with events 0x%x. Probably TX fail.\n",
3361 if (unlikely(events
& (NVREG_IRQ_UNKNOWN
))) {
3362 printk(KERN_DEBUG
"%s: received irq with unknown events 0x%x. Please report\n",
3365 if (unlikely(events
& NVREG_IRQ_RECOVER_ERROR
)) {
3366 spin_lock(&np
->lock
);
3367 /* disable interrupts on the nic */
3368 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
3369 writel(0, base
+ NvRegIrqMask
);
3371 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3374 if (!np
->in_shutdown
) {
3375 np
->nic_poll_irq
= np
->irqmask
;
3376 np
->recover_error
= 1;
3377 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3379 spin_unlock(&np
->lock
);
3382 if (unlikely(i
> max_interrupt_work
)) {
3383 spin_lock(&np
->lock
);
3384 /* disable interrupts on the nic */
3385 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
3386 writel(0, base
+ NvRegIrqMask
);
3388 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3391 if (!np
->in_shutdown
) {
3392 np
->nic_poll_irq
= np
->irqmask
;
3393 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3395 spin_unlock(&np
->lock
);
3396 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq.\n", dev
->name
, i
);
3401 dprintk(KERN_DEBUG
"%s: nv_nic_irq completed\n", dev
->name
);
3403 return IRQ_RETVAL(i
);
3407 * All _optimized functions are used to help increase performance
3408 * (reduce CPU and increase throughput). They use descripter version 3,
3409 * compiler directives, and reduce memory accesses.
3411 static irqreturn_t
nv_nic_irq_optimized(int foo
, void *data
)
3413 struct net_device
*dev
= (struct net_device
*) data
;
3414 struct fe_priv
*np
= netdev_priv(dev
);
3415 u8 __iomem
*base
= get_hwbase(dev
);
3419 dprintk(KERN_DEBUG
"%s: nv_nic_irq_optimized\n", dev
->name
);
3422 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
3423 events
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
3424 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
3426 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
3427 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
3429 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
3430 if (!(events
& np
->irqmask
))
3433 nv_msi_workaround(np
);
3435 spin_lock(&np
->lock
);
3436 nv_tx_done_optimized(dev
, TX_WORK_PER_LOOP
);
3437 spin_unlock(&np
->lock
);
3439 #ifdef CONFIG_FORCEDETH_NAPI
3440 if (events
& NVREG_IRQ_RX_ALL
) {
3441 netif_rx_schedule(dev
, &np
->napi
);
3443 /* Disable furthur receive irq's */
3444 spin_lock(&np
->lock
);
3445 np
->irqmask
&= ~NVREG_IRQ_RX_ALL
;
3447 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
3448 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
3450 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3451 spin_unlock(&np
->lock
);
3454 if (nv_rx_process_optimized(dev
, RX_WORK_PER_LOOP
)) {
3455 if (unlikely(nv_alloc_rx_optimized(dev
))) {
3456 spin_lock(&np
->lock
);
3457 if (!np
->in_shutdown
)
3458 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3459 spin_unlock(&np
->lock
);
3463 if (unlikely(events
& NVREG_IRQ_LINK
)) {
3464 spin_lock(&np
->lock
);
3466 spin_unlock(&np
->lock
);
3468 if (unlikely(np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
))) {
3469 spin_lock(&np
->lock
);
3471 spin_unlock(&np
->lock
);
3472 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
3474 if (unlikely(events
& (NVREG_IRQ_TX_ERR
))) {
3475 dprintk(KERN_DEBUG
"%s: received irq with events 0x%x. Probably TX fail.\n",
3478 if (unlikely(events
& (NVREG_IRQ_UNKNOWN
))) {
3479 printk(KERN_DEBUG
"%s: received irq with unknown events 0x%x. Please report\n",
3482 if (unlikely(events
& NVREG_IRQ_RECOVER_ERROR
)) {
3483 spin_lock(&np
->lock
);
3484 /* disable interrupts on the nic */
3485 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
3486 writel(0, base
+ NvRegIrqMask
);
3488 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3491 if (!np
->in_shutdown
) {
3492 np
->nic_poll_irq
= np
->irqmask
;
3493 np
->recover_error
= 1;
3494 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3496 spin_unlock(&np
->lock
);
3500 if (unlikely(i
> max_interrupt_work
)) {
3501 spin_lock(&np
->lock
);
3502 /* disable interrupts on the nic */
3503 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
3504 writel(0, base
+ NvRegIrqMask
);
3506 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3509 if (!np
->in_shutdown
) {
3510 np
->nic_poll_irq
= np
->irqmask
;
3511 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3513 spin_unlock(&np
->lock
);
3514 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq.\n", dev
->name
, i
);
3519 dprintk(KERN_DEBUG
"%s: nv_nic_irq_optimized completed\n", dev
->name
);
3521 return IRQ_RETVAL(i
);
3524 static irqreturn_t
nv_nic_irq_tx(int foo
, void *data
)
3526 struct net_device
*dev
= (struct net_device
*) data
;
3527 struct fe_priv
*np
= netdev_priv(dev
);
3528 u8 __iomem
*base
= get_hwbase(dev
);
3531 unsigned long flags
;
3533 dprintk(KERN_DEBUG
"%s: nv_nic_irq_tx\n", dev
->name
);
3536 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_TX_ALL
;
3537 writel(NVREG_IRQ_TX_ALL
, base
+ NvRegMSIXIrqStatus
);
3538 dprintk(KERN_DEBUG
"%s: tx irq: %08x\n", dev
->name
, events
);
3539 if (!(events
& np
->irqmask
))
3542 spin_lock_irqsave(&np
->lock
, flags
);
3543 nv_tx_done_optimized(dev
, TX_WORK_PER_LOOP
);
3544 spin_unlock_irqrestore(&np
->lock
, flags
);
3546 if (unlikely(events
& (NVREG_IRQ_TX_ERR
))) {
3547 dprintk(KERN_DEBUG
"%s: received irq with events 0x%x. Probably TX fail.\n",
3550 if (unlikely(i
> max_interrupt_work
)) {
3551 spin_lock_irqsave(&np
->lock
, flags
);
3552 /* disable interrupts on the nic */
3553 writel(NVREG_IRQ_TX_ALL
, base
+ NvRegIrqMask
);
3556 if (!np
->in_shutdown
) {
3557 np
->nic_poll_irq
|= NVREG_IRQ_TX_ALL
;
3558 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3560 spin_unlock_irqrestore(&np
->lock
, flags
);
3561 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev
->name
, i
);
3566 dprintk(KERN_DEBUG
"%s: nv_nic_irq_tx completed\n", dev
->name
);
3568 return IRQ_RETVAL(i
);
3571 #ifdef CONFIG_FORCEDETH_NAPI
3572 static int nv_napi_poll(struct napi_struct
*napi
, int budget
)
3574 struct fe_priv
*np
= container_of(napi
, struct fe_priv
, napi
);
3575 struct net_device
*dev
= np
->dev
;
3576 u8 __iomem
*base
= get_hwbase(dev
);
3577 unsigned long flags
;
3580 if (!nv_optimized(np
)) {
3581 pkts
= nv_rx_process(dev
, budget
);
3582 retcode
= nv_alloc_rx(dev
);
3584 pkts
= nv_rx_process_optimized(dev
, budget
);
3585 retcode
= nv_alloc_rx_optimized(dev
);
3589 spin_lock_irqsave(&np
->lock
, flags
);
3590 if (!np
->in_shutdown
)
3591 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3592 spin_unlock_irqrestore(&np
->lock
, flags
);
3595 if (pkts
< budget
) {
3596 /* re-enable receive interrupts */
3597 spin_lock_irqsave(&np
->lock
, flags
);
3599 __netif_rx_complete(dev
, napi
);
3601 np
->irqmask
|= NVREG_IRQ_RX_ALL
;
3602 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
3603 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
3605 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3607 spin_unlock_irqrestore(&np
->lock
, flags
);
3613 #ifdef CONFIG_FORCEDETH_NAPI
3614 static irqreturn_t
nv_nic_irq_rx(int foo
, void *data
)
3616 struct net_device
*dev
= (struct net_device
*) data
;
3617 struct fe_priv
*np
= netdev_priv(dev
);
3618 u8 __iomem
*base
= get_hwbase(dev
);
3621 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_RX_ALL
;
3622 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegMSIXIrqStatus
);
3625 netif_rx_schedule(dev
, &np
->napi
);
3626 /* disable receive interrupts on the nic */
3627 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
3633 static irqreturn_t
nv_nic_irq_rx(int foo
, void *data
)
3635 struct net_device
*dev
= (struct net_device
*) data
;
3636 struct fe_priv
*np
= netdev_priv(dev
);
3637 u8 __iomem
*base
= get_hwbase(dev
);
3640 unsigned long flags
;
3642 dprintk(KERN_DEBUG
"%s: nv_nic_irq_rx\n", dev
->name
);
3645 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_RX_ALL
;
3646 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegMSIXIrqStatus
);
3647 dprintk(KERN_DEBUG
"%s: rx irq: %08x\n", dev
->name
, events
);
3648 if (!(events
& np
->irqmask
))
3651 if (nv_rx_process_optimized(dev
, RX_WORK_PER_LOOP
)) {
3652 if (unlikely(nv_alloc_rx_optimized(dev
))) {
3653 spin_lock_irqsave(&np
->lock
, flags
);
3654 if (!np
->in_shutdown
)
3655 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3656 spin_unlock_irqrestore(&np
->lock
, flags
);
3660 if (unlikely(i
> max_interrupt_work
)) {
3661 spin_lock_irqsave(&np
->lock
, flags
);
3662 /* disable interrupts on the nic */
3663 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
3666 if (!np
->in_shutdown
) {
3667 np
->nic_poll_irq
|= NVREG_IRQ_RX_ALL
;
3668 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3670 spin_unlock_irqrestore(&np
->lock
, flags
);
3671 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev
->name
, i
);
3675 dprintk(KERN_DEBUG
"%s: nv_nic_irq_rx completed\n", dev
->name
);
3677 return IRQ_RETVAL(i
);
3681 static irqreturn_t
nv_nic_irq_other(int foo
, void *data
)
3683 struct net_device
*dev
= (struct net_device
*) data
;
3684 struct fe_priv
*np
= netdev_priv(dev
);
3685 u8 __iomem
*base
= get_hwbase(dev
);
3688 unsigned long flags
;
3690 dprintk(KERN_DEBUG
"%s: nv_nic_irq_other\n", dev
->name
);
3693 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_OTHER
;
3694 writel(NVREG_IRQ_OTHER
, base
+ NvRegMSIXIrqStatus
);
3695 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
3696 if (!(events
& np
->irqmask
))
3699 /* check tx in case we reached max loop limit in tx isr */
3700 spin_lock_irqsave(&np
->lock
, flags
);
3701 nv_tx_done_optimized(dev
, TX_WORK_PER_LOOP
);
3702 spin_unlock_irqrestore(&np
->lock
, flags
);
3704 if (events
& NVREG_IRQ_LINK
) {
3705 spin_lock_irqsave(&np
->lock
, flags
);
3707 spin_unlock_irqrestore(&np
->lock
, flags
);
3709 if (np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
)) {
3710 spin_lock_irqsave(&np
->lock
, flags
);
3712 spin_unlock_irqrestore(&np
->lock
, flags
);
3713 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
3715 if (events
& NVREG_IRQ_RECOVER_ERROR
) {
3716 spin_lock_irq(&np
->lock
);
3717 /* disable interrupts on the nic */
3718 writel(NVREG_IRQ_OTHER
, base
+ NvRegIrqMask
);
3721 if (!np
->in_shutdown
) {
3722 np
->nic_poll_irq
|= NVREG_IRQ_OTHER
;
3723 np
->recover_error
= 1;
3724 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3726 spin_unlock_irq(&np
->lock
);
3729 if (events
& (NVREG_IRQ_UNKNOWN
)) {
3730 printk(KERN_DEBUG
"%s: received irq with unknown events 0x%x. Please report\n",
3733 if (unlikely(i
> max_interrupt_work
)) {
3734 spin_lock_irqsave(&np
->lock
, flags
);
3735 /* disable interrupts on the nic */
3736 writel(NVREG_IRQ_OTHER
, base
+ NvRegIrqMask
);
3739 if (!np
->in_shutdown
) {
3740 np
->nic_poll_irq
|= NVREG_IRQ_OTHER
;
3741 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3743 spin_unlock_irqrestore(&np
->lock
, flags
);
3744 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_other.\n", dev
->name
, i
);
3749 dprintk(KERN_DEBUG
"%s: nv_nic_irq_other completed\n", dev
->name
);
3751 return IRQ_RETVAL(i
);
3754 static irqreturn_t
nv_nic_irq_test(int foo
, void *data
)
3756 struct net_device
*dev
= (struct net_device
*) data
;
3757 struct fe_priv
*np
= netdev_priv(dev
);
3758 u8 __iomem
*base
= get_hwbase(dev
);
3761 dprintk(KERN_DEBUG
"%s: nv_nic_irq_test\n", dev
->name
);
3763 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
3764 events
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
3765 writel(NVREG_IRQ_TIMER
, base
+ NvRegIrqStatus
);
3767 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
3768 writel(NVREG_IRQ_TIMER
, base
+ NvRegMSIXIrqStatus
);
3771 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
3772 if (!(events
& NVREG_IRQ_TIMER
))
3773 return IRQ_RETVAL(0);
3775 nv_msi_workaround(np
);
3777 spin_lock(&np
->lock
);
3779 spin_unlock(&np
->lock
);
3781 dprintk(KERN_DEBUG
"%s: nv_nic_irq_test completed\n", dev
->name
);
3783 return IRQ_RETVAL(1);
3786 static void set_msix_vector_map(struct net_device
*dev
, u32 vector
, u32 irqmask
)
3788 u8 __iomem
*base
= get_hwbase(dev
);
3792 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3793 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3794 * the remaining 8 interrupts.
3796 for (i
= 0; i
< 8; i
++) {
3797 if ((irqmask
>> i
) & 0x1) {
3798 msixmap
|= vector
<< (i
<< 2);
3801 writel(readl(base
+ NvRegMSIXMap0
) | msixmap
, base
+ NvRegMSIXMap0
);
3804 for (i
= 0; i
< 8; i
++) {
3805 if ((irqmask
>> (i
+ 8)) & 0x1) {
3806 msixmap
|= vector
<< (i
<< 2);
3809 writel(readl(base
+ NvRegMSIXMap1
) | msixmap
, base
+ NvRegMSIXMap1
);
3812 static int nv_request_irq(struct net_device
*dev
, int intr_test
)
3814 struct fe_priv
*np
= get_nvpriv(dev
);
3815 u8 __iomem
*base
= get_hwbase(dev
);
3818 irqreturn_t (*handler
)(int foo
, void *data
);
3821 handler
= nv_nic_irq_test
;
3823 if (nv_optimized(np
))
3824 handler
= nv_nic_irq_optimized
;
3826 handler
= nv_nic_irq
;
3829 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) {
3830 for (i
= 0; i
< (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
); i
++) {
3831 np
->msi_x_entry
[i
].entry
= i
;
3833 if ((ret
= pci_enable_msix(np
->pci_dev
, np
->msi_x_entry
, (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
))) == 0) {
3834 np
->msi_flags
|= NV_MSI_X_ENABLED
;
3835 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
&& !intr_test
) {
3836 /* Request irq for rx handling */
3837 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
, &nv_nic_irq_rx
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
3838 printk(KERN_INFO
"forcedeth: request_irq failed for rx %d\n", ret
);
3839 pci_disable_msix(np
->pci_dev
);
3840 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
3843 /* Request irq for tx handling */
3844 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
, &nv_nic_irq_tx
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
3845 printk(KERN_INFO
"forcedeth: request_irq failed for tx %d\n", ret
);
3846 pci_disable_msix(np
->pci_dev
);
3847 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
3850 /* Request irq for link and timer handling */
3851 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
, &nv_nic_irq_other
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
3852 printk(KERN_INFO
"forcedeth: request_irq failed for link %d\n", ret
);
3853 pci_disable_msix(np
->pci_dev
);
3854 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
3857 /* map interrupts to their respective vector */
3858 writel(0, base
+ NvRegMSIXMap0
);
3859 writel(0, base
+ NvRegMSIXMap1
);
3860 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_RX
, NVREG_IRQ_RX_ALL
);
3861 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_TX
, NVREG_IRQ_TX_ALL
);
3862 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_OTHER
, NVREG_IRQ_OTHER
);
3864 /* Request irq for all interrupts */
3865 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
, handler
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
3866 printk(KERN_INFO
"forcedeth: request_irq failed %d\n", ret
);
3867 pci_disable_msix(np
->pci_dev
);
3868 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
3872 /* map interrupts to vector 0 */
3873 writel(0, base
+ NvRegMSIXMap0
);
3874 writel(0, base
+ NvRegMSIXMap1
);
3878 if (ret
!= 0 && np
->msi_flags
& NV_MSI_CAPABLE
) {
3879 if ((ret
= pci_enable_msi(np
->pci_dev
)) == 0) {
3880 np
->msi_flags
|= NV_MSI_ENABLED
;
3881 dev
->irq
= np
->pci_dev
->irq
;
3882 if (request_irq(np
->pci_dev
->irq
, handler
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
3883 printk(KERN_INFO
"forcedeth: request_irq failed %d\n", ret
);
3884 pci_disable_msi(np
->pci_dev
);
3885 np
->msi_flags
&= ~NV_MSI_ENABLED
;
3886 dev
->irq
= np
->pci_dev
->irq
;
3890 /* map interrupts to vector 0 */
3891 writel(0, base
+ NvRegMSIMap0
);
3892 writel(0, base
+ NvRegMSIMap1
);
3893 /* enable msi vector 0 */
3894 writel(NVREG_MSI_VECTOR_0_ENABLED
, base
+ NvRegMSIIrqMask
);
3898 if (request_irq(np
->pci_dev
->irq
, handler
, IRQF_SHARED
, dev
->name
, dev
) != 0)
3905 free_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
, dev
);
3907 free_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
, dev
);
3912 static void nv_free_irq(struct net_device
*dev
)
3914 struct fe_priv
*np
= get_nvpriv(dev
);
3917 if (np
->msi_flags
& NV_MSI_X_ENABLED
) {
3918 for (i
= 0; i
< (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
); i
++) {
3919 free_irq(np
->msi_x_entry
[i
].vector
, dev
);
3921 pci_disable_msix(np
->pci_dev
);
3922 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
3924 free_irq(np
->pci_dev
->irq
, dev
);
3925 if (np
->msi_flags
& NV_MSI_ENABLED
) {
3926 pci_disable_msi(np
->pci_dev
);
3927 np
->msi_flags
&= ~NV_MSI_ENABLED
;
3932 static void nv_do_nic_poll(unsigned long data
)
3934 struct net_device
*dev
= (struct net_device
*) data
;
3935 struct fe_priv
*np
= netdev_priv(dev
);
3936 u8 __iomem
*base
= get_hwbase(dev
);
3940 * First disable irq(s) and then
3941 * reenable interrupts on the nic, we have to do this before calling
3942 * nv_nic_irq because that may decide to do otherwise
3945 if (!using_multi_irqs(dev
)) {
3946 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
3947 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
3949 disable_irq_lockdep(np
->pci_dev
->irq
);
3952 if (np
->nic_poll_irq
& NVREG_IRQ_RX_ALL
) {
3953 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
3954 mask
|= NVREG_IRQ_RX_ALL
;
3956 if (np
->nic_poll_irq
& NVREG_IRQ_TX_ALL
) {
3957 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
3958 mask
|= NVREG_IRQ_TX_ALL
;
3960 if (np
->nic_poll_irq
& NVREG_IRQ_OTHER
) {
3961 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
3962 mask
|= NVREG_IRQ_OTHER
;
3965 np
->nic_poll_irq
= 0;
3967 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3969 if (np
->recover_error
) {
3970 np
->recover_error
= 0;
3971 printk(KERN_INFO
"forcedeth: MAC in recoverable error state\n");
3972 if (netif_running(dev
)) {
3973 netif_tx_lock_bh(dev
);
3974 spin_lock(&np
->lock
);
3978 /* drain rx queue */
3980 /* reinit driver view of the rx queue */
3982 if (nv_init_ring(dev
)) {
3983 if (!np
->in_shutdown
)
3984 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3986 /* reinit nic view of the rx queue */
3987 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
3988 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
3989 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
3990 base
+ NvRegRingSizes
);
3992 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
3995 /* restart rx engine */
3997 spin_unlock(&np
->lock
);
3998 netif_tx_unlock_bh(dev
);
4003 writel(mask
, base
+ NvRegIrqMask
);
4006 if (!using_multi_irqs(dev
)) {
4007 if (nv_optimized(np
))
4008 nv_nic_irq_optimized(0, dev
);
4011 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
4012 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
4014 enable_irq_lockdep(np
->pci_dev
->irq
);
4016 if (np
->nic_poll_irq
& NVREG_IRQ_RX_ALL
) {
4017 nv_nic_irq_rx(0, dev
);
4018 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
4020 if (np
->nic_poll_irq
& NVREG_IRQ_TX_ALL
) {
4021 nv_nic_irq_tx(0, dev
);
4022 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
4024 if (np
->nic_poll_irq
& NVREG_IRQ_OTHER
) {
4025 nv_nic_irq_other(0, dev
);
4026 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
4031 #ifdef CONFIG_NET_POLL_CONTROLLER
4032 static void nv_poll_controller(struct net_device
*dev
)
4034 nv_do_nic_poll((unsigned long) dev
);
4038 static void nv_do_stats_poll(unsigned long data
)
4040 struct net_device
*dev
= (struct net_device
*) data
;
4041 struct fe_priv
*np
= netdev_priv(dev
);
4043 nv_get_hw_stats(dev
);
4045 if (!np
->in_shutdown
)
4046 mod_timer(&np
->stats_poll
,
4047 round_jiffies(jiffies
+ STATS_INTERVAL
));
4050 static void nv_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
4052 struct fe_priv
*np
= netdev_priv(dev
);
4053 strcpy(info
->driver
, DRV_NAME
);
4054 strcpy(info
->version
, FORCEDETH_VERSION
);
4055 strcpy(info
->bus_info
, pci_name(np
->pci_dev
));
4058 static void nv_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
4060 struct fe_priv
*np
= netdev_priv(dev
);
4061 wolinfo
->supported
= WAKE_MAGIC
;
4063 spin_lock_irq(&np
->lock
);
4065 wolinfo
->wolopts
= WAKE_MAGIC
;
4066 spin_unlock_irq(&np
->lock
);
4069 static int nv_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
4071 struct fe_priv
*np
= netdev_priv(dev
);
4072 u8 __iomem
*base
= get_hwbase(dev
);
4075 if (wolinfo
->wolopts
== 0) {
4077 } else if (wolinfo
->wolopts
& WAKE_MAGIC
) {
4079 flags
= NVREG_WAKEUPFLAGS_ENABLE
;
4081 if (netif_running(dev
)) {
4082 spin_lock_irq(&np
->lock
);
4083 writel(flags
, base
+ NvRegWakeUpFlags
);
4084 spin_unlock_irq(&np
->lock
);
4089 static int nv_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
4091 struct fe_priv
*np
= netdev_priv(dev
);
4094 spin_lock_irq(&np
->lock
);
4095 ecmd
->port
= PORT_MII
;
4096 if (!netif_running(dev
)) {
4097 /* We do not track link speed / duplex setting if the
4098 * interface is disabled. Force a link check */
4099 if (nv_update_linkspeed(dev
)) {
4100 if (!netif_carrier_ok(dev
))
4101 netif_carrier_on(dev
);
4103 if (netif_carrier_ok(dev
))
4104 netif_carrier_off(dev
);
4108 if (netif_carrier_ok(dev
)) {
4109 switch(np
->linkspeed
& (NVREG_LINKSPEED_MASK
)) {
4110 case NVREG_LINKSPEED_10
:
4111 ecmd
->speed
= SPEED_10
;
4113 case NVREG_LINKSPEED_100
:
4114 ecmd
->speed
= SPEED_100
;
4116 case NVREG_LINKSPEED_1000
:
4117 ecmd
->speed
= SPEED_1000
;
4120 ecmd
->duplex
= DUPLEX_HALF
;
4122 ecmd
->duplex
= DUPLEX_FULL
;
4128 ecmd
->autoneg
= np
->autoneg
;
4130 ecmd
->advertising
= ADVERTISED_MII
;
4132 ecmd
->advertising
|= ADVERTISED_Autoneg
;
4133 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4134 if (adv
& ADVERTISE_10HALF
)
4135 ecmd
->advertising
|= ADVERTISED_10baseT_Half
;
4136 if (adv
& ADVERTISE_10FULL
)
4137 ecmd
->advertising
|= ADVERTISED_10baseT_Full
;
4138 if (adv
& ADVERTISE_100HALF
)
4139 ecmd
->advertising
|= ADVERTISED_100baseT_Half
;
4140 if (adv
& ADVERTISE_100FULL
)
4141 ecmd
->advertising
|= ADVERTISED_100baseT_Full
;
4142 if (np
->gigabit
== PHY_GIGABIT
) {
4143 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
4144 if (adv
& ADVERTISE_1000FULL
)
4145 ecmd
->advertising
|= ADVERTISED_1000baseT_Full
;
4148 ecmd
->supported
= (SUPPORTED_Autoneg
|
4149 SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full
|
4150 SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
|
4152 if (np
->gigabit
== PHY_GIGABIT
)
4153 ecmd
->supported
|= SUPPORTED_1000baseT_Full
;
4155 ecmd
->phy_address
= np
->phyaddr
;
4156 ecmd
->transceiver
= XCVR_EXTERNAL
;
4158 /* ignore maxtxpkt, maxrxpkt for now */
4159 spin_unlock_irq(&np
->lock
);
4163 static int nv_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
4165 struct fe_priv
*np
= netdev_priv(dev
);
4167 if (ecmd
->port
!= PORT_MII
)
4169 if (ecmd
->transceiver
!= XCVR_EXTERNAL
)
4171 if (ecmd
->phy_address
!= np
->phyaddr
) {
4172 /* TODO: support switching between multiple phys. Should be
4173 * trivial, but not enabled due to lack of test hardware. */
4176 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
4179 mask
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
4180 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
;
4181 if (np
->gigabit
== PHY_GIGABIT
)
4182 mask
|= ADVERTISED_1000baseT_Full
;
4184 if ((ecmd
->advertising
& mask
) == 0)
4187 } else if (ecmd
->autoneg
== AUTONEG_DISABLE
) {
4188 /* Note: autonegotiation disable, speed 1000 intentionally
4189 * forbidden - noone should need that. */
4191 if (ecmd
->speed
!= SPEED_10
&& ecmd
->speed
!= SPEED_100
)
4193 if (ecmd
->duplex
!= DUPLEX_HALF
&& ecmd
->duplex
!= DUPLEX_FULL
)
4199 netif_carrier_off(dev
);
4200 if (netif_running(dev
)) {
4201 nv_disable_irq(dev
);
4202 netif_tx_lock_bh(dev
);
4203 spin_lock(&np
->lock
);
4206 spin_unlock(&np
->lock
);
4207 netif_tx_unlock_bh(dev
);
4210 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
4215 /* advertise only what has been requested */
4216 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4217 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
4218 if (ecmd
->advertising
& ADVERTISED_10baseT_Half
)
4219 adv
|= ADVERTISE_10HALF
;
4220 if (ecmd
->advertising
& ADVERTISED_10baseT_Full
)
4221 adv
|= ADVERTISE_10FULL
;
4222 if (ecmd
->advertising
& ADVERTISED_100baseT_Half
)
4223 adv
|= ADVERTISE_100HALF
;
4224 if (ecmd
->advertising
& ADVERTISED_100baseT_Full
)
4225 adv
|= ADVERTISE_100FULL
;
4226 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) /* for rx we set both advertisments but disable tx pause */
4227 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
4228 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
4229 adv
|= ADVERTISE_PAUSE_ASYM
;
4230 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
4232 if (np
->gigabit
== PHY_GIGABIT
) {
4233 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
4234 adv
&= ~ADVERTISE_1000FULL
;
4235 if (ecmd
->advertising
& ADVERTISED_1000baseT_Full
)
4236 adv
|= ADVERTISE_1000FULL
;
4237 mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, adv
);
4240 if (netif_running(dev
))
4241 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
4242 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4243 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
4244 bmcr
|= BMCR_ANENABLE
;
4245 /* reset the phy in order for settings to stick,
4246 * and cause autoneg to start */
4247 if (phy_reset(dev
, bmcr
)) {
4248 printk(KERN_INFO
"%s: phy reset failed\n", dev
->name
);
4252 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
4253 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4260 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4261 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
4262 if (ecmd
->speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_HALF
)
4263 adv
|= ADVERTISE_10HALF
;
4264 if (ecmd
->speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_FULL
)
4265 adv
|= ADVERTISE_10FULL
;
4266 if (ecmd
->speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_HALF
)
4267 adv
|= ADVERTISE_100HALF
;
4268 if (ecmd
->speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_FULL
)
4269 adv
|= ADVERTISE_100FULL
;
4270 np
->pause_flags
&= ~(NV_PAUSEFRAME_AUTONEG
|NV_PAUSEFRAME_RX_ENABLE
|NV_PAUSEFRAME_TX_ENABLE
);
4271 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) {/* for rx we set both advertisments but disable tx pause */
4272 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
4273 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
4275 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
) {
4276 adv
|= ADVERTISE_PAUSE_ASYM
;
4277 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
4279 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
4280 np
->fixed_mode
= adv
;
4282 if (np
->gigabit
== PHY_GIGABIT
) {
4283 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
4284 adv
&= ~ADVERTISE_1000FULL
;
4285 mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, adv
);
4288 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4289 bmcr
&= ~(BMCR_ANENABLE
|BMCR_SPEED100
|BMCR_SPEED1000
|BMCR_FULLDPLX
);
4290 if (np
->fixed_mode
& (ADVERTISE_10FULL
|ADVERTISE_100FULL
))
4291 bmcr
|= BMCR_FULLDPLX
;
4292 if (np
->fixed_mode
& (ADVERTISE_100HALF
|ADVERTISE_100FULL
))
4293 bmcr
|= BMCR_SPEED100
;
4294 if (np
->phy_oui
== PHY_OUI_MARVELL
) {
4295 /* reset the phy in order for forced mode settings to stick */
4296 if (phy_reset(dev
, bmcr
)) {
4297 printk(KERN_INFO
"%s: phy reset failed\n", dev
->name
);
4301 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4302 if (netif_running(dev
)) {
4303 /* Wait a bit and then reconfigure the nic. */
4310 if (netif_running(dev
)) {
4318 #define FORCEDETH_REGS_VER 1
4320 static int nv_get_regs_len(struct net_device
*dev
)
4322 struct fe_priv
*np
= netdev_priv(dev
);
4323 return np
->register_size
;
4326 static void nv_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
, void *buf
)
4328 struct fe_priv
*np
= netdev_priv(dev
);
4329 u8 __iomem
*base
= get_hwbase(dev
);
4333 regs
->version
= FORCEDETH_REGS_VER
;
4334 spin_lock_irq(&np
->lock
);
4335 for (i
= 0;i
<= np
->register_size
/sizeof(u32
); i
++)
4336 rbuf
[i
] = readl(base
+ i
*sizeof(u32
));
4337 spin_unlock_irq(&np
->lock
);
4340 static int nv_nway_reset(struct net_device
*dev
)
4342 struct fe_priv
*np
= netdev_priv(dev
);
4348 netif_carrier_off(dev
);
4349 if (netif_running(dev
)) {
4350 nv_disable_irq(dev
);
4351 netif_tx_lock_bh(dev
);
4352 spin_lock(&np
->lock
);
4355 spin_unlock(&np
->lock
);
4356 netif_tx_unlock_bh(dev
);
4357 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
4360 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4361 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
4362 bmcr
|= BMCR_ANENABLE
;
4363 /* reset the phy in order for settings to stick*/
4364 if (phy_reset(dev
, bmcr
)) {
4365 printk(KERN_INFO
"%s: phy reset failed\n", dev
->name
);
4369 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
4370 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4373 if (netif_running(dev
)) {
4385 static int nv_set_tso(struct net_device
*dev
, u32 value
)
4387 struct fe_priv
*np
= netdev_priv(dev
);
4389 if ((np
->driver_data
& DEV_HAS_CHECKSUM
))
4390 return ethtool_op_set_tso(dev
, value
);
4395 static void nv_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
* ring
)
4397 struct fe_priv
*np
= netdev_priv(dev
);
4399 ring
->rx_max_pending
= (np
->desc_ver
== DESC_VER_1
) ? RING_MAX_DESC_VER_1
: RING_MAX_DESC_VER_2_3
;
4400 ring
->rx_mini_max_pending
= 0;
4401 ring
->rx_jumbo_max_pending
= 0;
4402 ring
->tx_max_pending
= (np
->desc_ver
== DESC_VER_1
) ? RING_MAX_DESC_VER_1
: RING_MAX_DESC_VER_2_3
;
4404 ring
->rx_pending
= np
->rx_ring_size
;
4405 ring
->rx_mini_pending
= 0;
4406 ring
->rx_jumbo_pending
= 0;
4407 ring
->tx_pending
= np
->tx_ring_size
;
4410 static int nv_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
* ring
)
4412 struct fe_priv
*np
= netdev_priv(dev
);
4413 u8 __iomem
*base
= get_hwbase(dev
);
4414 u8
*rxtx_ring
, *rx_skbuff
, *tx_skbuff
;
4415 dma_addr_t ring_addr
;
4417 if (ring
->rx_pending
< RX_RING_MIN
||
4418 ring
->tx_pending
< TX_RING_MIN
||
4419 ring
->rx_mini_pending
!= 0 ||
4420 ring
->rx_jumbo_pending
!= 0 ||
4421 (np
->desc_ver
== DESC_VER_1
&&
4422 (ring
->rx_pending
> RING_MAX_DESC_VER_1
||
4423 ring
->tx_pending
> RING_MAX_DESC_VER_1
)) ||
4424 (np
->desc_ver
!= DESC_VER_1
&&
4425 (ring
->rx_pending
> RING_MAX_DESC_VER_2_3
||
4426 ring
->tx_pending
> RING_MAX_DESC_VER_2_3
))) {
4430 /* allocate new rings */
4431 if (!nv_optimized(np
)) {
4432 rxtx_ring
= pci_alloc_consistent(np
->pci_dev
,
4433 sizeof(struct ring_desc
) * (ring
->rx_pending
+ ring
->tx_pending
),
4436 rxtx_ring
= pci_alloc_consistent(np
->pci_dev
,
4437 sizeof(struct ring_desc_ex
) * (ring
->rx_pending
+ ring
->tx_pending
),
4440 rx_skbuff
= kmalloc(sizeof(struct nv_skb_map
) * ring
->rx_pending
, GFP_KERNEL
);
4441 tx_skbuff
= kmalloc(sizeof(struct nv_skb_map
) * ring
->tx_pending
, GFP_KERNEL
);
4442 if (!rxtx_ring
|| !rx_skbuff
|| !tx_skbuff
) {
4443 /* fall back to old rings */
4444 if (!nv_optimized(np
)) {
4446 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (ring
->rx_pending
+ ring
->tx_pending
),
4447 rxtx_ring
, ring_addr
);
4450 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc_ex
) * (ring
->rx_pending
+ ring
->tx_pending
),
4451 rxtx_ring
, ring_addr
);
4460 if (netif_running(dev
)) {
4461 nv_disable_irq(dev
);
4462 netif_tx_lock_bh(dev
);
4463 spin_lock(&np
->lock
);
4473 /* set new values */
4474 np
->rx_ring_size
= ring
->rx_pending
;
4475 np
->tx_ring_size
= ring
->tx_pending
;
4477 if (!nv_optimized(np
)) {
4478 np
->rx_ring
.orig
= (struct ring_desc
*)rxtx_ring
;
4479 np
->tx_ring
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
];
4481 np
->rx_ring
.ex
= (struct ring_desc_ex
*)rxtx_ring
;
4482 np
->tx_ring
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
];
4484 np
->rx_skb
= (struct nv_skb_map
*)rx_skbuff
;
4485 np
->tx_skb
= (struct nv_skb_map
*)tx_skbuff
;
4486 np
->ring_addr
= ring_addr
;
4488 memset(np
->rx_skb
, 0, sizeof(struct nv_skb_map
) * np
->rx_ring_size
);
4489 memset(np
->tx_skb
, 0, sizeof(struct nv_skb_map
) * np
->tx_ring_size
);
4491 if (netif_running(dev
)) {
4492 /* reinit driver view of the queues */
4494 if (nv_init_ring(dev
)) {
4495 if (!np
->in_shutdown
)
4496 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
4499 /* reinit nic view of the queues */
4500 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
4501 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
4502 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
4503 base
+ NvRegRingSizes
);
4505 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
4508 /* restart engines */
4510 spin_unlock(&np
->lock
);
4511 netif_tx_unlock_bh(dev
);
4519 static void nv_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
* pause
)
4521 struct fe_priv
*np
= netdev_priv(dev
);
4523 pause
->autoneg
= (np
->pause_flags
& NV_PAUSEFRAME_AUTONEG
) != 0;
4524 pause
->rx_pause
= (np
->pause_flags
& NV_PAUSEFRAME_RX_ENABLE
) != 0;
4525 pause
->tx_pause
= (np
->pause_flags
& NV_PAUSEFRAME_TX_ENABLE
) != 0;
4528 static int nv_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
* pause
)
4530 struct fe_priv
*np
= netdev_priv(dev
);
4533 if ((!np
->autoneg
&& np
->duplex
== 0) ||
4534 (np
->autoneg
&& !pause
->autoneg
&& np
->duplex
== 0)) {
4535 printk(KERN_INFO
"%s: can not set pause settings when forced link is in half duplex.\n",
4539 if (pause
->tx_pause
&& !(np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
)) {
4540 printk(KERN_INFO
"%s: hardware does not support tx pause frames.\n", dev
->name
);
4544 netif_carrier_off(dev
);
4545 if (netif_running(dev
)) {
4546 nv_disable_irq(dev
);
4547 netif_tx_lock_bh(dev
);
4548 spin_lock(&np
->lock
);
4551 spin_unlock(&np
->lock
);
4552 netif_tx_unlock_bh(dev
);
4555 np
->pause_flags
&= ~(NV_PAUSEFRAME_RX_REQ
|NV_PAUSEFRAME_TX_REQ
);
4556 if (pause
->rx_pause
)
4557 np
->pause_flags
|= NV_PAUSEFRAME_RX_REQ
;
4558 if (pause
->tx_pause
)
4559 np
->pause_flags
|= NV_PAUSEFRAME_TX_REQ
;
4561 if (np
->autoneg
&& pause
->autoneg
) {
4562 np
->pause_flags
|= NV_PAUSEFRAME_AUTONEG
;
4564 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4565 adv
&= ~(ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
4566 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) /* for rx we set both advertisments but disable tx pause */
4567 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
4568 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
4569 adv
|= ADVERTISE_PAUSE_ASYM
;
4570 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
4572 if (netif_running(dev
))
4573 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
4574 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4575 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
4576 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4578 np
->pause_flags
&= ~(NV_PAUSEFRAME_AUTONEG
|NV_PAUSEFRAME_RX_ENABLE
|NV_PAUSEFRAME_TX_ENABLE
);
4579 if (pause
->rx_pause
)
4580 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
4581 if (pause
->tx_pause
)
4582 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
4584 if (!netif_running(dev
))
4585 nv_update_linkspeed(dev
);
4587 nv_update_pause(dev
, np
->pause_flags
);
4590 if (netif_running(dev
)) {
4597 static u32
nv_get_rx_csum(struct net_device
*dev
)
4599 struct fe_priv
*np
= netdev_priv(dev
);
4600 return (np
->rx_csum
) != 0;
4603 static int nv_set_rx_csum(struct net_device
*dev
, u32 data
)
4605 struct fe_priv
*np
= netdev_priv(dev
);
4606 u8 __iomem
*base
= get_hwbase(dev
);
4609 if (np
->driver_data
& DEV_HAS_CHECKSUM
) {
4612 np
->txrxctl_bits
|= NVREG_TXRXCTL_RXCHECK
;
4615 /* vlan is dependent on rx checksum offload */
4616 if (!(np
->vlanctl_bits
& NVREG_VLANCONTROL_ENABLE
))
4617 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_RXCHECK
;
4619 if (netif_running(dev
)) {
4620 spin_lock_irq(&np
->lock
);
4621 writel(np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
4622 spin_unlock_irq(&np
->lock
);
4631 static int nv_set_tx_csum(struct net_device
*dev
, u32 data
)
4633 struct fe_priv
*np
= netdev_priv(dev
);
4635 if (np
->driver_data
& DEV_HAS_CHECKSUM
)
4636 return ethtool_op_set_tx_hw_csum(dev
, data
);
4641 static int nv_set_sg(struct net_device
*dev
, u32 data
)
4643 struct fe_priv
*np
= netdev_priv(dev
);
4645 if (np
->driver_data
& DEV_HAS_CHECKSUM
)
4646 return ethtool_op_set_sg(dev
, data
);
4651 static int nv_get_sset_count(struct net_device
*dev
, int sset
)
4653 struct fe_priv
*np
= netdev_priv(dev
);
4657 if (np
->driver_data
& DEV_HAS_TEST_EXTENDED
)
4658 return NV_TEST_COUNT_EXTENDED
;
4660 return NV_TEST_COUNT_BASE
;
4662 if (np
->driver_data
& DEV_HAS_STATISTICS_V1
)
4663 return NV_DEV_STATISTICS_V1_COUNT
;
4664 else if (np
->driver_data
& DEV_HAS_STATISTICS_V2
)
4665 return NV_DEV_STATISTICS_V2_COUNT
;
4673 static void nv_get_ethtool_stats(struct net_device
*dev
, struct ethtool_stats
*estats
, u64
*buffer
)
4675 struct fe_priv
*np
= netdev_priv(dev
);
4678 nv_do_stats_poll((unsigned long)dev
);
4680 memcpy(buffer
, &np
->estats
, nv_get_sset_count(dev
, ETH_SS_STATS
)*sizeof(u64
));
4683 static int nv_link_test(struct net_device
*dev
)
4685 struct fe_priv
*np
= netdev_priv(dev
);
4688 mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
4689 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
4691 /* check phy link status */
4692 if (!(mii_status
& BMSR_LSTATUS
))
4698 static int nv_register_test(struct net_device
*dev
)
4700 u8 __iomem
*base
= get_hwbase(dev
);
4702 u32 orig_read
, new_read
;
4705 orig_read
= readl(base
+ nv_registers_test
[i
].reg
);
4707 /* xor with mask to toggle bits */
4708 orig_read
^= nv_registers_test
[i
].mask
;
4710 writel(orig_read
, base
+ nv_registers_test
[i
].reg
);
4712 new_read
= readl(base
+ nv_registers_test
[i
].reg
);
4714 if ((new_read
& nv_registers_test
[i
].mask
) != (orig_read
& nv_registers_test
[i
].mask
))
4717 /* restore original value */
4718 orig_read
^= nv_registers_test
[i
].mask
;
4719 writel(orig_read
, base
+ nv_registers_test
[i
].reg
);
4721 } while (nv_registers_test
[++i
].reg
!= 0);
4726 static int nv_interrupt_test(struct net_device
*dev
)
4728 struct fe_priv
*np
= netdev_priv(dev
);
4729 u8 __iomem
*base
= get_hwbase(dev
);
4732 u32 save_msi_flags
, save_poll_interval
= 0;
4734 if (netif_running(dev
)) {
4735 /* free current irq */
4737 save_poll_interval
= readl(base
+NvRegPollingInterval
);
4740 /* flag to test interrupt handler */
4743 /* setup test irq */
4744 save_msi_flags
= np
->msi_flags
;
4745 np
->msi_flags
&= ~NV_MSI_X_VECTORS_MASK
;
4746 np
->msi_flags
|= 0x001; /* setup 1 vector */
4747 if (nv_request_irq(dev
, 1))
4750 /* setup timer interrupt */
4751 writel(NVREG_POLL_DEFAULT_CPU
, base
+ NvRegPollingInterval
);
4752 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
4754 nv_enable_hw_interrupts(dev
, NVREG_IRQ_TIMER
);
4756 /* wait for at least one interrupt */
4759 spin_lock_irq(&np
->lock
);
4761 /* flag should be set within ISR */
4762 testcnt
= np
->intr_test
;
4766 nv_disable_hw_interrupts(dev
, NVREG_IRQ_TIMER
);
4767 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
4768 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
4770 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
4772 spin_unlock_irq(&np
->lock
);
4776 np
->msi_flags
= save_msi_flags
;
4778 if (netif_running(dev
)) {
4779 writel(save_poll_interval
, base
+ NvRegPollingInterval
);
4780 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
4781 /* restore original irq */
4782 if (nv_request_irq(dev
, 0))
4789 static int nv_loopback_test(struct net_device
*dev
)
4791 struct fe_priv
*np
= netdev_priv(dev
);
4792 u8 __iomem
*base
= get_hwbase(dev
);
4793 struct sk_buff
*tx_skb
, *rx_skb
;
4794 dma_addr_t test_dma_addr
;
4795 u32 tx_flags_extra
= (np
->desc_ver
== DESC_VER_1
? NV_TX_LASTPACKET
: NV_TX2_LASTPACKET
);
4797 int len
, i
, pkt_len
;
4799 u32 filter_flags
= 0;
4800 u32 misc1_flags
= 0;
4803 if (netif_running(dev
)) {
4804 nv_disable_irq(dev
);
4805 filter_flags
= readl(base
+ NvRegPacketFilterFlags
);
4806 misc1_flags
= readl(base
+ NvRegMisc1
);
4811 /* reinit driver view of the rx queue */
4815 /* setup hardware for loopback */
4816 writel(NVREG_MISC1_FORCE
, base
+ NvRegMisc1
);
4817 writel(NVREG_PFF_ALWAYS
| NVREG_PFF_LOOPBACK
, base
+ NvRegPacketFilterFlags
);
4819 /* reinit nic view of the rx queue */
4820 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
4821 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
4822 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
4823 base
+ NvRegRingSizes
);
4826 /* restart rx engine */
4829 /* setup packet for tx */
4830 pkt_len
= ETH_DATA_LEN
;
4831 tx_skb
= dev_alloc_skb(pkt_len
);
4833 printk(KERN_ERR
"dev_alloc_skb() failed during loopback test"
4834 " of %s\n", dev
->name
);
4838 test_dma_addr
= pci_map_single(np
->pci_dev
, tx_skb
->data
,
4839 skb_tailroom(tx_skb
),
4840 PCI_DMA_FROMDEVICE
);
4841 pkt_data
= skb_put(tx_skb
, pkt_len
);
4842 for (i
= 0; i
< pkt_len
; i
++)
4843 pkt_data
[i
] = (u8
)(i
& 0xff);
4845 if (!nv_optimized(np
)) {
4846 np
->tx_ring
.orig
[0].buf
= cpu_to_le32(test_dma_addr
);
4847 np
->tx_ring
.orig
[0].flaglen
= cpu_to_le32((pkt_len
-1) | np
->tx_flags
| tx_flags_extra
);
4849 np
->tx_ring
.ex
[0].bufhigh
= cpu_to_le32(dma_high(test_dma_addr
));
4850 np
->tx_ring
.ex
[0].buflow
= cpu_to_le32(dma_low(test_dma_addr
));
4851 np
->tx_ring
.ex
[0].flaglen
= cpu_to_le32((pkt_len
-1) | np
->tx_flags
| tx_flags_extra
);
4853 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
4854 pci_push(get_hwbase(dev
));
4858 /* check for rx of the packet */
4859 if (!nv_optimized(np
)) {
4860 flags
= le32_to_cpu(np
->rx_ring
.orig
[0].flaglen
);
4861 len
= nv_descr_getlength(&np
->rx_ring
.orig
[0], np
->desc_ver
);
4864 flags
= le32_to_cpu(np
->rx_ring
.ex
[0].flaglen
);
4865 len
= nv_descr_getlength_ex(&np
->rx_ring
.ex
[0], np
->desc_ver
);
4868 if (flags
& NV_RX_AVAIL
) {
4870 } else if (np
->desc_ver
== DESC_VER_1
) {
4871 if (flags
& NV_RX_ERROR
)
4874 if (flags
& NV_RX2_ERROR
) {
4880 if (len
!= pkt_len
) {
4882 dprintk(KERN_DEBUG
"%s: loopback len mismatch %d vs %d\n",
4883 dev
->name
, len
, pkt_len
);
4885 rx_skb
= np
->rx_skb
[0].skb
;
4886 for (i
= 0; i
< pkt_len
; i
++) {
4887 if (rx_skb
->data
[i
] != (u8
)(i
& 0xff)) {
4889 dprintk(KERN_DEBUG
"%s: loopback pattern check failed on byte %d\n",
4896 dprintk(KERN_DEBUG
"%s: loopback - did not receive test packet\n", dev
->name
);
4899 pci_unmap_page(np
->pci_dev
, test_dma_addr
,
4900 (skb_end_pointer(tx_skb
) - tx_skb
->data
),
4902 dev_kfree_skb_any(tx_skb
);
4907 /* drain rx queue */
4910 if (netif_running(dev
)) {
4911 writel(misc1_flags
, base
+ NvRegMisc1
);
4912 writel(filter_flags
, base
+ NvRegPacketFilterFlags
);
4919 static void nv_self_test(struct net_device
*dev
, struct ethtool_test
*test
, u64
*buffer
)
4921 struct fe_priv
*np
= netdev_priv(dev
);
4922 u8 __iomem
*base
= get_hwbase(dev
);
4924 memset(buffer
, 0, nv_get_sset_count(dev
, ETH_SS_TEST
)*sizeof(u64
));
4926 if (!nv_link_test(dev
)) {
4927 test
->flags
|= ETH_TEST_FL_FAILED
;
4931 if (test
->flags
& ETH_TEST_FL_OFFLINE
) {
4932 if (netif_running(dev
)) {
4933 netif_stop_queue(dev
);
4934 #ifdef CONFIG_FORCEDETH_NAPI
4935 napi_disable(&np
->napi
);
4937 netif_tx_lock_bh(dev
);
4938 spin_lock_irq(&np
->lock
);
4939 nv_disable_hw_interrupts(dev
, np
->irqmask
);
4940 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
4941 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
4943 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
4948 /* drain rx queue */
4950 spin_unlock_irq(&np
->lock
);
4951 netif_tx_unlock_bh(dev
);
4954 if (!nv_register_test(dev
)) {
4955 test
->flags
|= ETH_TEST_FL_FAILED
;
4959 result
= nv_interrupt_test(dev
);
4961 test
->flags
|= ETH_TEST_FL_FAILED
;
4969 if (!nv_loopback_test(dev
)) {
4970 test
->flags
|= ETH_TEST_FL_FAILED
;
4974 if (netif_running(dev
)) {
4975 /* reinit driver view of the rx queue */
4977 if (nv_init_ring(dev
)) {
4978 if (!np
->in_shutdown
)
4979 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
4981 /* reinit nic view of the rx queue */
4982 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
4983 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
4984 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
4985 base
+ NvRegRingSizes
);
4987 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
4989 /* restart rx engine */
4991 netif_start_queue(dev
);
4992 #ifdef CONFIG_FORCEDETH_NAPI
4993 napi_enable(&np
->napi
);
4995 nv_enable_hw_interrupts(dev
, np
->irqmask
);
5000 static void nv_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buffer
)
5002 switch (stringset
) {
5004 memcpy(buffer
, &nv_estats_str
, nv_get_sset_count(dev
, ETH_SS_STATS
)*sizeof(struct nv_ethtool_str
));
5007 memcpy(buffer
, &nv_etests_str
, nv_get_sset_count(dev
, ETH_SS_TEST
)*sizeof(struct nv_ethtool_str
));
5012 static const struct ethtool_ops ops
= {
5013 .get_drvinfo
= nv_get_drvinfo
,
5014 .get_link
= ethtool_op_get_link
,
5015 .get_wol
= nv_get_wol
,
5016 .set_wol
= nv_set_wol
,
5017 .get_settings
= nv_get_settings
,
5018 .set_settings
= nv_set_settings
,
5019 .get_regs_len
= nv_get_regs_len
,
5020 .get_regs
= nv_get_regs
,
5021 .nway_reset
= nv_nway_reset
,
5022 .set_tso
= nv_set_tso
,
5023 .get_ringparam
= nv_get_ringparam
,
5024 .set_ringparam
= nv_set_ringparam
,
5025 .get_pauseparam
= nv_get_pauseparam
,
5026 .set_pauseparam
= nv_set_pauseparam
,
5027 .get_rx_csum
= nv_get_rx_csum
,
5028 .set_rx_csum
= nv_set_rx_csum
,
5029 .set_tx_csum
= nv_set_tx_csum
,
5030 .set_sg
= nv_set_sg
,
5031 .get_strings
= nv_get_strings
,
5032 .get_ethtool_stats
= nv_get_ethtool_stats
,
5033 .get_sset_count
= nv_get_sset_count
,
5034 .self_test
= nv_self_test
,
5037 static void nv_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
5039 struct fe_priv
*np
= get_nvpriv(dev
);
5041 spin_lock_irq(&np
->lock
);
5043 /* save vlan group */
5047 /* enable vlan on MAC */
5048 np
->txrxctl_bits
|= NVREG_TXRXCTL_VLANSTRIP
| NVREG_TXRXCTL_VLANINS
;
5050 /* disable vlan on MAC */
5051 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_VLANSTRIP
;
5052 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_VLANINS
;
5055 writel(np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
5057 spin_unlock_irq(&np
->lock
);
5060 /* The mgmt unit and driver use a semaphore to access the phy during init */
5061 static int nv_mgmt_acquire_sema(struct net_device
*dev
)
5063 u8 __iomem
*base
= get_hwbase(dev
);
5065 u32 tx_ctrl
, mgmt_sema
;
5067 for (i
= 0; i
< 10; i
++) {
5068 mgmt_sema
= readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_MGMT_SEMA_MASK
;
5069 if (mgmt_sema
== NVREG_XMITCTL_MGMT_SEMA_FREE
)
5074 if (mgmt_sema
!= NVREG_XMITCTL_MGMT_SEMA_FREE
)
5077 for (i
= 0; i
< 2; i
++) {
5078 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
5079 tx_ctrl
|= NVREG_XMITCTL_HOST_SEMA_ACQ
;
5080 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
5082 /* verify that semaphore was acquired */
5083 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
5084 if (((tx_ctrl
& NVREG_XMITCTL_HOST_SEMA_MASK
) == NVREG_XMITCTL_HOST_SEMA_ACQ
) &&
5085 ((tx_ctrl
& NVREG_XMITCTL_MGMT_SEMA_MASK
) == NVREG_XMITCTL_MGMT_SEMA_FREE
))
5094 static int nv_open(struct net_device
*dev
)
5096 struct fe_priv
*np
= netdev_priv(dev
);
5097 u8 __iomem
*base
= get_hwbase(dev
);
5102 dprintk(KERN_DEBUG
"nv_open: begin\n");
5104 /* erase previous misconfiguration */
5105 if (np
->driver_data
& DEV_HAS_POWER_CNTRL
)
5107 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
5108 writel(0, base
+ NvRegMulticastAddrB
);
5109 writel(NVREG_MCASTMASKA_NONE
, base
+ NvRegMulticastMaskA
);
5110 writel(NVREG_MCASTMASKB_NONE
, base
+ NvRegMulticastMaskB
);
5111 writel(0, base
+ NvRegPacketFilterFlags
);
5113 writel(0, base
+ NvRegTransmitterControl
);
5114 writel(0, base
+ NvRegReceiverControl
);
5116 writel(0, base
+ NvRegAdapterControl
);
5118 if (np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
)
5119 writel(NVREG_TX_PAUSEFRAME_DISABLE
, base
+ NvRegTxPauseFrame
);
5121 /* initialize descriptor rings */
5123 oom
= nv_init_ring(dev
);
5125 writel(0, base
+ NvRegLinkSpeed
);
5126 writel(readl(base
+ NvRegTransmitPoll
) & NVREG_TRANSMITPOLL_MAC_ADDR_REV
, base
+ NvRegTransmitPoll
);
5128 writel(0, base
+ NvRegUnknownSetupReg6
);
5130 np
->in_shutdown
= 0;
5133 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
5134 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
5135 base
+ NvRegRingSizes
);
5137 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
5138 if (np
->desc_ver
== DESC_VER_1
)
5139 writel(NVREG_TX_WM_DESC1_DEFAULT
, base
+ NvRegTxWatermark
);
5141 writel(NVREG_TX_WM_DESC2_3_DEFAULT
, base
+ NvRegTxWatermark
);
5142 writel(np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
5143 writel(np
->vlanctl_bits
, base
+ NvRegVlanControl
);
5145 writel(NVREG_TXRXCTL_BIT1
|np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
5146 reg_delay(dev
, NvRegUnknownSetupReg5
, NVREG_UNKSETUP5_BIT31
, NVREG_UNKSETUP5_BIT31
,
5147 NV_SETUP5_DELAY
, NV_SETUP5_DELAYMAX
,
5148 KERN_INFO
"open: SetupReg5, Bit 31 remained off\n");
5150 writel(0, base
+ NvRegMIIMask
);
5151 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
5152 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5154 writel(NVREG_MISC1_FORCE
| NVREG_MISC1_HD
, base
+ NvRegMisc1
);
5155 writel(readl(base
+ NvRegTransmitterStatus
), base
+ NvRegTransmitterStatus
);
5156 writel(NVREG_PFF_ALWAYS
, base
+ NvRegPacketFilterFlags
);
5157 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
5159 writel(readl(base
+ NvRegReceiverStatus
), base
+ NvRegReceiverStatus
);
5161 get_random_bytes(&low
, sizeof(low
));
5162 low
&= NVREG_SLOTTIME_MASK
;
5163 if (np
->desc_ver
== DESC_VER_1
) {
5164 writel(low
|NVREG_SLOTTIME_DEFAULT
, base
+ NvRegSlotTime
);
5166 if (!(np
->driver_data
& DEV_HAS_GEAR_MODE
)) {
5167 /* setup legacy backoff */
5168 writel(NVREG_SLOTTIME_LEGBF_ENABLED
|NVREG_SLOTTIME_10_100_FULL
|low
, base
+ NvRegSlotTime
);
5170 writel(NVREG_SLOTTIME_10_100_FULL
, base
+ NvRegSlotTime
);
5171 nv_gear_backoff_reseed(dev
);
5174 writel(NVREG_TX_DEFERRAL_DEFAULT
, base
+ NvRegTxDeferral
);
5175 writel(NVREG_RX_DEFERRAL_DEFAULT
, base
+ NvRegRxDeferral
);
5176 if (poll_interval
== -1) {
5177 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
)
5178 writel(NVREG_POLL_DEFAULT_THROUGHPUT
, base
+ NvRegPollingInterval
);
5180 writel(NVREG_POLL_DEFAULT_CPU
, base
+ NvRegPollingInterval
);
5183 writel(poll_interval
& 0xFFFF, base
+ NvRegPollingInterval
);
5184 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
5185 writel((np
->phyaddr
<< NVREG_ADAPTCTL_PHYSHIFT
)|NVREG_ADAPTCTL_PHYVALID
|NVREG_ADAPTCTL_RUNNING
,
5186 base
+ NvRegAdapterControl
);
5187 writel(NVREG_MIISPEED_BIT8
|NVREG_MIIDELAY
, base
+ NvRegMIISpeed
);
5188 writel(NVREG_MII_LINKCHANGE
, base
+ NvRegMIIMask
);
5190 writel(NVREG_WAKEUPFLAGS_ENABLE
, base
+ NvRegWakeUpFlags
);
5192 i
= readl(base
+ NvRegPowerState
);
5193 if ( (i
& NVREG_POWERSTATE_POWEREDUP
) == 0)
5194 writel(NVREG_POWERSTATE_POWEREDUP
|i
, base
+ NvRegPowerState
);
5198 writel(readl(base
+ NvRegPowerState
) | NVREG_POWERSTATE_VALID
, base
+ NvRegPowerState
);
5200 nv_disable_hw_interrupts(dev
, np
->irqmask
);
5202 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5203 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
5206 if (nv_request_irq(dev
, 0)) {
5210 /* ask for interrupts */
5211 nv_enable_hw_interrupts(dev
, np
->irqmask
);
5213 spin_lock_irq(&np
->lock
);
5214 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
5215 writel(0, base
+ NvRegMulticastAddrB
);
5216 writel(NVREG_MCASTMASKA_NONE
, base
+ NvRegMulticastMaskA
);
5217 writel(NVREG_MCASTMASKB_NONE
, base
+ NvRegMulticastMaskB
);
5218 writel(NVREG_PFF_ALWAYS
|NVREG_PFF_MYADDR
, base
+ NvRegPacketFilterFlags
);
5219 /* One manual link speed update: Interrupts are enabled, future link
5220 * speed changes cause interrupts and are handled by nv_link_irq().
5224 miistat
= readl(base
+ NvRegMIIStatus
);
5225 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5226 dprintk(KERN_INFO
"startup: got 0x%08x.\n", miistat
);
5228 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5231 ret
= nv_update_linkspeed(dev
);
5233 netif_start_queue(dev
);
5234 #ifdef CONFIG_FORCEDETH_NAPI
5235 napi_enable(&np
->napi
);
5239 netif_carrier_on(dev
);
5241 printk(KERN_INFO
"%s: no link during initialization.\n", dev
->name
);
5242 netif_carrier_off(dev
);
5245 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
5247 /* start statistics timer */
5248 if (np
->driver_data
& (DEV_HAS_STATISTICS_V1
|DEV_HAS_STATISTICS_V2
))
5249 mod_timer(&np
->stats_poll
,
5250 round_jiffies(jiffies
+ STATS_INTERVAL
));
5252 spin_unlock_irq(&np
->lock
);
5260 static int nv_close(struct net_device
*dev
)
5262 struct fe_priv
*np
= netdev_priv(dev
);
5265 spin_lock_irq(&np
->lock
);
5266 np
->in_shutdown
= 1;
5267 spin_unlock_irq(&np
->lock
);
5268 #ifdef CONFIG_FORCEDETH_NAPI
5269 napi_disable(&np
->napi
);
5271 synchronize_irq(np
->pci_dev
->irq
);
5273 del_timer_sync(&np
->oom_kick
);
5274 del_timer_sync(&np
->nic_poll
);
5275 del_timer_sync(&np
->stats_poll
);
5277 netif_stop_queue(dev
);
5278 spin_lock_irq(&np
->lock
);
5282 /* disable interrupts on the nic or we will lock up */
5283 base
= get_hwbase(dev
);
5284 nv_disable_hw_interrupts(dev
, np
->irqmask
);
5286 dprintk(KERN_INFO
"%s: Irqmask is zero again\n", dev
->name
);
5288 spin_unlock_irq(&np
->lock
);
5294 if (np
->wolenabled
) {
5295 writel(NVREG_PFF_ALWAYS
|NVREG_PFF_MYADDR
, base
+ NvRegPacketFilterFlags
);
5299 /* FIXME: power down nic */
5304 static int __devinit
nv_probe(struct pci_dev
*pci_dev
, const struct pci_device_id
*id
)
5306 struct net_device
*dev
;
5311 u32 powerstate
, txreg
;
5312 u32 phystate_orig
= 0, phystate
;
5313 int phyinitialized
= 0;
5314 DECLARE_MAC_BUF(mac
);
5315 static int printed_version
;
5317 if (!printed_version
++)
5318 printk(KERN_INFO
"%s: Reverse Engineered nForce ethernet"
5319 " driver. Version %s.\n", DRV_NAME
, FORCEDETH_VERSION
);
5321 dev
= alloc_etherdev(sizeof(struct fe_priv
));
5326 np
= netdev_priv(dev
);
5328 np
->pci_dev
= pci_dev
;
5329 spin_lock_init(&np
->lock
);
5330 SET_NETDEV_DEV(dev
, &pci_dev
->dev
);
5332 init_timer(&np
->oom_kick
);
5333 np
->oom_kick
.data
= (unsigned long) dev
;
5334 np
->oom_kick
.function
= &nv_do_rx_refill
; /* timer handler */
5335 init_timer(&np
->nic_poll
);
5336 np
->nic_poll
.data
= (unsigned long) dev
;
5337 np
->nic_poll
.function
= &nv_do_nic_poll
; /* timer handler */
5338 init_timer(&np
->stats_poll
);
5339 np
->stats_poll
.data
= (unsigned long) dev
;
5340 np
->stats_poll
.function
= &nv_do_stats_poll
; /* timer handler */
5342 err
= pci_enable_device(pci_dev
);
5346 pci_set_master(pci_dev
);
5348 err
= pci_request_regions(pci_dev
, DRV_NAME
);
5352 if (id
->driver_data
& (DEV_HAS_VLAN
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_STATISTICS_V2
))
5353 np
->register_size
= NV_PCI_REGSZ_VER3
;
5354 else if (id
->driver_data
& DEV_HAS_STATISTICS_V1
)
5355 np
->register_size
= NV_PCI_REGSZ_VER2
;
5357 np
->register_size
= NV_PCI_REGSZ_VER1
;
5361 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
5362 dprintk(KERN_DEBUG
"%s: resource %d start %p len %ld flags 0x%08lx.\n",
5363 pci_name(pci_dev
), i
, (void*)pci_resource_start(pci_dev
, i
),
5364 pci_resource_len(pci_dev
, i
),
5365 pci_resource_flags(pci_dev
, i
));
5366 if (pci_resource_flags(pci_dev
, i
) & IORESOURCE_MEM
&&
5367 pci_resource_len(pci_dev
, i
) >= np
->register_size
) {
5368 addr
= pci_resource_start(pci_dev
, i
);
5372 if (i
== DEVICE_COUNT_RESOURCE
) {
5373 dev_printk(KERN_INFO
, &pci_dev
->dev
,
5374 "Couldn't find register window\n");
5378 /* copy of driver data */
5379 np
->driver_data
= id
->driver_data
;
5380 /* copy of device id */
5381 np
->device_id
= id
->device
;
5383 /* handle different descriptor versions */
5384 if (id
->driver_data
& DEV_HAS_HIGH_DMA
) {
5385 /* packet format 3: supports 40-bit addressing */
5386 np
->desc_ver
= DESC_VER_3
;
5387 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_3
;
5389 if (pci_set_dma_mask(pci_dev
, DMA_39BIT_MASK
))
5390 dev_printk(KERN_INFO
, &pci_dev
->dev
,
5391 "64-bit DMA failed, using 32-bit addressing\n");
5393 dev
->features
|= NETIF_F_HIGHDMA
;
5394 if (pci_set_consistent_dma_mask(pci_dev
, DMA_39BIT_MASK
)) {
5395 dev_printk(KERN_INFO
, &pci_dev
->dev
,
5396 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5399 } else if (id
->driver_data
& DEV_HAS_LARGEDESC
) {
5400 /* packet format 2: supports jumbo frames */
5401 np
->desc_ver
= DESC_VER_2
;
5402 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_2
;
5404 /* original packet format */
5405 np
->desc_ver
= DESC_VER_1
;
5406 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_1
;
5409 np
->pkt_limit
= NV_PKTLIMIT_1
;
5410 if (id
->driver_data
& DEV_HAS_LARGEDESC
)
5411 np
->pkt_limit
= NV_PKTLIMIT_2
;
5413 if (id
->driver_data
& DEV_HAS_CHECKSUM
) {
5415 np
->txrxctl_bits
|= NVREG_TXRXCTL_RXCHECK
;
5416 dev
->features
|= NETIF_F_HW_CSUM
| NETIF_F_SG
;
5417 dev
->features
|= NETIF_F_TSO
;
5420 np
->vlanctl_bits
= 0;
5421 if (id
->driver_data
& DEV_HAS_VLAN
) {
5422 np
->vlanctl_bits
= NVREG_VLANCONTROL_ENABLE
;
5423 dev
->features
|= NETIF_F_HW_VLAN_RX
| NETIF_F_HW_VLAN_TX
;
5424 dev
->vlan_rx_register
= nv_vlan_rx_register
;
5428 if ((id
->driver_data
& DEV_HAS_MSI
) && msi
) {
5429 np
->msi_flags
|= NV_MSI_CAPABLE
;
5431 if ((id
->driver_data
& DEV_HAS_MSI_X
) && msix
) {
5432 np
->msi_flags
|= NV_MSI_X_CAPABLE
;
5435 np
->pause_flags
= NV_PAUSEFRAME_RX_CAPABLE
| NV_PAUSEFRAME_RX_REQ
| NV_PAUSEFRAME_AUTONEG
;
5436 if ((id
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V1
) ||
5437 (id
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V2
) ||
5438 (id
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V3
)) {
5439 np
->pause_flags
|= NV_PAUSEFRAME_TX_CAPABLE
| NV_PAUSEFRAME_TX_REQ
;
5444 np
->base
= ioremap(addr
, np
->register_size
);
5447 dev
->base_addr
= (unsigned long)np
->base
;
5449 dev
->irq
= pci_dev
->irq
;
5451 np
->rx_ring_size
= RX_RING_DEFAULT
;
5452 np
->tx_ring_size
= TX_RING_DEFAULT
;
5454 if (!nv_optimized(np
)) {
5455 np
->rx_ring
.orig
= pci_alloc_consistent(pci_dev
,
5456 sizeof(struct ring_desc
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
5458 if (!np
->rx_ring
.orig
)
5460 np
->tx_ring
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
];
5462 np
->rx_ring
.ex
= pci_alloc_consistent(pci_dev
,
5463 sizeof(struct ring_desc_ex
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
5465 if (!np
->rx_ring
.ex
)
5467 np
->tx_ring
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
];
5469 np
->rx_skb
= kcalloc(np
->rx_ring_size
, sizeof(struct nv_skb_map
), GFP_KERNEL
);
5470 np
->tx_skb
= kcalloc(np
->tx_ring_size
, sizeof(struct nv_skb_map
), GFP_KERNEL
);
5471 if (!np
->rx_skb
|| !np
->tx_skb
)
5474 dev
->open
= nv_open
;
5475 dev
->stop
= nv_close
;
5477 if (!nv_optimized(np
))
5478 dev
->hard_start_xmit
= nv_start_xmit
;
5480 dev
->hard_start_xmit
= nv_start_xmit_optimized
;
5481 dev
->get_stats
= nv_get_stats
;
5482 dev
->change_mtu
= nv_change_mtu
;
5483 dev
->set_mac_address
= nv_set_mac_address
;
5484 dev
->set_multicast_list
= nv_set_multicast
;
5485 #ifdef CONFIG_NET_POLL_CONTROLLER
5486 dev
->poll_controller
= nv_poll_controller
;
5488 #ifdef CONFIG_FORCEDETH_NAPI
5489 netif_napi_add(dev
, &np
->napi
, nv_napi_poll
, RX_WORK_PER_LOOP
);
5491 SET_ETHTOOL_OPS(dev
, &ops
);
5492 dev
->tx_timeout
= nv_tx_timeout
;
5493 dev
->watchdog_timeo
= NV_WATCHDOG_TIMEO
;
5495 pci_set_drvdata(pci_dev
, dev
);
5497 /* read the mac address */
5498 base
= get_hwbase(dev
);
5499 np
->orig_mac
[0] = readl(base
+ NvRegMacAddrA
);
5500 np
->orig_mac
[1] = readl(base
+ NvRegMacAddrB
);
5502 /* check the workaround bit for correct mac address order */
5503 txreg
= readl(base
+ NvRegTransmitPoll
);
5504 if (id
->driver_data
& DEV_HAS_CORRECT_MACADDR
) {
5505 /* mac address is already in correct order */
5506 dev
->dev_addr
[0] = (np
->orig_mac
[0] >> 0) & 0xff;
5507 dev
->dev_addr
[1] = (np
->orig_mac
[0] >> 8) & 0xff;
5508 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 16) & 0xff;
5509 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 24) & 0xff;
5510 dev
->dev_addr
[4] = (np
->orig_mac
[1] >> 0) & 0xff;
5511 dev
->dev_addr
[5] = (np
->orig_mac
[1] >> 8) & 0xff;
5512 } else if (txreg
& NVREG_TRANSMITPOLL_MAC_ADDR_REV
) {
5513 /* mac address is already in correct order */
5514 dev
->dev_addr
[0] = (np
->orig_mac
[0] >> 0) & 0xff;
5515 dev
->dev_addr
[1] = (np
->orig_mac
[0] >> 8) & 0xff;
5516 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 16) & 0xff;
5517 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 24) & 0xff;
5518 dev
->dev_addr
[4] = (np
->orig_mac
[1] >> 0) & 0xff;
5519 dev
->dev_addr
[5] = (np
->orig_mac
[1] >> 8) & 0xff;
5521 * Set orig mac address back to the reversed version.
5522 * This flag will be cleared during low power transition.
5523 * Therefore, we should always put back the reversed address.
5525 np
->orig_mac
[0] = (dev
->dev_addr
[5] << 0) + (dev
->dev_addr
[4] << 8) +
5526 (dev
->dev_addr
[3] << 16) + (dev
->dev_addr
[2] << 24);
5527 np
->orig_mac
[1] = (dev
->dev_addr
[1] << 0) + (dev
->dev_addr
[0] << 8);
5529 /* need to reverse mac address to correct order */
5530 dev
->dev_addr
[0] = (np
->orig_mac
[1] >> 8) & 0xff;
5531 dev
->dev_addr
[1] = (np
->orig_mac
[1] >> 0) & 0xff;
5532 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 24) & 0xff;
5533 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 16) & 0xff;
5534 dev
->dev_addr
[4] = (np
->orig_mac
[0] >> 8) & 0xff;
5535 dev
->dev_addr
[5] = (np
->orig_mac
[0] >> 0) & 0xff;
5536 writel(txreg
|NVREG_TRANSMITPOLL_MAC_ADDR_REV
, base
+ NvRegTransmitPoll
);
5538 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
5540 if (!is_valid_ether_addr(dev
->perm_addr
)) {
5542 * Bad mac address. At least one bios sets the mac address
5543 * to 01:23:45:67:89:ab
5545 dev_printk(KERN_ERR
, &pci_dev
->dev
,
5546 "Invalid Mac address detected: %s\n",
5547 print_mac(mac
, dev
->dev_addr
));
5548 dev_printk(KERN_ERR
, &pci_dev
->dev
,
5549 "Please complain to your hardware vendor. Switching to a random MAC.\n");
5550 dev
->dev_addr
[0] = 0x00;
5551 dev
->dev_addr
[1] = 0x00;
5552 dev
->dev_addr
[2] = 0x6c;
5553 get_random_bytes(&dev
->dev_addr
[3], 3);
5556 dprintk(KERN_DEBUG
"%s: MAC Address %s\n",
5557 pci_name(pci_dev
), print_mac(mac
, dev
->dev_addr
));
5559 /* set mac address */
5560 nv_copy_mac_to_hw(dev
);
5563 writel(0, base
+ NvRegWakeUpFlags
);
5566 if (id
->driver_data
& DEV_HAS_POWER_CNTRL
) {
5568 /* take phy and nic out of low power mode */
5569 powerstate
= readl(base
+ NvRegPowerState2
);
5570 powerstate
&= ~NVREG_POWERSTATE2_POWERUP_MASK
;
5571 if ((id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_12
||
5572 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_13
) &&
5573 pci_dev
->revision
>= 0xA3)
5574 powerstate
|= NVREG_POWERSTATE2_POWERUP_REV_A3
;
5575 writel(powerstate
, base
+ NvRegPowerState2
);
5578 if (np
->desc_ver
== DESC_VER_1
) {
5579 np
->tx_flags
= NV_TX_VALID
;
5581 np
->tx_flags
= NV_TX2_VALID
;
5583 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
) {
5584 np
->irqmask
= NVREG_IRQMASK_THROUGHPUT
;
5585 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) /* set number of vectors */
5586 np
->msi_flags
|= 0x0003;
5588 np
->irqmask
= NVREG_IRQMASK_CPU
;
5589 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) /* set number of vectors */
5590 np
->msi_flags
|= 0x0001;
5593 if (id
->driver_data
& DEV_NEED_TIMERIRQ
)
5594 np
->irqmask
|= NVREG_IRQ_TIMER
;
5595 if (id
->driver_data
& DEV_NEED_LINKTIMER
) {
5596 dprintk(KERN_INFO
"%s: link timer on.\n", pci_name(pci_dev
));
5597 np
->need_linktimer
= 1;
5598 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
5600 dprintk(KERN_INFO
"%s: link timer off.\n", pci_name(pci_dev
));
5601 np
->need_linktimer
= 0;
5604 /* Limit the number of tx's outstanding for hw bug */
5605 if (id
->driver_data
& DEV_NEED_TX_LIMIT
) {
5607 if ((id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_32
||
5608 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_33
||
5609 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_34
||
5610 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_35
||
5611 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_36
||
5612 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_37
||
5613 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_38
||
5614 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_39
) &&
5615 pci_dev
->revision
>= 0xA2)
5619 /* clear phy state and temporarily halt phy interrupts */
5620 writel(0, base
+ NvRegMIIMask
);
5621 phystate
= readl(base
+ NvRegAdapterControl
);
5622 if (phystate
& NVREG_ADAPTCTL_RUNNING
) {
5624 phystate
&= ~NVREG_ADAPTCTL_RUNNING
;
5625 writel(phystate
, base
+ NvRegAdapterControl
);
5627 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5629 if (id
->driver_data
& DEV_HAS_MGMT_UNIT
) {
5630 /* management unit running on the mac? */
5631 if (readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_SYNC_PHY_INIT
) {
5632 np
->mac_in_use
= readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_MGMT_ST
;
5633 dprintk(KERN_INFO
"%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev
), np
->mac_in_use
);
5634 if (nv_mgmt_acquire_sema(dev
)) {
5635 /* management unit setup the phy already? */
5636 if ((readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_SYNC_MASK
) ==
5637 NVREG_XMITCTL_SYNC_PHY_INIT
) {
5638 /* phy is inited by mgmt unit */
5640 dprintk(KERN_INFO
"%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev
));
5642 /* we need to init the phy */
5648 /* find a suitable phy */
5649 for (i
= 1; i
<= 32; i
++) {
5651 int phyaddr
= i
& 0x1F;
5653 spin_lock_irq(&np
->lock
);
5654 id1
= mii_rw(dev
, phyaddr
, MII_PHYSID1
, MII_READ
);
5655 spin_unlock_irq(&np
->lock
);
5656 if (id1
< 0 || id1
== 0xffff)
5658 spin_lock_irq(&np
->lock
);
5659 id2
= mii_rw(dev
, phyaddr
, MII_PHYSID2
, MII_READ
);
5660 spin_unlock_irq(&np
->lock
);
5661 if (id2
< 0 || id2
== 0xffff)
5664 np
->phy_model
= id2
& PHYID2_MODEL_MASK
;
5665 id1
= (id1
& PHYID1_OUI_MASK
) << PHYID1_OUI_SHFT
;
5666 id2
= (id2
& PHYID2_OUI_MASK
) >> PHYID2_OUI_SHFT
;
5667 dprintk(KERN_DEBUG
"%s: open: Found PHY %04x:%04x at address %d.\n",
5668 pci_name(pci_dev
), id1
, id2
, phyaddr
);
5669 np
->phyaddr
= phyaddr
;
5670 np
->phy_oui
= id1
| id2
;
5672 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5673 if (np
->phy_oui
== PHY_OUI_REALTEK2
)
5674 np
->phy_oui
= PHY_OUI_REALTEK
;
5675 /* Setup phy revision for Realtek */
5676 if (np
->phy_oui
== PHY_OUI_REALTEK
&& np
->phy_model
== PHY_MODEL_REALTEK_8211
)
5677 np
->phy_rev
= mii_rw(dev
, phyaddr
, MII_RESV1
, MII_READ
) & PHY_REV_MASK
;
5682 dev_printk(KERN_INFO
, &pci_dev
->dev
,
5683 "open: Could not find a valid PHY.\n");
5687 if (!phyinitialized
) {
5691 /* see if it is a gigabit phy */
5692 u32 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
5693 if (mii_status
& PHY_GIGABIT
) {
5694 np
->gigabit
= PHY_GIGABIT
;
5698 /* set default link speed settings */
5699 np
->linkspeed
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
5703 err
= register_netdev(dev
);
5705 dev_printk(KERN_INFO
, &pci_dev
->dev
,
5706 "unable to register netdev: %d\n", err
);
5710 dev_printk(KERN_INFO
, &pci_dev
->dev
, "ifname %s, PHY OUI 0x%x @ %d, "
5711 "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5722 dev_printk(KERN_INFO
, &pci_dev
->dev
, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5723 dev
->features
& NETIF_F_HIGHDMA
? "highdma " : "",
5724 dev
->features
& (NETIF_F_HW_CSUM
| NETIF_F_SG
) ?
5726 dev
->features
& (NETIF_F_HW_VLAN_RX
| NETIF_F_HW_VLAN_TX
) ?
5728 id
->driver_data
& DEV_HAS_POWER_CNTRL
? "pwrctl " : "",
5729 id
->driver_data
& DEV_HAS_MGMT_UNIT
? "mgmt " : "",
5730 id
->driver_data
& DEV_NEED_TIMERIRQ
? "timirq " : "",
5731 np
->gigabit
== PHY_GIGABIT
? "gbit " : "",
5732 np
->need_linktimer
? "lnktim " : "",
5733 np
->msi_flags
& NV_MSI_CAPABLE
? "msi " : "",
5734 np
->msi_flags
& NV_MSI_X_CAPABLE
? "msi-x " : "",
5741 writel(phystate
|NVREG_ADAPTCTL_RUNNING
, base
+ NvRegAdapterControl
);
5742 pci_set_drvdata(pci_dev
, NULL
);
5746 iounmap(get_hwbase(dev
));
5748 pci_release_regions(pci_dev
);
5750 pci_disable_device(pci_dev
);
5757 static void nv_restore_phy(struct net_device
*dev
)
5759 struct fe_priv
*np
= netdev_priv(dev
);
5760 u16 phy_reserved
, mii_control
;
5762 if (np
->phy_oui
== PHY_OUI_REALTEK
&&
5763 np
->phy_model
== PHY_MODEL_REALTEK_8201
&&
5764 phy_cross
== NV_CROSSOVER_DETECTION_DISABLED
) {
5765 mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
);
5766 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, MII_READ
);
5767 phy_reserved
&= ~PHY_REALTEK_INIT_MSK1
;
5768 phy_reserved
|= PHY_REALTEK_INIT8
;
5769 mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, phy_reserved
);
5770 mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
);
5772 /* restart auto negotiation */
5773 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
5774 mii_control
|= (BMCR_ANRESTART
| BMCR_ANENABLE
);
5775 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
);
5779 static void __devexit
nv_remove(struct pci_dev
*pci_dev
)
5781 struct net_device
*dev
= pci_get_drvdata(pci_dev
);
5782 struct fe_priv
*np
= netdev_priv(dev
);
5783 u8 __iomem
*base
= get_hwbase(dev
);
5785 unregister_netdev(dev
);
5787 /* special op: write back the misordered MAC address - otherwise
5788 * the next nv_probe would see a wrong address.
5790 writel(np
->orig_mac
[0], base
+ NvRegMacAddrA
);
5791 writel(np
->orig_mac
[1], base
+ NvRegMacAddrB
);
5792 writel(readl(base
+ NvRegTransmitPoll
) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV
,
5793 base
+ NvRegTransmitPoll
);
5795 /* restore any phy related changes */
5796 nv_restore_phy(dev
);
5798 /* free all structures */
5800 iounmap(get_hwbase(dev
));
5801 pci_release_regions(pci_dev
);
5802 pci_disable_device(pci_dev
);
5804 pci_set_drvdata(pci_dev
, NULL
);
5808 static int nv_suspend(struct pci_dev
*pdev
, pm_message_t state
)
5810 struct net_device
*dev
= pci_get_drvdata(pdev
);
5811 struct fe_priv
*np
= netdev_priv(dev
);
5812 u8 __iomem
*base
= get_hwbase(dev
);
5815 if (netif_running(dev
)) {
5819 netif_device_detach(dev
);
5821 /* save non-pci configuration space */
5822 for (i
= 0;i
<= np
->register_size
/sizeof(u32
); i
++)
5823 np
->saved_config_space
[i
] = readl(base
+ i
*sizeof(u32
));
5825 pci_save_state(pdev
);
5826 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), np
->wolenabled
);
5827 pci_disable_device(pdev
);
5828 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
5832 static int nv_resume(struct pci_dev
*pdev
)
5834 struct net_device
*dev
= pci_get_drvdata(pdev
);
5835 struct fe_priv
*np
= netdev_priv(dev
);
5836 u8 __iomem
*base
= get_hwbase(dev
);
5839 pci_set_power_state(pdev
, PCI_D0
);
5840 pci_restore_state(pdev
);
5841 /* ack any pending wake events, disable PME */
5842 pci_enable_wake(pdev
, PCI_D0
, 0);
5844 /* restore non-pci configuration space */
5845 for (i
= 0;i
<= np
->register_size
/sizeof(u32
); i
++)
5846 writel(np
->saved_config_space
[i
], base
+i
*sizeof(u32
));
5848 netif_device_attach(dev
);
5849 if (netif_running(dev
)) {
5851 nv_set_multicast(dev
);
5856 static void nv_shutdown(struct pci_dev
*pdev
)
5858 struct net_device
*dev
= pci_get_drvdata(pdev
);
5859 struct fe_priv
*np
= netdev_priv(dev
);
5861 if (netif_running(dev
))
5864 pci_enable_wake(pdev
, PCI_D3hot
, np
->wolenabled
);
5865 pci_enable_wake(pdev
, PCI_D3cold
, np
->wolenabled
);
5866 pci_disable_device(pdev
);
5867 pci_set_power_state(pdev
, PCI_D3hot
);
5870 #define nv_suspend NULL
5871 #define nv_shutdown NULL
5872 #define nv_resume NULL
5873 #endif /* CONFIG_PM */
5875 static struct pci_device_id pci_tbl
[] = {
5876 { /* nForce Ethernet Controller */
5877 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_1
),
5878 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
5880 { /* nForce2 Ethernet Controller */
5881 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_2
),
5882 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
5884 { /* nForce3 Ethernet Controller */
5885 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_3
),
5886 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
5888 { /* nForce3 Ethernet Controller */
5889 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_4
),
5890 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
5892 { /* nForce3 Ethernet Controller */
5893 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_5
),
5894 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
5896 { /* nForce3 Ethernet Controller */
5897 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_6
),
5898 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
5900 { /* nForce3 Ethernet Controller */
5901 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_7
),
5902 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
5904 { /* CK804 Ethernet Controller */
5905 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_8
),
5906 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
5908 { /* CK804 Ethernet Controller */
5909 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_9
),
5910 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
5912 { /* MCP04 Ethernet Controller */
5913 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_10
),
5914 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
5916 { /* MCP04 Ethernet Controller */
5917 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_11
),
5918 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
5920 { /* MCP51 Ethernet Controller */
5921 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_12
),
5922 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_STATISTICS_V1
,
5924 { /* MCP51 Ethernet Controller */
5925 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_13
),
5926 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_STATISTICS_V1
,
5928 { /* MCP55 Ethernet Controller */
5929 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_14
),
5930 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_VLAN
|DEV_HAS_MSI
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_NEED_TX_LIMIT
,
5932 { /* MCP55 Ethernet Controller */
5933 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_15
),
5934 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_VLAN
|DEV_HAS_MSI
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_NEED_TX_LIMIT
,
5936 { /* MCP61 Ethernet Controller */
5937 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_16
),
5938 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
,
5940 { /* MCP61 Ethernet Controller */
5941 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_17
),
5942 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
,
5944 { /* MCP61 Ethernet Controller */
5945 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_18
),
5946 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
,
5948 { /* MCP61 Ethernet Controller */
5949 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_19
),
5950 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
,
5952 { /* MCP65 Ethernet Controller */
5953 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_20
),
5954 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
5956 { /* MCP65 Ethernet Controller */
5957 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_21
),
5958 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
5960 { /* MCP65 Ethernet Controller */
5961 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_22
),
5962 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
5964 { /* MCP65 Ethernet Controller */
5965 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_23
),
5966 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
5968 { /* MCP67 Ethernet Controller */
5969 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_24
),
5970 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
,
5972 { /* MCP67 Ethernet Controller */
5973 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_25
),
5974 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
,
5976 { /* MCP67 Ethernet Controller */
5977 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_26
),
5978 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
,
5980 { /* MCP67 Ethernet Controller */
5981 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_27
),
5982 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
,
5984 { /* MCP73 Ethernet Controller */
5985 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_28
),
5986 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
,
5988 { /* MCP73 Ethernet Controller */
5989 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_29
),
5990 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
,
5992 { /* MCP73 Ethernet Controller */
5993 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_30
),
5994 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
,
5996 { /* MCP73 Ethernet Controller */
5997 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_31
),
5998 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
,
6000 { /* MCP77 Ethernet Controller */
6001 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_32
),
6002 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6004 { /* MCP77 Ethernet Controller */
6005 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_33
),
6006 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6008 { /* MCP77 Ethernet Controller */
6009 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_34
),
6010 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6012 { /* MCP77 Ethernet Controller */
6013 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_35
),
6014 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6016 { /* MCP79 Ethernet Controller */
6017 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_36
),
6018 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6020 { /* MCP79 Ethernet Controller */
6021 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_37
),
6022 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6024 { /* MCP79 Ethernet Controller */
6025 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_38
),
6026 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6028 { /* MCP79 Ethernet Controller */
6029 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_39
),
6030 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6035 static struct pci_driver driver
= {
6037 .id_table
= pci_tbl
,
6039 .remove
= __devexit_p(nv_remove
),
6040 .suspend
= nv_suspend
,
6041 .resume
= nv_resume
,
6042 .shutdown
= nv_shutdown
,
6045 static int __init
init_nic(void)
6047 return pci_register_driver(&driver
);
6050 static void __exit
exit_nic(void)
6052 pci_unregister_driver(&driver
);
6055 module_param(max_interrupt_work
, int, 0);
6056 MODULE_PARM_DESC(max_interrupt_work
, "forcedeth maximum events handled per interrupt");
6057 module_param(optimization_mode
, int, 0);
6058 MODULE_PARM_DESC(optimization_mode
, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
6059 module_param(poll_interval
, int, 0);
6060 MODULE_PARM_DESC(poll_interval
, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6061 module_param(msi
, int, 0);
6062 MODULE_PARM_DESC(msi
, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6063 module_param(msix
, int, 0);
6064 MODULE_PARM_DESC(msix
, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6065 module_param(dma_64bit
, int, 0);
6066 MODULE_PARM_DESC(dma_64bit
, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6067 module_param(phy_cross
, int, 0);
6068 MODULE_PARM_DESC(phy_cross
, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6070 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6071 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6072 MODULE_LICENSE("GPL");
6074 MODULE_DEVICE_TABLE(pci
, pci_tbl
);
6076 module_init(init_nic
);
6077 module_exit(exit_nic
);