drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include "i915_reg.h"
  34 #include "intel_bios.h"
  35 #include <linux/io-mapping.h>
  36
  37 /* General customization:
  38  */
  39
  40 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  41
  42 #define DRIVER_NAME             "i915"
  43 #define DRIVER_DESC             "Intel Graphics"
  44 #define DRIVER_DATE             "20080730"
  45
  46 enum pipe {
  47         PIPE_A = 0,
  48         PIPE_B,
  49 };
  50
  51 #define I915_NUM_PIPE   2
  52
  53 /* Interface history:
  54  *
  55  * 1.1: Original.
  56  * 1.2: Add Power Management
  57  * 1.3: Add vblank support
  58  * 1.4: Fix cmdbuffer path, add heap destroy
  59  * 1.5: Add vblank pipe configuration
  60  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  61  *      - Support vertical blank on secondary display pipe
  62  */
  63 #define DRIVER_MAJOR            1
  64 #define DRIVER_MINOR            6
  65 #define DRIVER_PATCHLEVEL       0
  66
  67 #define WATCH_COHERENCY 0
  68 #define WATCH_BUF       0
  69 #define WATCH_EXEC      0
  70 #define WATCH_LRU       0
  71 #define WATCH_RELOC     0
  72 #define WATCH_INACTIVE  0
  73 #define WATCH_PWRITE    0
  74
  75 #define I915_GEM_PHYS_CURSOR_0 1
  76 #define I915_GEM_PHYS_CURSOR_1 2
  77 #define I915_GEM_PHYS_OVERLAY_REGS 3
  78 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
  79
  80 struct drm_i915_gem_phys_object {
  81         int id;
  82         struct page **page_list;
  83         drm_dma_handle_t *handle;
  84         struct drm_gem_object *cur_obj;
  85 };
  86
  87 typedef struct _drm_i915_ring_buffer {
  88         int tail_mask;
  89         unsigned long Size;
  90         u8 *virtual_start;
  91         int head;
  92         int tail;
  93         int space;
  94         drm_local_map_t map;
  95         struct drm_gem_object *ring_obj;
  96 } drm_i915_ring_buffer_t;
  97
  98 struct mem_block {
  99         struct mem_block *next;
 100         struct mem_block *prev;
 101         int start;
 102         int size;
 103         struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
 104 };
 105
 106 struct opregion_header;
 107 struct opregion_acpi;
 108 struct opregion_swsci;
 109 struct opregion_asle;
 110
 111 struct intel_opregion {
 112         struct opregion_header *header;
 113         struct opregion_acpi *acpi;
 114         struct opregion_swsci *swsci;
 115         struct opregion_asle *asle;
 116         int enabled;
 117 };
 118
 119 struct drm_i915_master_private {
 120         drm_local_map_t *sarea;
 121         struct _drm_i915_sarea *sarea_priv;
 122 };
 123 #define I915_FENCE_REG_NONE -1
 124
 125 struct drm_i915_fence_reg {
 126         struct drm_gem_object *obj;
 127 };
 128
 129 typedef struct drm_i915_private {
 130         struct drm_device *dev;
 131
 132         int has_gem;
 133
 134         void __iomem *regs;
 135
 136         drm_i915_ring_buffer_t ring;
 137
 138         drm_dma_handle_t *status_page_dmah;
 139         void *hw_status_page;
 140         dma_addr_t dma_status_page;
 141         uint32_t counter;
 142         unsigned int status_gfx_addr;
 143         drm_local_map_t hws_map;
 144         struct drm_gem_object *hws_obj;
 145
 146         unsigned int cpp;
 147         int back_offset;
 148         int front_offset;
 149         int current_page;
 150         int page_flipping;
 151
 152         wait_queue_head_t irq_queue;
 153         atomic_t irq_received;
 154         /** Protects user_irq_refcount and irq_mask_reg */
 155         spinlock_t user_irq_lock;
 156         /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
 157         int user_irq_refcount;
 158         /** Cached value of IMR to avoid reads in updating the bitfield */
 159         u32 irq_mask_reg;
 160         u32 pipestat[2];
 161
 162         u32 hotplug_supported_mask;
 163         struct work_struct hotplug_work;
 164
 165         int tex_lru_log_granularity;
 166         int allow_batchbuffer;
 167         struct mem_block *agp_heap;
 168         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
 169         int vblank_pipe;
 170
 171         bool cursor_needs_physical;
 172
 173         struct drm_mm vram;
 174
 175         int irq_enabled;
 176
 177         struct intel_opregion opregion;
 178
 179         /* LVDS info */
 180         int backlight_duty_cycle;  /* restore backlight to this value */
 181         bool panel_wants_dither;
 182         struct drm_display_mode *panel_fixed_mode;
 183         struct drm_display_mode *vbt_mode; /* if any */
 184
 185         /* Feature bits from the VBIOS */
 186         unsigned int int_tv_support:1;
 187         unsigned int lvds_dither:1;
 188         unsigned int lvds_vbt:1;
 189         unsigned int int_crt_support:1;
 190         unsigned int lvds_use_ssc:1;
 191         int lvds_ssc_freq;
 192
 193         struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
 194         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
 195         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 196
 197         /* Register state */
 198         u8 saveLBB;
 199         u32 saveDSPACNTR;
 200         u32 saveDSPBCNTR;
 201         u32 saveDSPARB;
 202         u32 saveRENDERSTANDBY;
 203         u32 saveHWS;
 204         u32 savePIPEACONF;
 205         u32 savePIPEBCONF;
 206         u32 savePIPEASRC;
 207         u32 savePIPEBSRC;
 208         u32 saveFPA0;
 209         u32 saveFPA1;
 210         u32 saveDPLL_A;
 211         u32 saveDPLL_A_MD;
 212         u32 saveHTOTAL_A;
 213         u32 saveHBLANK_A;
 214         u32 saveHSYNC_A;
 215         u32 saveVTOTAL_A;
 216         u32 saveVBLANK_A;
 217         u32 saveVSYNC_A;
 218         u32 saveBCLRPAT_A;
 219         u32 savePIPEASTAT;
 220         u32 saveDSPASTRIDE;
 221         u32 saveDSPASIZE;
 222         u32 saveDSPAPOS;
 223         u32 saveDSPAADDR;
 224         u32 saveDSPASURF;
 225         u32 saveDSPATILEOFF;
 226         u32 savePFIT_PGM_RATIOS;
 227         u32 saveBLC_PWM_CTL;
 228         u32 saveBLC_PWM_CTL2;
 229         u32 saveFPB0;
 230         u32 saveFPB1;
 231         u32 saveDPLL_B;
 232         u32 saveDPLL_B_MD;
 233         u32 saveHTOTAL_B;
 234         u32 saveHBLANK_B;
 235         u32 saveHSYNC_B;
 236         u32 saveVTOTAL_B;
 237         u32 saveVBLANK_B;
 238         u32 saveVSYNC_B;
 239         u32 saveBCLRPAT_B;
 240         u32 savePIPEBSTAT;
 241         u32 saveDSPBSTRIDE;
 242         u32 saveDSPBSIZE;
 243         u32 saveDSPBPOS;
 244         u32 saveDSPBADDR;
 245         u32 saveDSPBSURF;
 246         u32 saveDSPBTILEOFF;
 247         u32 saveVGA0;
 248         u32 saveVGA1;
 249         u32 saveVGA_PD;
 250         u32 saveVGACNTRL;
 251         u32 saveADPA;
 252         u32 saveLVDS;
 253         u32 savePP_ON_DELAYS;
 254         u32 savePP_OFF_DELAYS;
 255         u32 saveDVOA;
 256         u32 saveDVOB;
 257         u32 saveDVOC;
 258         u32 savePP_ON;
 259         u32 savePP_OFF;
 260         u32 savePP_CONTROL;
 261         u32 savePP_DIVISOR;
 262         u32 savePFIT_CONTROL;
 263         u32 save_palette_a[256];
 264         u32 save_palette_b[256];
 265         u32 saveFBC_CFB_BASE;
 266         u32 saveFBC_LL_BASE;
 267         u32 saveFBC_CONTROL;
 268         u32 saveFBC_CONTROL2;
 269         u32 saveIER;
 270         u32 saveIIR;
 271         u32 saveIMR;
 272         u32 saveCACHE_MODE_0;
 273         u32 saveD_STATE;
 274         u32 saveCG_2D_DIS;
 275         u32 saveMI_ARB_STATE;
 276         u32 saveSWF0[16];
 277         u32 saveSWF1[16];
 278         u32 saveSWF2[3];
 279         u8 saveMSR;
 280         u8 saveSR[8];
 281         u8 saveGR[25];
 282         u8 saveAR_INDEX;
 283         u8 saveAR[21];
 284         u8 saveDACMASK;
 285         u8 saveCR[37];
 286
 287         struct {
 288                 struct drm_mm gtt_space;
 289
 290                 struct io_mapping *gtt_mapping;
 291                 int gtt_mtrr;
 292
 293                 /**
 294                  * List of objects currently involved in rendering from the
 295                  * ringbuffer.
 296                  *
 297                  * Includes buffers having the contents of their GPU caches
 298                  * flushed, not necessarily primitives.  last_rendering_seqno
 299                  * represents when the rendering involved will be completed.
 300                  *
 301                  * A reference is held on the buffer while on this list.
 302                  */
 303                 spinlock_t active_list_lock;
 304                 struct list_head active_list;
 305
 306                 /**
 307                  * List of objects which are not in the ringbuffer but which
 308                  * still have a write_domain which needs to be flushed before
 309                  * unbinding.
 310                  *
 311                  * last_rendering_seqno is 0 while an object is in this list.
 312                  *
 313                  * A reference is held on the buffer while on this list.
 314                  */
 315                 struct list_head flushing_list;
 316
 317                 /**
 318                  * LRU list of objects which are not in the ringbuffer and
 319                  * are ready to unbind, but are still in the GTT.
 320                  *
 321                  * last_rendering_seqno is 0 while an object is in this list.
 322                  *
 323                  * A reference is not held on the buffer while on this list,
 324                  * as merely being GTT-bound shouldn't prevent its being
 325                  * freed, and we'll pull it off the list in the free path.
 326                  */
 327                 struct list_head inactive_list;
 328
 329                 /**
 330                  * List of breadcrumbs associated with GPU requests currently
 331                  * outstanding.
 332                  */
 333                 struct list_head request_list;
 334
 335                 /**
 336                  * We leave the user IRQ off as much as possible,
 337                  * but this means that requests will finish and never
 338                  * be retired once the system goes idle. Set a timer to
 339                  * fire periodically while the ring is running. When it
 340                  * fires, go retire requests.
 341                  */
 342                 struct delayed_work retire_work;
 343
 344                 uint32_t next_gem_seqno;
 345
 346                 /**
 347                  * Waiting sequence number, if any
 348                  */
 349                 uint32_t waiting_gem_seqno;
 350
 351                 /**
 352                  * Last seq seen at irq time
 353                  */
 354                 uint32_t irq_gem_seqno;
 355
 356                 /**
 357                  * Flag if the X Server, and thus DRM, is not currently in
 358                  * control of the device.
 359                  *
 360                  * This is set between LeaveVT and EnterVT.  It needs to be
 361                  * replaced with a semaphore.  It also needs to be
 362                  * transitioned away from for kernel modesetting.
 363                  */
 364                 int suspended;
 365
 366                 /**
 367                  * Flag if the hardware appears to be wedged.
 368                  *
 369                  * This is set when attempts to idle the device timeout.
 370                  * It prevents command submission from occuring and makes
 371                  * every pending request fail
 372                  */
 373                 int wedged;
 374
 375                 /** Bit 6 swizzling required for X tiling */
 376                 uint32_t bit_6_swizzle_x;
 377                 /** Bit 6 swizzling required for Y tiling */
 378                 uint32_t bit_6_swizzle_y;
 379
 380                 /* storage for physical objects */
 381                 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
 382         } mm;
 383 } drm_i915_private_t;
 384
 385 /** driver private structure attached to each drm_gem_object */
 386 struct drm_i915_gem_object {
 387         struct drm_gem_object *obj;
 388
 389         /** Current space allocated to this object in the GTT, if any. */
 390         struct drm_mm_node *gtt_space;
 391
 392         /** This object's place on the active/flushing/inactive lists */
 393         struct list_head list;
 394
 395         /**
 396          * This is set if the object is on the active or flushing lists
 397          * (has pending rendering), and is not set if it's on inactive (ready
 398          * to be unbound).
 399          */
 400         int active;
 401
 402         /**
 403          * This is set if the object has been written to since last bound
 404          * to the GTT
 405          */
 406         int dirty;
 407
 408         /** AGP memory structure for our GTT binding. */
 409         DRM_AGP_MEM *agp_mem;
 410
 411         struct page **pages;
 412         int pages_refcount;
 413
 414         /**
 415          * Current offset of the object in GTT space.
 416          *
 417          * This is the same as gtt_space->start
 418          */
 419         uint32_t gtt_offset;
 420         /**
 421          * Required alignment for the object
 422          */
 423         uint32_t gtt_alignment;
 424         /**
 425          * Fake offset for use by mmap(2)
 426          */
 427         uint64_t mmap_offset;
 428
 429         /**
 430          * Fence register bits (if any) for this object.  Will be set
 431          * as needed when mapped into the GTT.
 432          * Protected by dev->struct_mutex.
 433          */
 434         int fence_reg;
 435
 436         /** Boolean whether this object has a valid gtt offset. */
 437         int gtt_bound;
 438
 439         /** How many users have pinned this object in GTT space */
 440         int pin_count;
 441
 442         /** Breadcrumb of last rendering to the buffer. */
 443         uint32_t last_rendering_seqno;
 444
 445         /** Current tiling mode for the object. */
 446         uint32_t tiling_mode;
 447         uint32_t stride;
 448
 449         /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
 450         uint32_t agp_type;
 451
 452         /**
 453          * If present, while GEM_DOMAIN_CPU is in the read domain this array
 454          * flags which individual pages are valid.
 455          */
 456         uint8_t *page_cpu_valid;
 457
 458         /** User space pin count and filp owning the pin */
 459         uint32_t user_pin_count;
 460         struct drm_file *pin_filp;
 461
 462         /** for phy allocated objects */
 463         struct drm_i915_gem_phys_object *phys_obj;
 464
 465         /**
 466          * Used for checking the object doesn't appear more than once
 467          * in an execbuffer object list.
 468          */
 469         int in_execbuffer;
 470 };
 471
 472 /**
 473  * Request queue structure.
 474  *
 475  * The request queue allows us to note sequence numbers that have been emitted
 476  * and may be associated with active buffers to be retired.
 477  *
 478  * By keeping this list, we can avoid having to do questionable
 479  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
 480  * an emission time with seqnos for tracking how far ahead of the GPU we are.
 481  */
 482 struct drm_i915_gem_request {
 483         /** GEM sequence number associated with this request. */
 484         uint32_t seqno;
 485
 486         /** Time at which this request was emitted, in jiffies. */
 487         unsigned long emitted_jiffies;
 488
 489         struct list_head list;
 490 };
 491
 492 struct drm_i915_file_private {
 493         struct {
 494                 uint32_t last_gem_seqno;
 495                 uint32_t last_gem_throttle_seqno;
 496         } mm;
 497 };
 498
 499 enum intel_chip_family {
 500         CHIP_I8XX = 0x01,
 501         CHIP_I9XX = 0x02,
 502         CHIP_I915 = 0x04,
 503         CHIP_I965 = 0x08,
 504 };
 505
 506 extern struct drm_ioctl_desc i915_ioctls[];
 507 extern int i915_max_ioctl;
 508 extern unsigned int i915_fbpercrtc;
 509
 510 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
 511 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
 512
 513                                 /* i915_dma.c */
 514 extern void i915_kernel_lost_context(struct drm_device * dev);
 515 extern int i915_driver_load(struct drm_device *, unsigned long flags);
 516 extern int i915_driver_unload(struct drm_device *);
 517 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
 518 extern void i915_driver_lastclose(struct drm_device * dev);
 519 extern void i915_driver_preclose(struct drm_device *dev,
 520                                  struct drm_file *file_priv);
 521 extern void i915_driver_postclose(struct drm_device *dev,
 522                                   struct drm_file *file_priv);
 523 extern int i915_driver_device_is_agp(struct drm_device * dev);
 524 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
 525                               unsigned long arg);
 526 extern int i915_emit_box(struct drm_device *dev,
 527                          struct drm_clip_rect *boxes,
 528                          int i, int DR1, int DR4);
 529
 530 /* i915_irq.c */
 531 extern int i915_irq_emit(struct drm_device *dev, void *data,
 532                          struct drm_file *file_priv);
 533 extern int i915_irq_wait(struct drm_device *dev, void *data,
 534                          struct drm_file *file_priv);
 535 void i915_user_irq_get(struct drm_device *dev);
 536 void i915_user_irq_put(struct drm_device *dev);
 537 extern void i915_enable_interrupt (struct drm_device *dev);
 538
 539 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
 540 extern void i915_driver_irq_preinstall(struct drm_device * dev);
 541 extern int i915_driver_irq_postinstall(struct drm_device *dev);
 542 extern void i915_driver_irq_uninstall(struct drm_device * dev);
 543 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 544                                 struct drm_file *file_priv);
 545 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 546                                 struct drm_file *file_priv);
 547 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
 548 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
 549 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
 550 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
 551 extern int i915_vblank_swap(struct drm_device *dev, void *data,
 552                             struct drm_file *file_priv);
 553 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
 554
 555 void
 556 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
 557
 558 void
 559 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
 560
 561
 562 /* i915_mem.c */
 563 extern int i915_mem_alloc(struct drm_device *dev, void *data,
 564                           struct drm_file *file_priv);
 565 extern int i915_mem_free(struct drm_device *dev, void *data,
 566                          struct drm_file *file_priv);
 567 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
 568                               struct drm_file *file_priv);
 569 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
 570                                  struct drm_file *file_priv);
 571 extern void i915_mem_takedown(struct mem_block **heap);
 572 extern void i915_mem_release(struct drm_device * dev,
 573                              struct drm_file *file_priv, struct mem_block *heap);
 574 /* i915_gem.c */
 575 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
 576                         struct drm_file *file_priv);
 577 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
 578                           struct drm_file *file_priv);
 579 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 580                          struct drm_file *file_priv);
 581 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 582                           struct drm_file *file_priv);
 583 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
 584                         struct drm_file *file_priv);
 585 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
 586                         struct drm_file *file_priv);
 587 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 588                               struct drm_file *file_priv);
 589 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
 590                              struct drm_file *file_priv);
 591 int i915_gem_execbuffer(struct drm_device *dev, void *data,
 592                         struct drm_file *file_priv);
 593 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
 594                        struct drm_file *file_priv);
 595 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
 596                          struct drm_file *file_priv);
 597 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
 598                         struct drm_file *file_priv);
 599 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
 600                             struct drm_file *file_priv);
 601 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
 602                            struct drm_file *file_priv);
 603 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
 604                            struct drm_file *file_priv);
 605 int i915_gem_set_tiling(struct drm_device *dev, void *data,
 606                         struct drm_file *file_priv);
 607 int i915_gem_get_tiling(struct drm_device *dev, void *data,
 608                         struct drm_file *file_priv);
 609 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 610                                 struct drm_file *file_priv);
 611 void i915_gem_load(struct drm_device *dev);
 612 int i915_gem_init_object(struct drm_gem_object *obj);
 613 void i915_gem_free_object(struct drm_gem_object *obj);
 614 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
 615 void i915_gem_object_unpin(struct drm_gem_object *obj);
 616 int i915_gem_object_unbind(struct drm_gem_object *obj);
 617 void i915_gem_lastclose(struct drm_device *dev);
 618 uint32_t i915_get_gem_seqno(struct drm_device *dev);
 619 void i915_gem_retire_requests(struct drm_device *dev);
 620 void i915_gem_retire_work_handler(struct work_struct *work);
 621 void i915_gem_clflush_object(struct drm_gem_object *obj);
 622 int i915_gem_object_set_domain(struct drm_gem_object *obj,
 623                                uint32_t read_domains,
 624                                uint32_t write_domain);
 625 int i915_gem_init_ringbuffer(struct drm_device *dev);
 626 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
 627 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
 628                      unsigned long end);
 629 int i915_gem_idle(struct drm_device *dev);
 630 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
 631 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
 632                                       int write);
 633 int i915_gem_attach_phys_object(struct drm_device *dev,
 634                                 struct drm_gem_object *obj, int id);
 635 void i915_gem_detach_phys_object(struct drm_device *dev,
 636                                  struct drm_gem_object *obj);
 637 void i915_gem_free_all_phys_object(struct drm_device *dev);
 638
 639 /* i915_gem_tiling.c */
 640 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
 641
 642 /* i915_gem_debug.c */
 643 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
 644                           const char *where, uint32_t mark);
 645 #if WATCH_INACTIVE
 646 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
 647 #else
 648 #define i915_verify_inactive(dev, file, line)
 649 #endif
 650 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
 651 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
 652                           const char *where, uint32_t mark);
 653 void i915_dump_lru(struct drm_device *dev, const char *where);
 654
 655 /* i915_debugfs.c */
 656 int i915_gem_debugfs_init(struct drm_minor *minor);
 657 void i915_gem_debugfs_cleanup(struct drm_minor *minor);
 658
 659 /* i915_suspend.c */
 660 extern int i915_save_state(struct drm_device *dev);
 661 extern int i915_restore_state(struct drm_device *dev);
 662
 663 /* i915_suspend.c */
 664 extern int i915_save_state(struct drm_device *dev);
 665 extern int i915_restore_state(struct drm_device *dev);
 666
 667 #ifdef CONFIG_ACPI
 668 /* i915_opregion.c */
 669 extern int intel_opregion_init(struct drm_device *dev, int resume);
 670 extern void intel_opregion_free(struct drm_device *dev);
 671 extern void opregion_asle_intr(struct drm_device *dev);
 672 extern void opregion_enable_asle(struct drm_device *dev);
 673 #else
 674 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
 675 static inline void intel_opregion_free(struct drm_device *dev) { return; }
 676 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
 677 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
 678 #endif
 679
 680 /* modesetting */
 681 extern void intel_modeset_init(struct drm_device *dev);
 682 extern void intel_modeset_cleanup(struct drm_device *dev);
 683
 684 /**
 685  * Lock test for when it's just for synchronization of ring access.
 686  *
 687  * In that case, we don't need to do it when GEM is initialized as nobody else
 688  * has access to the ring.
 689  */
 690 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do {                 \
 691         if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
 692                 LOCK_TEST_WITH_RETURN(dev, file_priv);                  \
 693 } while (0)
 694
 695 #define I915_READ(reg)          readl(dev_priv->regs + (reg))
 696 #define I915_WRITE(reg, val)     writel(val, dev_priv->regs + (reg))
 697 #define I915_READ16(reg)        readw(dev_priv->regs + (reg))
 698 #define I915_WRITE16(reg, val)  writel(val, dev_priv->regs + (reg))
 699 #define I915_READ8(reg)         readb(dev_priv->regs + (reg))
 700 #define I915_WRITE8(reg, val)   writeb(val, dev_priv->regs + (reg))
 701 #ifdef writeq
 702 #define I915_WRITE64(reg, val)  writeq(val, dev_priv->regs + (reg))
 703 #else
 704 #define I915_WRITE64(reg, val)  (writel(val, dev_priv->regs + (reg)), \
 705                                  writel(upper_32_bits(val), dev_priv->regs + \
 706                                         (reg) + 4))
 707 #endif
 708 #define POSTING_READ(reg)       (void)I915_READ(reg)
 709
 710 #define I915_VERBOSE 0
 711
 712 #define RING_LOCALS     unsigned int outring, ringmask, outcount; \
 713                         volatile char *virt;
 714
 715 #define BEGIN_LP_RING(n) do {                           \
 716         if (I915_VERBOSE)                               \
 717                 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n));  \
 718         if (dev_priv->ring.space < (n)*4)               \
 719                 i915_wait_ring(dev, (n)*4, __func__);           \
 720         outcount = 0;                                   \
 721         outring = dev_priv->ring.tail;                  \
 722         ringmask = dev_priv->ring.tail_mask;            \
 723         virt = dev_priv->ring.virtual_start;            \
 724 } while (0)
 725
 726 #define OUT_RING(n) do {                                        \
 727         if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));      \
 728         *(volatile unsigned int *)(virt + outring) = (n);       \
 729         outcount++;                                             \
 730         outring += 4;                                           \
 731         outring &= ringmask;                                    \
 732 } while (0)
 733
 734 #define ADVANCE_LP_RING() do {                                          \
 735         if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);   \
 736         dev_priv->ring.tail = outring;                                  \
 737         dev_priv->ring.space -= outcount * 4;                           \
 738         I915_WRITE(PRB0_TAIL, outring);                 \
 739 } while(0)
 740
 741 /**
 742  * Reads a dword out of the status page, which is written to from the command
 743  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 744  * MI_STORE_DATA_IMM.
 745  *
 746  * The following dwords have a reserved meaning:
 747  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 748  * 0x04: ring 0 head pointer
 749  * 0x05: ring 1 head pointer (915-class)
 750  * 0x06: ring 2 head pointer (915-class)
 751  * 0x10-0x1b: Context status DWords (GM45)
 752  * 0x1f: Last written status offset. (GM45)
 753  *
 754  * The area from dword 0x20 to 0x3ff is available for driver usage.
 755  */
 756 #define READ_HWSP(dev_priv, reg)  (((volatile u32*)(dev_priv->hw_status_page))[reg])
 757 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
 758 #define I915_GEM_HWS_INDEX              0x20
 759 #define I915_BREADCRUMB_INDEX           0x21
 760
 761 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 762
 763 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
 764 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
 765 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
 766 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
 767 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
 768
 769 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
 770 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
 771 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
 772 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
 773                         (dev)->pci_device == 0x27AE)
 774 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
 775                        (dev)->pci_device == 0x2982 || \
 776                        (dev)->pci_device == 0x2992 || \
 777                        (dev)->pci_device == 0x29A2 || \
 778                        (dev)->pci_device == 0x2A02 || \
 779                        (dev)->pci_device == 0x2A12 || \
 780                        (dev)->pci_device == 0x2A42 || \
 781                        (dev)->pci_device == 0x2E02 || \
 782                        (dev)->pci_device == 0x2E12 || \
 783                        (dev)->pci_device == 0x2E22)
 784
 785 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
 786
 787 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
 788
 789 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
 790                      (dev)->pci_device == 0x2E12 || \
 791                      (dev)->pci_device == 0x2E22 || \
 792                      IS_GM45(dev))
 793
 794 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
 795 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
 796 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
 797
 798 #define IS_G33(dev)    ((dev)->pci_device == 0x29C2 ||  \
 799                         (dev)->pci_device == 0x29B2 ||  \
 800                         (dev)->pci_device == 0x29D2 ||  \
 801                         (IS_IGD(dev)))
 802
 803 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
 804                       IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
 805
 806 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
 807                         IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
 808                         IS_IGD(dev))
 809
 810 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
 811 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 812  * rows, which changed the alignment requirements and fence programming.
 813  */
 814 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
 815                                                       IS_I915GM(dev)))
 816 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev))
 817 #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev))
 818
 819 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
 820
 821 #endif