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arch/tile: various top-level Makefile cleanups
[linux-2.6/x86.git] / drivers / ata / sata_sx4.c
blobbedd5188e5b0d646c34da9e5ce20d6130a1c2381
1 /*
2 * sata_sx4.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware documentation available under NDA.
30 *
31 */
32
33 /*
34 Theory of operation
35 -------------------
36
37 The SX4 (PDC20621) chip features a single Host DMA (HDMA) copy
38 engine, DIMM memory, and four ATA engines (one per SATA port).
39 Data is copied to/from DIMM memory by the HDMA engine, before
40 handing off to one (or more) of the ATA engines. The ATA
41 engines operate solely on DIMM memory.
42
43 The SX4 behaves like a PATA chip, with no SATA controls or
44 knowledge whatsoever, leading to the presumption that
45 PATA<->SATA bridges exist on SX4 boards, external to the
46 PDC20621 chip itself.
47
48 The chip is quite capable, supporting an XOR engine and linked
49 hardware commands (permits a string to transactions to be
50 submitted and waited-on as a single unit), and an optional
51 microprocessor.
52
53 The limiting factor is largely software. This Linux driver was
54 written to multiplex the single HDMA engine to copy disk
55 transactions into a fixed DIMM memory space, from where an ATA
56 engine takes over. As a result, each WRITE looks like this:
57
58 submit HDMA packet to hardware
59 hardware copies data from system memory to DIMM
60 hardware raises interrupt
61
62 submit ATA packet to hardware
63 hardware executes ATA WRITE command, w/ data in DIMM
64 hardware raises interrupt
65
66 and each READ looks like this:
67
68 submit ATA packet to hardware
69 hardware executes ATA READ command, w/ data in DIMM
70 hardware raises interrupt
71
72 submit HDMA packet to hardware
73 hardware copies data from DIMM to system memory
74 hardware raises interrupt
75
76 This is a very slow, lock-step way of doing things that can
77 certainly be improved by motivated kernel hackers.
78
79 */
80
81 #include <linux/kernel.h>
82 #include <linux/module.h>
83 #include <linux/pci.h>
84 #include <linux/slab.h>
85 #include <linux/init.h>
86 #include <linux/blkdev.h>
87 #include <linux/delay.h>
88 #include <linux/interrupt.h>
89 #include <linux/device.h>
90 #include <scsi/scsi_host.h>
91 #include <scsi/scsi_cmnd.h>
92 #include <linux/libata.h>
93 #include "sata_promise.h"
94
95 #define DRV_NAME "sata_sx4"
96 #define DRV_VERSION "0.12"
97
98
99 enum {
100 PDC_MMIO_BAR = 3,
101 PDC_DIMM_BAR = 4,
102
103 PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */
104
105 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
106 PDC_HDMA_PKT_SUBMIT = 0x100, /* Host DMA packet pointer addr */
107 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
108 PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */
109
110 PDC_CTLSTAT = 0x60, /* IDEn control / status */
111
112 PDC_20621_SEQCTL = 0x400,
113 PDC_20621_SEQMASK = 0x480,
114 PDC_20621_GENERAL_CTL = 0x484,
115 PDC_20621_PAGE_SIZE = (32 * 1024),
116
117 /* chosen, not constant, values; we design our own DIMM mem map */
118 PDC_20621_DIMM_WINDOW = 0x0C, /* page# for 32K DIMM window */
119 PDC_20621_DIMM_BASE = 0x00200000,
120 PDC_20621_DIMM_DATA = (64 * 1024),
121 PDC_DIMM_DATA_STEP = (256 * 1024),
122 PDC_DIMM_WINDOW_STEP = (8 * 1024),
123 PDC_DIMM_HOST_PRD = (6 * 1024),
124 PDC_DIMM_HOST_PKT = (128 * 0),
125 PDC_DIMM_HPKT_PRD = (128 * 1),
126 PDC_DIMM_ATA_PKT = (128 * 2),
127 PDC_DIMM_APKT_PRD = (128 * 3),
128 PDC_DIMM_HEADER_SZ = PDC_DIMM_APKT_PRD + 128,
129 PDC_PAGE_WINDOW = 0x40,
130 PDC_PAGE_DATA = PDC_PAGE_WINDOW +
131 (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
132 PDC_PAGE_SET = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
133
134 PDC_CHIP0_OFS = 0xC0000, /* offset of chip #0 */
135
136 PDC_20621_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
137 (1<<23),
138
139 board_20621 = 0, /* FastTrak S150 SX4 */
140
141 PDC_MASK_INT = (1 << 10), /* HDMA/ATA mask int */
142 PDC_RESET = (1 << 11), /* HDMA/ATA reset */
143 PDC_DMA_ENABLE = (1 << 7), /* DMA start/stop */
144
145 PDC_MAX_HDMA = 32,
146 PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1),
147
148 PDC_DIMM0_SPD_DEV_ADDRESS = 0x50,
149 PDC_DIMM1_SPD_DEV_ADDRESS = 0x51,
150 PDC_I2C_CONTROL = 0x48,
151 PDC_I2C_ADDR_DATA = 0x4C,
152 PDC_DIMM0_CONTROL = 0x80,
153 PDC_DIMM1_CONTROL = 0x84,
154 PDC_SDRAM_CONTROL = 0x88,
155 PDC_I2C_WRITE = 0, /* master -> slave */
156 PDC_I2C_READ = (1 << 6), /* master <- slave */
157 PDC_I2C_START = (1 << 7), /* start I2C proto */
158 PDC_I2C_MASK_INT = (1 << 5), /* mask I2C interrupt */
159 PDC_I2C_COMPLETE = (1 << 16), /* I2C normal compl. */
160 PDC_I2C_NO_ACK = (1 << 20), /* slave no-ack addr */
161 PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
162 PDC_DIMM_SPD_SUBADDRESS_END = 0x7F,
163 PDC_DIMM_SPD_ROW_NUM = 3,
164 PDC_DIMM_SPD_COLUMN_NUM = 4,
165 PDC_DIMM_SPD_MODULE_ROW = 5,
166 PDC_DIMM_SPD_TYPE = 11,
167 PDC_DIMM_SPD_FRESH_RATE = 12,
168 PDC_DIMM_SPD_BANK_NUM = 17,
169 PDC_DIMM_SPD_CAS_LATENCY = 18,
170 PDC_DIMM_SPD_ATTRIBUTE = 21,
171 PDC_DIMM_SPD_ROW_PRE_CHARGE = 27,
172 PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
173 PDC_DIMM_SPD_RAS_CAS_DELAY = 29,
174 PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
175 PDC_DIMM_SPD_SYSTEM_FREQ = 126,
176 PDC_CTL_STATUS = 0x08,
177 PDC_DIMM_WINDOW_CTLR = 0x0C,
178 PDC_TIME_CONTROL = 0x3C,
179 PDC_TIME_PERIOD = 0x40,
180 PDC_TIME_COUNTER = 0x44,
181 PDC_GENERAL_CTLR = 0x484,
182 PCI_PLL_INIT = 0x8A531824,
183 PCI_X_TCOUNT = 0xEE1E5CFF,
184
185 /* PDC_TIME_CONTROL bits */
186 PDC_TIMER_BUZZER = (1 << 10),
187 PDC_TIMER_MODE_PERIODIC = 0, /* bits 9:8 == 00 */
188 PDC_TIMER_MODE_ONCE = (1 << 8), /* bits 9:8 == 01 */
189 PDC_TIMER_ENABLE = (1 << 7),
190 PDC_TIMER_MASK_INT = (1 << 5),
191 PDC_TIMER_SEQ_MASK = 0x1f, /* SEQ ID for timer */
192 PDC_TIMER_DEFAULT = PDC_TIMER_MODE_ONCE |
193 PDC_TIMER_ENABLE |
194 PDC_TIMER_MASK_INT,
195 };
196
197 #define ECC_ERASE_BUF_SZ (128 * 1024)
198
199 struct pdc_port_priv {
200 u8 dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
201 u8 *pkt;
202 dma_addr_t pkt_dma;
203 };
204
205 struct pdc_host_priv {
206 unsigned int doing_hdma;
207 unsigned int hdma_prod;
208 unsigned int hdma_cons;
209 struct {
210 struct ata_queued_cmd *qc;
211 unsigned int seq;
212 unsigned long pkt_ofs;
213 } hdma[32];
214 };
215
216
217 static int pdc_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
218 static void pdc_error_handler(struct ata_port *ap);
219 static void pdc_freeze(struct ata_port *ap);
220 static void pdc_thaw(struct ata_port *ap);
221 static int pdc_port_start(struct ata_port *ap);
222 static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
223 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
224 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
225 static unsigned int pdc20621_dimm_init(struct ata_host *host);
226 static int pdc20621_detect_dimm(struct ata_host *host);
227 static unsigned int pdc20621_i2c_read(struct ata_host *host,
228 u32 device, u32 subaddr, u32 *pdata);
229 static int pdc20621_prog_dimm0(struct ata_host *host);
230 static unsigned int pdc20621_prog_dimm_global(struct ata_host *host);
231 #ifdef ATA_VERBOSE_DEBUG
232 static void pdc20621_get_from_dimm(struct ata_host *host,
233 void *psource, u32 offset, u32 size);
234 #endif
235 static void pdc20621_put_to_dimm(struct ata_host *host,
236 void *psource, u32 offset, u32 size);
237 static void pdc20621_irq_clear(struct ata_port *ap);
238 static unsigned int pdc20621_qc_issue(struct ata_queued_cmd *qc);
239 static int pdc_softreset(struct ata_link *link, unsigned int *class,
240 unsigned long deadline);
241 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
242 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
243
244
245 static struct scsi_host_template pdc_sata_sht = {
246 ATA_BASE_SHT(DRV_NAME),
247 .sg_tablesize = LIBATA_MAX_PRD,
248 .dma_boundary = ATA_DMA_BOUNDARY,
249 };
250
251 /* TODO: inherit from base port_ops after converting to new EH */
252 static struct ata_port_operations pdc_20621_ops = {
253 .inherits = &ata_sff_port_ops,
254
255 .check_atapi_dma = pdc_check_atapi_dma,
256 .qc_prep = pdc20621_qc_prep,
257 .qc_issue = pdc20621_qc_issue,
258
259 .freeze = pdc_freeze,
260 .thaw = pdc_thaw,
261 .softreset = pdc_softreset,
262 .error_handler = pdc_error_handler,
263 .lost_interrupt = ATA_OP_NULL,
264 .post_internal_cmd = pdc_post_internal_cmd,
265
266 .port_start = pdc_port_start,
267
268 .sff_tf_load = pdc_tf_load_mmio,
269 .sff_exec_command = pdc_exec_command_mmio,
270 .sff_irq_clear = pdc20621_irq_clear,
271 };
272
273 static const struct ata_port_info pdc_port_info[] = {
274 /* board_20621 */
275 {
276 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
277 ATA_FLAG_SRST | ATA_FLAG_MMIO |
278 ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING,
279 .pio_mask = ATA_PIO4,
280 .mwdma_mask = ATA_MWDMA2,
281 .udma_mask = ATA_UDMA6,
282 .port_ops = &pdc_20621_ops,
283 },
284
285 };
286
287 static const struct pci_device_id pdc_sata_pci_tbl[] = {
288 { PCI_VDEVICE(PROMISE, 0x6622), board_20621 },
289
290 { } /* terminate list */
291 };
292
293 static struct pci_driver pdc_sata_pci_driver = {
294 .name = DRV_NAME,
295 .id_table = pdc_sata_pci_tbl,
296 .probe = pdc_sata_init_one,
297 .remove = ata_pci_remove_one,
298 };
299
300
301 static int pdc_port_start(struct ata_port *ap)
302 {
303 struct device *dev = ap->host->dev;
304 struct pdc_port_priv *pp;
305
306 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
307 if (!pp)
308 return -ENOMEM;
309
310 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
311 if (!pp->pkt)
312 return -ENOMEM;
313
314 ap->private_data = pp;
315
316 return 0;
317 }
318
319 static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
320 unsigned int portno,
321 unsigned int total_len)
322 {
323 u32 addr;
324 unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
325 __le32 *buf32 = (__le32 *) buf;
326
327 /* output ATA packet S/G table */
328 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
329 (PDC_DIMM_DATA_STEP * portno);
330 VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
331 buf32[dw] = cpu_to_le32(addr);
332 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
333
334 VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
335 PDC_20621_DIMM_BASE +
336 (PDC_DIMM_WINDOW_STEP * portno) +
337 PDC_DIMM_APKT_PRD,
338 buf32[dw], buf32[dw + 1]);
339 }
340
341 static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
342 unsigned int portno,
343 unsigned int total_len)
344 {
345 u32 addr;
346 unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
347 __le32 *buf32 = (__le32 *) buf;
348
349 /* output Host DMA packet S/G table */
350 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
351 (PDC_DIMM_DATA_STEP * portno);
352
353 buf32[dw] = cpu_to_le32(addr);
354 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
355
356 VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
357 PDC_20621_DIMM_BASE +
358 (PDC_DIMM_WINDOW_STEP * portno) +
359 PDC_DIMM_HPKT_PRD,
360 buf32[dw], buf32[dw + 1]);
361 }
362
363 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
364 unsigned int devno, u8 *buf,
365 unsigned int portno)
366 {
367 unsigned int i, dw;
368 __le32 *buf32 = (__le32 *) buf;
369 u8 dev_reg;
370
371 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
372 (PDC_DIMM_WINDOW_STEP * portno) +
373 PDC_DIMM_APKT_PRD;
374 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
375
376 i = PDC_DIMM_ATA_PKT;
377
378 /*
379 * Set up ATA packet
380 */
381 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
382 buf[i++] = PDC_PKT_READ;
383 else if (tf->protocol == ATA_PROT_NODATA)
384 buf[i++] = PDC_PKT_NODATA;
385 else
386 buf[i++] = 0;
387 buf[i++] = 0; /* reserved */
388 buf[i++] = portno + 1; /* seq. id */
389 buf[i++] = 0xff; /* delay seq. id */
390
391 /* dimm dma S/G, and next-pkt */
392 dw = i >> 2;
393 if (tf->protocol == ATA_PROT_NODATA)
394 buf32[dw] = 0;
395 else
396 buf32[dw] = cpu_to_le32(dimm_sg);
397 buf32[dw + 1] = 0;
398 i += 8;
399
400 if (devno == 0)
401 dev_reg = ATA_DEVICE_OBS;
402 else
403 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
404
405 /* select device */
406 buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
407 buf[i++] = dev_reg;
408
409 /* device control register */
410 buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
411 buf[i++] = tf->ctl;
412
413 return i;
414 }
415
416 static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
417 unsigned int portno)
418 {
419 unsigned int dw;
420 u32 tmp;
421 __le32 *buf32 = (__le32 *) buf;
422
423 unsigned int host_sg = PDC_20621_DIMM_BASE +
424 (PDC_DIMM_WINDOW_STEP * portno) +
425 PDC_DIMM_HOST_PRD;
426 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
427 (PDC_DIMM_WINDOW_STEP * portno) +
428 PDC_DIMM_HPKT_PRD;
429 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
430 VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
431
432 dw = PDC_DIMM_HOST_PKT >> 2;
433
434 /*
435 * Set up Host DMA packet
436 */
437 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
438 tmp = PDC_PKT_READ;
439 else
440 tmp = 0;
441 tmp |= ((portno + 1 + 4) << 16); /* seq. id */
442 tmp |= (0xff << 24); /* delay seq. id */
443 buf32[dw + 0] = cpu_to_le32(tmp);
444 buf32[dw + 1] = cpu_to_le32(host_sg);
445 buf32[dw + 2] = cpu_to_le32(dimm_sg);
446 buf32[dw + 3] = 0;
447
448 VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
449 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
450 PDC_DIMM_HOST_PKT,
451 buf32[dw + 0],
452 buf32[dw + 1],
453 buf32[dw + 2],
454 buf32[dw + 3]);
455 }
456
457 static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
458 {
459 struct scatterlist *sg;
460 struct ata_port *ap = qc->ap;
461 struct pdc_port_priv *pp = ap->private_data;
462 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
463 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
464 unsigned int portno = ap->port_no;
465 unsigned int i, si, idx, total_len = 0, sgt_len;
466 __le32 *buf = (__le32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
467
468 WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
469
470 VPRINTK("ata%u: ENTER\n", ap->print_id);
471
472 /* hard-code chip #0 */
473 mmio += PDC_CHIP0_OFS;
474
475 /*
476 * Build S/G table
477 */
478 idx = 0;
479 for_each_sg(qc->sg, sg, qc->n_elem, si) {
480 buf[idx++] = cpu_to_le32(sg_dma_address(sg));
481 buf[idx++] = cpu_to_le32(sg_dma_len(sg));
482 total_len += sg_dma_len(sg);
483 }
484 buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
485 sgt_len = idx * 4;
486
487 /*
488 * Build ATA, host DMA packets
489 */
490 pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
491 pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
492
493 pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
494 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
495
496 if (qc->tf.flags & ATA_TFLAG_LBA48)
497 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
498 else
499 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
500
501 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
502
503 /* copy three S/G tables and two packets to DIMM MMIO window */
504 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
505 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
506 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
507 PDC_DIMM_HOST_PRD,
508 &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
509
510 /* force host FIFO dump */
511 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
512
513 readl(dimm_mmio); /* MMIO PCI posting flush */
514
515 VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
516 }
517
518 static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
519 {
520 struct ata_port *ap = qc->ap;
521 struct pdc_port_priv *pp = ap->private_data;
522 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
523 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
524 unsigned int portno = ap->port_no;
525 unsigned int i;
526
527 VPRINTK("ata%u: ENTER\n", ap->print_id);
528
529 /* hard-code chip #0 */
530 mmio += PDC_CHIP0_OFS;
531
532 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
533
534 if (qc->tf.flags & ATA_TFLAG_LBA48)
535 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
536 else
537 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
538
539 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
540
541 /* copy three S/G tables and two packets to DIMM MMIO window */
542 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
543 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
544
545 /* force host FIFO dump */
546 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
547
548 readl(dimm_mmio); /* MMIO PCI posting flush */
549
550 VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
551 }
552
553 static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
554 {
555 switch (qc->tf.protocol) {
556 case ATA_PROT_DMA:
557 pdc20621_dma_prep(qc);
558 break;
559 case ATA_PROT_NODATA:
560 pdc20621_nodata_prep(qc);
561 break;
562 default:
563 break;
564 }
565 }
566
567 static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
568 unsigned int seq,
569 u32 pkt_ofs)
570 {
571 struct ata_port *ap = qc->ap;
572 struct ata_host *host = ap->host;
573 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
574
575 /* hard-code chip #0 */
576 mmio += PDC_CHIP0_OFS;
577
578 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
579 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
580
581 writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
582 readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */
583 }
584
585 static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
586 unsigned int seq,
587 u32 pkt_ofs)
588 {
589 struct ata_port *ap = qc->ap;
590 struct pdc_host_priv *pp = ap->host->private_data;
591 unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
592
593 if (!pp->doing_hdma) {
594 __pdc20621_push_hdma(qc, seq, pkt_ofs);
595 pp->doing_hdma = 1;
596 return;
597 }
598
599 pp->hdma[idx].qc = qc;
600 pp->hdma[idx].seq = seq;
601 pp->hdma[idx].pkt_ofs = pkt_ofs;
602 pp->hdma_prod++;
603 }
604
605 static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
606 {
607 struct ata_port *ap = qc->ap;
608 struct pdc_host_priv *pp = ap->host->private_data;
609 unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
610
611 /* if nothing on queue, we're done */
612 if (pp->hdma_prod == pp->hdma_cons) {
613 pp->doing_hdma = 0;
614 return;
615 }
616
617 __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
618 pp->hdma[idx].pkt_ofs);
619 pp->hdma_cons++;
620 }
621
622 #ifdef ATA_VERBOSE_DEBUG
623 static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
624 {
625 struct ata_port *ap = qc->ap;
626 unsigned int port_no = ap->port_no;
627 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
628
629 dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
630 dimm_mmio += PDC_DIMM_HOST_PKT;
631
632 printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
633 printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
634 printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
635 printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
636 }
637 #else
638 static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
639 #endif /* ATA_VERBOSE_DEBUG */
640
641 static void pdc20621_packet_start(struct ata_queued_cmd *qc)
642 {
643 struct ata_port *ap = qc->ap;
644 struct ata_host *host = ap->host;
645 unsigned int port_no = ap->port_no;
646 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
647 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
648 u8 seq = (u8) (port_no + 1);
649 unsigned int port_ofs;
650
651 /* hard-code chip #0 */
652 mmio += PDC_CHIP0_OFS;
653
654 VPRINTK("ata%u: ENTER\n", ap->print_id);
655
656 wmb(); /* flush PRD, pkt writes */
657
658 port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
659
660 /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
661 if (rw && qc->tf.protocol == ATA_PROT_DMA) {
662 seq += 4;
663
664 pdc20621_dump_hdma(qc);
665 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
666 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
667 port_ofs + PDC_DIMM_HOST_PKT,
668 port_ofs + PDC_DIMM_HOST_PKT,
669 seq);
670 } else {
671 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
672 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
673
674 writel(port_ofs + PDC_DIMM_ATA_PKT,
675 ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
676 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
677 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
678 port_ofs + PDC_DIMM_ATA_PKT,
679 port_ofs + PDC_DIMM_ATA_PKT,
680 seq);
681 }
682 }
683
684 static unsigned int pdc20621_qc_issue(struct ata_queued_cmd *qc)
685 {
686 switch (qc->tf.protocol) {
687 case ATA_PROT_NODATA:
688 if (qc->tf.flags & ATA_TFLAG_POLLING)
689 break;
690 /*FALLTHROUGH*/
691 case ATA_PROT_DMA:
692 pdc20621_packet_start(qc);
693 return 0;
694
695 case ATAPI_PROT_DMA:
696 BUG();
697 break;
698
699 default:
700 break;
701 }
702
703 return ata_sff_qc_issue(qc);
704 }
705
706 static inline unsigned int pdc20621_host_intr(struct ata_port *ap,
707 struct ata_queued_cmd *qc,
708 unsigned int doing_hdma,
709 void __iomem *mmio)
710 {
711 unsigned int port_no = ap->port_no;
712 unsigned int port_ofs =
713 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
714 u8 status;
715 unsigned int handled = 0;
716
717 VPRINTK("ENTER\n");
718
719 if ((qc->tf.protocol == ATA_PROT_DMA) && /* read */
720 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
721
722 /* step two - DMA from DIMM to host */
723 if (doing_hdma) {
724 VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->print_id,
725 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
726 /* get drive status; clear intr; complete txn */
727 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
728 ata_qc_complete(qc);
729 pdc20621_pop_hdma(qc);
730 }
731
732 /* step one - exec ATA command */
733 else {
734 u8 seq = (u8) (port_no + 1 + 4);
735 VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->print_id,
736 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
737
738 /* submit hdma pkt */
739 pdc20621_dump_hdma(qc);
740 pdc20621_push_hdma(qc, seq,
741 port_ofs + PDC_DIMM_HOST_PKT);
742 }
743 handled = 1;
744
745 } else if (qc->tf.protocol == ATA_PROT_DMA) { /* write */
746
747 /* step one - DMA from host to DIMM */
748 if (doing_hdma) {
749 u8 seq = (u8) (port_no + 1);
750 VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->print_id,
751 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
752
753 /* submit ata pkt */
754 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
755 readl(mmio + PDC_20621_SEQCTL + (seq * 4));
756 writel(port_ofs + PDC_DIMM_ATA_PKT,
757 ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
758 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
759 }
760
761 /* step two - execute ATA command */
762 else {
763 VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->print_id,
764 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
765 /* get drive status; clear intr; complete txn */
766 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
767 ata_qc_complete(qc);
768 pdc20621_pop_hdma(qc);
769 }
770 handled = 1;
771
772 /* command completion, but no data xfer */
773 } else if (qc->tf.protocol == ATA_PROT_NODATA) {
774
775 status = ata_sff_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
776 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
777 qc->err_mask |= ac_err_mask(status);
778 ata_qc_complete(qc);
779 handled = 1;
780
781 } else {
782 ap->stats.idle_irq++;
783 }
784
785 return handled;
786 }
787
788 static void pdc20621_irq_clear(struct ata_port *ap)
789 {
790 ioread8(ap->ioaddr.status_addr);
791 }
792
793 static irqreturn_t pdc20621_interrupt(int irq, void *dev_instance)
794 {
795 struct ata_host *host = dev_instance;
796 struct ata_port *ap;
797 u32 mask = 0;
798 unsigned int i, tmp, port_no;
799 unsigned int handled = 0;
800 void __iomem *mmio_base;
801
802 VPRINTK("ENTER\n");
803
804 if (!host || !host->iomap[PDC_MMIO_BAR]) {
805 VPRINTK("QUICK EXIT\n");
806 return IRQ_NONE;
807 }
808
809 mmio_base = host->iomap[PDC_MMIO_BAR];
810
811 /* reading should also clear interrupts */
812 mmio_base += PDC_CHIP0_OFS;
813 mask = readl(mmio_base + PDC_20621_SEQMASK);
814 VPRINTK("mask == 0x%x\n", mask);
815
816 if (mask == 0xffffffff) {
817 VPRINTK("QUICK EXIT 2\n");
818 return IRQ_NONE;
819 }
820 mask &= 0xffff; /* only 16 tags possible */
821 if (!mask) {
822 VPRINTK("QUICK EXIT 3\n");
823 return IRQ_NONE;
824 }
825
826 spin_lock(&host->lock);
827
828 for (i = 1; i < 9; i++) {
829 port_no = i - 1;
830 if (port_no > 3)
831 port_no -= 4;
832 if (port_no >= host->n_ports)
833 ap = NULL;
834 else
835 ap = host->ports[port_no];
836 tmp = mask & (1 << i);
837 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
838 if (tmp && ap) {
839 struct ata_queued_cmd *qc;
840
841 qc = ata_qc_from_tag(ap, ap->link.active_tag);
842 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
843 handled += pdc20621_host_intr(ap, qc, (i > 4),
844 mmio_base);
845 }
846 }
847
848 spin_unlock(&host->lock);
849
850 VPRINTK("mask == 0x%x\n", mask);
851
852 VPRINTK("EXIT\n");
853
854 return IRQ_RETVAL(handled);
855 }
856
857 static void pdc_freeze(struct ata_port *ap)
858 {
859 void __iomem *mmio = ap->ioaddr.cmd_addr;
860 u32 tmp;
861
862 /* FIXME: if all 4 ATA engines are stopped, also stop HDMA engine */
863
864 tmp = readl(mmio + PDC_CTLSTAT);
865 tmp |= PDC_MASK_INT;
866 tmp &= ~PDC_DMA_ENABLE;
867 writel(tmp, mmio + PDC_CTLSTAT);
868 readl(mmio + PDC_CTLSTAT); /* flush */
869 }
870
871 static void pdc_thaw(struct ata_port *ap)
872 {
873 void __iomem *mmio = ap->ioaddr.cmd_addr;
874 u32 tmp;
875
876 /* FIXME: start HDMA engine, if zero ATA engines running */
877
878 /* clear IRQ */
879 ioread8(ap->ioaddr.status_addr);
880
881 /* turn IRQ back on */
882 tmp = readl(mmio + PDC_CTLSTAT);
883 tmp &= ~PDC_MASK_INT;
884 writel(tmp, mmio + PDC_CTLSTAT);
885 readl(mmio + PDC_CTLSTAT); /* flush */
886 }
887
888 static void pdc_reset_port(struct ata_port *ap)
889 {
890 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
891 unsigned int i;
892 u32 tmp;
893
894 /* FIXME: handle HDMA copy engine */
895
896 for (i = 11; i > 0; i--) {
897 tmp = readl(mmio);
898 if (tmp & PDC_RESET)
899 break;
900
901 udelay(100);
902
903 tmp |= PDC_RESET;
904 writel(tmp, mmio);
905 }
906
907 tmp &= ~PDC_RESET;
908 writel(tmp, mmio);
909 readl(mmio); /* flush */
910 }
911
912 static int pdc_softreset(struct ata_link *link, unsigned int *class,
913 unsigned long deadline)
914 {
915 pdc_reset_port(link->ap);
916 return ata_sff_softreset(link, class, deadline);
917 }
918
919 static void pdc_error_handler(struct ata_port *ap)
920 {
921 if (!(ap->pflags & ATA_PFLAG_FROZEN))
922 pdc_reset_port(ap);
923
924 ata_sff_error_handler(ap);
925 }
926
927 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
928 {
929 struct ata_port *ap = qc->ap;
930
931 /* make DMA engine forget about the failed command */
932 if (qc->flags & ATA_QCFLAG_FAILED)
933 pdc_reset_port(ap);
934 }
935
936 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
937 {
938 u8 *scsicmd = qc->scsicmd->cmnd;
939 int pio = 1; /* atapi dma off by default */
940
941 /* Whitelist commands that may use DMA. */
942 switch (scsicmd[0]) {
943 case WRITE_12:
944 case WRITE_10:
945 case WRITE_6:
946 case READ_12:
947 case READ_10:
948 case READ_6:
949 case 0xad: /* READ_DVD_STRUCTURE */
950 case 0xbe: /* READ_CD */
951 pio = 0;
952 }
953 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
954 if (scsicmd[0] == WRITE_10) {
955 unsigned int lba =
956 (scsicmd[2] << 24) |
957 (scsicmd[3] << 16) |
958 (scsicmd[4] << 8) |
959 scsicmd[5];
960 if (lba >= 0xFFFF4FA2)
961 pio = 1;
962 }
963 return pio;
964 }
965
966 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
967 {
968 WARN_ON(tf->protocol == ATA_PROT_DMA ||
969 tf->protocol == ATAPI_PROT_DMA);
970 ata_sff_tf_load(ap, tf);
971 }
972
973
974 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
975 {
976 WARN_ON(tf->protocol == ATA_PROT_DMA ||
977 tf->protocol == ATAPI_PROT_DMA);
978 ata_sff_exec_command(ap, tf);
979 }
980
981
982 static void pdc_sata_setup_port(struct ata_ioports *port, void __iomem *base)
983 {
984 port->cmd_addr = base;
985 port->data_addr = base;
986 port->feature_addr =
987 port->error_addr = base + 0x4;
988 port->nsect_addr = base + 0x8;
989 port->lbal_addr = base + 0xc;
990 port->lbam_addr = base + 0x10;
991 port->lbah_addr = base + 0x14;
992 port->device_addr = base + 0x18;
993 port->command_addr =
994 port->status_addr = base + 0x1c;
995 port->altstatus_addr =
996 port->ctl_addr = base + 0x38;
997 }
998
999
1000 #ifdef ATA_VERBOSE_DEBUG
1001 static void pdc20621_get_from_dimm(struct ata_host *host, void *psource,
1002 u32 offset, u32 size)
1003 {
1004 u32 window_size;
1005 u16 idx;
1006 u8 page_mask;
1007 long dist;
1008 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1009 void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
1010
1011 /* hard-code chip #0 */
1012 mmio += PDC_CHIP0_OFS;
1013
1014 page_mask = 0x00;
1015 window_size = 0x2000 * 4; /* 32K byte uchar size */
1016 idx = (u16) (offset / window_size);
1017
1018 writel(0x01, mmio + PDC_GENERAL_CTLR);
1019 readl(mmio + PDC_GENERAL_CTLR);
1020 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1021 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1022
1023 offset -= (idx * window_size);
1024 idx++;
1025 dist = ((long) (window_size - (offset + size))) >= 0 ? size :
1026 (long) (window_size - offset);
1027 memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
1028 dist);
1029
1030 psource += dist;
1031 size -= dist;
1032 for (; (long) size >= (long) window_size ;) {
1033 writel(0x01, mmio + PDC_GENERAL_CTLR);
1034 readl(mmio + PDC_GENERAL_CTLR);
1035 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1036 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1037 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
1038 window_size / 4);
1039 psource += window_size;
1040 size -= window_size;
1041 idx++;
1042 }
1043
1044 if (size) {
1045 writel(0x01, mmio + PDC_GENERAL_CTLR);
1046 readl(mmio + PDC_GENERAL_CTLR);
1047 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1048 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1049 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
1050 size / 4);
1051 }
1052 }
1053 #endif
1054
1055
1056 static void pdc20621_put_to_dimm(struct ata_host *host, void *psource,
1057 u32 offset, u32 size)
1058 {
1059 u32 window_size;
1060 u16 idx;
1061 u8 page_mask;
1062 long dist;
1063 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1064 void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
1065
1066 /* hard-code chip #0 */
1067 mmio += PDC_CHIP0_OFS;
1068
1069 page_mask = 0x00;
1070 window_size = 0x2000 * 4; /* 32K byte uchar size */
1071 idx = (u16) (offset / window_size);
1072
1073 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1074 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1075 offset -= (idx * window_size);
1076 idx++;
1077 dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
1078 (long) (window_size - offset);
1079 memcpy_toio(dimm_mmio + offset / 4, psource, dist);
1080 writel(0x01, mmio + PDC_GENERAL_CTLR);
1081 readl(mmio + PDC_GENERAL_CTLR);
1082
1083 psource += dist;
1084 size -= dist;
1085 for (; (long) size >= (long) window_size ;) {
1086 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1087 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1088 memcpy_toio(dimm_mmio, psource, window_size / 4);
1089 writel(0x01, mmio + PDC_GENERAL_CTLR);
1090 readl(mmio + PDC_GENERAL_CTLR);
1091 psource += window_size;
1092 size -= window_size;
1093 idx++;
1094 }
1095
1096 if (size) {
1097 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1098 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1099 memcpy_toio(dimm_mmio, psource, size / 4);
1100 writel(0x01, mmio + PDC_GENERAL_CTLR);
1101 readl(mmio + PDC_GENERAL_CTLR);
1102 }
1103 }
1104
1105
1106 static unsigned int pdc20621_i2c_read(struct ata_host *host, u32 device,
1107 u32 subaddr, u32 *pdata)
1108 {
1109 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1110 u32 i2creg = 0;
1111 u32 status;
1112 u32 count = 0;
1113
1114 /* hard-code chip #0 */
1115 mmio += PDC_CHIP0_OFS;
1116
1117 i2creg |= device << 24;
1118 i2creg |= subaddr << 16;
1119
1120 /* Set the device and subaddress */
1121 writel(i2creg, mmio + PDC_I2C_ADDR_DATA);
1122 readl(mmio + PDC_I2C_ADDR_DATA);
1123
1124 /* Write Control to perform read operation, mask int */
1125 writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
1126 mmio + PDC_I2C_CONTROL);
1127
1128 for (count = 0; count <= 1000; count ++) {
1129 status = readl(mmio + PDC_I2C_CONTROL);
1130 if (status & PDC_I2C_COMPLETE) {
1131 status = readl(mmio + PDC_I2C_ADDR_DATA);
1132 break;
1133 } else if (count == 1000)
1134 return 0;
1135 }
1136
1137 *pdata = (status >> 8) & 0x000000ff;
1138 return 1;
1139 }
1140
1141
1142 static int pdc20621_detect_dimm(struct ata_host *host)
1143 {
1144 u32 data = 0;
1145 if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1146 PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1147 if (data == 100)
1148 return 100;
1149 } else
1150 return 0;
1151
1152 if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
1153 if (data <= 0x75)
1154 return 133;
1155 } else
1156 return 0;
1157
1158 return 0;
1159 }
1160
1161
1162 static int pdc20621_prog_dimm0(struct ata_host *host)
1163 {
1164 u32 spd0[50];
1165 u32 data = 0;
1166 int size, i;
1167 u8 bdimmsize;
1168 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1169 static const struct {
1170 unsigned int reg;
1171 unsigned int ofs;
1172 } pdc_i2c_read_data [] = {
1173 { PDC_DIMM_SPD_TYPE, 11 },
1174 { PDC_DIMM_SPD_FRESH_RATE, 12 },
1175 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1176 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1177 { PDC_DIMM_SPD_ROW_NUM, 3 },
1178 { PDC_DIMM_SPD_BANK_NUM, 17 },
1179 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1180 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1181 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1182 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1183 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
1184 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1185 };
1186
1187 /* hard-code chip #0 */
1188 mmio += PDC_CHIP0_OFS;
1189
1190 for (i = 0; i < ARRAY_SIZE(pdc_i2c_read_data); i++)
1191 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1192 pdc_i2c_read_data[i].reg,
1193 &spd0[pdc_i2c_read_data[i].ofs]);
1194
1195 data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
1196 data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1197 ((((spd0[27] + 9) / 10) - 1) << 8) ;
1198 data |= (((((spd0[29] > spd0[28])
1199 ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1200 data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
1201
1202 if (spd0[18] & 0x08)
1203 data |= ((0x03) << 14);
1204 else if (spd0[18] & 0x04)
1205 data |= ((0x02) << 14);
1206 else if (spd0[18] & 0x01)
1207 data |= ((0x01) << 14);
1208 else
1209 data |= (0 << 14);
1210
1211 /*
1212 Calculate the size of bDIMMSize (power of 2) and
1213 merge the DIMM size by program start/end address.
1214 */
1215
1216 bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1217 size = (1 << bdimmsize) >> 20; /* size = xxx(MB) */
1218 data |= (((size / 16) - 1) << 16);
1219 data |= (0 << 23);
1220 data |= 8;
1221 writel(data, mmio + PDC_DIMM0_CONTROL);
1222 readl(mmio + PDC_DIMM0_CONTROL);
1223 return size;
1224 }
1225
1226
1227 static unsigned int pdc20621_prog_dimm_global(struct ata_host *host)
1228 {
1229 u32 data, spd0;
1230 int error, i;
1231 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1232
1233 /* hard-code chip #0 */
1234 mmio += PDC_CHIP0_OFS;
1235
1236 /*
1237 Set To Default : DIMM Module Global Control Register (0x022259F1)
1238 DIMM Arbitration Disable (bit 20)
1239 DIMM Data/Control Output Driving Selection (bit12 - bit15)
1240 Refresh Enable (bit 17)
1241 */
1242
1243 data = 0x022259F1;
1244 writel(data, mmio + PDC_SDRAM_CONTROL);
1245 readl(mmio + PDC_SDRAM_CONTROL);
1246
1247 /* Turn on for ECC */
1248 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1249 PDC_DIMM_SPD_TYPE, &spd0);
1250 if (spd0 == 0x02) {
1251 data |= (0x01 << 16);
1252 writel(data, mmio + PDC_SDRAM_CONTROL);
1253 readl(mmio + PDC_SDRAM_CONTROL);
1254 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1255 }
1256
1257 /* DIMM Initialization Select/Enable (bit 18/19) */
1258 data &= (~(1<<18));
1259 data |= (1<<19);
1260 writel(data, mmio + PDC_SDRAM_CONTROL);
1261
1262 error = 1;
1263 for (i = 1; i <= 10; i++) { /* polling ~5 secs */
1264 data = readl(mmio + PDC_SDRAM_CONTROL);
1265 if (!(data & (1<<19))) {
1266 error = 0;
1267 break;
1268 }
1269 msleep(i*100);
1270 }
1271 return error;
1272 }
1273
1274
1275 static unsigned int pdc20621_dimm_init(struct ata_host *host)
1276 {
1277 int speed, size, length;
1278 u32 addr, spd0, pci_status;
1279 u32 time_period = 0;
1280 u32 tcount = 0;
1281 u32 ticks = 0;
1282 u32 clock = 0;
1283 u32 fparam = 0;
1284 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1285
1286 /* hard-code chip #0 */
1287 mmio += PDC_CHIP0_OFS;
1288
1289 /* Initialize PLL based upon PCI Bus Frequency */
1290
1291 /* Initialize Time Period Register */
1292 writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1293 time_period = readl(mmio + PDC_TIME_PERIOD);
1294 VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1295
1296 /* Enable timer */
1297 writel(PDC_TIMER_DEFAULT, mmio + PDC_TIME_CONTROL);
1298 readl(mmio + PDC_TIME_CONTROL);
1299
1300 /* Wait 3 seconds */
1301 msleep(3000);
1302
1303 /*
1304 When timer is enabled, counter is decreased every internal
1305 clock cycle.
1306 */
1307
1308 tcount = readl(mmio + PDC_TIME_COUNTER);
1309 VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1310
1311 /*
1312 If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1313 register should be >= (0xffffffff - 3x10^8).
1314 */
1315 if (tcount >= PCI_X_TCOUNT) {
1316 ticks = (time_period - tcount);
1317 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
1318
1319 clock = (ticks / 300000);
1320 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
1321
1322 clock = (clock * 33);
1323 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1324
1325 /* PLL F Param (bit 22:16) */
1326 fparam = (1400000 / clock) - 2;
1327 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
1328
1329 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1330 pci_status = (0x8a001824 | (fparam << 16));
1331 } else
1332 pci_status = PCI_PLL_INIT;
1333
1334 /* Initialize PLL. */
1335 VPRINTK("pci_status: 0x%x\n", pci_status);
1336 writel(pci_status, mmio + PDC_CTL_STATUS);
1337 readl(mmio + PDC_CTL_STATUS);
1338
1339 /*
1340 Read SPD of DIMM by I2C interface,
1341 and program the DIMM Module Controller.
1342 */
1343 if (!(speed = pdc20621_detect_dimm(host))) {
1344 printk(KERN_ERR "Detect Local DIMM Fail\n");
1345 return 1; /* DIMM error */
1346 }
1347 VPRINTK("Local DIMM Speed = %d\n", speed);
1348
1349 /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1350 size = pdc20621_prog_dimm0(host);
1351 VPRINTK("Local DIMM Size = %dMB\n", size);
1352
1353 /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1354 if (pdc20621_prog_dimm_global(host)) {
1355 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1356 return 1;
1357 }
1358
1359 #ifdef ATA_VERBOSE_DEBUG
1360 {
1361 u8 test_parttern1[40] =
1362 {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1363 'N','o','t',' ','Y','e','t',' ',
1364 'D','e','f','i','n','e','d',' ',
1365 '1','.','1','0',
1366 '9','8','0','3','1','6','1','2',0,0};
1367 u8 test_parttern2[40] = {0};
1368
1369 pdc20621_put_to_dimm(host, test_parttern2, 0x10040, 40);
1370 pdc20621_put_to_dimm(host, test_parttern2, 0x40, 40);
1371
1372 pdc20621_put_to_dimm(host, test_parttern1, 0x10040, 40);
1373 pdc20621_get_from_dimm(host, test_parttern2, 0x40, 40);
1374 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1375 test_parttern2[1], &(test_parttern2[2]));
1376 pdc20621_get_from_dimm(host, test_parttern2, 0x10040,
1377 40);
1378 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1379 test_parttern2[1], &(test_parttern2[2]));
1380
1381 pdc20621_put_to_dimm(host, test_parttern1, 0x40, 40);
1382 pdc20621_get_from_dimm(host, test_parttern2, 0x40, 40);
1383 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1384 test_parttern2[1], &(test_parttern2[2]));
1385 }
1386 #endif
1387
1388 /* ECC initiliazation. */
1389
1390 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1391 PDC_DIMM_SPD_TYPE, &spd0);
1392 if (spd0 == 0x02) {
1393 void *buf;
1394 VPRINTK("Start ECC initialization\n");
1395 addr = 0;
1396 length = size * 1024 * 1024;
1397 buf = kzalloc(ECC_ERASE_BUF_SZ, GFP_KERNEL);
1398 while (addr < length) {
1399 pdc20621_put_to_dimm(host, buf, addr,
1400 ECC_ERASE_BUF_SZ);
1401 addr += ECC_ERASE_BUF_SZ;
1402 }
1403 kfree(buf);
1404 VPRINTK("Finish ECC initialization\n");
1405 }
1406 return 0;
1407 }
1408
1409
1410 static void pdc_20621_init(struct ata_host *host)
1411 {
1412 u32 tmp;
1413 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1414
1415 /* hard-code chip #0 */
1416 mmio += PDC_CHIP0_OFS;
1417
1418 /*
1419 * Select page 0x40 for our 32k DIMM window
1420 */
1421 tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1422 tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1423 writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1424
1425 /*
1426 * Reset Host DMA
1427 */
1428 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1429 tmp |= PDC_RESET;
1430 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1431 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1432
1433 udelay(10);
1434
1435 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1436 tmp &= ~PDC_RESET;
1437 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1438 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1439 }
1440
1441 static int pdc_sata_init_one(struct pci_dev *pdev,
1442 const struct pci_device_id *ent)
1443 {
1444 static int printed_version;
1445 const struct ata_port_info *ppi[] =
1446 { &pdc_port_info[ent->driver_data], NULL };
1447 struct ata_host *host;
1448 struct pdc_host_priv *hpriv;
1449 int i, rc;
1450
1451 if (!printed_version++)
1452 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1453
1454 /* allocate host */
1455 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
1456 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
1457 if (!host || !hpriv)
1458 return -ENOMEM;
1459
1460 host->private_data = hpriv;
1461
1462 /* acquire resources and fill host */
1463 rc = pcim_enable_device(pdev);
1464 if (rc)
1465 return rc;
1466
1467 rc = pcim_iomap_regions(pdev, (1 << PDC_MMIO_BAR) | (1 << PDC_DIMM_BAR),
1468 DRV_NAME);
1469 if (rc == -EBUSY)
1470 pcim_pin_device(pdev);
1471 if (rc)
1472 return rc;
1473 host->iomap = pcim_iomap_table(pdev);
1474
1475 for (i = 0; i < 4; i++) {
1476 struct ata_port *ap = host->ports[i];
1477 void __iomem *base = host->iomap[PDC_MMIO_BAR] + PDC_CHIP0_OFS;
1478 unsigned int offset = 0x200 + i * 0x80;
1479
1480 pdc_sata_setup_port(&ap->ioaddr, base + offset);
1481
1482 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1483 ata_port_pbar_desc(ap, PDC_DIMM_BAR, -1, "dimm");
1484 ata_port_pbar_desc(ap, PDC_MMIO_BAR, offset, "port");
1485 }
1486
1487 /* configure and activate */
1488 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1489 if (rc)
1490 return rc;
1491 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1492 if (rc)
1493 return rc;
1494
1495 if (pdc20621_dimm_init(host))
1496 return -ENOMEM;
1497 pdc_20621_init(host);
1498
1499 pci_set_master(pdev);
1500 return ata_host_activate(host, pdev->irq, pdc20621_interrupt,
1501 IRQF_SHARED, &pdc_sata_sht);
1502 }
1503
1504
1505 static int __init pdc_sata_init(void)
1506 {
1507 return pci_register_driver(&pdc_sata_pci_driver);
1508 }
1509
1510
1511 static void __exit pdc_sata_exit(void)
1512 {
1513 pci_unregister_driver(&pdc_sata_pci_driver);
1514 }
1515
1516
1517 MODULE_AUTHOR("Jeff Garzik");
1518 MODULE_DESCRIPTION("Promise SATA low-level driver");
1519 MODULE_LICENSE("GPL");
1520 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1521 MODULE_VERSION(DRV_VERSION);
1522
1523 module_init(pdc_sata_init);
1524 module_exit(pdc_sata_exit);
x86 "subsystem" repository