1 /* Copyright (C) 2004 Mips Technologies, Inc */
3 #include <linux/kernel.h>
4 #include <linux/sched.h>
5 #include <linux/cpumask.h>
6 #include <linux/interrupt.h>
7 #include <linux/kernel_stat.h>
8 #include <linux/module.h>
11 #include <asm/processor.h>
12 #include <asm/atomic.h>
13 #include <asm/system.h>
14 #include <asm/hardirq.h>
15 #include <asm/hazards.h>
17 #include <asm/mmu_context.h>
19 #include <asm/mipsregs.h>
20 #include <asm/cacheflush.h>
22 #include <asm/addrspace.h>
24 #include <asm/smtc_ipi.h>
25 #include <asm/smtc_proc.h>
28 * SMTC Kernel needs to manipulate low-level CPU interrupt mask
29 * in do_IRQ. These are passed in setup_irq_smtc() and stored
32 unsigned long irq_hwmask
[NR_IRQS
];
34 #define LOCK_MT_PRA() \
35 local_irq_save(flags); \
38 #define UNLOCK_MT_PRA() \
40 local_irq_restore(flags)
42 #define LOCK_CORE_PRA() \
43 local_irq_save(flags); \
46 #define UNLOCK_CORE_PRA() \
48 local_irq_restore(flags)
51 * Data structures purely associated with SMTC parallelism
56 * Table for tracking ASIDs whose lifetime is prolonged.
59 asiduse smtc_live_asid
[MAX_SMTC_TLBS
][MAX_SMTC_ASIDS
];
62 * Clock interrupt "latch" buffers, per "CPU"
65 unsigned int ipi_timer_latch
[NR_CPUS
];
68 * Number of InterProcessor Interupt (IPI) message buffers to allocate
71 #define IPIBUF_PER_CPU 4
73 static struct smtc_ipi_q IPIQ
[NR_CPUS
];
74 static struct smtc_ipi_q freeIPIq
;
77 /* Forward declarations */
79 void ipi_decode(struct smtc_ipi
*);
80 static void post_direct_ipi(int cpu
, struct smtc_ipi
*pipi
);
81 static void setup_cross_vpe_interrupts(unsigned int nvpe
);
82 void init_smtc_stats(void);
84 /* Global SMTC Status */
86 unsigned int smtc_status
= 0;
88 /* Boot command line configuration overrides */
90 static int ipibuffers
= 0;
91 static int nostlb
= 0;
92 static int asidmask
= 0;
93 unsigned long smtc_asid_mask
= 0xff;
95 static int __init
ipibufs(char *str
)
97 get_option(&str
, &ipibuffers
);
101 static int __init
stlb_disable(char *s
)
107 static int __init
asidmask_set(char *str
)
109 get_option(&str
, &asidmask
);
119 smtc_asid_mask
= (unsigned long)asidmask
;
122 printk("ILLEGAL ASID mask 0x%x from command line\n", asidmask
);
127 __setup("ipibufs=", ipibufs
);
128 __setup("nostlb", stlb_disable
);
129 __setup("asidmask=", asidmask_set
);
131 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
133 static int hang_trig
= 0;
135 static int __init
hangtrig_enable(char *s
)
142 __setup("hangtrig", hangtrig_enable
);
144 #define DEFAULT_BLOCKED_IPI_LIMIT 32
146 static int timerq_limit
= DEFAULT_BLOCKED_IPI_LIMIT
;
148 static int __init
tintq(char *str
)
150 get_option(&str
, &timerq_limit
);
154 __setup("tintq=", tintq
);
156 static int imstuckcount
[2][8];
157 /* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */
158 static int vpemask
[2][8] = {
159 {0, 0, 1, 0, 0, 0, 0, 1},
160 {0, 0, 0, 0, 0, 0, 0, 1}
162 int tcnoprog
[NR_CPUS
];
163 static atomic_t idle_hook_initialized
= {0};
164 static int clock_hang_reported
[NR_CPUS
];
166 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
168 /* Initialize shared TLB - the should probably migrate to smtc_setup_cpus() */
170 void __init
sanitize_tlb_entries(void)
172 printk("Deprecated sanitize_tlb_entries() invoked\n");
177 * Configure shared TLB - VPC configuration bit must be set by caller
180 static void smtc_configure_tlb(void)
183 unsigned long mvpconf0
;
184 unsigned long config1val
;
186 /* Set up ASID preservation table */
187 for (vpes
=0; vpes
<MAX_SMTC_TLBS
; vpes
++) {
188 for(i
= 0; i
< MAX_SMTC_ASIDS
; i
++) {
189 smtc_live_asid
[vpes
][i
] = 0;
192 mvpconf0
= read_c0_mvpconf0();
194 if ((vpes
= ((mvpconf0
& MVPCONF0_PVPE
)
195 >> MVPCONF0_PVPE_SHIFT
) + 1) > 1) {
196 /* If we have multiple VPEs, try to share the TLB */
197 if ((mvpconf0
& MVPCONF0_TLBS
) && !nostlb
) {
199 * If TLB sizing is programmable, shared TLB
200 * size is the total available complement.
201 * Otherwise, we have to take the sum of all
202 * static VPE TLB entries.
204 if ((tlbsiz
= ((mvpconf0
& MVPCONF0_PTLBE
)
205 >> MVPCONF0_PTLBE_SHIFT
)) == 0) {
207 * If there's more than one VPE, there had better
208 * be more than one TC, because we need one to bind
209 * to each VPE in turn to be able to read
210 * its configuration state!
213 /* Stop the TC from doing anything foolish */
214 write_tc_c0_tchalt(TCHALT_H
);
216 /* No need to un-Halt - that happens later anyway */
217 for (i
=0; i
< vpes
; i
++) {
218 write_tc_c0_tcbind(i
);
220 * To be 100% sure we're really getting the right
221 * information, we exit the configuration state
222 * and do an IHB after each rebinding.
225 read_c0_mvpcontrol() & ~ MVPCONTROL_VPC
);
228 * Only count if the MMU Type indicated is TLB
230 if (((read_vpe_c0_config() & MIPS_CONF_MT
) >> 7) == 1) {
231 config1val
= read_vpe_c0_config1();
232 tlbsiz
+= ((config1val
>> 25) & 0x3f) + 1;
235 /* Put core back in configuration state */
237 read_c0_mvpcontrol() | MVPCONTROL_VPC
);
241 write_c0_mvpcontrol(read_c0_mvpcontrol() | MVPCONTROL_STLB
);
245 * Setup kernel data structures to use software total,
246 * rather than read the per-VPE Config1 value. The values
247 * for "CPU 0" gets copied to all the other CPUs as part
248 * of their initialization in smtc_cpu_setup().
251 /* MIPS32 limits TLB indices to 64 */
254 cpu_data
[0].tlbsize
= current_cpu_data
.tlbsize
= tlbsiz
;
255 smtc_status
|= SMTC_TLB_SHARED
;
256 local_flush_tlb_all();
258 printk("TLB of %d entry pairs shared by %d VPEs\n",
261 printk("WARNING: TLB Not Sharable on SMTC Boot!\n");
268 * Incrementally build the CPU map out of constituent MIPS MT cores,
269 * using the specified available VPEs and TCs. Plaform code needs
270 * to ensure that each MIPS MT core invokes this routine on reset,
273 * This version of the build_cpu_map and prepare_cpus routines assumes
274 * that *all* TCs of a MIPS MT core will be used for Linux, and that
275 * they will be spread across *all* available VPEs (to minimise the
276 * loss of efficiency due to exception service serialization).
277 * An improved version would pick up configuration information and
278 * possibly leave some TCs/VPEs as "slave" processors.
280 * Use c0_MVPConf0 to find out how many TCs are available, setting up
281 * phys_cpu_present_map and the logical/physical mappings.
284 int __init
mipsmt_build_cpu_map(int start_cpu_slot
)
289 * The CPU map isn't actually used for anything at this point,
290 * so it's not clear what else we should do apart from set
291 * everything up so that "logical" = "physical".
293 ntcs
= ((read_c0_mvpconf0() & MVPCONF0_PTC
) >> MVPCONF0_PTC_SHIFT
) + 1;
294 for (i
=start_cpu_slot
; i
<NR_CPUS
&& i
<ntcs
; i
++) {
295 cpu_set(i
, phys_cpu_present_map
);
296 __cpu_number_map
[i
] = i
;
297 __cpu_logical_map
[i
] = i
;
299 /* Initialize map of CPUs with FPUs */
300 cpus_clear(mt_fpu_cpumask
);
302 /* One of those TC's is the one booting, and not a secondary... */
303 printk("%i available secondary CPU TC(s)\n", i
- 1);
309 * Common setup before any secondaries are started
310 * Make sure all CPU's are in a sensible state before we boot any of the
313 * For MIPS MT "SMTC" operation, we set up all TCs, spread as evenly
314 * as possible across the available VPEs.
317 static void smtc_tc_setup(int vpe
, int tc
, int cpu
)
320 write_tc_c0_tchalt(TCHALT_H
);
322 write_tc_c0_tcstatus((read_tc_c0_tcstatus()
323 & ~(TCSTATUS_TKSU
| TCSTATUS_DA
| TCSTATUS_IXMT
))
325 write_tc_c0_tccontext(0);
327 write_tc_c0_tcbind(vpe
);
328 /* In general, all TCs should have the same cpu_data indications */
329 memcpy(&cpu_data
[cpu
], &cpu_data
[0], sizeof(struct cpuinfo_mips
));
330 /* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */
331 if (cpu_data
[0].cputype
== CPU_34K
)
332 cpu_data
[cpu
].options
&= ~MIPS_CPU_FPU
;
333 cpu_data
[cpu
].vpe_id
= vpe
;
334 cpu_data
[cpu
].tc_id
= tc
;
338 void mipsmt_prepare_cpus(void)
340 int i
, vpe
, tc
, ntc
, nvpe
, tcpervpe
, slop
, cpu
;
344 struct smtc_ipi
*pipi
;
346 /* disable interrupts so we can disable MT */
347 local_irq_save(flags
);
348 /* disable MT so we can configure */
352 spin_lock_init(&freeIPIq
.lock
);
355 * We probably don't have as many VPEs as we do SMP "CPUs",
356 * but it's possible - and in any case we'll never use more!
358 for (i
=0; i
<NR_CPUS
; i
++) {
359 IPIQ
[i
].head
= IPIQ
[i
].tail
= NULL
;
360 spin_lock_init(&IPIQ
[i
].lock
);
362 ipi_timer_latch
[i
] = 0;
365 /* cpu_data index starts at zero */
367 cpu_data
[cpu
].vpe_id
= 0;
368 cpu_data
[cpu
].tc_id
= 0;
371 /* Report on boot-time options */
372 mips_mt_set_cpuoptions ();
374 printk("Limit of %d VPEs set\n", vpelimit
);
376 printk("Limit of %d TCs set\n", tclimit
);
378 printk("Shared TLB Use Inhibited - UNSAFE for Multi-VPE Operation\n");
381 printk("ASID mask value override to 0x%x\n", asidmask
);
384 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
386 printk("Logic Analyser Trigger on suspected TC hang\n");
387 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
389 /* Put MVPE's into 'configuration state' */
390 write_c0_mvpcontrol( read_c0_mvpcontrol() | MVPCONTROL_VPC
);
392 val
= read_c0_mvpconf0();
393 nvpe
= ((val
& MVPCONF0_PVPE
) >> MVPCONF0_PVPE_SHIFT
) + 1;
394 if (vpelimit
> 0 && nvpe
> vpelimit
)
396 ntc
= ((val
& MVPCONF0_PTC
) >> MVPCONF0_PTC_SHIFT
) + 1;
399 if (tclimit
> 0 && ntc
> tclimit
)
401 tcpervpe
= ntc
/ nvpe
;
402 slop
= ntc
% nvpe
; /* Residual TCs, < NVPE */
404 /* Set up shared TLB */
405 smtc_configure_tlb();
407 for (tc
= 0, vpe
= 0 ; (vpe
< nvpe
) && (tc
< ntc
) ; vpe
++) {
412 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_MVP
);
415 printk("VPE %d: TC", vpe
);
416 for (i
= 0; i
< tcpervpe
; i
++) {
418 * TC 0 is bound to VPE 0 at reset,
419 * and is presumably executing this
420 * code. Leave it alone!
423 smtc_tc_setup(vpe
,tc
, cpu
);
431 smtc_tc_setup(vpe
,tc
, cpu
);
440 * Clear any stale software interrupts from VPE's Cause
442 write_vpe_c0_cause(0);
445 * Clear ERL/EXL of VPEs other than 0
446 * and set restricted interrupt enable/mask.
448 write_vpe_c0_status((read_vpe_c0_status()
449 & ~(ST0_BEV
| ST0_ERL
| ST0_EXL
| ST0_IM
))
450 | (STATUSF_IP0
| STATUSF_IP1
| STATUSF_IP7
453 * set config to be the same as vpe0,
454 * particularly kseg0 coherency alg
456 write_vpe_c0_config(read_c0_config());
457 /* Clear any pending timer interrupt */
458 write_vpe_c0_compare(0);
459 /* Propagate Config7 */
460 write_vpe_c0_config7(read_c0_config7());
461 write_vpe_c0_count(read_c0_count());
463 /* enable multi-threading within VPE */
464 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() | VPECONTROL_TE
);
466 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA
);
470 * Pull any physically present but unused TCs out of circulation.
472 while (tc
< (((val
& MVPCONF0_PTC
) >> MVPCONF0_PTC_SHIFT
) + 1)) {
473 cpu_clear(tc
, phys_cpu_present_map
);
474 cpu_clear(tc
, cpu_present_map
);
478 /* release config state */
479 write_c0_mvpcontrol( read_c0_mvpcontrol() & ~ MVPCONTROL_VPC
);
483 /* Set up coprocessor affinity CPU mask(s) */
485 for (tc
= 0; tc
< ntc
; tc
++) {
486 if (cpu_data
[tc
].options
& MIPS_CPU_FPU
)
487 cpu_set(tc
, mt_fpu_cpumask
);
490 /* set up ipi interrupts... */
492 /* If we have multiple VPEs running, set up the cross-VPE interrupt */
494 setup_cross_vpe_interrupts(nvpe
);
496 /* Set up queue of free IPI "messages". */
497 nipi
= NR_CPUS
* IPIBUF_PER_CPU
;
501 pipi
= kmalloc(nipi
*sizeof(struct smtc_ipi
), GFP_KERNEL
);
503 panic("kmalloc of IPI message buffers failed\n");
505 printk("IPI buffer pool of %d buffers\n", nipi
);
506 for (i
= 0; i
< nipi
; i
++) {
507 smtc_ipi_nq(&freeIPIq
, pipi
);
511 /* Arm multithreading and enable other VPEs - but all TCs are Halted */
514 local_irq_restore(flags
);
515 /* Initialize SMTC /proc statistics/diagnostics */
521 * Setup the PC, SP, and GP of a secondary processor and start it
523 * smp_bootstrap is the place to resume from
524 * __KSTK_TOS(idle) is apparently the stack pointer
525 * (unsigned long)idle->thread_info the gp
528 void __cpuinit
smtc_boot_secondary(int cpu
, struct task_struct
*idle
)
530 extern u32 kernelsp
[NR_CPUS
];
535 if (cpu_data
[cpu
].vpe_id
!= cpu_data
[smp_processor_id()].vpe_id
) {
538 settc(cpu_data
[cpu
].tc_id
);
541 write_tc_c0_tcrestart((unsigned long)&smp_bootstrap
);
544 kernelsp
[cpu
] = __KSTK_TOS(idle
);
545 write_tc_gpr_sp(__KSTK_TOS(idle
));
548 write_tc_gpr_gp((unsigned long)task_thread_info(idle
));
550 smtc_status
|= SMTC_MTC_ACTIVE
;
551 write_tc_c0_tchalt(0);
552 if (cpu_data
[cpu
].vpe_id
!= cpu_data
[smp_processor_id()].vpe_id
) {
558 void smtc_init_secondary(void)
561 * Start timer on secondary VPEs if necessary.
562 * plat_timer_setup has already have been invoked by init/main
563 * on "boot" TC. Like per_cpu_trap_init() hack, this assumes that
564 * SMTC init code assigns TCs consdecutively and in ascending order
565 * to across available VPEs.
567 if (((read_c0_tcbind() & TCBIND_CURTC
) != 0) &&
568 ((read_c0_tcbind() & TCBIND_CURVPE
)
569 != cpu_data
[smp_processor_id() - 1].vpe_id
)){
570 write_c0_compare (read_c0_count() + mips_hpt_frequency
/HZ
);
576 void smtc_smp_finish(void)
578 printk("TC %d going on-line as CPU %d\n",
579 cpu_data
[smp_processor_id()].tc_id
, smp_processor_id());
582 void smtc_cpus_done(void)
587 * Support for SMTC-optimized driver IRQ registration
591 * SMTC Kernel needs to manipulate low-level CPU interrupt mask
592 * in do_IRQ. These are passed in setup_irq_smtc() and stored
596 int setup_irq_smtc(unsigned int irq
, struct irqaction
* new,
597 unsigned long hwmask
)
599 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
600 unsigned int vpe
= current_cpu_data
.vpe_id
;
602 vpemask
[vpe
][irq
- MIPS_CPU_IRQ_BASE
] = 1;
604 irq_hwmask
[irq
] = hwmask
;
606 return setup_irq(irq
, new);
610 * IPI model for SMTC is tricky, because interrupts aren't TC-specific.
611 * Within a VPE one TC can interrupt another by different approaches.
612 * The easiest to get right would probably be to make all TCs except
613 * the target IXMT and set a software interrupt, but an IXMT-based
614 * scheme requires that a handler must run before a new IPI could
615 * be sent, which would break the "broadcast" loops in MIPS MT.
616 * A more gonzo approach within a VPE is to halt the TC, extract
617 * its Restart, Status, and a couple of GPRs, and program the Restart
618 * address to emulate an interrupt.
620 * Within a VPE, one can be confident that the target TC isn't in
621 * a critical EXL state when halted, since the write to the Halt
622 * register could not have issued on the writing thread if the
623 * halting thread had EXL set. So k0 and k1 of the target TC
624 * can be used by the injection code. Across VPEs, one can't
625 * be certain that the target TC isn't in a critical exception
626 * state. So we try a two-step process of sending a software
627 * interrupt to the target VPE, which either handles the event
628 * itself (if it was the target) or injects the event within
632 static void smtc_ipi_qdump(void)
636 for (i
= 0; i
< NR_CPUS
;i
++) {
637 printk("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n",
638 i
, (unsigned)IPIQ
[i
].head
, (unsigned)IPIQ
[i
].tail
,
644 * The standard atomic.h primitives don't quite do what we want
645 * here: We need an atomic add-and-return-previous-value (which
646 * could be done with atomic_add_return and a decrement) and an
647 * atomic set/zero-and-return-previous-value (which can't really
648 * be done with the atomic.h primitives). And since this is
649 * MIPS MT, we can assume that we have LL/SC.
651 static __inline__
int atomic_postincrement(unsigned int *pv
)
653 unsigned long result
;
657 __asm__
__volatile__(
663 : "=&r" (result
), "=&r" (temp
), "=m" (*pv
)
670 void smtc_send_ipi(int cpu
, int type
, unsigned int action
)
673 struct smtc_ipi
*pipi
;
677 if (cpu
== smp_processor_id()) {
678 printk("Cannot Send IPI to self!\n");
681 /* Set up a descriptor, to be delivered either promptly or queued */
682 pipi
= smtc_ipi_dq(&freeIPIq
);
685 mips_mt_regdump(dvpe());
686 panic("IPI Msg. Buffers Depleted\n");
689 pipi
->arg
= (void *)action
;
691 if (cpu_data
[cpu
].vpe_id
!= cpu_data
[smp_processor_id()].vpe_id
) {
692 /* If not on same VPE, enqueue and send cross-VPE interupt */
693 smtc_ipi_nq(&IPIQ
[cpu
], pipi
);
695 settc(cpu_data
[cpu
].tc_id
);
696 write_vpe_c0_cause(read_vpe_c0_cause() | C_SW1
);
700 * Not sufficient to do a LOCK_MT_PRA (dmt) here,
701 * since ASID shootdown on the other VPE may
702 * collide with this operation.
705 settc(cpu_data
[cpu
].tc_id
);
706 /* Halt the targeted TC */
707 write_tc_c0_tchalt(TCHALT_H
);
711 * Inspect TCStatus - if IXMT is set, we have to queue
712 * a message. Otherwise, we set up the "interrupt"
715 tcstatus
= read_tc_c0_tcstatus();
717 if ((tcstatus
& TCSTATUS_IXMT
) != 0) {
719 * Spin-waiting here can deadlock,
720 * so we queue the message for the target TC.
722 write_tc_c0_tchalt(0);
724 /* Try to reduce redundant timer interrupt messages */
725 if (type
== SMTC_CLOCK_TICK
) {
726 if (atomic_postincrement(&ipi_timer_latch
[cpu
])!=0){
727 smtc_ipi_nq(&freeIPIq
, pipi
);
731 smtc_ipi_nq(&IPIQ
[cpu
], pipi
);
733 post_direct_ipi(cpu
, pipi
);
734 write_tc_c0_tchalt(0);
741 * Send IPI message to Halted TC, TargTC/TargVPE already having been set
743 static void post_direct_ipi(int cpu
, struct smtc_ipi
*pipi
)
745 struct pt_regs
*kstack
;
746 unsigned long tcstatus
;
747 unsigned long tcrestart
;
748 extern u32 kernelsp
[NR_CPUS
];
749 extern void __smtc_ipi_vector(void);
751 /* Extract Status, EPC from halted TC */
752 tcstatus
= read_tc_c0_tcstatus();
753 tcrestart
= read_tc_c0_tcrestart();
754 /* If TCRestart indicates a WAIT instruction, advance the PC */
755 if ((tcrestart
& 0x80000000)
756 && ((*(unsigned int *)tcrestart
& 0xfe00003f) == 0x42000020)) {
760 * Save on TC's future kernel stack
762 * CU bit of Status is indicator that TC was
763 * already running on a kernel stack...
765 if (tcstatus
& ST0_CU0
) {
766 /* Note that this "- 1" is pointer arithmetic */
767 kstack
= ((struct pt_regs
*)read_tc_gpr_sp()) - 1;
769 kstack
= ((struct pt_regs
*)kernelsp
[cpu
]) - 1;
772 kstack
->cp0_epc
= (long)tcrestart
;
774 kstack
->cp0_tcstatus
= tcstatus
;
775 /* Pass token of operation to be performed kernel stack pad area */
776 kstack
->pad0
[4] = (unsigned long)pipi
;
777 /* Pass address of function to be called likewise */
778 kstack
->pad0
[5] = (unsigned long)&ipi_decode
;
779 /* Set interrupt exempt and kernel mode */
780 tcstatus
|= TCSTATUS_IXMT
;
781 tcstatus
&= ~TCSTATUS_TKSU
;
782 write_tc_c0_tcstatus(tcstatus
);
784 /* Set TC Restart address to be SMTC IPI vector */
785 write_tc_c0_tcrestart(__smtc_ipi_vector
);
788 static void ipi_resched_interrupt(void)
790 /* Return from interrupt should be enough to cause scheduler check */
794 static void ipi_call_interrupt(void)
796 /* Invoke generic function invocation code in smp.c */
797 smp_call_function_interrupt();
800 void ipi_decode(struct smtc_ipi
*pipi
)
802 void *arg_copy
= pipi
->arg
;
803 int type_copy
= pipi
->type
;
804 int dest_copy
= pipi
->dest
;
806 smtc_ipi_nq(&freeIPIq
, pipi
);
808 case SMTC_CLOCK_TICK
:
810 kstat_this_cpu
.irqs
[MIPS_CPU_IRQ_BASE
+ cp0_compare_irq
]++;
811 /* Invoke Clock "Interrupt" */
812 ipi_timer_latch
[dest_copy
] = 0;
813 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
814 clock_hang_reported
[dest_copy
] = 0;
815 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
816 local_timer_interrupt(0, NULL
);
820 switch ((int)arg_copy
) {
821 case SMP_RESCHEDULE_YOURSELF
:
822 ipi_resched_interrupt();
824 case SMP_CALL_FUNCTION
:
825 ipi_call_interrupt();
828 printk("Impossible SMTC IPI Argument 0x%x\n",
834 printk("Impossible SMTC IPI Type 0x%x\n", type_copy
);
839 void deferred_smtc_ipi(void)
841 struct smtc_ipi
*pipi
;
844 int q
= smp_processor_id();
847 * Test is not atomic, but much faster than a dequeue,
848 * and the vast majority of invocations will have a null queue.
850 if (IPIQ
[q
].head
!= NULL
) {
851 while((pipi
= smtc_ipi_dq(&IPIQ
[q
])) != NULL
) {
852 /* ipi_decode() should be called with interrupts off */
853 local_irq_save(flags
);
855 local_irq_restore(flags
);
861 * Send clock tick to all TCs except the one executing the funtion
864 void smtc_timer_broadcast(void)
867 int myTC
= cpu_data
[smp_processor_id()].tc_id
;
868 int myVPE
= cpu_data
[smp_processor_id()].vpe_id
;
870 smtc_cpu_stats
[smp_processor_id()].timerints
++;
872 for_each_online_cpu(cpu
) {
873 if (cpu_data
[cpu
].vpe_id
== myVPE
&&
874 cpu_data
[cpu
].tc_id
!= myTC
)
875 smtc_send_ipi(cpu
, SMTC_CLOCK_TICK
, 0);
880 * Cross-VPE interrupts in the SMTC prototype use "software interrupts"
881 * set via cross-VPE MTTR manipulation of the Cause register. It would be
882 * in some regards preferable to have external logic for "doorbell" hardware
886 static int cpu_ipi_irq
= MIPS_CPU_IRQ_BASE
+ MIPS_CPU_IPI_IRQ
;
888 static irqreturn_t
ipi_interrupt(int irq
, void *dev_idm
)
890 int my_vpe
= cpu_data
[smp_processor_id()].vpe_id
;
891 int my_tc
= cpu_data
[smp_processor_id()].tc_id
;
893 struct smtc_ipi
*pipi
;
894 unsigned long tcstatus
;
897 unsigned int mtflags
;
898 unsigned int vpflags
;
901 * So long as cross-VPE interrupts are done via
902 * MFTR/MTTR read-modify-writes of Cause, we need
903 * to stop other VPEs whenever the local VPE does
906 local_irq_save(flags
);
908 clear_c0_cause(0x100 << MIPS_CPU_IPI_IRQ
);
909 set_c0_status(0x100 << MIPS_CPU_IPI_IRQ
);
912 local_irq_restore(flags
);
915 * Cross-VPE Interrupt handler: Try to directly deliver IPIs
916 * queued for TCs on this VPE other than the current one.
917 * Return-from-interrupt should cause us to drain the queue
918 * for the current TC, so we ought not to have to do it explicitly here.
921 for_each_online_cpu(cpu
) {
922 if (cpu_data
[cpu
].vpe_id
!= my_vpe
)
925 pipi
= smtc_ipi_dq(&IPIQ
[cpu
]);
927 if (cpu_data
[cpu
].tc_id
!= my_tc
) {
930 settc(cpu_data
[cpu
].tc_id
);
931 write_tc_c0_tchalt(TCHALT_H
);
933 tcstatus
= read_tc_c0_tcstatus();
934 if ((tcstatus
& TCSTATUS_IXMT
) == 0) {
935 post_direct_ipi(cpu
, pipi
);
938 write_tc_c0_tchalt(0);
941 smtc_ipi_req(&IPIQ
[cpu
], pipi
);
945 * ipi_decode() should be called
946 * with interrupts off
948 local_irq_save(flags
);
950 local_irq_restore(flags
);
958 static void ipi_irq_dispatch(void)
963 static struct irqaction irq_ipi
= {
964 .handler
= ipi_interrupt
,
965 .flags
= IRQF_DISABLED
,
970 static void setup_cross_vpe_interrupts(unsigned int nvpe
)
976 panic("SMTC Kernel requires Vectored Interupt support");
978 set_vi_handler(MIPS_CPU_IPI_IRQ
, ipi_irq_dispatch
);
980 setup_irq_smtc(cpu_ipi_irq
, &irq_ipi
, (0x100 << MIPS_CPU_IPI_IRQ
));
982 set_irq_handler(cpu_ipi_irq
, handle_percpu_irq
);
986 * SMTC-specific hacks invoked from elsewhere in the kernel.
988 * smtc_ipi_replay is called from raw_local_irq_restore which is only ever
989 * called with interrupts disabled. We do rely on interrupts being disabled
990 * here because using spin_lock_irqsave()/spin_unlock_irqrestore() would
991 * result in a recursive call to raw_local_irq_restore().
994 static void __smtc_ipi_replay(void)
996 unsigned int cpu
= smp_processor_id();
999 * To the extent that we've ever turned interrupts off,
1000 * we may have accumulated deferred IPIs. This is subtle.
1001 * If we use the smtc_ipi_qdepth() macro, we'll get an
1002 * exact number - but we'll also disable interrupts
1003 * and create a window of failure where a new IPI gets
1004 * queued after we test the depth but before we re-enable
1005 * interrupts. So long as IXMT never gets set, however,
1006 * we should be OK: If we pick up something and dispatch
1007 * it here, that's great. If we see nothing, but concurrent
1008 * with this operation, another TC sends us an IPI, IXMT
1009 * is clear, and we'll handle it as a real pseudo-interrupt
1010 * and not a pseudo-pseudo interrupt.
1012 if (IPIQ
[cpu
].depth
> 0) {
1014 struct smtc_ipi_q
*q
= &IPIQ
[cpu
];
1015 struct smtc_ipi
*pipi
;
1016 extern void self_ipi(struct smtc_ipi
*);
1018 spin_lock(&q
->lock
);
1019 pipi
= __smtc_ipi_dq(q
);
1020 spin_unlock(&q
->lock
);
1025 smtc_cpu_stats
[cpu
].selfipis
++;
1030 void smtc_ipi_replay(void)
1032 raw_local_irq_disable();
1033 __smtc_ipi_replay();
1036 EXPORT_SYMBOL(smtc_ipi_replay
);
1038 void smtc_idle_loop_hook(void)
1040 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
1049 * printk within DMT-protected regions can deadlock,
1050 * so buffer diagnostic messages for later output.
1053 char id_ho_db_msg
[768]; /* worst-case use should be less than 700 */
1055 if (atomic_read(&idle_hook_initialized
) == 0) { /* fast test */
1056 if (atomic_add_return(1, &idle_hook_initialized
) == 1) {
1058 /* Tedious stuff to just do once */
1059 mvpconf0
= read_c0_mvpconf0();
1060 hook_ntcs
= ((mvpconf0
& MVPCONF0_PTC
) >> MVPCONF0_PTC_SHIFT
) + 1;
1061 if (hook_ntcs
> NR_CPUS
)
1062 hook_ntcs
= NR_CPUS
;
1063 for (tc
= 0; tc
< hook_ntcs
; tc
++) {
1065 clock_hang_reported
[tc
] = 0;
1067 for (vpe
= 0; vpe
< 2; vpe
++)
1068 for (im
= 0; im
< 8; im
++)
1069 imstuckcount
[vpe
][im
] = 0;
1070 printk("Idle loop test hook initialized for %d TCs\n", hook_ntcs
);
1071 atomic_set(&idle_hook_initialized
, 1000);
1073 /* Someone else is initializing in parallel - let 'em finish */
1074 while (atomic_read(&idle_hook_initialized
) < 1000)
1079 /* Have we stupidly left IXMT set somewhere? */
1080 if (read_c0_tcstatus() & 0x400) {
1081 write_c0_tcstatus(read_c0_tcstatus() & ~0x400);
1083 printk("Dangling IXMT in cpu_idle()\n");
1086 /* Have we stupidly left an IM bit turned off? */
1087 #define IM_LIMIT 2000
1088 local_irq_save(flags
);
1090 pdb_msg
= &id_ho_db_msg
[0];
1091 im
= read_c0_status();
1092 vpe
= current_cpu_data
.vpe_id
;
1093 for (bit
= 0; bit
< 8; bit
++) {
1095 * In current prototype, I/O interrupts
1096 * are masked for VPE > 0
1098 if (vpemask
[vpe
][bit
]) {
1099 if (!(im
& (0x100 << bit
)))
1100 imstuckcount
[vpe
][bit
]++;
1102 imstuckcount
[vpe
][bit
] = 0;
1103 if (imstuckcount
[vpe
][bit
] > IM_LIMIT
) {
1104 set_c0_status(0x100 << bit
);
1106 imstuckcount
[vpe
][bit
] = 0;
1107 pdb_msg
+= sprintf(pdb_msg
,
1108 "Dangling IM %d fixed for VPE %d\n", bit
,
1115 * Now that we limit outstanding timer IPIs, check for hung TC
1117 for (tc
= 0; tc
< NR_CPUS
; tc
++) {
1118 /* Don't check ourself - we'll dequeue IPIs just below */
1119 if ((tc
!= smp_processor_id()) &&
1120 ipi_timer_latch
[tc
] > timerq_limit
) {
1121 if (clock_hang_reported
[tc
] == 0) {
1122 pdb_msg
+= sprintf(pdb_msg
,
1123 "TC %d looks hung with timer latch at %d\n",
1124 tc
, ipi_timer_latch
[tc
]);
1125 clock_hang_reported
[tc
]++;
1130 local_irq_restore(flags
);
1131 if (pdb_msg
!= &id_ho_db_msg
[0])
1132 printk("CPU%d: %s", smp_processor_id(), id_ho_db_msg
);
1133 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
1136 * Replay any accumulated deferred IPIs. If "Instant Replay"
1137 * is in use, there should never be any.
1139 #ifndef CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY
1141 unsigned long flags
;
1143 local_irq_save(flags
);
1144 __smtc_ipi_replay();
1145 local_irq_restore(flags
);
1147 #endif /* CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY */
1150 void smtc_soft_dump(void)
1154 printk("Counter Interrupts taken per CPU (TC)\n");
1155 for (i
=0; i
< NR_CPUS
; i
++) {
1156 printk("%d: %ld\n", i
, smtc_cpu_stats
[i
].timerints
);
1158 printk("Self-IPI invocations:\n");
1159 for (i
=0; i
< NR_CPUS
; i
++) {
1160 printk("%d: %ld\n", i
, smtc_cpu_stats
[i
].selfipis
);
1163 printk("Timer IPI Backlogs:\n");
1164 for (i
=0; i
< NR_CPUS
; i
++) {
1165 printk("%d: %d\n", i
, ipi_timer_latch
[i
]);
1167 printk("%d Recoveries of \"stolen\" FPU\n",
1168 atomic_read(&smtc_fpu_recoveries
));
1173 * TLB management routines special to SMTC
1176 void smtc_get_new_mmu_context(struct mm_struct
*mm
, unsigned long cpu
)
1178 unsigned long flags
, mtflags
, tcstat
, prevhalt
, asid
;
1182 * It would be nice to be able to use a spinlock here,
1183 * but this is invoked from within TLB flush routines
1184 * that protect themselves with DVPE, so if a lock is
1185 * held by another TC, it'll never be freed.
1187 * DVPE/DMT must not be done with interrupts enabled,
1188 * so even so most callers will already have disabled
1189 * them, let's be really careful...
1192 local_irq_save(flags
);
1193 if (smtc_status
& SMTC_TLB_SHARED
) {
1198 tlb
= cpu_data
[cpu
].vpe_id
;
1200 asid
= asid_cache(cpu
);
1203 if (!((asid
+= ASID_INC
) & ASID_MASK
) ) {
1204 if (cpu_has_vtag_icache
)
1206 /* Traverse all online CPUs (hack requires contigous range) */
1207 for (i
= 0; i
< num_online_cpus(); i
++) {
1209 * We don't need to worry about our own CPU, nor those of
1210 * CPUs who don't share our TLB.
1212 if ((i
!= smp_processor_id()) &&
1213 ((smtc_status
& SMTC_TLB_SHARED
) ||
1214 (cpu_data
[i
].vpe_id
== cpu_data
[cpu
].vpe_id
))) {
1215 settc(cpu_data
[i
].tc_id
);
1216 prevhalt
= read_tc_c0_tchalt() & TCHALT_H
;
1218 write_tc_c0_tchalt(TCHALT_H
);
1221 tcstat
= read_tc_c0_tcstatus();
1222 smtc_live_asid
[tlb
][(tcstat
& ASID_MASK
)] |= (asiduse
)(0x1 << i
);
1224 write_tc_c0_tchalt(0);
1227 if (!asid
) /* fix version if needed */
1228 asid
= ASID_FIRST_VERSION
;
1229 local_flush_tlb_all(); /* start new asid cycle */
1231 } while (smtc_live_asid
[tlb
][(asid
& ASID_MASK
)]);
1234 * SMTC shares the TLB within VPEs and possibly across all VPEs.
1236 for (i
= 0; i
< num_online_cpus(); i
++) {
1237 if ((smtc_status
& SMTC_TLB_SHARED
) ||
1238 (cpu_data
[i
].vpe_id
== cpu_data
[cpu
].vpe_id
))
1239 cpu_context(i
, mm
) = asid_cache(i
) = asid
;
1242 if (smtc_status
& SMTC_TLB_SHARED
)
1246 local_irq_restore(flags
);
1250 * Invoked from macros defined in mmu_context.h
1251 * which must already have disabled interrupts
1252 * and done a DVPE or DMT as appropriate.
1255 void smtc_flush_tlb_asid(unsigned long asid
)
1260 entry
= read_c0_wired();
1262 /* Traverse all non-wired entries */
1263 while (entry
< current_cpu_data
.tlbsize
) {
1264 write_c0_index(entry
);
1268 ehi
= read_c0_entryhi();
1269 if ((ehi
& ASID_MASK
) == asid
) {
1271 * Invalidate only entries with specified ASID,
1272 * makiing sure all entries differ.
1274 write_c0_entryhi(CKSEG0
+ (entry
<< (PAGE_SHIFT
+ 1)));
1275 write_c0_entrylo0(0);
1276 write_c0_entrylo1(0);
1278 tlb_write_indexed();
1282 write_c0_index(PARKED_INDEX
);
1287 * Support for single-threading cache flush operations.
1290 static int halt_state_save
[NR_CPUS
];
1293 * To really, really be sure that nothing is being done
1294 * by other TCs, halt them all. This code assumes that
1295 * a DVPE has already been done, so while their Halted
1296 * state is theoretically architecturally unstable, in
1297 * practice, it's not going to change while we're looking
1301 void smtc_cflush_lockdown(void)
1305 for_each_online_cpu(cpu
) {
1306 if (cpu
!= smp_processor_id()) {
1307 settc(cpu_data
[cpu
].tc_id
);
1308 halt_state_save
[cpu
] = read_tc_c0_tchalt();
1309 write_tc_c0_tchalt(TCHALT_H
);
1315 /* It would be cheating to change the cpu_online states during a flush! */
1317 void smtc_cflush_release(void)
1322 * Start with a hazard barrier to ensure
1323 * that all CACHE ops have played through.
1327 for_each_online_cpu(cpu
) {
1328 if (cpu
!= smp_processor_id()) {
1329 settc(cpu_data
[cpu
].tc_id
);
1330 write_tc_c0_tchalt(halt_state_save
[cpu
]);