arch/mips/kernel/irq-msc01.c

   1 /*
   2  * This program is free software; you can redistribute  it and/or modify it
   3  * under  the terms of  the GNU General  Public License as published by the
   4  * Free Software Foundation;  either version 2 of the  License, or (at your
   5  * option) any later version.
   6  *
   7  * Copyright (c) 2004 MIPS Inc
   8  * Author: chris@mips.com
   9  *
  10  * Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org>
  11  */
  12 #include <linux/module.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel.h>
  15 #include <linux/sched.h>
  16 #include <linux/kernel_stat.h>
  17 #include <asm/io.h>
  18 #include <asm/irq.h>
  19 #include <asm/msc01_ic.h>
  20
  21 static unsigned long _icctrl_msc;
  22 #define MSC01_IC_REG_BASE       _icctrl_msc
  23
  24 #define MSCIC_WRITE(reg, data)  do { *(volatile u32 *)(reg) = data; } while (0)
  25 #define MSCIC_READ(reg, data)   do { data = *(volatile u32 *)(reg); } while (0)
  26
  27 static unsigned int irq_base;
  28
  29 /* mask off an interrupt */
  30 static inline void mask_msc_irq(unsigned int irq)
  31 {
  32         if (irq < (irq_base + 32))
  33                 MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base));
  34         else
  35                 MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32));
  36 }
  37
  38 /* unmask an interrupt */
  39 static inline void unmask_msc_irq(unsigned int irq)
  40 {
  41         if (irq < (irq_base + 32))
  42                 MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));
  43         else
  44                 MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32));
  45 }
  46
  47 /*
  48  * Masks and ACKs an IRQ
  49  */
  50 static void level_mask_and_ack_msc_irq(unsigned int irq)
  51 {
  52         mask_msc_irq(irq);
  53         if (!cpu_has_veic)
  54                 MSCIC_WRITE(MSC01_IC_EOI, 0);
  55         /* This actually needs to be a call into platform code */
  56         smtc_im_ack_irq(irq);
  57 }
  58
  59 /*
  60  * Masks and ACKs an IRQ
  61  */
  62 static void edge_mask_and_ack_msc_irq(unsigned int irq)
  63 {
  64         mask_msc_irq(irq);
  65         if (!cpu_has_veic)
  66                 MSCIC_WRITE(MSC01_IC_EOI, 0);
  67         else {
  68                 u32 r;
  69                 MSCIC_READ(MSC01_IC_SUP+irq*8, r);
  70                 MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT);
  71                 MSCIC_WRITE(MSC01_IC_SUP+irq*8, r);
  72         }
  73         smtc_im_ack_irq(irq);
  74 }
  75
  76 /*
  77  * End IRQ processing
  78  */
  79 static void end_msc_irq(unsigned int irq)
  80 {
  81         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
  82                 unmask_msc_irq(irq);
  83 }
  84
  85 /*
  86  * Interrupt handler for interrupts coming from SOC-it.
  87  */
  88 void ll_msc_irq(void)
  89 {
  90         unsigned int irq;
  91
  92         /* read the interrupt vector register */
  93         MSCIC_READ(MSC01_IC_VEC, irq);
  94         if (irq < 64)
  95                 do_IRQ(irq + irq_base);
  96         else {
  97                 /* Ignore spurious interrupt */
  98         }
  99 }
 100
 101 void
 102 msc_bind_eic_interrupt (unsigned int irq, unsigned int set)
 103 {
 104         MSCIC_WRITE(MSC01_IC_RAMW,
 105                     (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
 106 }
 107
 108 struct irq_chip msc_levelirq_type = {
 109         .name = "SOC-it-Level",
 110         .ack = level_mask_and_ack_msc_irq,
 111         .mask = mask_msc_irq,
 112         .mask_ack = level_mask_and_ack_msc_irq,
 113         .unmask = unmask_msc_irq,
 114         .eoi = unmask_msc_irq,
 115         .end = end_msc_irq,
 116 };
 117
 118 struct irq_chip msc_edgeirq_type = {
 119         .name = "SOC-it-Edge",
 120         .ack = edge_mask_and_ack_msc_irq,
 121         .mask = mask_msc_irq,
 122         .mask_ack = edge_mask_and_ack_msc_irq,
 123         .unmask = unmask_msc_irq,
 124         .eoi = unmask_msc_irq,
 125         .end = end_msc_irq,
 126 };
 127
 128
 129 void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq)
 130 {
 131         extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset);
 132
 133         _icctrl_msc = (unsigned long) ioremap (icubase, 0x40000);
 134
 135         /* Reset interrupt controller - initialises all registers to 0 */
 136         MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
 137
 138         board_bind_eic_interrupt = &msc_bind_eic_interrupt;
 139
 140         for (; nirq >= 0; nirq--, imp++) {
 141                 int n = imp->im_irq;
 142
 143                 switch (imp->im_type) {
 144                 case MSC01_IRQ_EDGE:
 145                         set_irq_chip(irqbase+n, &msc_edgeirq_type);
 146                         if (cpu_has_veic)
 147                                 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
 148                         else
 149                                 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
 150                         break;
 151                 case MSC01_IRQ_LEVEL:
 152                         set_irq_chip(irqbase+n, &msc_levelirq_type);
 153                         if (cpu_has_veic)
 154                                 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
 155                         else
 156                                 MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);
 157                 }
 158         }
 159
 160         irq_base = irqbase;
 161
 162         MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT);     /* Enable interrupt generation */
 163
 164 }