2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/init.h>
30 #include <linux/kmod.h>
31 #include <linux/poll.h>
32 #include <linux/nmi.h>
33 #include <linux/cpu.h>
34 #include <linux/smp.h>
38 #include <asm/processor.h>
39 #include <asm/hw_irq.h>
46 #include "mce-internal.h"
48 int mce_disabled __read_mostly
;
50 #define MISC_MCELOG_MINOR 227
52 #define SPINUNIT 100 /* 100ns */
56 DEFINE_PER_CPU(unsigned, mce_exception_count
);
60 * 0: always panic on uncorrected errors, log corrected errors
61 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
62 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
63 * 3: never panic or SIGBUS, log all errors (for testing only)
65 static int tolerant __read_mostly
= 1;
66 static int banks __read_mostly
;
67 static int rip_msr __read_mostly
;
68 static int mce_bootlog __read_mostly
= -1;
69 static int monarch_timeout __read_mostly
= -1;
70 static int mce_panic_timeout __read_mostly
;
71 static int mce_dont_log_ce __read_mostly
;
72 int mce_cmci_disabled __read_mostly
;
73 int mce_ignore_ce __read_mostly
;
74 int mce_ser __read_mostly
;
76 struct mce_bank
*mce_banks __read_mostly
;
78 /* User mode helper program triggered by machine check event */
79 static unsigned long mce_need_notify
;
80 static char mce_helper
[128];
81 static char *mce_helper_argv
[2] = { mce_helper
, NULL
};
83 static DECLARE_WAIT_QUEUE_HEAD(mce_wait
);
84 static DEFINE_PER_CPU(struct mce
, mces_seen
);
85 static int cpu_missing
;
88 /* MCA banks polled by the period polling timer for corrected events */
89 DEFINE_PER_CPU(mce_banks_t
, mce_poll_banks
) = {
90 [0 ... BITS_TO_LONGS(MAX_NR_BANKS
)-1] = ~0UL
93 static DEFINE_PER_CPU(struct work_struct
, mce_work
);
95 /* Do initial initialization of a struct mce */
96 void mce_setup(struct mce
*m
)
98 memset(m
, 0, sizeof(struct mce
));
99 m
->cpu
= m
->extcpu
= smp_processor_id();
101 /* We hope get_seconds stays lockless */
102 m
->time
= get_seconds();
103 m
->cpuvendor
= boot_cpu_data
.x86_vendor
;
104 m
->cpuid
= cpuid_eax(1);
106 m
->socketid
= cpu_data(m
->extcpu
).phys_proc_id
;
108 m
->apicid
= cpu_data(m
->extcpu
).initial_apicid
;
109 rdmsrl(MSR_IA32_MCG_CAP
, m
->mcgcap
);
112 DEFINE_PER_CPU(struct mce
, injectm
);
113 EXPORT_PER_CPU_SYMBOL_GPL(injectm
);
116 * Lockless MCE logging infrastructure.
117 * This avoids deadlocks on printk locks without having to break locks. Also
118 * separate MCEs from kernel messages to avoid bogus bug reports.
121 static struct mce_log mcelog
= {
122 .signature
= MCE_LOG_SIGNATURE
,
124 .recordlen
= sizeof(struct mce
),
127 void mce_log(struct mce
*mce
)
129 unsigned next
, entry
;
134 entry
= rcu_dereference(mcelog
.next
);
137 * When the buffer fills up discard new entries.
138 * Assume that the earlier errors are the more
141 if (entry
>= MCE_LOG_LEN
) {
142 set_bit(MCE_OVERFLOW
,
143 (unsigned long *)&mcelog
.flags
);
146 /* Old left over entry. Skip: */
147 if (mcelog
.entry
[entry
].finished
) {
155 if (cmpxchg(&mcelog
.next
, entry
, next
) == entry
)
158 memcpy(mcelog
.entry
+ entry
, mce
, sizeof(struct mce
));
160 mcelog
.entry
[entry
].finished
= 1;
164 set_bit(0, &mce_need_notify
);
167 static void print_mce(struct mce
*m
)
170 "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
171 m
->extcpu
, m
->mcgstatus
, m
->bank
, m
->status
);
173 printk(KERN_EMERG
"RIP%s %02x:<%016Lx> ",
174 !(m
->mcgstatus
& MCG_STATUS_EIPV
) ? " !INEXACT!" : "",
176 if (m
->cs
== __KERNEL_CS
)
177 print_symbol("{%s}", m
->ip
);
180 printk(KERN_EMERG
"TSC %llx ", m
->tsc
);
182 printk("ADDR %llx ", m
->addr
);
184 printk("MISC %llx ", m
->misc
);
186 printk(KERN_EMERG
"PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
187 m
->cpuvendor
, m
->cpuid
, m
->time
, m
->socketid
,
191 static void print_mce_head(void)
193 printk(KERN_EMERG
"\n" KERN_EMERG
"HARDWARE ERROR\n");
196 static void print_mce_tail(void)
198 printk(KERN_EMERG
"This is not a software problem!\n"
199 KERN_EMERG
"Run through mcelog --ascii to decode and contact your hardware vendor\n");
202 #define PANIC_TIMEOUT 5 /* 5 seconds */
204 static atomic_t mce_paniced
;
206 /* Panic in progress. Enable interrupts and wait for final IPI */
207 static void wait_for_panic(void)
209 long timeout
= PANIC_TIMEOUT
*USEC_PER_SEC
;
212 while (timeout
-- > 0)
214 if (panic_timeout
== 0)
215 panic_timeout
= mce_panic_timeout
;
216 panic("Panicing machine check CPU died");
219 static void mce_panic(char *msg
, struct mce
*final
, char *exp
)
224 * Make sure only one CPU runs in machine check panic
226 if (atomic_inc_return(&mce_paniced
) > 1)
233 /* First print corrected ones that are still unlogged */
234 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
235 struct mce
*m
= &mcelog
.entry
[i
];
236 if (!(m
->status
& MCI_STATUS_VAL
))
238 if (!(m
->status
& MCI_STATUS_UC
))
241 /* Now print uncorrected but with the final one last */
242 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
243 struct mce
*m
= &mcelog
.entry
[i
];
244 if (!(m
->status
& MCI_STATUS_VAL
))
246 if (!(m
->status
& MCI_STATUS_UC
))
248 if (!final
|| memcmp(m
, final
, sizeof(struct mce
)))
254 printk(KERN_EMERG
"Some CPUs didn't answer in synchronization\n");
257 printk(KERN_EMERG
"Machine check: %s\n", exp
);
258 if (panic_timeout
== 0)
259 panic_timeout
= mce_panic_timeout
;
263 /* Support code for software error injection */
265 static int msr_to_offset(u32 msr
)
267 unsigned bank
= __get_cpu_var(injectm
.bank
);
269 return offsetof(struct mce
, ip
);
270 if (msr
== MSR_IA32_MCx_STATUS(bank
))
271 return offsetof(struct mce
, status
);
272 if (msr
== MSR_IA32_MCx_ADDR(bank
))
273 return offsetof(struct mce
, addr
);
274 if (msr
== MSR_IA32_MCx_MISC(bank
))
275 return offsetof(struct mce
, misc
);
276 if (msr
== MSR_IA32_MCG_STATUS
)
277 return offsetof(struct mce
, mcgstatus
);
281 /* MSR access wrappers used for error injection */
282 static u64
mce_rdmsrl(u32 msr
)
285 if (__get_cpu_var(injectm
).finished
) {
286 int offset
= msr_to_offset(msr
);
289 return *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
);
295 static void mce_wrmsrl(u32 msr
, u64 v
)
297 if (__get_cpu_var(injectm
).finished
) {
298 int offset
= msr_to_offset(msr
);
300 *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
) = v
;
307 * Simple lockless ring to communicate PFNs from the exception handler with the
308 * process context work function. This is vastly simplified because there's
309 * only a single reader and a single writer.
311 #define MCE_RING_SIZE 16 /* we use one entry less */
314 unsigned short start
;
316 unsigned long ring
[MCE_RING_SIZE
];
318 static DEFINE_PER_CPU(struct mce_ring
, mce_ring
);
320 /* Runs with CPU affinity in workqueue */
321 static int mce_ring_empty(void)
323 struct mce_ring
*r
= &__get_cpu_var(mce_ring
);
325 return r
->start
== r
->end
;
328 static int mce_ring_get(unsigned long *pfn
)
335 r
= &__get_cpu_var(mce_ring
);
336 if (r
->start
== r
->end
)
338 *pfn
= r
->ring
[r
->start
];
339 r
->start
= (r
->start
+ 1) % MCE_RING_SIZE
;
346 /* Always runs in MCE context with preempt off */
347 static int mce_ring_add(unsigned long pfn
)
349 struct mce_ring
*r
= &__get_cpu_var(mce_ring
);
352 next
= (r
->end
+ 1) % MCE_RING_SIZE
;
353 if (next
== r
->start
)
355 r
->ring
[r
->end
] = pfn
;
361 int mce_available(struct cpuinfo_x86
*c
)
365 return cpu_has(c
, X86_FEATURE_MCE
) && cpu_has(c
, X86_FEATURE_MCA
);
368 static void mce_schedule_work(void)
370 if (!mce_ring_empty()) {
371 struct work_struct
*work
= &__get_cpu_var(mce_work
);
372 if (!work_pending(work
))
378 * Get the address of the instruction at the time of the machine check
381 static inline void mce_get_rip(struct mce
*m
, struct pt_regs
*regs
)
384 if (regs
&& (m
->mcgstatus
& (MCG_STATUS_RIPV
|MCG_STATUS_EIPV
))) {
392 m
->ip
= mce_rdmsrl(rip_msr
);
395 #ifdef CONFIG_X86_LOCAL_APIC
397 * Called after interrupts have been reenabled again
398 * when a MCE happened during an interrupts off region
401 asmlinkage
void smp_mce_self_interrupt(struct pt_regs
*regs
)
412 static void mce_report_event(struct pt_regs
*regs
)
414 if (regs
->flags
& (X86_VM_MASK
|X86_EFLAGS_IF
)) {
417 * Triggering the work queue here is just an insurance
418 * policy in case the syscall exit notify handler
419 * doesn't run soon enough or ends up running on the
420 * wrong CPU (can happen when audit sleeps)
426 #ifdef CONFIG_X86_LOCAL_APIC
428 * Without APIC do not notify. The event will be picked
435 * When interrupts are disabled we cannot use
436 * kernel services safely. Trigger an self interrupt
437 * through the APIC to instead do the notification
438 * after interrupts are reenabled again.
440 apic
->send_IPI_self(MCE_SELF_VECTOR
);
443 * Wait for idle afterwards again so that we don't leave the
444 * APIC in a non idle state because the normal APIC writes
447 apic_wait_icr_idle();
451 DEFINE_PER_CPU(unsigned, mce_poll_count
);
454 * Poll for corrected events or events that happened before reset.
455 * Those are just logged through /dev/mcelog.
457 * This is executed in standard interrupt context.
459 * Note: spec recommends to panic for fatal unsignalled
460 * errors here. However this would be quite problematic --
461 * we would need to reimplement the Monarch handling and
462 * it would mess up the exclusion between exception handler
463 * and poll hander -- * so we skip this for now.
464 * These cases should not happen anyways, or only when the CPU
465 * is already totally * confused. In this case it's likely it will
466 * not fully execute the machine check handler either.
468 void machine_check_poll(enum mcp_flags flags
, mce_banks_t
*b
)
473 __get_cpu_var(mce_poll_count
)++;
477 m
.mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
478 for (i
= 0; i
< banks
; i
++) {
479 if (!mce_banks
[i
].ctl
|| !test_bit(i
, *b
))
488 m
.status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
489 if (!(m
.status
& MCI_STATUS_VAL
))
493 * Uncorrected or signalled events are handled by the exception
494 * handler when it is enabled, so don't process those here.
496 * TBD do the same check for MCI_STATUS_EN here?
498 if (!(flags
& MCP_UC
) &&
499 (m
.status
& (mce_ser
? MCI_STATUS_S
: MCI_STATUS_UC
)))
502 if (m
.status
& MCI_STATUS_MISCV
)
503 m
.misc
= mce_rdmsrl(MSR_IA32_MCx_MISC(i
));
504 if (m
.status
& MCI_STATUS_ADDRV
)
505 m
.addr
= mce_rdmsrl(MSR_IA32_MCx_ADDR(i
));
507 if (!(flags
& MCP_TIMESTAMP
))
510 * Don't get the IP here because it's unlikely to
511 * have anything to do with the actual error location.
513 if (!(flags
& MCP_DONTLOG
) && !mce_dont_log_ce
) {
515 add_taint(TAINT_MACHINE_CHECK
);
519 * Clear state for this bank.
521 mce_wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
525 * Don't clear MCG_STATUS here because it's only defined for
531 EXPORT_SYMBOL_GPL(machine_check_poll
);
534 * Do a quick check if any of the events requires a panic.
535 * This decides if we keep the events around or clear them.
537 static int mce_no_way_out(struct mce
*m
, char **msg
)
541 for (i
= 0; i
< banks
; i
++) {
542 m
->status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
543 if (mce_severity(m
, tolerant
, msg
) >= MCE_PANIC_SEVERITY
)
550 * Variable to establish order between CPUs while scanning.
551 * Each CPU spins initially until executing is equal its number.
553 static atomic_t mce_executing
;
556 * Defines order of CPUs on entry. First CPU becomes Monarch.
558 static atomic_t mce_callin
;
561 * Check if a timeout waiting for other CPUs happened.
563 static int mce_timed_out(u64
*t
)
566 * The others already did panic for some reason.
567 * Bail out like in a timeout.
568 * rmb() to tell the compiler that system_state
569 * might have been modified by someone else.
572 if (atomic_read(&mce_paniced
))
574 if (!monarch_timeout
)
576 if ((s64
)*t
< SPINUNIT
) {
577 /* CHECKME: Make panic default for 1 too? */
579 mce_panic("Timeout synchronizing machine check over CPUs",
586 touch_nmi_watchdog();
591 * The Monarch's reign. The Monarch is the CPU who entered
592 * the machine check handler first. It waits for the others to
593 * raise the exception too and then grades them. When any
594 * error is fatal panic. Only then let the others continue.
596 * The other CPUs entering the MCE handler will be controlled by the
597 * Monarch. They are called Subjects.
599 * This way we prevent any potential data corruption in a unrecoverable case
600 * and also makes sure always all CPU's errors are examined.
602 * Also this detects the case of an machine check event coming from outer
603 * space (not detected by any CPUs) In this case some external agent wants
604 * us to shut down, so panic too.
606 * The other CPUs might still decide to panic if the handler happens
607 * in a unrecoverable place, but in this case the system is in a semi-stable
608 * state and won't corrupt anything by itself. It's ok to let the others
609 * continue for a bit first.
611 * All the spin loops have timeouts; when a timeout happens a CPU
612 * typically elects itself to be Monarch.
614 static void mce_reign(void)
617 struct mce
*m
= NULL
;
618 int global_worst
= 0;
623 * This CPU is the Monarch and the other CPUs have run
624 * through their handlers.
625 * Grade the severity of the errors of all the CPUs.
627 for_each_possible_cpu(cpu
) {
628 int severity
= mce_severity(&per_cpu(mces_seen
, cpu
), tolerant
,
630 if (severity
> global_worst
) {
632 global_worst
= severity
;
633 m
= &per_cpu(mces_seen
, cpu
);
638 * Cannot recover? Panic here then.
639 * This dumps all the mces in the log buffer and stops the
642 if (m
&& global_worst
>= MCE_PANIC_SEVERITY
&& tolerant
< 3)
643 mce_panic("Fatal Machine check", m
, msg
);
646 * For UC somewhere we let the CPU who detects it handle it.
647 * Also must let continue the others, otherwise the handling
648 * CPU could deadlock on a lock.
652 * No machine check event found. Must be some external
653 * source or one CPU is hung. Panic.
655 if (!m
&& tolerant
< 3)
656 mce_panic("Machine check from unknown source", NULL
, NULL
);
659 * Now clear all the mces_seen so that they don't reappear on
662 for_each_possible_cpu(cpu
)
663 memset(&per_cpu(mces_seen
, cpu
), 0, sizeof(struct mce
));
666 static atomic_t global_nwo
;
669 * Start of Monarch synchronization. This waits until all CPUs have
670 * entered the exception handler and then determines if any of them
671 * saw a fatal event that requires panic. Then it executes them
672 * in the entry order.
673 * TBD double check parallel CPU hotunplug
675 static int mce_start(int *no_way_out
)
678 int cpus
= num_online_cpus();
679 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
684 atomic_add(*no_way_out
, &global_nwo
);
686 * global_nwo should be updated before mce_callin
689 order
= atomic_inc_return(&mce_callin
);
694 while (atomic_read(&mce_callin
) != cpus
) {
695 if (mce_timed_out(&timeout
)) {
696 atomic_set(&global_nwo
, 0);
703 * mce_callin should be read before global_nwo
709 * Monarch: Starts executing now, the others wait.
711 atomic_set(&mce_executing
, 1);
714 * Subject: Now start the scanning loop one by one in
715 * the original callin order.
716 * This way when there are any shared banks it will be
717 * only seen by one CPU before cleared, avoiding duplicates.
719 while (atomic_read(&mce_executing
) < order
) {
720 if (mce_timed_out(&timeout
)) {
721 atomic_set(&global_nwo
, 0);
729 * Cache the global no_way_out state.
731 *no_way_out
= atomic_read(&global_nwo
);
737 * Synchronize between CPUs after main scanning loop.
738 * This invokes the bulk of the Monarch processing.
740 static int mce_end(int order
)
743 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
751 * Allow others to run.
753 atomic_inc(&mce_executing
);
756 /* CHECKME: Can this race with a parallel hotplug? */
757 int cpus
= num_online_cpus();
760 * Monarch: Wait for everyone to go through their scanning
763 while (atomic_read(&mce_executing
) <= cpus
) {
764 if (mce_timed_out(&timeout
))
774 * Subject: Wait for Monarch to finish.
776 while (atomic_read(&mce_executing
) != 0) {
777 if (mce_timed_out(&timeout
))
783 * Don't reset anything. That's done by the Monarch.
789 * Reset all global state.
792 atomic_set(&global_nwo
, 0);
793 atomic_set(&mce_callin
, 0);
797 * Let others run again.
799 atomic_set(&mce_executing
, 0);
804 * Check if the address reported by the CPU is in a format we can parse.
805 * It would be possible to add code for most other cases, but all would
806 * be somewhat complicated (e.g. segment offset would require an instruction
807 * parser). So only support physical addresses upto page granuality for now.
809 static int mce_usable_address(struct mce
*m
)
811 if (!(m
->status
& MCI_STATUS_MISCV
) || !(m
->status
& MCI_STATUS_ADDRV
))
813 if ((m
->misc
& 0x3f) > PAGE_SHIFT
)
815 if (((m
->misc
>> 6) & 7) != MCM_ADDR_PHYS
)
820 static void mce_clear_state(unsigned long *toclear
)
824 for (i
= 0; i
< banks
; i
++) {
825 if (test_bit(i
, toclear
))
826 mce_wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
831 * The actual machine check handler. This only handles real
832 * exceptions when something got corrupted coming in through int 18.
834 * This is executed in NMI context not subject to normal locking rules. This
835 * implies that most kernel services cannot be safely used. Don't even
836 * think about putting a printk in there!
838 * On Intel systems this is entered on all CPUs in parallel through
839 * MCE broadcast. However some CPUs might be broken beyond repair,
840 * so be always careful when synchronizing with others.
842 void do_machine_check(struct pt_regs
*regs
, long error_code
)
844 struct mce m
, *final
;
849 * Establish sequential order between the CPUs entering the machine
854 * If no_way_out gets set, there is no safe way to recover from this
855 * MCE. If tolerant is cranked up, we'll try anyway.
859 * If kill_it gets set, there might be a way to recover from this
863 DECLARE_BITMAP(toclear
, MAX_NR_BANKS
);
864 char *msg
= "Unknown";
866 atomic_inc(&mce_entry
);
868 __get_cpu_var(mce_exception_count
)++;
870 if (notify_die(DIE_NMI
, "machine check", regs
, error_code
,
871 18, SIGKILL
) == NOTIFY_STOP
)
878 m
.mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
879 no_way_out
= mce_no_way_out(&m
, &msg
);
881 final
= &__get_cpu_var(mces_seen
);
887 * When no restart IP must always kill or panic.
889 if (!(m
.mcgstatus
& MCG_STATUS_RIPV
))
893 * Go through all the banks in exclusion of the other CPUs.
894 * This way we don't report duplicated events on shared banks
895 * because the first one to see it will clear it.
897 order
= mce_start(&no_way_out
);
898 for (i
= 0; i
< banks
; i
++) {
899 __clear_bit(i
, toclear
);
900 if (!mce_banks
[i
].ctl
)
907 m
.status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
908 if ((m
.status
& MCI_STATUS_VAL
) == 0)
912 * Non uncorrected or non signaled errors are handled by
913 * machine_check_poll. Leave them alone, unless this panics.
915 if (!(m
.status
& (mce_ser
? MCI_STATUS_S
: MCI_STATUS_UC
)) &&
920 * Set taint even when machine check was not enabled.
922 add_taint(TAINT_MACHINE_CHECK
);
924 severity
= mce_severity(&m
, tolerant
, NULL
);
927 * When machine check was for corrected handler don't touch,
928 * unless we're panicing.
930 if (severity
== MCE_KEEP_SEVERITY
&& !no_way_out
)
932 __set_bit(i
, toclear
);
933 if (severity
== MCE_NO_SEVERITY
) {
935 * Machine check event was not enabled. Clear, but
942 * Kill on action required.
944 if (severity
== MCE_AR_SEVERITY
)
947 if (m
.status
& MCI_STATUS_MISCV
)
948 m
.misc
= mce_rdmsrl(MSR_IA32_MCx_MISC(i
));
949 if (m
.status
& MCI_STATUS_ADDRV
)
950 m
.addr
= mce_rdmsrl(MSR_IA32_MCx_ADDR(i
));
953 * Action optional error. Queue address for later processing.
954 * When the ring overflows we just ignore the AO error.
955 * RED-PEN add some logging mechanism when
956 * usable_address or mce_add_ring fails.
957 * RED-PEN don't ignore overflow for tolerant == 0
959 if (severity
== MCE_AO_SEVERITY
&& mce_usable_address(&m
))
960 mce_ring_add(m
.addr
>> PAGE_SHIFT
);
962 mce_get_rip(&m
, regs
);
965 if (severity
> worst
) {
972 mce_clear_state(toclear
);
975 * Do most of the synchronization with other CPUs.
976 * When there's any problem use only local no_way_out state.
978 if (mce_end(order
) < 0)
979 no_way_out
= worst
>= MCE_PANIC_SEVERITY
;
982 * If we have decided that we just CAN'T continue, and the user
983 * has not set tolerant to an insane level, give up and die.
985 * This is mainly used in the case when the system doesn't
986 * support MCE broadcasting or it has been disabled.
988 if (no_way_out
&& tolerant
< 3)
989 mce_panic("Fatal machine check on current CPU", final
, msg
);
992 * If the error seems to be unrecoverable, something should be
993 * done. Try to kill as little as possible. If we can kill just
994 * one task, do that. If the user has set the tolerance very
995 * high, don't try to do anything at all.
998 if (kill_it
&& tolerant
< 3)
999 force_sig(SIGBUS
, current
);
1001 /* notify userspace ASAP */
1002 set_thread_flag(TIF_MCE_NOTIFY
);
1005 mce_report_event(regs
);
1006 mce_wrmsrl(MSR_IA32_MCG_STATUS
, 0);
1008 atomic_dec(&mce_entry
);
1011 EXPORT_SYMBOL_GPL(do_machine_check
);
1013 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1014 void __attribute__((weak
)) memory_failure(unsigned long pfn
, int vector
)
1016 printk(KERN_ERR
"Action optional memory failure at %lx ignored\n", pfn
);
1020 * Called after mce notification in process context. This code
1021 * is allowed to sleep. Call the high level VM handler to process
1022 * any corrupted pages.
1023 * Assume that the work queue code only calls this one at a time
1025 * Note we don't disable preemption, so this code might run on the wrong
1026 * CPU. In this case the event is picked up by the scheduled work queue.
1027 * This is merely a fast path to expedite processing in some common
1030 void mce_notify_process(void)
1034 while (mce_ring_get(&pfn
))
1035 memory_failure(pfn
, MCE_VECTOR
);
1038 static void mce_process_work(struct work_struct
*dummy
)
1040 mce_notify_process();
1043 #ifdef CONFIG_X86_MCE_INTEL
1045 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1046 * @cpu: The CPU on which the event occurred.
1047 * @status: Event status information
1049 * This function should be called by the thermal interrupt after the
1050 * event has been processed and the decision was made to log the event
1053 * The status parameter will be saved to the 'status' field of 'struct mce'
1054 * and historically has been the register value of the
1055 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1057 void mce_log_therm_throt_event(__u64 status
)
1062 m
.bank
= MCE_THERMAL_BANK
;
1066 #endif /* CONFIG_X86_MCE_INTEL */
1069 * Periodic polling timer for "silent" machine check errors. If the
1070 * poller finds an MCE, poll 2x faster. When the poller finds no more
1071 * errors, poll 2x slower (up to check_interval seconds).
1073 static int check_interval
= 5 * 60; /* 5 minutes */
1075 static DEFINE_PER_CPU(int, next_interval
); /* in jiffies */
1076 static DEFINE_PER_CPU(struct timer_list
, mce_timer
);
1078 static void mcheck_timer(unsigned long data
)
1080 struct timer_list
*t
= &per_cpu(mce_timer
, data
);
1083 WARN_ON(smp_processor_id() != data
);
1085 if (mce_available(¤t_cpu_data
)) {
1086 machine_check_poll(MCP_TIMESTAMP
,
1087 &__get_cpu_var(mce_poll_banks
));
1091 * Alert userspace if needed. If we logged an MCE, reduce the
1092 * polling interval, otherwise increase the polling interval.
1094 n
= &__get_cpu_var(next_interval
);
1095 if (mce_notify_irq())
1096 *n
= max(*n
/2, HZ
/100);
1098 *n
= min(*n
*2, (int)round_jiffies_relative(check_interval
*HZ
));
1100 t
->expires
= jiffies
+ *n
;
1104 static void mce_do_trigger(struct work_struct
*work
)
1106 call_usermodehelper(mce_helper
, mce_helper_argv
, NULL
, UMH_NO_WAIT
);
1109 static DECLARE_WORK(mce_trigger_work
, mce_do_trigger
);
1112 * Notify the user(s) about new machine check events.
1113 * Can be called from interrupt context, but not from machine check/NMI
1116 int mce_notify_irq(void)
1118 /* Not more than two messages every minute */
1119 static DEFINE_RATELIMIT_STATE(ratelimit
, 60*HZ
, 2);
1121 clear_thread_flag(TIF_MCE_NOTIFY
);
1123 if (test_and_clear_bit(0, &mce_need_notify
)) {
1124 wake_up_interruptible(&mce_wait
);
1127 * There is no risk of missing notifications because
1128 * work_pending is always cleared before the function is
1131 if (mce_helper
[0] && !work_pending(&mce_trigger_work
))
1132 schedule_work(&mce_trigger_work
);
1134 if (__ratelimit(&ratelimit
))
1135 printk(KERN_INFO
"Machine check events logged\n");
1141 EXPORT_SYMBOL_GPL(mce_notify_irq
);
1143 static int mce_banks_init(void)
1147 mce_banks
= kzalloc(banks
* sizeof(struct mce_bank
), GFP_KERNEL
);
1150 for (i
= 0; i
< banks
; i
++) {
1151 struct mce_bank
*b
= &mce_banks
[i
];
1159 * Initialize Machine Checks for a CPU.
1161 static int __cpuinit
mce_cap_init(void)
1166 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1168 b
= cap
& MCG_BANKCNT_MASK
;
1169 printk(KERN_INFO
"mce: CPU supports %d MCE banks\n", b
);
1171 if (b
> MAX_NR_BANKS
) {
1173 "MCE: Using only %u machine check banks out of %u\n",
1178 /* Don't support asymmetric configurations today */
1179 WARN_ON(banks
!= 0 && b
!= banks
);
1182 int err
= mce_banks_init();
1187 /* Use accurate RIP reporting if available. */
1188 if ((cap
& MCG_EXT_P
) && MCG_EXT_CNT(cap
) >= 9)
1189 rip_msr
= MSR_IA32_MCG_EIP
;
1191 if (cap
& MCG_SER_P
)
1197 static void mce_init(void)
1199 mce_banks_t all_banks
;
1204 * Log the machine checks left over from the previous reset.
1206 bitmap_fill(all_banks
, MAX_NR_BANKS
);
1207 machine_check_poll(MCP_UC
|(!mce_bootlog
? MCP_DONTLOG
: 0), &all_banks
);
1209 set_in_cr4(X86_CR4_MCE
);
1211 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1212 if (cap
& MCG_CTL_P
)
1213 wrmsr(MSR_IA32_MCG_CTL
, 0xffffffff, 0xffffffff);
1215 for (i
= 0; i
< banks
; i
++) {
1216 struct mce_bank
*b
= &mce_banks
[i
];
1219 wrmsrl(MSR_IA32_MCx_CTL(i
), b
->ctl
);
1220 wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
1224 /* Add per CPU specific workarounds here */
1225 static void __cpuinit
mce_cpu_quirks(struct cpuinfo_x86
*c
)
1227 /* This should be disabled by the BIOS, but isn't always */
1228 if (c
->x86_vendor
== X86_VENDOR_AMD
) {
1229 if (c
->x86
== 15 && banks
> 4) {
1231 * disable GART TBL walk error reporting, which
1232 * trips off incorrectly with the IOMMU & 3ware
1235 clear_bit(10, (unsigned long *)&mce_banks
[4].ctl
);
1237 if (c
->x86
<= 17 && mce_bootlog
< 0) {
1239 * Lots of broken BIOS around that don't clear them
1240 * by default and leave crap in there. Don't log:
1245 * Various K7s with broken bank 0 around. Always disable
1248 if (c
->x86
== 6 && banks
> 0)
1249 mce_banks
[0].ctl
= 0;
1252 if (c
->x86_vendor
== X86_VENDOR_INTEL
) {
1254 * SDM documents that on family 6 bank 0 should not be written
1255 * because it aliases to another special BIOS controlled
1257 * But it's not aliased anymore on model 0x1a+
1258 * Don't ignore bank 0 completely because there could be a
1259 * valid event later, merely don't write CTL0.
1262 if (c
->x86
== 6 && c
->x86_model
< 0x1A && banks
> 0)
1263 mce_banks
[0].init
= 0;
1266 * All newer Intel systems support MCE broadcasting. Enable
1267 * synchronization with a one second timeout.
1269 if ((c
->x86
> 6 || (c
->x86
== 6 && c
->x86_model
>= 0xe)) &&
1270 monarch_timeout
< 0)
1271 monarch_timeout
= USEC_PER_SEC
;
1273 /* There are also broken BIOSes on some Pentium M systems. */
1274 if (c
->x86
== 6 && c
->x86_model
== 13 && mce_bootlog
< 0)
1277 if (monarch_timeout
< 0)
1278 monarch_timeout
= 0;
1279 if (mce_bootlog
!= 0)
1280 mce_panic_timeout
= 30;
1283 static void __cpuinit
mce_ancient_init(struct cpuinfo_x86
*c
)
1287 switch (c
->x86_vendor
) {
1288 case X86_VENDOR_INTEL
:
1289 intel_p5_mcheck_init(c
);
1291 case X86_VENDOR_CENTAUR
:
1292 winchip_mcheck_init(c
);
1297 static void mce_cpu_features(struct cpuinfo_x86
*c
)
1299 switch (c
->x86_vendor
) {
1300 case X86_VENDOR_INTEL
:
1301 mce_intel_feature_init(c
);
1303 case X86_VENDOR_AMD
:
1304 mce_amd_feature_init(c
);
1311 static void mce_init_timer(void)
1313 struct timer_list
*t
= &__get_cpu_var(mce_timer
);
1314 int *n
= &__get_cpu_var(next_interval
);
1319 *n
= check_interval
* HZ
;
1322 setup_timer(t
, mcheck_timer
, smp_processor_id());
1323 t
->expires
= round_jiffies(jiffies
+ *n
);
1327 /* Handle unconfigured int18 (should never happen) */
1328 static void unexpected_machine_check(struct pt_regs
*regs
, long error_code
)
1330 printk(KERN_ERR
"CPU#%d: Unexpected int18 (Machine Check).\n",
1331 smp_processor_id());
1334 /* Call the installed machine check handler for this CPU setup. */
1335 void (*machine_check_vector
)(struct pt_regs
*, long error_code
) =
1336 unexpected_machine_check
;
1339 * Called for each booted CPU to set up machine checks.
1340 * Must be called with preempt off:
1342 void __cpuinit
mcheck_init(struct cpuinfo_x86
*c
)
1347 mce_ancient_init(c
);
1349 if (!mce_available(c
))
1352 if (mce_cap_init() < 0) {
1358 machine_check_vector
= do_machine_check
;
1361 mce_cpu_features(c
);
1363 INIT_WORK(&__get_cpu_var(mce_work
), mce_process_work
);
1367 * Character device to read and clear the MCE log.
1370 static DEFINE_SPINLOCK(mce_state_lock
);
1371 static int open_count
; /* #times opened */
1372 static int open_exclu
; /* already open exclusive? */
1374 static int mce_open(struct inode
*inode
, struct file
*file
)
1376 spin_lock(&mce_state_lock
);
1378 if (open_exclu
|| (open_count
&& (file
->f_flags
& O_EXCL
))) {
1379 spin_unlock(&mce_state_lock
);
1384 if (file
->f_flags
& O_EXCL
)
1388 spin_unlock(&mce_state_lock
);
1390 return nonseekable_open(inode
, file
);
1393 static int mce_release(struct inode
*inode
, struct file
*file
)
1395 spin_lock(&mce_state_lock
);
1400 spin_unlock(&mce_state_lock
);
1405 static void collect_tscs(void *data
)
1407 unsigned long *cpu_tsc
= (unsigned long *)data
;
1409 rdtscll(cpu_tsc
[smp_processor_id()]);
1412 static DEFINE_MUTEX(mce_read_mutex
);
1414 static ssize_t
mce_read(struct file
*filp
, char __user
*ubuf
, size_t usize
,
1417 char __user
*buf
= ubuf
;
1418 unsigned long *cpu_tsc
;
1419 unsigned prev
, next
;
1422 cpu_tsc
= kmalloc(nr_cpu_ids
* sizeof(long), GFP_KERNEL
);
1426 mutex_lock(&mce_read_mutex
);
1427 next
= rcu_dereference(mcelog
.next
);
1429 /* Only supports full reads right now */
1430 if (*off
!= 0 || usize
< MCE_LOG_LEN
*sizeof(struct mce
)) {
1431 mutex_unlock(&mce_read_mutex
);
1440 for (i
= prev
; i
< next
; i
++) {
1441 unsigned long start
= jiffies
;
1443 while (!mcelog
.entry
[i
].finished
) {
1444 if (time_after_eq(jiffies
, start
+ 2)) {
1445 memset(mcelog
.entry
+ i
, 0,
1446 sizeof(struct mce
));
1452 err
|= copy_to_user(buf
, mcelog
.entry
+ i
,
1453 sizeof(struct mce
));
1454 buf
+= sizeof(struct mce
);
1459 memset(mcelog
.entry
+ prev
, 0,
1460 (next
- prev
) * sizeof(struct mce
));
1462 next
= cmpxchg(&mcelog
.next
, prev
, 0);
1463 } while (next
!= prev
);
1465 synchronize_sched();
1468 * Collect entries that were still getting written before the
1471 on_each_cpu(collect_tscs
, cpu_tsc
, 1);
1473 for (i
= next
; i
< MCE_LOG_LEN
; i
++) {
1474 if (mcelog
.entry
[i
].finished
&&
1475 mcelog
.entry
[i
].tsc
< cpu_tsc
[mcelog
.entry
[i
].cpu
]) {
1476 err
|= copy_to_user(buf
, mcelog
.entry
+i
,
1477 sizeof(struct mce
));
1479 buf
+= sizeof(struct mce
);
1480 memset(&mcelog
.entry
[i
], 0, sizeof(struct mce
));
1483 mutex_unlock(&mce_read_mutex
);
1486 return err
? -EFAULT
: buf
- ubuf
;
1489 static unsigned int mce_poll(struct file
*file
, poll_table
*wait
)
1491 poll_wait(file
, &mce_wait
, wait
);
1492 if (rcu_dereference(mcelog
.next
))
1493 return POLLIN
| POLLRDNORM
;
1497 static long mce_ioctl(struct file
*f
, unsigned int cmd
, unsigned long arg
)
1499 int __user
*p
= (int __user
*)arg
;
1501 if (!capable(CAP_SYS_ADMIN
))
1505 case MCE_GET_RECORD_LEN
:
1506 return put_user(sizeof(struct mce
), p
);
1507 case MCE_GET_LOG_LEN
:
1508 return put_user(MCE_LOG_LEN
, p
);
1509 case MCE_GETCLEAR_FLAGS
: {
1513 flags
= mcelog
.flags
;
1514 } while (cmpxchg(&mcelog
.flags
, flags
, 0) != flags
);
1516 return put_user(flags
, p
);
1523 /* Modified in mce-inject.c, so not static or const */
1524 struct file_operations mce_chrdev_ops
= {
1526 .release
= mce_release
,
1529 .unlocked_ioctl
= mce_ioctl
,
1531 EXPORT_SYMBOL_GPL(mce_chrdev_ops
);
1533 static struct miscdevice mce_log_device
= {
1540 * mce=off Disables machine check
1541 * mce=no_cmci Disables CMCI
1542 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1543 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1544 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1545 * monarchtimeout is how long to wait for other CPUs on machine
1546 * check, or 0 to not wait
1547 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1548 * mce=nobootlog Don't log MCEs from before booting.
1550 static int __init
mcheck_enable(char *str
)
1558 if (!strcmp(str
, "off"))
1560 else if (!strcmp(str
, "no_cmci"))
1561 mce_cmci_disabled
= 1;
1562 else if (!strcmp(str
, "dont_log_ce"))
1563 mce_dont_log_ce
= 1;
1564 else if (!strcmp(str
, "ignore_ce"))
1566 else if (!strcmp(str
, "bootlog") || !strcmp(str
, "nobootlog"))
1567 mce_bootlog
= (str
[0] == 'b');
1568 else if (isdigit(str
[0])) {
1569 get_option(&str
, &tolerant
);
1572 get_option(&str
, &monarch_timeout
);
1575 printk(KERN_INFO
"mce argument %s ignored. Please use /sys\n",
1581 __setup("mce", mcheck_enable
);
1588 * Disable machine checks on suspend and shutdown. We can't really handle
1591 static int mce_disable(void)
1595 for (i
= 0; i
< banks
; i
++) {
1596 struct mce_bank
*b
= &mce_banks
[i
];
1598 wrmsrl(MSR_IA32_MCx_CTL(i
), 0);
1603 static int mce_suspend(struct sys_device
*dev
, pm_message_t state
)
1605 return mce_disable();
1608 static int mce_shutdown(struct sys_device
*dev
)
1610 return mce_disable();
1614 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1615 * Only one CPU is active at this time, the others get re-added later using
1618 static int mce_resume(struct sys_device
*dev
)
1621 mce_cpu_features(¤t_cpu_data
);
1626 static void mce_cpu_restart(void *data
)
1628 del_timer_sync(&__get_cpu_var(mce_timer
));
1629 if (!mce_available(¤t_cpu_data
))
1635 /* Reinit MCEs after user configuration changes */
1636 static void mce_restart(void)
1638 on_each_cpu(mce_cpu_restart
, NULL
, 1);
1641 /* Toggle features for corrected errors */
1642 static void mce_disable_ce(void *all
)
1644 if (!mce_available(¤t_cpu_data
))
1647 del_timer_sync(&__get_cpu_var(mce_timer
));
1651 static void mce_enable_ce(void *all
)
1653 if (!mce_available(¤t_cpu_data
))
1661 static struct sysdev_class mce_sysclass
= {
1662 .suspend
= mce_suspend
,
1663 .shutdown
= mce_shutdown
,
1664 .resume
= mce_resume
,
1665 .name
= "machinecheck",
1668 DEFINE_PER_CPU(struct sys_device
, mce_dev
);
1671 void (*threshold_cpu_callback
)(unsigned long action
, unsigned int cpu
);
1673 static inline struct mce_bank
*attr_to_bank(struct sysdev_attribute
*attr
)
1675 return container_of(attr
, struct mce_bank
, attr
);
1678 static ssize_t
show_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1681 return sprintf(buf
, "%llx\n", attr_to_bank(attr
)->ctl
);
1684 static ssize_t
set_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1685 const char *buf
, size_t size
)
1689 if (strict_strtoull(buf
, 0, &new) < 0)
1692 attr_to_bank(attr
)->ctl
= new;
1699 show_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
, char *buf
)
1701 strcpy(buf
, mce_helper
);
1703 return strlen(mce_helper
) + 1;
1706 static ssize_t
set_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1707 const char *buf
, size_t siz
)
1712 strncpy(mce_helper
, buf
, sizeof(mce_helper
));
1713 mce_helper
[sizeof(mce_helper
)-1] = 0;
1714 len
= strlen(mce_helper
);
1715 p
= strchr(mce_helper
, '\n');
1723 static ssize_t
set_ignore_ce(struct sys_device
*s
,
1724 struct sysdev_attribute
*attr
,
1725 const char *buf
, size_t size
)
1729 if (strict_strtoull(buf
, 0, &new) < 0)
1732 if (mce_ignore_ce
^ !!new) {
1734 /* disable ce features */
1735 on_each_cpu(mce_disable_ce
, (void *)1, 1);
1738 /* enable ce features */
1740 on_each_cpu(mce_enable_ce
, (void *)1, 1);
1746 static ssize_t
set_cmci_disabled(struct sys_device
*s
,
1747 struct sysdev_attribute
*attr
,
1748 const char *buf
, size_t size
)
1752 if (strict_strtoull(buf
, 0, &new) < 0)
1755 if (mce_cmci_disabled
^ !!new) {
1758 on_each_cpu(mce_disable_ce
, NULL
, 1);
1759 mce_cmci_disabled
= 1;
1762 mce_cmci_disabled
= 0;
1763 on_each_cpu(mce_enable_ce
, NULL
, 1);
1769 static ssize_t
store_int_with_restart(struct sys_device
*s
,
1770 struct sysdev_attribute
*attr
,
1771 const char *buf
, size_t size
)
1773 ssize_t ret
= sysdev_store_int(s
, attr
, buf
, size
);
1778 static SYSDEV_ATTR(trigger
, 0644, show_trigger
, set_trigger
);
1779 static SYSDEV_INT_ATTR(tolerant
, 0644, tolerant
);
1780 static SYSDEV_INT_ATTR(monarch_timeout
, 0644, monarch_timeout
);
1781 static SYSDEV_INT_ATTR(dont_log_ce
, 0644, mce_dont_log_ce
);
1783 static struct sysdev_ext_attribute attr_check_interval
= {
1784 _SYSDEV_ATTR(check_interval
, 0644, sysdev_show_int
,
1785 store_int_with_restart
),
1789 static struct sysdev_ext_attribute attr_ignore_ce
= {
1790 _SYSDEV_ATTR(ignore_ce
, 0644, sysdev_show_int
, set_ignore_ce
),
1794 static struct sysdev_ext_attribute attr_cmci_disabled
= {
1795 _SYSDEV_ATTR(cmci_disabled
, 0644, sysdev_show_int
, set_cmci_disabled
),
1799 static struct sysdev_attribute
*mce_attrs
[] = {
1800 &attr_tolerant
.attr
,
1801 &attr_check_interval
.attr
,
1803 &attr_monarch_timeout
.attr
,
1804 &attr_dont_log_ce
.attr
,
1805 &attr_ignore_ce
.attr
,
1806 &attr_cmci_disabled
.attr
,
1810 static cpumask_var_t mce_dev_initialized
;
1812 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1813 static __cpuinit
int mce_create_device(unsigned int cpu
)
1818 if (!mce_available(&boot_cpu_data
))
1821 memset(&per_cpu(mce_dev
, cpu
).kobj
, 0, sizeof(struct kobject
));
1822 per_cpu(mce_dev
, cpu
).id
= cpu
;
1823 per_cpu(mce_dev
, cpu
).cls
= &mce_sysclass
;
1825 err
= sysdev_register(&per_cpu(mce_dev
, cpu
));
1829 for (i
= 0; mce_attrs
[i
]; i
++) {
1830 err
= sysdev_create_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1834 for (j
= 0; j
< banks
; j
++) {
1835 err
= sysdev_create_file(&per_cpu(mce_dev
, cpu
),
1836 &mce_banks
[j
].attr
);
1840 cpumask_set_cpu(cpu
, mce_dev_initialized
);
1845 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), &mce_banks
[j
].attr
);
1848 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), &mce_banks
[i
].attr
);
1850 sysdev_unregister(&per_cpu(mce_dev
, cpu
));
1855 static __cpuinit
void mce_remove_device(unsigned int cpu
)
1859 if (!cpumask_test_cpu(cpu
, mce_dev_initialized
))
1862 for (i
= 0; mce_attrs
[i
]; i
++)
1863 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1865 for (i
= 0; i
< banks
; i
++)
1866 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), &mce_banks
[i
].attr
);
1868 sysdev_unregister(&per_cpu(mce_dev
, cpu
));
1869 cpumask_clear_cpu(cpu
, mce_dev_initialized
);
1872 /* Make sure there are no machine checks on offlined CPUs. */
1873 static void mce_disable_cpu(void *h
)
1875 unsigned long action
= *(unsigned long *)h
;
1878 if (!mce_available(¤t_cpu_data
))
1880 if (!(action
& CPU_TASKS_FROZEN
))
1882 for (i
= 0; i
< banks
; i
++) {
1883 struct mce_bank
*b
= &mce_banks
[i
];
1885 wrmsrl(MSR_IA32_MCx_CTL(i
), 0);
1889 static void mce_reenable_cpu(void *h
)
1891 unsigned long action
= *(unsigned long *)h
;
1894 if (!mce_available(¤t_cpu_data
))
1897 if (!(action
& CPU_TASKS_FROZEN
))
1899 for (i
= 0; i
< banks
; i
++) {
1900 struct mce_bank
*b
= &mce_banks
[i
];
1902 wrmsrl(MSR_IA32_MCx_CTL(i
), b
->ctl
);
1906 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1907 static int __cpuinit
1908 mce_cpu_callback(struct notifier_block
*nfb
, unsigned long action
, void *hcpu
)
1910 unsigned int cpu
= (unsigned long)hcpu
;
1911 struct timer_list
*t
= &per_cpu(mce_timer
, cpu
);
1915 case CPU_ONLINE_FROZEN
:
1916 mce_create_device(cpu
);
1917 if (threshold_cpu_callback
)
1918 threshold_cpu_callback(action
, cpu
);
1921 case CPU_DEAD_FROZEN
:
1922 if (threshold_cpu_callback
)
1923 threshold_cpu_callback(action
, cpu
);
1924 mce_remove_device(cpu
);
1926 case CPU_DOWN_PREPARE
:
1927 case CPU_DOWN_PREPARE_FROZEN
:
1929 smp_call_function_single(cpu
, mce_disable_cpu
, &action
, 1);
1931 case CPU_DOWN_FAILED
:
1932 case CPU_DOWN_FAILED_FROZEN
:
1933 t
->expires
= round_jiffies(jiffies
+
1934 __get_cpu_var(next_interval
));
1935 add_timer_on(t
, cpu
);
1936 smp_call_function_single(cpu
, mce_reenable_cpu
, &action
, 1);
1939 /* intentionally ignoring frozen here */
1940 cmci_rediscover(cpu
);
1946 static struct notifier_block mce_cpu_notifier __cpuinitdata
= {
1947 .notifier_call
= mce_cpu_callback
,
1950 static __init
void mce_init_banks(void)
1954 for (i
= 0; i
< banks
; i
++) {
1955 struct mce_bank
*b
= &mce_banks
[i
];
1956 struct sysdev_attribute
*a
= &b
->attr
;
1958 a
->attr
.name
= b
->attrname
;
1959 snprintf(b
->attrname
, ATTR_LEN
, "bank%d", i
);
1961 a
->attr
.mode
= 0644;
1962 a
->show
= show_bank
;
1963 a
->store
= set_bank
;
1967 static __init
int mce_init_device(void)
1972 if (!mce_available(&boot_cpu_data
))
1975 zalloc_cpumask_var(&mce_dev_initialized
, GFP_KERNEL
);
1979 err
= sysdev_class_register(&mce_sysclass
);
1983 for_each_online_cpu(i
) {
1984 err
= mce_create_device(i
);
1989 register_hotcpu_notifier(&mce_cpu_notifier
);
1990 misc_register(&mce_log_device
);
1995 device_initcall(mce_init_device
);
1998 * Old style boot options parsing. Only for compatibility.
2000 static int __init
mcheck_disable(char *str
)
2005 __setup("nomce", mcheck_disable
);