include/asm-arm26/system.h

   1 #ifndef __ASM_ARM_SYSTEM_H
   2 #define __ASM_ARM_SYSTEM_H
   3
   4 #ifdef __KERNEL__
   5
   6
   7 /*
   8  * This is used to ensure the compiler did actually allocate the register we
   9  * asked it for some inline assembly sequences.  Apparently we can't trust
  10  * the compiler from one version to another so a bit of paranoia won't hurt.
  11  * This string is meant to be concatenated with the inline asm string and
  12  * will cause compilation to stop on mismatch. (From ARM32 - may come in handy)
  13  */
  14 #define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
  15
  16 #ifndef __ASSEMBLY__
  17
  18 #include <linux/linkage.h>
  19
  20 struct thread_info;
  21 struct task_struct;
  22
  23 #if 0
  24 /* information about the system we're running on */
  25 extern unsigned int system_rev;
  26 extern unsigned int system_serial_low;
  27 extern unsigned int system_serial_high;
  28 extern unsigned int mem_fclk_21285;
  29
  30 FIXME - sort this
  31 /*
  32  * We need to turn the caches off before calling the reset vector - RiscOS
  33  * messes up if we don't
  34  */
  35 #define proc_hard_reset()       cpu_proc_fin()
  36
  37 #endif
  38
  39 struct pt_regs;
  40
  41 void die(const char *msg, struct pt_regs *regs, int err)
  42                 __attribute__((noreturn));
  43
  44 void die_if_kernel(const char *str, struct pt_regs *regs, int err);
  45
  46 void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
  47                                        struct pt_regs *),
  48                      int sig, const char *name);
  49
  50 #include <asm/proc-fns.h>
  51
  52 #define xchg(ptr,x) \
  53         ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
  54
  55 #define tas(ptr) (xchg((ptr),1))
  56
  57 extern asmlinkage void __backtrace(void);
  58
  59 #define set_cr(x)                                       \
  60         __asm__ __volatile__(                           \
  61         "mcr    p15, 0, %0, c1, c0, 0   @ set CR"       \
  62         : : "r" (x) : "cc")
  63
  64 #define get_cr()                                        \
  65         ({                                              \
  66         unsigned int __val;                             \
  67         __asm__ __volatile__(                           \
  68         "mrc    p15, 0, %0, c1, c0, 0   @ get CR"       \
  69         : "=r" (__val) : : "cc");                       \
  70         __val;                                          \
  71         })
  72
  73 extern unsigned long cr_no_alignment;   /* defined in entry-armv.S */
  74 extern unsigned long cr_alignment;      /* defined in entry-armv.S */
  75
  76 #define UDBG_UNDEFINED  (1 << 0)
  77 #define UDBG_SYSCALL    (1 << 1)
  78 #define UDBG_BADABORT   (1 << 2)
  79 #define UDBG_SEGV       (1 << 3)
  80 #define UDBG_BUS        (1 << 4)
  81
  82 extern unsigned int user_debug;
  83
  84 #define vectors_base()  (0)
  85
  86 #define mb() __asm__ __volatile__ ("" : : : "memory")
  87 #define rmb() mb()
  88 #define wmb() mb()
  89 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
  90
  91 #define read_barrier_depends() do { } while(0)
  92 #define set_mb(var, value)  do { var = value; mb(); } while (0)
  93 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
  94
  95 /*
  96  * We assume knowledge of how
  97  * spin_unlock_irq() and friends are implemented.  This avoids
  98  * us needlessly decrementing and incrementing the preempt count.
  99  */
 100 #define prepare_arch_switch(next)       local_irq_enable()
 101 #define finish_arch_switch(prev)        spin_unlock(&(rq)->lock)
 102
 103 /*
 104  * switch_to(prev, next) should switch from task `prev' to `next'
 105  * `prev' will never be the same as `next'.  schedule() itself
 106  * contains the memory barrier to tell GCC not to cache `current'.
 107  */
 108 extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
 109
 110 #define switch_to(prev,next,last)                                       \
 111 do {                                                                    \
 112         last = __switch_to(prev,task_thread_info(prev),task_thread_info(next)); \
 113 } while (0)
 114
 115 /*
 116  * On SMP systems, when the scheduler does migration-cost autodetection,
 117  * it needs a way to flush as much of the CPU's caches as possible.
 118  *
 119  * TODO: fill this in!
 120  */
 121 static inline void sched_cacheflush(void)
 122 {
 123 }
 124
 125 /*
 126  * Save the current interrupt enable state & disable IRQs
 127  */
 128 #define local_irq_save(x)                               \
 129         do {                                            \
 130           unsigned long temp;                           \
 131           __asm__ __volatile__(                         \
 132 "       mov     %0, pc          @ save_flags_cli\n"     \
 133 "       orr     %1, %0, #0x08000000\n"                  \
 134 "       and     %0, %0, #0x0c000000\n"                  \
 135 "       teqp    %1, #0\n"                               \
 136           : "=r" (x), "=r" (temp)                       \
 137           :                                             \
 138           : "memory");                                  \
 139         } while (0)
 140
 141 /*
 142  * Enable IRQs  (sti)
 143  */
 144 #define local_irq_enable()                                      \
 145         do {                                    \
 146           unsigned long temp;                   \
 147           __asm__ __volatile__(                 \
 148 "       mov     %0, pc          @ sti\n"        \
 149 "       bic     %0, %0, #0x08000000\n"          \
 150 "       teqp    %0, #0\n"                       \
 151           : "=r" (temp)                         \
 152           :                                     \
 153           : "memory");                          \
 154         } while(0)
 155
 156 /*
 157  * Disable IRQs (cli)
 158  */
 159 #define local_irq_disable()                                     \
 160         do {                                    \
 161           unsigned long temp;                   \
 162           __asm__ __volatile__(                 \
 163 "       mov     %0, pc          @ cli\n"        \
 164 "       orr     %0, %0, #0x08000000\n"          \
 165 "       teqp    %0, #0\n"                       \
 166           : "=r" (temp)                         \
 167           :                                     \
 168           : "memory");                          \
 169         } while(0)
 170
 171 /* Enable FIQs (stf) */
 172
 173 #define __stf() do {                            \
 174         unsigned long temp;                     \
 175         __asm__ __volatile__(                   \
 176 "       mov     %0, pc          @ stf\n"        \
 177 "       bic     %0, %0, #0x04000000\n"          \
 178 "       teqp    %0, #0\n"                       \
 179         : "=r" (temp));                         \
 180     } while(0)
 181
 182 /* Disable FIQs  (clf) */
 183
 184 #define __clf() do {                            \
 185         unsigned long temp;                     \
 186         __asm__ __volatile__(                   \
 187 "       mov     %0, pc          @ clf\n"        \
 188 "       orr     %0, %0, #0x04000000\n"          \
 189 "       teqp    %0, #0\n"                       \
 190         : "=r" (temp));                         \
 191     } while(0)
 192
 193
 194 /*
 195  * Save the current interrupt enable state.
 196  */
 197 #define local_save_flags(x)                             \
 198         do {                                    \
 199           __asm__ __volatile__(                 \
 200 "       mov     %0, pc          @ save_flags\n" \
 201 "       and     %0, %0, #0x0c000000\n"          \
 202           : "=r" (x));                          \
 203         } while (0)
 204
 205
 206 /*
 207  * restore saved IRQ & FIQ state
 208  */
 209 #define local_irq_restore(x)                            \
 210         do {                                            \
 211           unsigned long temp;                           \
 212           __asm__ __volatile__(                         \
 213 "       mov     %0, pc          @ restore_flags\n"      \
 214 "       bic     %0, %0, #0x0c000000\n"                  \
 215 "       orr     %0, %0, %1\n"                           \
 216 "       teqp    %0, #0\n"                               \
 217           : "=&r" (temp)                                \
 218           : "r" (x)                                     \
 219           : "memory");                                  \
 220         } while (0)
 221
 222
 223 #ifdef CONFIG_SMP
 224 #error SMP not supported
 225 #endif
 226
 227 #define smp_mb()                barrier()
 228 #define smp_rmb()               barrier()
 229 #define smp_wmb()               barrier()
 230 #define smp_read_barrier_depends()              do { } while(0)
 231
 232 #define clf()                   __clf()
 233 #define stf()                   __stf()
 234
 235 #define irqs_disabled()                 \
 236 ({                                      \
 237         unsigned long flags;            \
 238         local_save_flags(flags);        \
 239         flags & PSR_I_BIT;              \
 240 })
 241
 242 static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
 243 {
 244         extern void __bad_xchg(volatile void *, int);
 245
 246         switch (size) {
 247                 case 1: return cpu_xchg_1(x, ptr);
 248                 case 4: return cpu_xchg_4(x, ptr);
 249                 default: __bad_xchg(ptr, size);
 250         }
 251         return 0;
 252 }
 253
 254 #endif /* __ASSEMBLY__ */
 255
 256 #define arch_align_stack(x) (x)
 257
 258 #endif /* __KERNEL__ */
 259
 260 #endif