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ide: add PIO masks
[linux-2.6/x86.git] / drivers / ide / pci / pdc202xx_new.c
blob8a66a2871b3a019c68e7a22900defadcc094190c
1 /*
2 * Promise TX2/TX4/TX2000/133 IDE driver
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Split from:
10 * linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
11 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
12 * Copyright (C) 2005-2006 MontaVista Software, Inc.
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 * Author: Frank Tiernan (frankt@promise.com)
15 * Released under terms of General Public License
16 */
17
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/delay.h>
22 #include <linux/timer.h>
23 #include <linux/mm.h>
24 #include <linux/ioport.h>
25 #include <linux/blkdev.h>
26 #include <linux/hdreg.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/ide.h>
31
32 #include <asm/io.h>
33 #include <asm/irq.h>
34
35 #ifdef CONFIG_PPC_PMAC
36 #include <asm/prom.h>
37 #include <asm/pci-bridge.h>
38 #endif
39
40 #undef DEBUG
41
42 #ifdef DEBUG
43 #define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
44 #else
45 #define DBG(fmt, args...)
46 #endif
47
48 static const char *pdc_quirk_drives[] = {
49 "QUANTUM FIREBALLlct08 08",
50 "QUANTUM FIREBALLP KA6.4",
51 "QUANTUM FIREBALLP KA9.1",
52 "QUANTUM FIREBALLP LM20.4",
53 "QUANTUM FIREBALLP KX13.6",
54 "QUANTUM FIREBALLP KX20.5",
55 "QUANTUM FIREBALLP KX27.3",
56 "QUANTUM FIREBALLP LM20.5",
57 NULL
58 };
59
60 static u8 max_dma_rate(struct pci_dev *pdev)
61 {
62 u8 mode;
63
64 switch(pdev->device) {
65 case PCI_DEVICE_ID_PROMISE_20277:
66 case PCI_DEVICE_ID_PROMISE_20276:
67 case PCI_DEVICE_ID_PROMISE_20275:
68 case PCI_DEVICE_ID_PROMISE_20271:
69 case PCI_DEVICE_ID_PROMISE_20269:
70 mode = 4;
71 break;
72 case PCI_DEVICE_ID_PROMISE_20270:
73 case PCI_DEVICE_ID_PROMISE_20268:
74 mode = 3;
75 break;
76 default:
77 return 0;
78 }
79
80 return mode;
81 }
82
83 /**
84 * get_indexed_reg - Get indexed register
85 * @hwif: for the port address
86 * @index: index of the indexed register
87 */
88 static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
89 {
90 u8 value;
91
92 outb(index, hwif->dma_vendor1);
93 value = inb(hwif->dma_vendor3);
94
95 DBG("index[%02X] value[%02X]\n", index, value);
96 return value;
97 }
98
99 /**
100 * set_indexed_reg - Set indexed register
101 * @hwif: for the port address
102 * @index: index of the indexed register
103 */
104 static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
105 {
106 outb(index, hwif->dma_vendor1);
107 outb(value, hwif->dma_vendor3);
108 DBG("index[%02X] value[%02X]\n", index, value);
109 }
110
111 /*
112 * ATA Timing Tables based on 133 MHz PLL output clock.
113 *
114 * If the PLL outputs 100 MHz clock, the ASIC hardware will set
115 * the timing registers automatically when "set features" command is
116 * issued to the device. However, if the PLL output clock is 133 MHz,
117 * the following tables must be used.
118 */
119 static struct pio_timing {
120 u8 reg0c, reg0d, reg13;
121 } pio_timings [] = {
122 { 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
123 { 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
124 { 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
125 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
126 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
127 };
128
129 static struct mwdma_timing {
130 u8 reg0e, reg0f;
131 } mwdma_timings [] = {
132 { 0xdf, 0x5f }, /* MWDMA mode 0 */
133 { 0x6b, 0x27 }, /* MWDMA mode 1 */
134 { 0x69, 0x25 }, /* MWDMA mode 2 */
135 };
136
137 static struct udma_timing {
138 u8 reg10, reg11, reg12;
139 } udma_timings [] = {
140 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
141 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
142 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
143 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
144 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
145 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
146 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
147 };
148
149 static int pdcnew_tune_chipset(ide_drive_t *drive, u8 speed)
150 {
151 ide_hwif_t *hwif = HWIF(drive);
152 u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
153 int err;
154
155 speed = ide_rate_filter(drive, speed);
156
157 /*
158 * Issue SETFEATURES_XFER to the drive first. PDC202xx hardware will
159 * automatically set the timing registers based on 100 MHz PLL output.
160 */
161 err = ide_config_drive_speed(drive, speed);
162
163 /*
164 * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
165 * chips, we must override the default register settings...
166 */
167 if (max_dma_rate(hwif->pci_dev) == 4) {
168 u8 mode = speed & 0x07;
169
170 switch (speed) {
171 case XFER_UDMA_6:
172 case XFER_UDMA_5:
173 case XFER_UDMA_4:
174 case XFER_UDMA_3:
175 case XFER_UDMA_2:
176 case XFER_UDMA_1:
177 case XFER_UDMA_0:
178 set_indexed_reg(hwif, 0x10 + adj,
179 udma_timings[mode].reg10);
180 set_indexed_reg(hwif, 0x11 + adj,
181 udma_timings[mode].reg11);
182 set_indexed_reg(hwif, 0x12 + adj,
183 udma_timings[mode].reg12);
184 break;
185
186 case XFER_MW_DMA_2:
187 case XFER_MW_DMA_1:
188 case XFER_MW_DMA_0:
189 set_indexed_reg(hwif, 0x0e + adj,
190 mwdma_timings[mode].reg0e);
191 set_indexed_reg(hwif, 0x0f + adj,
192 mwdma_timings[mode].reg0f);
193 break;
194 case XFER_PIO_4:
195 case XFER_PIO_3:
196 case XFER_PIO_2:
197 case XFER_PIO_1:
198 case XFER_PIO_0:
199 set_indexed_reg(hwif, 0x0c + adj,
200 pio_timings[mode].reg0c);
201 set_indexed_reg(hwif, 0x0d + adj,
202 pio_timings[mode].reg0d);
203 set_indexed_reg(hwif, 0x13 + adj,
204 pio_timings[mode].reg13);
205 break;
206 default:
207 printk(KERN_ERR "pdc202xx_new: "
208 "Unknown speed %d ignored\n", speed);
209 }
210 } else if (speed == XFER_UDMA_2) {
211 /* Set tHOLD bit to 0 if using UDMA mode 2 */
212 u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
213
214 set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
215 }
216
217 return err;
218 }
219
220 static void pdcnew_tune_drive(ide_drive_t *drive, u8 pio)
221 {
222 pio = ide_get_best_pio_mode(drive, pio, 4);
223 (void)pdcnew_tune_chipset(drive, XFER_PIO_0 + pio);
224 }
225
226 static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
227 {
228 if (get_indexed_reg(hwif, 0x0b) & 0x04)
229 return ATA_CBL_PATA40;
230 else
231 return ATA_CBL_PATA80;
232 }
233
234 static int pdcnew_config_drive_xfer_rate(ide_drive_t *drive)
235 {
236 drive->init_speed = 0;
237
238 if (ide_tune_dma(drive))
239 return 0;
240
241 if (ide_use_fast_pio(drive))
242 pdcnew_tune_drive(drive, 255);
243
244 return -1;
245 }
246
247 static int pdcnew_quirkproc(ide_drive_t *drive)
248 {
249 const char **list, *model = drive->id->model;
250
251 for (list = pdc_quirk_drives; *list != NULL; list++)
252 if (strstr(model, *list) != NULL)
253 return 2;
254 return 0;
255 }
256
257 static void pdcnew_reset(ide_drive_t *drive)
258 {
259 /*
260 * Deleted this because it is redundant from the caller.
261 */
262 printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
263 HWIF(drive)->channel ? "Secondary" : "Primary");
264 }
265
266 /**
267 * read_counter - Read the byte count registers
268 * @dma_base: for the port address
269 */
270 static long __devinit read_counter(u32 dma_base)
271 {
272 u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
273 u8 cnt0, cnt1, cnt2, cnt3;
274 long count = 0, last;
275 int retry = 3;
276
277 do {
278 last = count;
279
280 /* Read the current count */
281 outb(0x20, pri_dma_base + 0x01);
282 cnt0 = inb(pri_dma_base + 0x03);
283 outb(0x21, pri_dma_base + 0x01);
284 cnt1 = inb(pri_dma_base + 0x03);
285 outb(0x20, sec_dma_base + 0x01);
286 cnt2 = inb(sec_dma_base + 0x03);
287 outb(0x21, sec_dma_base + 0x01);
288 cnt3 = inb(sec_dma_base + 0x03);
289
290 count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;
291
292 /*
293 * The 30-bit decrementing counter is read in 4 pieces.
294 * Incorrect value may be read when the most significant bytes
295 * are changing...
296 */
297 } while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));
298
299 DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
300 cnt0, cnt1, cnt2, cnt3);
301
302 return count;
303 }
304
305 /**
306 * detect_pll_input_clock - Detect the PLL input clock in Hz.
307 * @dma_base: for the port address
308 * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
309 */
310 static long __devinit detect_pll_input_clock(unsigned long dma_base)
311 {
312 struct timeval start_time, end_time;
313 long start_count, end_count;
314 long pll_input, usec_elapsed;
315 u8 scr1;
316
317 start_count = read_counter(dma_base);
318 do_gettimeofday(&start_time);
319
320 /* Start the test mode */
321 outb(0x01, dma_base + 0x01);
322 scr1 = inb(dma_base + 0x03);
323 DBG("scr1[%02X]\n", scr1);
324 outb(scr1 | 0x40, dma_base + 0x03);
325
326 /* Let the counter run for 10 ms. */
327 mdelay(10);
328
329 end_count = read_counter(dma_base);
330 do_gettimeofday(&end_time);
331
332 /* Stop the test mode */
333 outb(0x01, dma_base + 0x01);
334 scr1 = inb(dma_base + 0x03);
335 DBG("scr1[%02X]\n", scr1);
336 outb(scr1 & ~0x40, dma_base + 0x03);
337
338 /*
339 * Calculate the input clock in Hz
340 * (the clock counter is 30 bit wide and counts down)
341 */
342 usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
343 (end_time.tv_usec - start_time.tv_usec);
344 pll_input = ((start_count - end_count) & 0x3ffffff) / 10 *
345 (10000000 / usec_elapsed);
346
347 DBG("start[%ld] end[%ld]\n", start_count, end_count);
348
349 return pll_input;
350 }
351
352 #ifdef CONFIG_PPC_PMAC
353 static void __devinit apple_kiwi_init(struct pci_dev *pdev)
354 {
355 struct device_node *np = pci_device_to_OF_node(pdev);
356 unsigned int class_rev = 0;
357 u8 conf;
358
359 if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
360 return;
361
362 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
363 class_rev &= 0xff;
364
365 if (class_rev >= 0x03) {
366 /* Setup chip magic config stuff (from darwin) */
367 pci_read_config_byte (pdev, 0x40, &conf);
368 pci_write_config_byte(pdev, 0x40, (conf | 0x01));
369 }
370 }
371 #endif /* CONFIG_PPC_PMAC */
372
373 static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev, const char *name)
374 {
375 unsigned long dma_base = pci_resource_start(dev, 4);
376 unsigned long sec_dma_base = dma_base + 0x08;
377 long pll_input, pll_output, ratio;
378 int f, r;
379 u8 pll_ctl0, pll_ctl1;
380
381 #ifdef CONFIG_PPC_PMAC
382 apple_kiwi_init(dev);
383 #endif
384
385 /* Calculate the required PLL output frequency */
386 switch(max_dma_rate(dev)) {
387 case 4: /* it's 133 MHz for Ultra133 chips */
388 pll_output = 133333333;
389 break;
390 case 3: /* and 100 MHz for Ultra100 chips */
391 default:
392 pll_output = 100000000;
393 break;
394 }
395
396 /*
397 * Detect PLL input clock.
398 * On some systems, where PCI bus is running at non-standard clock rate
399 * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
400 * PDC20268 and newer chips employ PLL circuit to help correct timing
401 * registers setting.
402 */
403 pll_input = detect_pll_input_clock(dma_base);
404 printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);
405
406 /* Sanity check */
407 if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
408 printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
409 name, pll_input);
410 goto out;
411 }
412
413 #ifdef DEBUG
414 DBG("pll_output is %ld Hz\n", pll_output);
415
416 /* Show the current clock value of PLL control register
417 * (maybe already configured by the BIOS)
418 */
419 outb(0x02, sec_dma_base + 0x01);
420 pll_ctl0 = inb(sec_dma_base + 0x03);
421 outb(0x03, sec_dma_base + 0x01);
422 pll_ctl1 = inb(sec_dma_base + 0x03);
423
424 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
425 #endif
426
427 /*
428 * Calculate the ratio of F, R and NO
429 * POUT = (F + 2) / (( R + 2) * NO)
430 */
431 ratio = pll_output / (pll_input / 1000);
432 if (ratio < 8600L) { /* 8.6x */
433 /* Using NO = 0x01, R = 0x0d */
434 r = 0x0d;
435 } else if (ratio < 12900L) { /* 12.9x */
436 /* Using NO = 0x01, R = 0x08 */
437 r = 0x08;
438 } else if (ratio < 16100L) { /* 16.1x */
439 /* Using NO = 0x01, R = 0x06 */
440 r = 0x06;
441 } else if (ratio < 64000L) { /* 64x */
442 r = 0x00;
443 } else {
444 /* Invalid ratio */
445 printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
446 goto out;
447 }
448
449 f = (ratio * (r + 2)) / 1000 - 2;
450
451 DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
452
453 if (unlikely(f < 0 || f > 127)) {
454 /* Invalid F */
455 printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
456 goto out;
457 }
458
459 pll_ctl0 = (u8) f;
460 pll_ctl1 = (u8) r;
461
462 DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
463
464 outb(0x02, sec_dma_base + 0x01);
465 outb(pll_ctl0, sec_dma_base + 0x03);
466 outb(0x03, sec_dma_base + 0x01);
467 outb(pll_ctl1, sec_dma_base + 0x03);
468
469 /* Wait the PLL circuit to be stable */
470 mdelay(30);
471
472 #ifdef DEBUG
473 /*
474 * Show the current clock value of PLL control register
475 */
476 outb(0x02, sec_dma_base + 0x01);
477 pll_ctl0 = inb(sec_dma_base + 0x03);
478 outb(0x03, sec_dma_base + 0x01);
479 pll_ctl1 = inb(sec_dma_base + 0x03);
480
481 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
482 #endif
483
484 out:
485 return dev->irq;
486 }
487
488 static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
489 {
490 hwif->autodma = 0;
491
492 hwif->tuneproc = &pdcnew_tune_drive;
493 hwif->quirkproc = &pdcnew_quirkproc;
494 hwif->speedproc = &pdcnew_tune_chipset;
495 hwif->resetproc = &pdcnew_reset;
496
497 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
498
499 hwif->atapi_dma = 1;
500
501 hwif->ultra_mask = hwif->cds->udma_mask;
502 hwif->mwdma_mask = 0x07;
503
504 hwif->err_stops_fifo = 1;
505
506 hwif->ide_dma_check = &pdcnew_config_drive_xfer_rate;
507
508 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
509 hwif->cbl = pdcnew_cable_detect(hwif);
510
511 if (!noautodma)
512 hwif->autodma = 1;
513 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
514 }
515
516 static int __devinit init_setup_pdcnew(struct pci_dev *dev, ide_pci_device_t *d)
517 {
518 return ide_setup_pci_device(dev, d);
519 }
520
521 static int __devinit init_setup_pdc20270(struct pci_dev *dev,
522 ide_pci_device_t *d)
523 {
524 struct pci_dev *findev = NULL;
525 int ret;
526
527 if ((dev->bus->self &&
528 dev->bus->self->vendor == PCI_VENDOR_ID_DEC) &&
529 (dev->bus->self->device == PCI_DEVICE_ID_DEC_21150)) {
530 if (PCI_SLOT(dev->devfn) & 2)
531 return -ENODEV;
532 d->extra = 0;
533 while ((findev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
534 if ((findev->vendor == dev->vendor) &&
535 (findev->device == dev->device) &&
536 (PCI_SLOT(findev->devfn) & 2)) {
537 if (findev->irq != dev->irq) {
538 findev->irq = dev->irq;
539 }
540 ret = ide_setup_pci_devices(dev, findev, d);
541 pci_dev_put(findev);
542 return ret;
543 }
544 }
545 }
546 return ide_setup_pci_device(dev, d);
547 }
548
549 static int __devinit init_setup_pdc20276(struct pci_dev *dev,
550 ide_pci_device_t *d)
551 {
552 if ((dev->bus->self) &&
553 (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
554 ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
555 (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
556 printk(KERN_INFO "ide: Skipping Promise PDC20276 "
557 "attached to I2O RAID controller.\n");
558 return -ENODEV;
559 }
560 return ide_setup_pci_device(dev, d);
561 }
562
563 static ide_pci_device_t pdcnew_chipsets[] __devinitdata = {
564 { /* 0 */
565 .name = "PDC20268",
566 .init_setup = init_setup_pdcnew,
567 .init_chipset = init_chipset_pdcnew,
568 .init_hwif = init_hwif_pdc202new,
569 .autodma = AUTODMA,
570 .bootable = OFF_BOARD,
571 .pio_mask = ATA_PIO4,
572 .udma_mask = 0x3f, /* udma0-5 */
573 },{ /* 1 */
574 .name = "PDC20269",
575 .init_setup = init_setup_pdcnew,
576 .init_chipset = init_chipset_pdcnew,
577 .init_hwif = init_hwif_pdc202new,
578 .autodma = AUTODMA,
579 .bootable = OFF_BOARD,
580 .pio_mask = ATA_PIO4,
581 .udma_mask = 0x7f, /* udma0-6*/
582 },{ /* 2 */
583 .name = "PDC20270",
584 .init_setup = init_setup_pdc20270,
585 .init_chipset = init_chipset_pdcnew,
586 .init_hwif = init_hwif_pdc202new,
587 .autodma = AUTODMA,
588 .bootable = OFF_BOARD,
589 .pio_mask = ATA_PIO4,
590 .udma_mask = 0x3f, /* udma0-5 */
591 },{ /* 3 */
592 .name = "PDC20271",
593 .init_setup = init_setup_pdcnew,
594 .init_chipset = init_chipset_pdcnew,
595 .init_hwif = init_hwif_pdc202new,
596 .autodma = AUTODMA,
597 .bootable = OFF_BOARD,
598 .pio_mask = ATA_PIO4,
599 .udma_mask = 0x7f, /* udma0-6*/
600 },{ /* 4 */
601 .name = "PDC20275",
602 .init_setup = init_setup_pdcnew,
603 .init_chipset = init_chipset_pdcnew,
604 .init_hwif = init_hwif_pdc202new,
605 .autodma = AUTODMA,
606 .bootable = OFF_BOARD,
607 .pio_mask = ATA_PIO4,
608 .udma_mask = 0x7f, /* udma0-6*/
609 },{ /* 5 */
610 .name = "PDC20276",
611 .init_setup = init_setup_pdc20276,
612 .init_chipset = init_chipset_pdcnew,
613 .init_hwif = init_hwif_pdc202new,
614 .autodma = AUTODMA,
615 .bootable = OFF_BOARD,
616 .pio_mask = ATA_PIO4,
617 .udma_mask = 0x7f, /* udma0-6*/
618 },{ /* 6 */
619 .name = "PDC20277",
620 .init_setup = init_setup_pdcnew,
621 .init_chipset = init_chipset_pdcnew,
622 .init_hwif = init_hwif_pdc202new,
623 .autodma = AUTODMA,
624 .bootable = OFF_BOARD,
625 .pio_mask = ATA_PIO4,
626 .udma_mask = 0x7f, /* udma0-6*/
627 }
628 };
629
630 /**
631 * pdc202new_init_one - called when a pdc202xx is found
632 * @dev: the pdc202new device
633 * @id: the matching pci id
634 *
635 * Called when the PCI registration layer (or the IDE initialization)
636 * finds a device matching our IDE device tables.
637 */
638
639 static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
640 {
641 ide_pci_device_t *d = &pdcnew_chipsets[id->driver_data];
642
643 return d->init_setup(dev, d);
644 }
645
646 static struct pci_device_id pdc202new_pci_tbl[] = {
647 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
648 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
649 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
650 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20271, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
651 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
652 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
653 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20277, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
654 { 0, },
655 };
656 MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
657
658 static struct pci_driver driver = {
659 .name = "Promise_IDE",
660 .id_table = pdc202new_pci_tbl,
661 .probe = pdc202new_init_one,
662 };
663
664 static int __init pdc202new_ide_init(void)
665 {
666 return ide_pci_register_driver(&driver);
667 }
668
669 module_init(pdc202new_ide_init);
670
671 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
672 MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
673 MODULE_LICENSE("GPL");
x86 "subsystem" repository