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pci/xen: When free-ing MSI-X/MSI irq->desc also use generic code.
[linux-2.6/x86.git] / drivers / net / forcedeth.c
blobaf09296ef0ddc974d2bb60d0c66d7cd8b75fa4cd
1 /*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
7 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * Known bugs:
33 * We suspect that on some hardware no TX done interrupts are generated.
34 * This means recovery from netif_stop_queue only happens if the hw timer
35 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37 * If your hardware reliably generates tx done interrupts, then you can remove
38 * DEV_NEED_TIMERIRQ from the driver_data flags.
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic.
41 */
42
43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
45 #define FORCEDETH_VERSION "0.64"
46 #define DRV_NAME "forcedeth"
47
48 #include <linux/module.h>
49 #include <linux/types.h>
50 #include <linux/pci.h>
51 #include <linux/interrupt.h>
52 #include <linux/netdevice.h>
53 #include <linux/etherdevice.h>
54 #include <linux/delay.h>
55 #include <linux/sched.h>
56 #include <linux/spinlock.h>
57 #include <linux/ethtool.h>
58 #include <linux/timer.h>
59 #include <linux/skbuff.h>
60 #include <linux/mii.h>
61 #include <linux/random.h>
62 #include <linux/init.h>
63 #include <linux/if_vlan.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/slab.h>
66 #include <linux/uaccess.h>
67 #include <linux/io.h>
68
69 #include <asm/irq.h>
70 #include <asm/system.h>
71
72 #define TX_WORK_PER_LOOP 64
73 #define RX_WORK_PER_LOOP 64
74
75 /*
76 * Hardware access:
77 */
78
79 #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
80 #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
81 #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
82 #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
83 #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
84 #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
85 #define DEV_HAS_MSI 0x0000040 /* device supports MSI */
86 #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
87 #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
88 #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
89 #define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */
90 #define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */
91 #define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */
92 #define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */
93 #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
94 #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
95 #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
96 #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
97 #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
98 #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
99 #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
100 #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
101 #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
102 #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
103 #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
104 #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
105 #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
106
107 enum {
108 NvRegIrqStatus = 0x000,
109 #define NVREG_IRQSTAT_MIIEVENT 0x040
110 #define NVREG_IRQSTAT_MASK 0x83ff
111 NvRegIrqMask = 0x004,
112 #define NVREG_IRQ_RX_ERROR 0x0001
113 #define NVREG_IRQ_RX 0x0002
114 #define NVREG_IRQ_RX_NOBUF 0x0004
115 #define NVREG_IRQ_TX_ERR 0x0008
116 #define NVREG_IRQ_TX_OK 0x0010
117 #define NVREG_IRQ_TIMER 0x0020
118 #define NVREG_IRQ_LINK 0x0040
119 #define NVREG_IRQ_RX_FORCED 0x0080
120 #define NVREG_IRQ_TX_FORCED 0x0100
121 #define NVREG_IRQ_RECOVER_ERROR 0x8200
122 #define NVREG_IRQMASK_THROUGHPUT 0x00df
123 #define NVREG_IRQMASK_CPU 0x0060
124 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
125 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
126 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
127
128 NvRegUnknownSetupReg6 = 0x008,
129 #define NVREG_UNKSETUP6_VAL 3
130
131 /*
132 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
133 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
134 */
135 NvRegPollingInterval = 0x00c,
136 #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
137 #define NVREG_POLL_DEFAULT_CPU 13
138 NvRegMSIMap0 = 0x020,
139 NvRegMSIMap1 = 0x024,
140 NvRegMSIIrqMask = 0x030,
141 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
142 NvRegMisc1 = 0x080,
143 #define NVREG_MISC1_PAUSE_TX 0x01
144 #define NVREG_MISC1_HD 0x02
145 #define NVREG_MISC1_FORCE 0x3b0f3c
146
147 NvRegMacReset = 0x34,
148 #define NVREG_MAC_RESET_ASSERT 0x0F3
149 NvRegTransmitterControl = 0x084,
150 #define NVREG_XMITCTL_START 0x01
151 #define NVREG_XMITCTL_MGMT_ST 0x40000000
152 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
153 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
154 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
155 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
156 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
157 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
158 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
159 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
160 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
161 #define NVREG_XMITCTL_DATA_START 0x00100000
162 #define NVREG_XMITCTL_DATA_READY 0x00010000
163 #define NVREG_XMITCTL_DATA_ERROR 0x00020000
164 NvRegTransmitterStatus = 0x088,
165 #define NVREG_XMITSTAT_BUSY 0x01
166
167 NvRegPacketFilterFlags = 0x8c,
168 #define NVREG_PFF_PAUSE_RX 0x08
169 #define NVREG_PFF_ALWAYS 0x7F0000
170 #define NVREG_PFF_PROMISC 0x80
171 #define NVREG_PFF_MYADDR 0x20
172 #define NVREG_PFF_LOOPBACK 0x10
173
174 NvRegOffloadConfig = 0x90,
175 #define NVREG_OFFLOAD_HOMEPHY 0x601
176 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
177 NvRegReceiverControl = 0x094,
178 #define NVREG_RCVCTL_START 0x01
179 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
180 NvRegReceiverStatus = 0x98,
181 #define NVREG_RCVSTAT_BUSY 0x01
182
183 NvRegSlotTime = 0x9c,
184 #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
185 #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
186 #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
187 #define NVREG_SLOTTIME_HALF 0x0000ff00
188 #define NVREG_SLOTTIME_DEFAULT 0x00007f00
189 #define NVREG_SLOTTIME_MASK 0x000000ff
190
191 NvRegTxDeferral = 0xA0,
192 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
193 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
194 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
195 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
196 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
197 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
198 NvRegRxDeferral = 0xA4,
199 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
200 NvRegMacAddrA = 0xA8,
201 NvRegMacAddrB = 0xAC,
202 NvRegMulticastAddrA = 0xB0,
203 #define NVREG_MCASTADDRA_FORCE 0x01
204 NvRegMulticastAddrB = 0xB4,
205 NvRegMulticastMaskA = 0xB8,
206 #define NVREG_MCASTMASKA_NONE 0xffffffff
207 NvRegMulticastMaskB = 0xBC,
208 #define NVREG_MCASTMASKB_NONE 0xffff
209
210 NvRegPhyInterface = 0xC0,
211 #define PHY_RGMII 0x10000000
212 NvRegBackOffControl = 0xC4,
213 #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
214 #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
215 #define NVREG_BKOFFCTRL_SELECT 24
216 #define NVREG_BKOFFCTRL_GEAR 12
217
218 NvRegTxRingPhysAddr = 0x100,
219 NvRegRxRingPhysAddr = 0x104,
220 NvRegRingSizes = 0x108,
221 #define NVREG_RINGSZ_TXSHIFT 0
222 #define NVREG_RINGSZ_RXSHIFT 16
223 NvRegTransmitPoll = 0x10c,
224 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
225 NvRegLinkSpeed = 0x110,
226 #define NVREG_LINKSPEED_FORCE 0x10000
227 #define NVREG_LINKSPEED_10 1000
228 #define NVREG_LINKSPEED_100 100
229 #define NVREG_LINKSPEED_1000 50
230 #define NVREG_LINKSPEED_MASK (0xFFF)
231 NvRegUnknownSetupReg5 = 0x130,
232 #define NVREG_UNKSETUP5_BIT31 (1<<31)
233 NvRegTxWatermark = 0x13c,
234 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
235 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
236 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
237 NvRegTxRxControl = 0x144,
238 #define NVREG_TXRXCTL_KICK 0x0001
239 #define NVREG_TXRXCTL_BIT1 0x0002
240 #define NVREG_TXRXCTL_BIT2 0x0004
241 #define NVREG_TXRXCTL_IDLE 0x0008
242 #define NVREG_TXRXCTL_RESET 0x0010
243 #define NVREG_TXRXCTL_RXCHECK 0x0400
244 #define NVREG_TXRXCTL_DESC_1 0
245 #define NVREG_TXRXCTL_DESC_2 0x002100
246 #define NVREG_TXRXCTL_DESC_3 0xc02200
247 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
248 #define NVREG_TXRXCTL_VLANINS 0x00080
249 NvRegTxRingPhysAddrHigh = 0x148,
250 NvRegRxRingPhysAddrHigh = 0x14C,
251 NvRegTxPauseFrame = 0x170,
252 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
253 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
254 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
255 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
256 NvRegTxPauseFrameLimit = 0x174,
257 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
258 NvRegMIIStatus = 0x180,
259 #define NVREG_MIISTAT_ERROR 0x0001
260 #define NVREG_MIISTAT_LINKCHANGE 0x0008
261 #define NVREG_MIISTAT_MASK_RW 0x0007
262 #define NVREG_MIISTAT_MASK_ALL 0x000f
263 NvRegMIIMask = 0x184,
264 #define NVREG_MII_LINKCHANGE 0x0008
265
266 NvRegAdapterControl = 0x188,
267 #define NVREG_ADAPTCTL_START 0x02
268 #define NVREG_ADAPTCTL_LINKUP 0x04
269 #define NVREG_ADAPTCTL_PHYVALID 0x40000
270 #define NVREG_ADAPTCTL_RUNNING 0x100000
271 #define NVREG_ADAPTCTL_PHYSHIFT 24
272 NvRegMIISpeed = 0x18c,
273 #define NVREG_MIISPEED_BIT8 (1<<8)
274 #define NVREG_MIIDELAY 5
275 NvRegMIIControl = 0x190,
276 #define NVREG_MIICTL_INUSE 0x08000
277 #define NVREG_MIICTL_WRITE 0x00400
278 #define NVREG_MIICTL_ADDRSHIFT 5
279 NvRegMIIData = 0x194,
280 NvRegTxUnicast = 0x1a0,
281 NvRegTxMulticast = 0x1a4,
282 NvRegTxBroadcast = 0x1a8,
283 NvRegWakeUpFlags = 0x200,
284 #define NVREG_WAKEUPFLAGS_VAL 0x7770
285 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
286 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
287 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
288 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
289 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
290 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
291 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
292 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
293 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
294 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
295
296 NvRegMgmtUnitGetVersion = 0x204,
297 #define NVREG_MGMTUNITGETVERSION 0x01
298 NvRegMgmtUnitVersion = 0x208,
299 #define NVREG_MGMTUNITVERSION 0x08
300 NvRegPowerCap = 0x268,
301 #define NVREG_POWERCAP_D3SUPP (1<<30)
302 #define NVREG_POWERCAP_D2SUPP (1<<26)
303 #define NVREG_POWERCAP_D1SUPP (1<<25)
304 NvRegPowerState = 0x26c,
305 #define NVREG_POWERSTATE_POWEREDUP 0x8000
306 #define NVREG_POWERSTATE_VALID 0x0100
307 #define NVREG_POWERSTATE_MASK 0x0003
308 #define NVREG_POWERSTATE_D0 0x0000
309 #define NVREG_POWERSTATE_D1 0x0001
310 #define NVREG_POWERSTATE_D2 0x0002
311 #define NVREG_POWERSTATE_D3 0x0003
312 NvRegMgmtUnitControl = 0x278,
313 #define NVREG_MGMTUNITCONTROL_INUSE 0x20000
314 NvRegTxCnt = 0x280,
315 NvRegTxZeroReXmt = 0x284,
316 NvRegTxOneReXmt = 0x288,
317 NvRegTxManyReXmt = 0x28c,
318 NvRegTxLateCol = 0x290,
319 NvRegTxUnderflow = 0x294,
320 NvRegTxLossCarrier = 0x298,
321 NvRegTxExcessDef = 0x29c,
322 NvRegTxRetryErr = 0x2a0,
323 NvRegRxFrameErr = 0x2a4,
324 NvRegRxExtraByte = 0x2a8,
325 NvRegRxLateCol = 0x2ac,
326 NvRegRxRunt = 0x2b0,
327 NvRegRxFrameTooLong = 0x2b4,
328 NvRegRxOverflow = 0x2b8,
329 NvRegRxFCSErr = 0x2bc,
330 NvRegRxFrameAlignErr = 0x2c0,
331 NvRegRxLenErr = 0x2c4,
332 NvRegRxUnicast = 0x2c8,
333 NvRegRxMulticast = 0x2cc,
334 NvRegRxBroadcast = 0x2d0,
335 NvRegTxDef = 0x2d4,
336 NvRegTxFrame = 0x2d8,
337 NvRegRxCnt = 0x2dc,
338 NvRegTxPause = 0x2e0,
339 NvRegRxPause = 0x2e4,
340 NvRegRxDropFrame = 0x2e8,
341 NvRegVlanControl = 0x300,
342 #define NVREG_VLANCONTROL_ENABLE 0x2000
343 NvRegMSIXMap0 = 0x3e0,
344 NvRegMSIXMap1 = 0x3e4,
345 NvRegMSIXIrqStatus = 0x3f0,
346
347 NvRegPowerState2 = 0x600,
348 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
349 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
350 #define NVREG_POWERSTATE2_PHY_RESET 0x0004
351 #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
352 };
353
354 /* Big endian: should work, but is untested */
355 struct ring_desc {
356 __le32 buf;
357 __le32 flaglen;
358 };
359
360 struct ring_desc_ex {
361 __le32 bufhigh;
362 __le32 buflow;
363 __le32 txvlan;
364 __le32 flaglen;
365 };
366
367 union ring_type {
368 struct ring_desc *orig;
369 struct ring_desc_ex *ex;
370 };
371
372 #define FLAG_MASK_V1 0xffff0000
373 #define FLAG_MASK_V2 0xffffc000
374 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
375 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
376
377 #define NV_TX_LASTPACKET (1<<16)
378 #define NV_TX_RETRYERROR (1<<19)
379 #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
380 #define NV_TX_FORCED_INTERRUPT (1<<24)
381 #define NV_TX_DEFERRED (1<<26)
382 #define NV_TX_CARRIERLOST (1<<27)
383 #define NV_TX_LATECOLLISION (1<<28)
384 #define NV_TX_UNDERFLOW (1<<29)
385 #define NV_TX_ERROR (1<<30)
386 #define NV_TX_VALID (1<<31)
387
388 #define NV_TX2_LASTPACKET (1<<29)
389 #define NV_TX2_RETRYERROR (1<<18)
390 #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
391 #define NV_TX2_FORCED_INTERRUPT (1<<30)
392 #define NV_TX2_DEFERRED (1<<25)
393 #define NV_TX2_CARRIERLOST (1<<26)
394 #define NV_TX2_LATECOLLISION (1<<27)
395 #define NV_TX2_UNDERFLOW (1<<28)
396 /* error and valid are the same for both */
397 #define NV_TX2_ERROR (1<<30)
398 #define NV_TX2_VALID (1<<31)
399 #define NV_TX2_TSO (1<<28)
400 #define NV_TX2_TSO_SHIFT 14
401 #define NV_TX2_TSO_MAX_SHIFT 14
402 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
403 #define NV_TX2_CHECKSUM_L3 (1<<27)
404 #define NV_TX2_CHECKSUM_L4 (1<<26)
405
406 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
407
408 #define NV_RX_DESCRIPTORVALID (1<<16)
409 #define NV_RX_MISSEDFRAME (1<<17)
410 #define NV_RX_SUBSTRACT1 (1<<18)
411 #define NV_RX_ERROR1 (1<<23)
412 #define NV_RX_ERROR2 (1<<24)
413 #define NV_RX_ERROR3 (1<<25)
414 #define NV_RX_ERROR4 (1<<26)
415 #define NV_RX_CRCERR (1<<27)
416 #define NV_RX_OVERFLOW (1<<28)
417 #define NV_RX_FRAMINGERR (1<<29)
418 #define NV_RX_ERROR (1<<30)
419 #define NV_RX_AVAIL (1<<31)
420 #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
421
422 #define NV_RX2_CHECKSUMMASK (0x1C000000)
423 #define NV_RX2_CHECKSUM_IP (0x10000000)
424 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
425 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
426 #define NV_RX2_DESCRIPTORVALID (1<<29)
427 #define NV_RX2_SUBSTRACT1 (1<<25)
428 #define NV_RX2_ERROR1 (1<<18)
429 #define NV_RX2_ERROR2 (1<<19)
430 #define NV_RX2_ERROR3 (1<<20)
431 #define NV_RX2_ERROR4 (1<<21)
432 #define NV_RX2_CRCERR (1<<22)
433 #define NV_RX2_OVERFLOW (1<<23)
434 #define NV_RX2_FRAMINGERR (1<<24)
435 /* error and avail are the same for both */
436 #define NV_RX2_ERROR (1<<30)
437 #define NV_RX2_AVAIL (1<<31)
438 #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
439
440 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
441 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
442
443 /* Miscelaneous hardware related defines: */
444 #define NV_PCI_REGSZ_VER1 0x270
445 #define NV_PCI_REGSZ_VER2 0x2d4
446 #define NV_PCI_REGSZ_VER3 0x604
447 #define NV_PCI_REGSZ_MAX 0x604
448
449 /* various timeout delays: all in usec */
450 #define NV_TXRX_RESET_DELAY 4
451 #define NV_TXSTOP_DELAY1 10
452 #define NV_TXSTOP_DELAY1MAX 500000
453 #define NV_TXSTOP_DELAY2 100
454 #define NV_RXSTOP_DELAY1 10
455 #define NV_RXSTOP_DELAY1MAX 500000
456 #define NV_RXSTOP_DELAY2 100
457 #define NV_SETUP5_DELAY 5
458 #define NV_SETUP5_DELAYMAX 50000
459 #define NV_POWERUP_DELAY 5
460 #define NV_POWERUP_DELAYMAX 5000
461 #define NV_MIIBUSY_DELAY 50
462 #define NV_MIIPHY_DELAY 10
463 #define NV_MIIPHY_DELAYMAX 10000
464 #define NV_MAC_RESET_DELAY 64
465
466 #define NV_WAKEUPPATTERNS 5
467 #define NV_WAKEUPMASKENTRIES 4
468
469 /* General driver defaults */
470 #define NV_WATCHDOG_TIMEO (5*HZ)
471
472 #define RX_RING_DEFAULT 512
473 #define TX_RING_DEFAULT 256
474 #define RX_RING_MIN 128
475 #define TX_RING_MIN 64
476 #define RING_MAX_DESC_VER_1 1024
477 #define RING_MAX_DESC_VER_2_3 16384
478
479 /* rx/tx mac addr + type + vlan + align + slack*/
480 #define NV_RX_HEADERS (64)
481 /* even more slack. */
482 #define NV_RX_ALLOC_PAD (64)
483
484 /* maximum mtu size */
485 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
486 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
487
488 #define OOM_REFILL (1+HZ/20)
489 #define POLL_WAIT (1+HZ/100)
490 #define LINK_TIMEOUT (3*HZ)
491 #define STATS_INTERVAL (10*HZ)
492
493 /*
494 * desc_ver values:
495 * The nic supports three different descriptor types:
496 * - DESC_VER_1: Original
497 * - DESC_VER_2: support for jumbo frames.
498 * - DESC_VER_3: 64-bit format.
499 */
500 #define DESC_VER_1 1
501 #define DESC_VER_2 2
502 #define DESC_VER_3 3
503
504 /* PHY defines */
505 #define PHY_OUI_MARVELL 0x5043
506 #define PHY_OUI_CICADA 0x03f1
507 #define PHY_OUI_VITESSE 0x01c1
508 #define PHY_OUI_REALTEK 0x0732
509 #define PHY_OUI_REALTEK2 0x0020
510 #define PHYID1_OUI_MASK 0x03ff
511 #define PHYID1_OUI_SHFT 6
512 #define PHYID2_OUI_MASK 0xfc00
513 #define PHYID2_OUI_SHFT 10
514 #define PHYID2_MODEL_MASK 0x03f0
515 #define PHY_MODEL_REALTEK_8211 0x0110
516 #define PHY_REV_MASK 0x0001
517 #define PHY_REV_REALTEK_8211B 0x0000
518 #define PHY_REV_REALTEK_8211C 0x0001
519 #define PHY_MODEL_REALTEK_8201 0x0200
520 #define PHY_MODEL_MARVELL_E3016 0x0220
521 #define PHY_MARVELL_E3016_INITMASK 0x0300
522 #define PHY_CICADA_INIT1 0x0f000
523 #define PHY_CICADA_INIT2 0x0e00
524 #define PHY_CICADA_INIT3 0x01000
525 #define PHY_CICADA_INIT4 0x0200
526 #define PHY_CICADA_INIT5 0x0004
527 #define PHY_CICADA_INIT6 0x02000
528 #define PHY_VITESSE_INIT_REG1 0x1f
529 #define PHY_VITESSE_INIT_REG2 0x10
530 #define PHY_VITESSE_INIT_REG3 0x11
531 #define PHY_VITESSE_INIT_REG4 0x12
532 #define PHY_VITESSE_INIT_MSK1 0xc
533 #define PHY_VITESSE_INIT_MSK2 0x0180
534 #define PHY_VITESSE_INIT1 0x52b5
535 #define PHY_VITESSE_INIT2 0xaf8a
536 #define PHY_VITESSE_INIT3 0x8
537 #define PHY_VITESSE_INIT4 0x8f8a
538 #define PHY_VITESSE_INIT5 0xaf86
539 #define PHY_VITESSE_INIT6 0x8f86
540 #define PHY_VITESSE_INIT7 0xaf82
541 #define PHY_VITESSE_INIT8 0x0100
542 #define PHY_VITESSE_INIT9 0x8f82
543 #define PHY_VITESSE_INIT10 0x0
544 #define PHY_REALTEK_INIT_REG1 0x1f
545 #define PHY_REALTEK_INIT_REG2 0x19
546 #define PHY_REALTEK_INIT_REG3 0x13
547 #define PHY_REALTEK_INIT_REG4 0x14
548 #define PHY_REALTEK_INIT_REG5 0x18
549 #define PHY_REALTEK_INIT_REG6 0x11
550 #define PHY_REALTEK_INIT_REG7 0x01
551 #define PHY_REALTEK_INIT1 0x0000
552 #define PHY_REALTEK_INIT2 0x8e00
553 #define PHY_REALTEK_INIT3 0x0001
554 #define PHY_REALTEK_INIT4 0xad17
555 #define PHY_REALTEK_INIT5 0xfb54
556 #define PHY_REALTEK_INIT6 0xf5c7
557 #define PHY_REALTEK_INIT7 0x1000
558 #define PHY_REALTEK_INIT8 0x0003
559 #define PHY_REALTEK_INIT9 0x0008
560 #define PHY_REALTEK_INIT10 0x0005
561 #define PHY_REALTEK_INIT11 0x0200
562 #define PHY_REALTEK_INIT_MSK1 0x0003
563
564 #define PHY_GIGABIT 0x0100
565
566 #define PHY_TIMEOUT 0x1
567 #define PHY_ERROR 0x2
568
569 #define PHY_100 0x1
570 #define PHY_1000 0x2
571 #define PHY_HALF 0x100
572
573 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
574 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
575 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
576 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
577 #define NV_PAUSEFRAME_RX_REQ 0x0010
578 #define NV_PAUSEFRAME_TX_REQ 0x0020
579 #define NV_PAUSEFRAME_AUTONEG 0x0040
580
581 /* MSI/MSI-X defines */
582 #define NV_MSI_X_MAX_VECTORS 8
583 #define NV_MSI_X_VECTORS_MASK 0x000f
584 #define NV_MSI_CAPABLE 0x0010
585 #define NV_MSI_X_CAPABLE 0x0020
586 #define NV_MSI_ENABLED 0x0040
587 #define NV_MSI_X_ENABLED 0x0080
588
589 #define NV_MSI_X_VECTOR_ALL 0x0
590 #define NV_MSI_X_VECTOR_RX 0x0
591 #define NV_MSI_X_VECTOR_TX 0x1
592 #define NV_MSI_X_VECTOR_OTHER 0x2
593
594 #define NV_MSI_PRIV_OFFSET 0x68
595 #define NV_MSI_PRIV_VALUE 0xffffffff
596
597 #define NV_RESTART_TX 0x1
598 #define NV_RESTART_RX 0x2
599
600 #define NV_TX_LIMIT_COUNT 16
601
602 #define NV_DYNAMIC_THRESHOLD 4
603 #define NV_DYNAMIC_MAX_QUIET_COUNT 2048
604
605 /* statistics */
606 struct nv_ethtool_str {
607 char name[ETH_GSTRING_LEN];
608 };
609
610 static const struct nv_ethtool_str nv_estats_str[] = {
611 { "tx_bytes" },
612 { "tx_zero_rexmt" },
613 { "tx_one_rexmt" },
614 { "tx_many_rexmt" },
615 { "tx_late_collision" },
616 { "tx_fifo_errors" },
617 { "tx_carrier_errors" },
618 { "tx_excess_deferral" },
619 { "tx_retry_error" },
620 { "rx_frame_error" },
621 { "rx_extra_byte" },
622 { "rx_late_collision" },
623 { "rx_runt" },
624 { "rx_frame_too_long" },
625 { "rx_over_errors" },
626 { "rx_crc_errors" },
627 { "rx_frame_align_error" },
628 { "rx_length_error" },
629 { "rx_unicast" },
630 { "rx_multicast" },
631 { "rx_broadcast" },
632 { "rx_packets" },
633 { "rx_errors_total" },
634 { "tx_errors_total" },
635
636 /* version 2 stats */
637 { "tx_deferral" },
638 { "tx_packets" },
639 { "rx_bytes" },
640 { "tx_pause" },
641 { "rx_pause" },
642 { "rx_drop_frame" },
643
644 /* version 3 stats */
645 { "tx_unicast" },
646 { "tx_multicast" },
647 { "tx_broadcast" }
648 };
649
650 struct nv_ethtool_stats {
651 u64 tx_bytes;
652 u64 tx_zero_rexmt;
653 u64 tx_one_rexmt;
654 u64 tx_many_rexmt;
655 u64 tx_late_collision;
656 u64 tx_fifo_errors;
657 u64 tx_carrier_errors;
658 u64 tx_excess_deferral;
659 u64 tx_retry_error;
660 u64 rx_frame_error;
661 u64 rx_extra_byte;
662 u64 rx_late_collision;
663 u64 rx_runt;
664 u64 rx_frame_too_long;
665 u64 rx_over_errors;
666 u64 rx_crc_errors;
667 u64 rx_frame_align_error;
668 u64 rx_length_error;
669 u64 rx_unicast;
670 u64 rx_multicast;
671 u64 rx_broadcast;
672 u64 rx_packets;
673 u64 rx_errors_total;
674 u64 tx_errors_total;
675
676 /* version 2 stats */
677 u64 tx_deferral;
678 u64 tx_packets;
679 u64 rx_bytes;
680 u64 tx_pause;
681 u64 rx_pause;
682 u64 rx_drop_frame;
683
684 /* version 3 stats */
685 u64 tx_unicast;
686 u64 tx_multicast;
687 u64 tx_broadcast;
688 };
689
690 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
691 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
692 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
693
694 /* diagnostics */
695 #define NV_TEST_COUNT_BASE 3
696 #define NV_TEST_COUNT_EXTENDED 4
697
698 static const struct nv_ethtool_str nv_etests_str[] = {
699 { "link (online/offline)" },
700 { "register (offline) " },
701 { "interrupt (offline) " },
702 { "loopback (offline) " }
703 };
704
705 struct register_test {
706 __u32 reg;
707 __u32 mask;
708 };
709
710 static const struct register_test nv_registers_test[] = {
711 { NvRegUnknownSetupReg6, 0x01 },
712 { NvRegMisc1, 0x03c },
713 { NvRegOffloadConfig, 0x03ff },
714 { NvRegMulticastAddrA, 0xffffffff },
715 { NvRegTxWatermark, 0x0ff },
716 { NvRegWakeUpFlags, 0x07777 },
717 { 0, 0 }
718 };
719
720 struct nv_skb_map {
721 struct sk_buff *skb;
722 dma_addr_t dma;
723 unsigned int dma_len:31;
724 unsigned int dma_single:1;
725 struct ring_desc_ex *first_tx_desc;
726 struct nv_skb_map *next_tx_ctx;
727 };
728
729 /*
730 * SMP locking:
731 * All hardware access under netdev_priv(dev)->lock, except the performance
732 * critical parts:
733 * - rx is (pseudo-) lockless: it relies on the single-threading provided
734 * by the arch code for interrupts.
735 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
736 * needs netdev_priv(dev)->lock :-(
737 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
738 */
739
740 /* in dev: base, irq */
741 struct fe_priv {
742 spinlock_t lock;
743
744 struct net_device *dev;
745 struct napi_struct napi;
746
747 /* General data:
748 * Locking: spin_lock(&np->lock); */
749 struct nv_ethtool_stats estats;
750 int in_shutdown;
751 u32 linkspeed;
752 int duplex;
753 int autoneg;
754 int fixed_mode;
755 int phyaddr;
756 int wolenabled;
757 unsigned int phy_oui;
758 unsigned int phy_model;
759 unsigned int phy_rev;
760 u16 gigabit;
761 int intr_test;
762 int recover_error;
763 int quiet_count;
764
765 /* General data: RO fields */
766 dma_addr_t ring_addr;
767 struct pci_dev *pci_dev;
768 u32 orig_mac[2];
769 u32 events;
770 u32 irqmask;
771 u32 desc_ver;
772 u32 txrxctl_bits;
773 u32 vlanctl_bits;
774 u32 driver_data;
775 u32 device_id;
776 u32 register_size;
777 int rx_csum;
778 u32 mac_in_use;
779 int mgmt_version;
780 int mgmt_sema;
781
782 void __iomem *base;
783
784 /* rx specific fields.
785 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
786 */
787 union ring_type get_rx, put_rx, first_rx, last_rx;
788 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
789 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
790 struct nv_skb_map *rx_skb;
791
792 union ring_type rx_ring;
793 unsigned int rx_buf_sz;
794 unsigned int pkt_limit;
795 struct timer_list oom_kick;
796 struct timer_list nic_poll;
797 struct timer_list stats_poll;
798 u32 nic_poll_irq;
799 int rx_ring_size;
800
801 /* media detection workaround.
802 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
803 */
804 int need_linktimer;
805 unsigned long link_timeout;
806 /*
807 * tx specific fields.
808 */
809 union ring_type get_tx, put_tx, first_tx, last_tx;
810 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
811 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
812 struct nv_skb_map *tx_skb;
813
814 union ring_type tx_ring;
815 u32 tx_flags;
816 int tx_ring_size;
817 int tx_limit;
818 u32 tx_pkts_in_progress;
819 struct nv_skb_map *tx_change_owner;
820 struct nv_skb_map *tx_end_flip;
821 int tx_stop;
822
823 /* vlan fields */
824 struct vlan_group *vlangrp;
825
826 /* msi/msi-x fields */
827 u32 msi_flags;
828 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
829
830 /* flow control */
831 u32 pause_flags;
832
833 /* power saved state */
834 u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
835
836 /* for different msi-x irq type */
837 char name_rx[IFNAMSIZ + 3]; /* -rx */
838 char name_tx[IFNAMSIZ + 3]; /* -tx */
839 char name_other[IFNAMSIZ + 6]; /* -other */
840 };
841
842 /*
843 * Maximum number of loops until we assume that a bit in the irq mask
844 * is stuck. Overridable with module param.
845 */
846 static int max_interrupt_work = 4;
847
848 /*
849 * Optimization can be either throuput mode or cpu mode
850 *
851 * Throughput Mode: Every tx and rx packet will generate an interrupt.
852 * CPU Mode: Interrupts are controlled by a timer.
853 */
854 enum {
855 NV_OPTIMIZATION_MODE_THROUGHPUT,
856 NV_OPTIMIZATION_MODE_CPU,
857 NV_OPTIMIZATION_MODE_DYNAMIC
858 };
859 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
860
861 /*
862 * Poll interval for timer irq
863 *
864 * This interval determines how frequent an interrupt is generated.
865 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
866 * Min = 0, and Max = 65535
867 */
868 static int poll_interval = -1;
869
870 /*
871 * MSI interrupts
872 */
873 enum {
874 NV_MSI_INT_DISABLED,
875 NV_MSI_INT_ENABLED
876 };
877 static int msi = NV_MSI_INT_ENABLED;
878
879 /*
880 * MSIX interrupts
881 */
882 enum {
883 NV_MSIX_INT_DISABLED,
884 NV_MSIX_INT_ENABLED
885 };
886 static int msix = NV_MSIX_INT_ENABLED;
887
888 /*
889 * DMA 64bit
890 */
891 enum {
892 NV_DMA_64BIT_DISABLED,
893 NV_DMA_64BIT_ENABLED
894 };
895 static int dma_64bit = NV_DMA_64BIT_ENABLED;
896
897 /*
898 * Crossover Detection
899 * Realtek 8201 phy + some OEM boards do not work properly.
900 */
901 enum {
902 NV_CROSSOVER_DETECTION_DISABLED,
903 NV_CROSSOVER_DETECTION_ENABLED
904 };
905 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
906
907 /*
908 * Power down phy when interface is down (persists through reboot;
909 * older Linux and other OSes may not power it up again)
910 */
911 static int phy_power_down;
912
913 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
914 {
915 return netdev_priv(dev);
916 }
917
918 static inline u8 __iomem *get_hwbase(struct net_device *dev)
919 {
920 return ((struct fe_priv *)netdev_priv(dev))->base;
921 }
922
923 static inline void pci_push(u8 __iomem *base)
924 {
925 /* force out pending posted writes */
926 readl(base);
927 }
928
929 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
930 {
931 return le32_to_cpu(prd->flaglen)
932 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
933 }
934
935 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
936 {
937 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
938 }
939
940 static bool nv_optimized(struct fe_priv *np)
941 {
942 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
943 return false;
944 return true;
945 }
946
947 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
948 int delay, int delaymax)
949 {
950 u8 __iomem *base = get_hwbase(dev);
951
952 pci_push(base);
953 do {
954 udelay(delay);
955 delaymax -= delay;
956 if (delaymax < 0)
957 return 1;
958 } while ((readl(base + offset) & mask) != target);
959 return 0;
960 }
961
962 #define NV_SETUP_RX_RING 0x01
963 #define NV_SETUP_TX_RING 0x02
964
965 static inline u32 dma_low(dma_addr_t addr)
966 {
967 return addr;
968 }
969
970 static inline u32 dma_high(dma_addr_t addr)
971 {
972 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
973 }
974
975 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
976 {
977 struct fe_priv *np = get_nvpriv(dev);
978 u8 __iomem *base = get_hwbase(dev);
979
980 if (!nv_optimized(np)) {
981 if (rxtx_flags & NV_SETUP_RX_RING)
982 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
983 if (rxtx_flags & NV_SETUP_TX_RING)
984 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
985 } else {
986 if (rxtx_flags & NV_SETUP_RX_RING) {
987 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
988 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
989 }
990 if (rxtx_flags & NV_SETUP_TX_RING) {
991 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
992 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
993 }
994 }
995 }
996
997 static void free_rings(struct net_device *dev)
998 {
999 struct fe_priv *np = get_nvpriv(dev);
1000
1001 if (!nv_optimized(np)) {
1002 if (np->rx_ring.orig)
1003 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1004 np->rx_ring.orig, np->ring_addr);
1005 } else {
1006 if (np->rx_ring.ex)
1007 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1008 np->rx_ring.ex, np->ring_addr);
1009 }
1010 kfree(np->rx_skb);
1011 kfree(np->tx_skb);
1012 }
1013
1014 static int using_multi_irqs(struct net_device *dev)
1015 {
1016 struct fe_priv *np = get_nvpriv(dev);
1017
1018 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1019 ((np->msi_flags & NV_MSI_X_ENABLED) &&
1020 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1021 return 0;
1022 else
1023 return 1;
1024 }
1025
1026 static void nv_txrx_gate(struct net_device *dev, bool gate)
1027 {
1028 struct fe_priv *np = get_nvpriv(dev);
1029 u8 __iomem *base = get_hwbase(dev);
1030 u32 powerstate;
1031
1032 if (!np->mac_in_use &&
1033 (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1034 powerstate = readl(base + NvRegPowerState2);
1035 if (gate)
1036 powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1037 else
1038 powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1039 writel(powerstate, base + NvRegPowerState2);
1040 }
1041 }
1042
1043 static void nv_enable_irq(struct net_device *dev)
1044 {
1045 struct fe_priv *np = get_nvpriv(dev);
1046
1047 if (!using_multi_irqs(dev)) {
1048 if (np->msi_flags & NV_MSI_X_ENABLED)
1049 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1050 else
1051 enable_irq(np->pci_dev->irq);
1052 } else {
1053 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1054 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1055 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1056 }
1057 }
1058
1059 static void nv_disable_irq(struct net_device *dev)
1060 {
1061 struct fe_priv *np = get_nvpriv(dev);
1062
1063 if (!using_multi_irqs(dev)) {
1064 if (np->msi_flags & NV_MSI_X_ENABLED)
1065 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1066 else
1067 disable_irq(np->pci_dev->irq);
1068 } else {
1069 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1070 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1071 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1072 }
1073 }
1074
1075 /* In MSIX mode, a write to irqmask behaves as XOR */
1076 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1077 {
1078 u8 __iomem *base = get_hwbase(dev);
1079
1080 writel(mask, base + NvRegIrqMask);
1081 }
1082
1083 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1084 {
1085 struct fe_priv *np = get_nvpriv(dev);
1086 u8 __iomem *base = get_hwbase(dev);
1087
1088 if (np->msi_flags & NV_MSI_X_ENABLED) {
1089 writel(mask, base + NvRegIrqMask);
1090 } else {
1091 if (np->msi_flags & NV_MSI_ENABLED)
1092 writel(0, base + NvRegMSIIrqMask);
1093 writel(0, base + NvRegIrqMask);
1094 }
1095 }
1096
1097 static void nv_napi_enable(struct net_device *dev)
1098 {
1099 struct fe_priv *np = get_nvpriv(dev);
1100
1101 napi_enable(&np->napi);
1102 }
1103
1104 static void nv_napi_disable(struct net_device *dev)
1105 {
1106 struct fe_priv *np = get_nvpriv(dev);
1107
1108 napi_disable(&np->napi);
1109 }
1110
1111 #define MII_READ (-1)
1112 /* mii_rw: read/write a register on the PHY.
1113 *
1114 * Caller must guarantee serialization
1115 */
1116 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1117 {
1118 u8 __iomem *base = get_hwbase(dev);
1119 u32 reg;
1120 int retval;
1121
1122 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1123
1124 reg = readl(base + NvRegMIIControl);
1125 if (reg & NVREG_MIICTL_INUSE) {
1126 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1127 udelay(NV_MIIBUSY_DELAY);
1128 }
1129
1130 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1131 if (value != MII_READ) {
1132 writel(value, base + NvRegMIIData);
1133 reg |= NVREG_MIICTL_WRITE;
1134 }
1135 writel(reg, base + NvRegMIIControl);
1136
1137 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1138 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
1139 retval = -1;
1140 } else if (value != MII_READ) {
1141 /* it was a write operation - fewer failures are detectable */
1142 retval = 0;
1143 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1144 retval = -1;
1145 } else {
1146 retval = readl(base + NvRegMIIData);
1147 }
1148
1149 return retval;
1150 }
1151
1152 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1153 {
1154 struct fe_priv *np = netdev_priv(dev);
1155 u32 miicontrol;
1156 unsigned int tries = 0;
1157
1158 miicontrol = BMCR_RESET | bmcr_setup;
1159 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
1160 return -1;
1161
1162 /* wait for 500ms */
1163 msleep(500);
1164
1165 /* must wait till reset is deasserted */
1166 while (miicontrol & BMCR_RESET) {
1167 usleep_range(10000, 20000);
1168 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1169 /* FIXME: 100 tries seem excessive */
1170 if (tries++ > 100)
1171 return -1;
1172 }
1173 return 0;
1174 }
1175
1176 static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1177 {
1178 static const struct {
1179 int reg;
1180 int init;
1181 } ri[] = {
1182 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1183 { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
1184 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
1185 { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
1186 { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
1187 { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
1188 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1189 };
1190 int i;
1191
1192 for (i = 0; i < ARRAY_SIZE(ri); i++) {
1193 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
1194 return PHY_ERROR;
1195 }
1196
1197 return 0;
1198 }
1199
1200 static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
1201 {
1202 u32 reg;
1203 u8 __iomem *base = get_hwbase(dev);
1204 u32 powerstate = readl(base + NvRegPowerState2);
1205
1206 /* need to perform hw phy reset */
1207 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1208 writel(powerstate, base + NvRegPowerState2);
1209 msleep(25);
1210
1211 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1212 writel(powerstate, base + NvRegPowerState2);
1213 msleep(25);
1214
1215 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1216 reg |= PHY_REALTEK_INIT9;
1217 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1218 return PHY_ERROR;
1219 if (mii_rw(dev, np->phyaddr,
1220 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
1221 return PHY_ERROR;
1222 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1223 if (!(reg & PHY_REALTEK_INIT11)) {
1224 reg |= PHY_REALTEK_INIT11;
1225 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1226 return PHY_ERROR;
1227 }
1228 if (mii_rw(dev, np->phyaddr,
1229 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1230 return PHY_ERROR;
1231
1232 return 0;
1233 }
1234
1235 static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
1236 {
1237 u32 phy_reserved;
1238
1239 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1240 phy_reserved = mii_rw(dev, np->phyaddr,
1241 PHY_REALTEK_INIT_REG6, MII_READ);
1242 phy_reserved |= PHY_REALTEK_INIT7;
1243 if (mii_rw(dev, np->phyaddr,
1244 PHY_REALTEK_INIT_REG6, phy_reserved))
1245 return PHY_ERROR;
1246 }
1247
1248 return 0;
1249 }
1250
1251 static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
1252 {
1253 u32 phy_reserved;
1254
1255 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1256 if (mii_rw(dev, np->phyaddr,
1257 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
1258 return PHY_ERROR;
1259 phy_reserved = mii_rw(dev, np->phyaddr,
1260 PHY_REALTEK_INIT_REG2, MII_READ);
1261 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1262 phy_reserved |= PHY_REALTEK_INIT3;
1263 if (mii_rw(dev, np->phyaddr,
1264 PHY_REALTEK_INIT_REG2, phy_reserved))
1265 return PHY_ERROR;
1266 if (mii_rw(dev, np->phyaddr,
1267 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1268 return PHY_ERROR;
1269 }
1270
1271 return 0;
1272 }
1273
1274 static int init_cicada(struct net_device *dev, struct fe_priv *np,
1275 u32 phyinterface)
1276 {
1277 u32 phy_reserved;
1278
1279 if (phyinterface & PHY_RGMII) {
1280 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1281 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1282 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1283 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1284 return PHY_ERROR;
1285 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1286 phy_reserved |= PHY_CICADA_INIT5;
1287 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1288 return PHY_ERROR;
1289 }
1290 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1291 phy_reserved |= PHY_CICADA_INIT6;
1292 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1293 return PHY_ERROR;
1294
1295 return 0;
1296 }
1297
1298 static int init_vitesse(struct net_device *dev, struct fe_priv *np)
1299 {
1300 u32 phy_reserved;
1301
1302 if (mii_rw(dev, np->phyaddr,
1303 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
1304 return PHY_ERROR;
1305 if (mii_rw(dev, np->phyaddr,
1306 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
1307 return PHY_ERROR;
1308 phy_reserved = mii_rw(dev, np->phyaddr,
1309 PHY_VITESSE_INIT_REG4, MII_READ);
1310 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1311 return PHY_ERROR;
1312 phy_reserved = mii_rw(dev, np->phyaddr,
1313 PHY_VITESSE_INIT_REG3, MII_READ);
1314 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1315 phy_reserved |= PHY_VITESSE_INIT3;
1316 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1317 return PHY_ERROR;
1318 if (mii_rw(dev, np->phyaddr,
1319 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
1320 return PHY_ERROR;
1321 if (mii_rw(dev, np->phyaddr,
1322 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
1323 return PHY_ERROR;
1324 phy_reserved = mii_rw(dev, np->phyaddr,
1325 PHY_VITESSE_INIT_REG4, MII_READ);
1326 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1327 phy_reserved |= PHY_VITESSE_INIT3;
1328 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1329 return PHY_ERROR;
1330 phy_reserved = mii_rw(dev, np->phyaddr,
1331 PHY_VITESSE_INIT_REG3, MII_READ);
1332 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1333 return PHY_ERROR;
1334 if (mii_rw(dev, np->phyaddr,
1335 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
1336 return PHY_ERROR;
1337 if (mii_rw(dev, np->phyaddr,
1338 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
1339 return PHY_ERROR;
1340 phy_reserved = mii_rw(dev, np->phyaddr,
1341 PHY_VITESSE_INIT_REG4, MII_READ);
1342 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1343 return PHY_ERROR;
1344 phy_reserved = mii_rw(dev, np->phyaddr,
1345 PHY_VITESSE_INIT_REG3, MII_READ);
1346 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1347 phy_reserved |= PHY_VITESSE_INIT8;
1348 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1349 return PHY_ERROR;
1350 if (mii_rw(dev, np->phyaddr,
1351 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
1352 return PHY_ERROR;
1353 if (mii_rw(dev, np->phyaddr,
1354 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
1355 return PHY_ERROR;
1356
1357 return 0;
1358 }
1359
1360 static int phy_init(struct net_device *dev)
1361 {
1362 struct fe_priv *np = get_nvpriv(dev);
1363 u8 __iomem *base = get_hwbase(dev);
1364 u32 phyinterface;
1365 u32 mii_status, mii_control, mii_control_1000, reg;
1366
1367 /* phy errata for E3016 phy */
1368 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1369 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1370 reg &= ~PHY_MARVELL_E3016_INITMASK;
1371 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1372 netdev_info(dev, "%s: phy write to errata reg failed\n",
1373 pci_name(np->pci_dev));
1374 return PHY_ERROR;
1375 }
1376 }
1377 if (np->phy_oui == PHY_OUI_REALTEK) {
1378 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1379 np->phy_rev == PHY_REV_REALTEK_8211B) {
1380 if (init_realtek_8211b(dev, np)) {
1381 netdev_info(dev, "%s: phy init failed\n",
1382 pci_name(np->pci_dev));
1383 return PHY_ERROR;
1384 }
1385 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1386 np->phy_rev == PHY_REV_REALTEK_8211C) {
1387 if (init_realtek_8211c(dev, np)) {
1388 netdev_info(dev, "%s: phy init failed\n",
1389 pci_name(np->pci_dev));
1390 return PHY_ERROR;
1391 }
1392 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1393 if (init_realtek_8201(dev, np)) {
1394 netdev_info(dev, "%s: phy init failed\n",
1395 pci_name(np->pci_dev));
1396 return PHY_ERROR;
1397 }
1398 }
1399 }
1400
1401 /* set advertise register */
1402 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1403 reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1404 ADVERTISE_100HALF | ADVERTISE_100FULL |
1405 ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1406 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1407 netdev_info(dev, "%s: phy write to advertise failed\n",
1408 pci_name(np->pci_dev));
1409 return PHY_ERROR;
1410 }
1411
1412 /* get phy interface type */
1413 phyinterface = readl(base + NvRegPhyInterface);
1414
1415 /* see if gigabit phy */
1416 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1417 if (mii_status & PHY_GIGABIT) {
1418 np->gigabit = PHY_GIGABIT;
1419 mii_control_1000 = mii_rw(dev, np->phyaddr,
1420 MII_CTRL1000, MII_READ);
1421 mii_control_1000 &= ~ADVERTISE_1000HALF;
1422 if (phyinterface & PHY_RGMII)
1423 mii_control_1000 |= ADVERTISE_1000FULL;
1424 else
1425 mii_control_1000 &= ~ADVERTISE_1000FULL;
1426
1427 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1428 netdev_info(dev, "%s: phy init failed\n",
1429 pci_name(np->pci_dev));
1430 return PHY_ERROR;
1431 }
1432 } else
1433 np->gigabit = 0;
1434
1435 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1436 mii_control |= BMCR_ANENABLE;
1437
1438 if (np->phy_oui == PHY_OUI_REALTEK &&
1439 np->phy_model == PHY_MODEL_REALTEK_8211 &&
1440 np->phy_rev == PHY_REV_REALTEK_8211C) {
1441 /* start autoneg since we already performed hw reset above */
1442 mii_control |= BMCR_ANRESTART;
1443 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1444 netdev_info(dev, "%s: phy init failed\n",
1445 pci_name(np->pci_dev));
1446 return PHY_ERROR;
1447 }
1448 } else {
1449 /* reset the phy
1450 * (certain phys need bmcr to be setup with reset)
1451 */
1452 if (phy_reset(dev, mii_control)) {
1453 netdev_info(dev, "%s: phy reset failed\n",
1454 pci_name(np->pci_dev));
1455 return PHY_ERROR;
1456 }
1457 }
1458
1459 /* phy vendor specific configuration */
1460 if ((np->phy_oui == PHY_OUI_CICADA)) {
1461 if (init_cicada(dev, np, phyinterface)) {
1462 netdev_info(dev, "%s: phy init failed\n",
1463 pci_name(np->pci_dev));
1464 return PHY_ERROR;
1465 }
1466 } else if (np->phy_oui == PHY_OUI_VITESSE) {
1467 if (init_vitesse(dev, np)) {
1468 netdev_info(dev, "%s: phy init failed\n",
1469 pci_name(np->pci_dev));
1470 return PHY_ERROR;
1471 }
1472 } else if (np->phy_oui == PHY_OUI_REALTEK) {
1473 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1474 np->phy_rev == PHY_REV_REALTEK_8211B) {
1475 /* reset could have cleared these out, set them back */
1476 if (init_realtek_8211b(dev, np)) {
1477 netdev_info(dev, "%s: phy init failed\n",
1478 pci_name(np->pci_dev));
1479 return PHY_ERROR;
1480 }
1481 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1482 if (init_realtek_8201(dev, np) ||
1483 init_realtek_8201_cross(dev, np)) {
1484 netdev_info(dev, "%s: phy init failed\n",
1485 pci_name(np->pci_dev));
1486 return PHY_ERROR;
1487 }
1488 }
1489 }
1490
1491 /* some phys clear out pause advertisment on reset, set it back */
1492 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1493
1494 /* restart auto negotiation, power down phy */
1495 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1496 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1497 if (phy_power_down)
1498 mii_control |= BMCR_PDOWN;
1499 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
1500 return PHY_ERROR;
1501
1502 return 0;
1503 }
1504
1505 static void nv_start_rx(struct net_device *dev)
1506 {
1507 struct fe_priv *np = netdev_priv(dev);
1508 u8 __iomem *base = get_hwbase(dev);
1509 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1510
1511 /* Already running? Stop it. */
1512 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1513 rx_ctrl &= ~NVREG_RCVCTL_START;
1514 writel(rx_ctrl, base + NvRegReceiverControl);
1515 pci_push(base);
1516 }
1517 writel(np->linkspeed, base + NvRegLinkSpeed);
1518 pci_push(base);
1519 rx_ctrl |= NVREG_RCVCTL_START;
1520 if (np->mac_in_use)
1521 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1522 writel(rx_ctrl, base + NvRegReceiverControl);
1523 pci_push(base);
1524 }
1525
1526 static void nv_stop_rx(struct net_device *dev)
1527 {
1528 struct fe_priv *np = netdev_priv(dev);
1529 u8 __iomem *base = get_hwbase(dev);
1530 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1531
1532 if (!np->mac_in_use)
1533 rx_ctrl &= ~NVREG_RCVCTL_START;
1534 else
1535 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1536 writel(rx_ctrl, base + NvRegReceiverControl);
1537 if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1538 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
1539 netdev_info(dev, "%s: ReceiverStatus remained busy\n",
1540 __func__);
1541
1542 udelay(NV_RXSTOP_DELAY2);
1543 if (!np->mac_in_use)
1544 writel(0, base + NvRegLinkSpeed);
1545 }
1546
1547 static void nv_start_tx(struct net_device *dev)
1548 {
1549 struct fe_priv *np = netdev_priv(dev);
1550 u8 __iomem *base = get_hwbase(dev);
1551 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1552
1553 tx_ctrl |= NVREG_XMITCTL_START;
1554 if (np->mac_in_use)
1555 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1556 writel(tx_ctrl, base + NvRegTransmitterControl);
1557 pci_push(base);
1558 }
1559
1560 static void nv_stop_tx(struct net_device *dev)
1561 {
1562 struct fe_priv *np = netdev_priv(dev);
1563 u8 __iomem *base = get_hwbase(dev);
1564 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1565
1566 if (!np->mac_in_use)
1567 tx_ctrl &= ~NVREG_XMITCTL_START;
1568 else
1569 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1570 writel(tx_ctrl, base + NvRegTransmitterControl);
1571 if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1572 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
1573 netdev_info(dev, "%s: TransmitterStatus remained busy\n",
1574 __func__);
1575
1576 udelay(NV_TXSTOP_DELAY2);
1577 if (!np->mac_in_use)
1578 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1579 base + NvRegTransmitPoll);
1580 }
1581
1582 static void nv_start_rxtx(struct net_device *dev)
1583 {
1584 nv_start_rx(dev);
1585 nv_start_tx(dev);
1586 }
1587
1588 static void nv_stop_rxtx(struct net_device *dev)
1589 {
1590 nv_stop_rx(dev);
1591 nv_stop_tx(dev);
1592 }
1593
1594 static void nv_txrx_reset(struct net_device *dev)
1595 {
1596 struct fe_priv *np = netdev_priv(dev);
1597 u8 __iomem *base = get_hwbase(dev);
1598
1599 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1600 pci_push(base);
1601 udelay(NV_TXRX_RESET_DELAY);
1602 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1603 pci_push(base);
1604 }
1605
1606 static void nv_mac_reset(struct net_device *dev)
1607 {
1608 struct fe_priv *np = netdev_priv(dev);
1609 u8 __iomem *base = get_hwbase(dev);
1610 u32 temp1, temp2, temp3;
1611
1612 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1613 pci_push(base);
1614
1615 /* save registers since they will be cleared on reset */
1616 temp1 = readl(base + NvRegMacAddrA);
1617 temp2 = readl(base + NvRegMacAddrB);
1618 temp3 = readl(base + NvRegTransmitPoll);
1619
1620 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1621 pci_push(base);
1622 udelay(NV_MAC_RESET_DELAY);
1623 writel(0, base + NvRegMacReset);
1624 pci_push(base);
1625 udelay(NV_MAC_RESET_DELAY);
1626
1627 /* restore saved registers */
1628 writel(temp1, base + NvRegMacAddrA);
1629 writel(temp2, base + NvRegMacAddrB);
1630 writel(temp3, base + NvRegTransmitPoll);
1631
1632 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1633 pci_push(base);
1634 }
1635
1636 static void nv_get_hw_stats(struct net_device *dev)
1637 {
1638 struct fe_priv *np = netdev_priv(dev);
1639 u8 __iomem *base = get_hwbase(dev);
1640
1641 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1642 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1643 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1644 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1645 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1646 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1647 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1648 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1649 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1650 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1651 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1652 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1653 np->estats.rx_runt += readl(base + NvRegRxRunt);
1654 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1655 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1656 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1657 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1658 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1659 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1660 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1661 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1662 np->estats.rx_packets =
1663 np->estats.rx_unicast +
1664 np->estats.rx_multicast +
1665 np->estats.rx_broadcast;
1666 np->estats.rx_errors_total =
1667 np->estats.rx_crc_errors +
1668 np->estats.rx_over_errors +
1669 np->estats.rx_frame_error +
1670 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1671 np->estats.rx_late_collision +
1672 np->estats.rx_runt +
1673 np->estats.rx_frame_too_long;
1674 np->estats.tx_errors_total =
1675 np->estats.tx_late_collision +
1676 np->estats.tx_fifo_errors +
1677 np->estats.tx_carrier_errors +
1678 np->estats.tx_excess_deferral +
1679 np->estats.tx_retry_error;
1680
1681 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1682 np->estats.tx_deferral += readl(base + NvRegTxDef);
1683 np->estats.tx_packets += readl(base + NvRegTxFrame);
1684 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1685 np->estats.tx_pause += readl(base + NvRegTxPause);
1686 np->estats.rx_pause += readl(base + NvRegRxPause);
1687 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1688 }
1689
1690 if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1691 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1692 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1693 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1694 }
1695 }
1696
1697 /*
1698 * nv_get_stats: dev->get_stats function
1699 * Get latest stats value from the nic.
1700 * Called with read_lock(&dev_base_lock) held for read -
1701 * only synchronized against unregister_netdevice.
1702 */
1703 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1704 {
1705 struct fe_priv *np = netdev_priv(dev);
1706
1707 /* If the nic supports hw counters then retrieve latest values */
1708 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1709 nv_get_hw_stats(dev);
1710
1711 /* copy to net_device stats */
1712 dev->stats.tx_bytes = np->estats.tx_bytes;
1713 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1714 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1715 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1716 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1717 dev->stats.rx_errors = np->estats.rx_errors_total;
1718 dev->stats.tx_errors = np->estats.tx_errors_total;
1719 }
1720
1721 return &dev->stats;
1722 }
1723
1724 /*
1725 * nv_alloc_rx: fill rx ring entries.
1726 * Return 1 if the allocations for the skbs failed and the
1727 * rx engine is without Available descriptors
1728 */
1729 static int nv_alloc_rx(struct net_device *dev)
1730 {
1731 struct fe_priv *np = netdev_priv(dev);
1732 struct ring_desc *less_rx;
1733
1734 less_rx = np->get_rx.orig;
1735 if (less_rx-- == np->first_rx.orig)
1736 less_rx = np->last_rx.orig;
1737
1738 while (np->put_rx.orig != less_rx) {
1739 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1740 if (skb) {
1741 np->put_rx_ctx->skb = skb;
1742 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1743 skb->data,
1744 skb_tailroom(skb),
1745 PCI_DMA_FROMDEVICE);
1746 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1747 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1748 wmb();
1749 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1750 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1751 np->put_rx.orig = np->first_rx.orig;
1752 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1753 np->put_rx_ctx = np->first_rx_ctx;
1754 } else
1755 return 1;
1756 }
1757 return 0;
1758 }
1759
1760 static int nv_alloc_rx_optimized(struct net_device *dev)
1761 {
1762 struct fe_priv *np = netdev_priv(dev);
1763 struct ring_desc_ex *less_rx;
1764
1765 less_rx = np->get_rx.ex;
1766 if (less_rx-- == np->first_rx.ex)
1767 less_rx = np->last_rx.ex;
1768
1769 while (np->put_rx.ex != less_rx) {
1770 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1771 if (skb) {
1772 np->put_rx_ctx->skb = skb;
1773 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1774 skb->data,
1775 skb_tailroom(skb),
1776 PCI_DMA_FROMDEVICE);
1777 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1778 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1779 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1780 wmb();
1781 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1782 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1783 np->put_rx.ex = np->first_rx.ex;
1784 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1785 np->put_rx_ctx = np->first_rx_ctx;
1786 } else
1787 return 1;
1788 }
1789 return 0;
1790 }
1791
1792 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1793 static void nv_do_rx_refill(unsigned long data)
1794 {
1795 struct net_device *dev = (struct net_device *) data;
1796 struct fe_priv *np = netdev_priv(dev);
1797
1798 /* Just reschedule NAPI rx processing */
1799 napi_schedule(&np->napi);
1800 }
1801
1802 static void nv_init_rx(struct net_device *dev)
1803 {
1804 struct fe_priv *np = netdev_priv(dev);
1805 int i;
1806
1807 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1808
1809 if (!nv_optimized(np))
1810 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1811 else
1812 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1813 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1814 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1815
1816 for (i = 0; i < np->rx_ring_size; i++) {
1817 if (!nv_optimized(np)) {
1818 np->rx_ring.orig[i].flaglen = 0;
1819 np->rx_ring.orig[i].buf = 0;
1820 } else {
1821 np->rx_ring.ex[i].flaglen = 0;
1822 np->rx_ring.ex[i].txvlan = 0;
1823 np->rx_ring.ex[i].bufhigh = 0;
1824 np->rx_ring.ex[i].buflow = 0;
1825 }
1826 np->rx_skb[i].skb = NULL;
1827 np->rx_skb[i].dma = 0;
1828 }
1829 }
1830
1831 static void nv_init_tx(struct net_device *dev)
1832 {
1833 struct fe_priv *np = netdev_priv(dev);
1834 int i;
1835
1836 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1837
1838 if (!nv_optimized(np))
1839 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1840 else
1841 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1842 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1843 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1844 np->tx_pkts_in_progress = 0;
1845 np->tx_change_owner = NULL;
1846 np->tx_end_flip = NULL;
1847 np->tx_stop = 0;
1848
1849 for (i = 0; i < np->tx_ring_size; i++) {
1850 if (!nv_optimized(np)) {
1851 np->tx_ring.orig[i].flaglen = 0;
1852 np->tx_ring.orig[i].buf = 0;
1853 } else {
1854 np->tx_ring.ex[i].flaglen = 0;
1855 np->tx_ring.ex[i].txvlan = 0;
1856 np->tx_ring.ex[i].bufhigh = 0;
1857 np->tx_ring.ex[i].buflow = 0;
1858 }
1859 np->tx_skb[i].skb = NULL;
1860 np->tx_skb[i].dma = 0;
1861 np->tx_skb[i].dma_len = 0;
1862 np->tx_skb[i].dma_single = 0;
1863 np->tx_skb[i].first_tx_desc = NULL;
1864 np->tx_skb[i].next_tx_ctx = NULL;
1865 }
1866 }
1867
1868 static int nv_init_ring(struct net_device *dev)
1869 {
1870 struct fe_priv *np = netdev_priv(dev);
1871
1872 nv_init_tx(dev);
1873 nv_init_rx(dev);
1874
1875 if (!nv_optimized(np))
1876 return nv_alloc_rx(dev);
1877 else
1878 return nv_alloc_rx_optimized(dev);
1879 }
1880
1881 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1882 {
1883 if (tx_skb->dma) {
1884 if (tx_skb->dma_single)
1885 pci_unmap_single(np->pci_dev, tx_skb->dma,
1886 tx_skb->dma_len,
1887 PCI_DMA_TODEVICE);
1888 else
1889 pci_unmap_page(np->pci_dev, tx_skb->dma,
1890 tx_skb->dma_len,
1891 PCI_DMA_TODEVICE);
1892 tx_skb->dma = 0;
1893 }
1894 }
1895
1896 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1897 {
1898 nv_unmap_txskb(np, tx_skb);
1899 if (tx_skb->skb) {
1900 dev_kfree_skb_any(tx_skb->skb);
1901 tx_skb->skb = NULL;
1902 return 1;
1903 }
1904 return 0;
1905 }
1906
1907 static void nv_drain_tx(struct net_device *dev)
1908 {
1909 struct fe_priv *np = netdev_priv(dev);
1910 unsigned int i;
1911
1912 for (i = 0; i < np->tx_ring_size; i++) {
1913 if (!nv_optimized(np)) {
1914 np->tx_ring.orig[i].flaglen = 0;
1915 np->tx_ring.orig[i].buf = 0;
1916 } else {
1917 np->tx_ring.ex[i].flaglen = 0;
1918 np->tx_ring.ex[i].txvlan = 0;
1919 np->tx_ring.ex[i].bufhigh = 0;
1920 np->tx_ring.ex[i].buflow = 0;
1921 }
1922 if (nv_release_txskb(np, &np->tx_skb[i]))
1923 dev->stats.tx_dropped++;
1924 np->tx_skb[i].dma = 0;
1925 np->tx_skb[i].dma_len = 0;
1926 np->tx_skb[i].dma_single = 0;
1927 np->tx_skb[i].first_tx_desc = NULL;
1928 np->tx_skb[i].next_tx_ctx = NULL;
1929 }
1930 np->tx_pkts_in_progress = 0;
1931 np->tx_change_owner = NULL;
1932 np->tx_end_flip = NULL;
1933 }
1934
1935 static void nv_drain_rx(struct net_device *dev)
1936 {
1937 struct fe_priv *np = netdev_priv(dev);
1938 int i;
1939
1940 for (i = 0; i < np->rx_ring_size; i++) {
1941 if (!nv_optimized(np)) {
1942 np->rx_ring.orig[i].flaglen = 0;
1943 np->rx_ring.orig[i].buf = 0;
1944 } else {
1945 np->rx_ring.ex[i].flaglen = 0;
1946 np->rx_ring.ex[i].txvlan = 0;
1947 np->rx_ring.ex[i].bufhigh = 0;
1948 np->rx_ring.ex[i].buflow = 0;
1949 }
1950 wmb();
1951 if (np->rx_skb[i].skb) {
1952 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1953 (skb_end_pointer(np->rx_skb[i].skb) -
1954 np->rx_skb[i].skb->data),
1955 PCI_DMA_FROMDEVICE);
1956 dev_kfree_skb(np->rx_skb[i].skb);
1957 np->rx_skb[i].skb = NULL;
1958 }
1959 }
1960 }
1961
1962 static void nv_drain_rxtx(struct net_device *dev)
1963 {
1964 nv_drain_tx(dev);
1965 nv_drain_rx(dev);
1966 }
1967
1968 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1969 {
1970 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1971 }
1972
1973 static void nv_legacybackoff_reseed(struct net_device *dev)
1974 {
1975 u8 __iomem *base = get_hwbase(dev);
1976 u32 reg;
1977 u32 low;
1978 int tx_status = 0;
1979
1980 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1981 get_random_bytes(&low, sizeof(low));
1982 reg |= low & NVREG_SLOTTIME_MASK;
1983
1984 /* Need to stop tx before change takes effect.
1985 * Caller has already gained np->lock.
1986 */
1987 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
1988 if (tx_status)
1989 nv_stop_tx(dev);
1990 nv_stop_rx(dev);
1991 writel(reg, base + NvRegSlotTime);
1992 if (tx_status)
1993 nv_start_tx(dev);
1994 nv_start_rx(dev);
1995 }
1996
1997 /* Gear Backoff Seeds */
1998 #define BACKOFF_SEEDSET_ROWS 8
1999 #define BACKOFF_SEEDSET_LFSRS 15
2000
2001 /* Known Good seed sets */
2002 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2003 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2004 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2005 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2006 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2007 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2008 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2009 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
2010 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
2011
2012 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2013 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2014 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2015 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2016 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2017 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2018 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2019 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2020 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
2021
2022 static void nv_gear_backoff_reseed(struct net_device *dev)
2023 {
2024 u8 __iomem *base = get_hwbase(dev);
2025 u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2026 u32 temp, seedset, combinedSeed;
2027 int i;
2028
2029 /* Setup seed for free running LFSR */
2030 /* We are going to read the time stamp counter 3 times
2031 and swizzle bits around to increase randomness */
2032 get_random_bytes(&miniseed1, sizeof(miniseed1));
2033 miniseed1 &= 0x0fff;
2034 if (miniseed1 == 0)
2035 miniseed1 = 0xabc;
2036
2037 get_random_bytes(&miniseed2, sizeof(miniseed2));
2038 miniseed2 &= 0x0fff;
2039 if (miniseed2 == 0)
2040 miniseed2 = 0xabc;
2041 miniseed2_reversed =
2042 ((miniseed2 & 0xF00) >> 8) |
2043 (miniseed2 & 0x0F0) |
2044 ((miniseed2 & 0x00F) << 8);
2045
2046 get_random_bytes(&miniseed3, sizeof(miniseed3));
2047 miniseed3 &= 0x0fff;
2048 if (miniseed3 == 0)
2049 miniseed3 = 0xabc;
2050 miniseed3_reversed =
2051 ((miniseed3 & 0xF00) >> 8) |
2052 (miniseed3 & 0x0F0) |
2053 ((miniseed3 & 0x00F) << 8);
2054
2055 combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2056 (miniseed2 ^ miniseed3_reversed);
2057
2058 /* Seeds can not be zero */
2059 if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2060 combinedSeed |= 0x08;
2061 if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2062 combinedSeed |= 0x8000;
2063
2064 /* No need to disable tx here */
2065 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2066 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2067 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2068 writel(temp, base + NvRegBackOffControl);
2069
2070 /* Setup seeds for all gear LFSRs. */
2071 get_random_bytes(&seedset, sizeof(seedset));
2072 seedset = seedset % BACKOFF_SEEDSET_ROWS;
2073 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
2074 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2075 temp |= main_seedset[seedset][i-1] & 0x3ff;
2076 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2077 writel(temp, base + NvRegBackOffControl);
2078 }
2079 }
2080
2081 /*
2082 * nv_start_xmit: dev->hard_start_xmit function
2083 * Called with netif_tx_lock held.
2084 */
2085 static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2086 {
2087 struct fe_priv *np = netdev_priv(dev);
2088 u32 tx_flags = 0;
2089 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2090 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2091 unsigned int i;
2092 u32 offset = 0;
2093 u32 bcnt;
2094 u32 size = skb_headlen(skb);
2095 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2096 u32 empty_slots;
2097 struct ring_desc *put_tx;
2098 struct ring_desc *start_tx;
2099 struct ring_desc *prev_tx;
2100 struct nv_skb_map *prev_tx_ctx;
2101 unsigned long flags;
2102
2103 /* add fragments to entries count */
2104 for (i = 0; i < fragments; i++) {
2105 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2106 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2107 }
2108
2109 spin_lock_irqsave(&np->lock, flags);
2110 empty_slots = nv_get_empty_tx_slots(np);
2111 if (unlikely(empty_slots <= entries)) {
2112 netif_stop_queue(dev);
2113 np->tx_stop = 1;
2114 spin_unlock_irqrestore(&np->lock, flags);
2115 return NETDEV_TX_BUSY;
2116 }
2117 spin_unlock_irqrestore(&np->lock, flags);
2118
2119 start_tx = put_tx = np->put_tx.orig;
2120
2121 /* setup the header buffer */
2122 do {
2123 prev_tx = put_tx;
2124 prev_tx_ctx = np->put_tx_ctx;
2125 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2126 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2127 PCI_DMA_TODEVICE);
2128 np->put_tx_ctx->dma_len = bcnt;
2129 np->put_tx_ctx->dma_single = 1;
2130 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2131 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2132
2133 tx_flags = np->tx_flags;
2134 offset += bcnt;
2135 size -= bcnt;
2136 if (unlikely(put_tx++ == np->last_tx.orig))
2137 put_tx = np->first_tx.orig;
2138 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2139 np->put_tx_ctx = np->first_tx_ctx;
2140 } while (size);
2141
2142 /* setup the fragments */
2143 for (i = 0; i < fragments; i++) {
2144 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2145 u32 size = frag->size;
2146 offset = 0;
2147
2148 do {
2149 prev_tx = put_tx;
2150 prev_tx_ctx = np->put_tx_ctx;
2151 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2152 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2153 PCI_DMA_TODEVICE);
2154 np->put_tx_ctx->dma_len = bcnt;
2155 np->put_tx_ctx->dma_single = 0;
2156 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2157 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2158
2159 offset += bcnt;
2160 size -= bcnt;
2161 if (unlikely(put_tx++ == np->last_tx.orig))
2162 put_tx = np->first_tx.orig;
2163 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2164 np->put_tx_ctx = np->first_tx_ctx;
2165 } while (size);
2166 }
2167
2168 /* set last fragment flag */
2169 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2170
2171 /* save skb in this slot's context area */
2172 prev_tx_ctx->skb = skb;
2173
2174 if (skb_is_gso(skb))
2175 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2176 else
2177 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2178 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2179
2180 spin_lock_irqsave(&np->lock, flags);
2181
2182 /* set tx flags */
2183 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2184 np->put_tx.orig = put_tx;
2185
2186 spin_unlock_irqrestore(&np->lock, flags);
2187
2188 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2189 return NETDEV_TX_OK;
2190 }
2191
2192 static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2193 struct net_device *dev)
2194 {
2195 struct fe_priv *np = netdev_priv(dev);
2196 u32 tx_flags = 0;
2197 u32 tx_flags_extra;
2198 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2199 unsigned int i;
2200 u32 offset = 0;
2201 u32 bcnt;
2202 u32 size = skb_headlen(skb);
2203 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2204 u32 empty_slots;
2205 struct ring_desc_ex *put_tx;
2206 struct ring_desc_ex *start_tx;
2207 struct ring_desc_ex *prev_tx;
2208 struct nv_skb_map *prev_tx_ctx;
2209 struct nv_skb_map *start_tx_ctx;
2210 unsigned long flags;
2211
2212 /* add fragments to entries count */
2213 for (i = 0; i < fragments; i++) {
2214 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2215 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2216 }
2217
2218 spin_lock_irqsave(&np->lock, flags);
2219 empty_slots = nv_get_empty_tx_slots(np);
2220 if (unlikely(empty_slots <= entries)) {
2221 netif_stop_queue(dev);
2222 np->tx_stop = 1;
2223 spin_unlock_irqrestore(&np->lock, flags);
2224 return NETDEV_TX_BUSY;
2225 }
2226 spin_unlock_irqrestore(&np->lock, flags);
2227
2228 start_tx = put_tx = np->put_tx.ex;
2229 start_tx_ctx = np->put_tx_ctx;
2230
2231 /* setup the header buffer */
2232 do {
2233 prev_tx = put_tx;
2234 prev_tx_ctx = np->put_tx_ctx;
2235 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2236 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2237 PCI_DMA_TODEVICE);
2238 np->put_tx_ctx->dma_len = bcnt;
2239 np->put_tx_ctx->dma_single = 1;
2240 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2241 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2242 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2243
2244 tx_flags = NV_TX2_VALID;
2245 offset += bcnt;
2246 size -= bcnt;
2247 if (unlikely(put_tx++ == np->last_tx.ex))
2248 put_tx = np->first_tx.ex;
2249 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2250 np->put_tx_ctx = np->first_tx_ctx;
2251 } while (size);
2252
2253 /* setup the fragments */
2254 for (i = 0; i < fragments; i++) {
2255 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2256 u32 size = frag->size;
2257 offset = 0;
2258
2259 do {
2260 prev_tx = put_tx;
2261 prev_tx_ctx = np->put_tx_ctx;
2262 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2263 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2264 PCI_DMA_TODEVICE);
2265 np->put_tx_ctx->dma_len = bcnt;
2266 np->put_tx_ctx->dma_single = 0;
2267 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2268 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2269 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2270
2271 offset += bcnt;
2272 size -= bcnt;
2273 if (unlikely(put_tx++ == np->last_tx.ex))
2274 put_tx = np->first_tx.ex;
2275 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2276 np->put_tx_ctx = np->first_tx_ctx;
2277 } while (size);
2278 }
2279
2280 /* set last fragment flag */
2281 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2282
2283 /* save skb in this slot's context area */
2284 prev_tx_ctx->skb = skb;
2285
2286 if (skb_is_gso(skb))
2287 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2288 else
2289 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2290 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2291
2292 /* vlan tag */
2293 if (vlan_tx_tag_present(skb))
2294 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2295 vlan_tx_tag_get(skb));
2296 else
2297 start_tx->txvlan = 0;
2298
2299 spin_lock_irqsave(&np->lock, flags);
2300
2301 if (np->tx_limit) {
2302 /* Limit the number of outstanding tx. Setup all fragments, but
2303 * do not set the VALID bit on the first descriptor. Save a pointer
2304 * to that descriptor and also for next skb_map element.
2305 */
2306
2307 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2308 if (!np->tx_change_owner)
2309 np->tx_change_owner = start_tx_ctx;
2310
2311 /* remove VALID bit */
2312 tx_flags &= ~NV_TX2_VALID;
2313 start_tx_ctx->first_tx_desc = start_tx;
2314 start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2315 np->tx_end_flip = np->put_tx_ctx;
2316 } else {
2317 np->tx_pkts_in_progress++;
2318 }
2319 }
2320
2321 /* set tx flags */
2322 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2323 np->put_tx.ex = put_tx;
2324
2325 spin_unlock_irqrestore(&np->lock, flags);
2326
2327 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2328 return NETDEV_TX_OK;
2329 }
2330
2331 static inline void nv_tx_flip_ownership(struct net_device *dev)
2332 {
2333 struct fe_priv *np = netdev_priv(dev);
2334
2335 np->tx_pkts_in_progress--;
2336 if (np->tx_change_owner) {
2337 np->tx_change_owner->first_tx_desc->flaglen |=
2338 cpu_to_le32(NV_TX2_VALID);
2339 np->tx_pkts_in_progress++;
2340
2341 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2342 if (np->tx_change_owner == np->tx_end_flip)
2343 np->tx_change_owner = NULL;
2344
2345 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2346 }
2347 }
2348
2349 /*
2350 * nv_tx_done: check for completed packets, release the skbs.
2351 *
2352 * Caller must own np->lock.
2353 */
2354 static int nv_tx_done(struct net_device *dev, int limit)
2355 {
2356 struct fe_priv *np = netdev_priv(dev);
2357 u32 flags;
2358 int tx_work = 0;
2359 struct ring_desc *orig_get_tx = np->get_tx.orig;
2360
2361 while ((np->get_tx.orig != np->put_tx.orig) &&
2362 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2363 (tx_work < limit)) {
2364
2365 nv_unmap_txskb(np, np->get_tx_ctx);
2366
2367 if (np->desc_ver == DESC_VER_1) {
2368 if (flags & NV_TX_LASTPACKET) {
2369 if (flags & NV_TX_ERROR) {
2370 if (flags & NV_TX_UNDERFLOW)
2371 dev->stats.tx_fifo_errors++;
2372 if (flags & NV_TX_CARRIERLOST)
2373 dev->stats.tx_carrier_errors++;
2374 if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2375 nv_legacybackoff_reseed(dev);
2376 dev->stats.tx_errors++;
2377 } else {
2378 dev->stats.tx_packets++;
2379 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2380 }
2381 dev_kfree_skb_any(np->get_tx_ctx->skb);
2382 np->get_tx_ctx->skb = NULL;
2383 tx_work++;
2384 }
2385 } else {
2386 if (flags & NV_TX2_LASTPACKET) {
2387 if (flags & NV_TX2_ERROR) {
2388 if (flags & NV_TX2_UNDERFLOW)
2389 dev->stats.tx_fifo_errors++;
2390 if (flags & NV_TX2_CARRIERLOST)
2391 dev->stats.tx_carrier_errors++;
2392 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2393 nv_legacybackoff_reseed(dev);
2394 dev->stats.tx_errors++;
2395 } else {
2396 dev->stats.tx_packets++;
2397 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2398 }
2399 dev_kfree_skb_any(np->get_tx_ctx->skb);
2400 np->get_tx_ctx->skb = NULL;
2401 tx_work++;
2402 }
2403 }
2404 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2405 np->get_tx.orig = np->first_tx.orig;
2406 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2407 np->get_tx_ctx = np->first_tx_ctx;
2408 }
2409 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2410 np->tx_stop = 0;
2411 netif_wake_queue(dev);
2412 }
2413 return tx_work;
2414 }
2415
2416 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2417 {
2418 struct fe_priv *np = netdev_priv(dev);
2419 u32 flags;
2420 int tx_work = 0;
2421 struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
2422
2423 while ((np->get_tx.ex != np->put_tx.ex) &&
2424 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
2425 (tx_work < limit)) {
2426
2427 nv_unmap_txskb(np, np->get_tx_ctx);
2428
2429 if (flags & NV_TX2_LASTPACKET) {
2430 if (!(flags & NV_TX2_ERROR))
2431 dev->stats.tx_packets++;
2432 else {
2433 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2434 if (np->driver_data & DEV_HAS_GEAR_MODE)
2435 nv_gear_backoff_reseed(dev);
2436 else
2437 nv_legacybackoff_reseed(dev);
2438 }
2439 }
2440
2441 dev_kfree_skb_any(np->get_tx_ctx->skb);
2442 np->get_tx_ctx->skb = NULL;
2443 tx_work++;
2444
2445 if (np->tx_limit)
2446 nv_tx_flip_ownership(dev);
2447 }
2448 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2449 np->get_tx.ex = np->first_tx.ex;
2450 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2451 np->get_tx_ctx = np->first_tx_ctx;
2452 }
2453 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2454 np->tx_stop = 0;
2455 netif_wake_queue(dev);
2456 }
2457 return tx_work;
2458 }
2459
2460 /*
2461 * nv_tx_timeout: dev->tx_timeout function
2462 * Called with netif_tx_lock held.
2463 */
2464 static void nv_tx_timeout(struct net_device *dev)
2465 {
2466 struct fe_priv *np = netdev_priv(dev);
2467 u8 __iomem *base = get_hwbase(dev);
2468 u32 status;
2469 union ring_type put_tx;
2470 int saved_tx_limit;
2471 int i;
2472
2473 if (np->msi_flags & NV_MSI_X_ENABLED)
2474 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2475 else
2476 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2477
2478 netdev_info(dev, "Got tx_timeout. irq: %08x\n", status);
2479
2480 netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
2481 netdev_info(dev, "Dumping tx registers\n");
2482 for (i = 0; i <= np->register_size; i += 32) {
2483 netdev_info(dev,
2484 "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2485 i,
2486 readl(base + i + 0), readl(base + i + 4),
2487 readl(base + i + 8), readl(base + i + 12),
2488 readl(base + i + 16), readl(base + i + 20),
2489 readl(base + i + 24), readl(base + i + 28));
2490 }
2491 netdev_info(dev, "Dumping tx ring\n");
2492 for (i = 0; i < np->tx_ring_size; i += 4) {
2493 if (!nv_optimized(np)) {
2494 netdev_info(dev,
2495 "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2496 i,
2497 le32_to_cpu(np->tx_ring.orig[i].buf),
2498 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2499 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2500 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2501 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2502 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2503 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2504 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2505 } else {
2506 netdev_info(dev,
2507 "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2508 i,
2509 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2510 le32_to_cpu(np->tx_ring.ex[i].buflow),
2511 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2512 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2513 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2514 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2515 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2516 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2517 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2518 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2519 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2520 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2521 }
2522 }
2523
2524 spin_lock_irq(&np->lock);
2525
2526 /* 1) stop tx engine */
2527 nv_stop_tx(dev);
2528
2529 /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2530 saved_tx_limit = np->tx_limit;
2531 np->tx_limit = 0; /* prevent giving HW any limited pkts */
2532 np->tx_stop = 0; /* prevent waking tx queue */
2533 if (!nv_optimized(np))
2534 nv_tx_done(dev, np->tx_ring_size);
2535 else
2536 nv_tx_done_optimized(dev, np->tx_ring_size);
2537
2538 /* save current HW postion */
2539 if (np->tx_change_owner)
2540 put_tx.ex = np->tx_change_owner->first_tx_desc;
2541 else
2542 put_tx = np->put_tx;
2543
2544 /* 3) clear all tx state */
2545 nv_drain_tx(dev);
2546 nv_init_tx(dev);
2547
2548 /* 4) restore state to current HW position */
2549 np->get_tx = np->put_tx = put_tx;
2550 np->tx_limit = saved_tx_limit;
2551
2552 /* 5) restart tx engine */
2553 nv_start_tx(dev);
2554 netif_wake_queue(dev);
2555 spin_unlock_irq(&np->lock);
2556 }
2557
2558 /*
2559 * Called when the nic notices a mismatch between the actual data len on the
2560 * wire and the len indicated in the 802 header
2561 */
2562 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2563 {
2564 int hdrlen; /* length of the 802 header */
2565 int protolen; /* length as stored in the proto field */
2566
2567 /* 1) calculate len according to header */
2568 if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2569 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
2570 hdrlen = VLAN_HLEN;
2571 } else {
2572 protolen = ntohs(((struct ethhdr *)packet)->h_proto);
2573 hdrlen = ETH_HLEN;
2574 }
2575 if (protolen > ETH_DATA_LEN)
2576 return datalen; /* Value in proto field not a len, no checks possible */
2577
2578 protolen += hdrlen;
2579 /* consistency checks: */
2580 if (datalen > ETH_ZLEN) {
2581 if (datalen >= protolen) {
2582 /* more data on wire than in 802 header, trim of
2583 * additional data.
2584 */
2585 return protolen;
2586 } else {
2587 /* less data on wire than mentioned in header.
2588 * Discard the packet.
2589 */
2590 return -1;
2591 }
2592 } else {
2593 /* short packet. Accept only if 802 values are also short */
2594 if (protolen > ETH_ZLEN) {
2595 return -1;
2596 }
2597 return datalen;
2598 }
2599 }
2600
2601 static int nv_rx_process(struct net_device *dev, int limit)
2602 {
2603 struct fe_priv *np = netdev_priv(dev);
2604 u32 flags;
2605 int rx_work = 0;
2606 struct sk_buff *skb;
2607 int len;
2608
2609 while ((np->get_rx.orig != np->put_rx.orig) &&
2610 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2611 (rx_work < limit)) {
2612
2613 /*
2614 * the packet is for us - immediately tear down the pci mapping.
2615 * TODO: check if a prefetch of the first cacheline improves
2616 * the performance.
2617 */
2618 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2619 np->get_rx_ctx->dma_len,
2620 PCI_DMA_FROMDEVICE);
2621 skb = np->get_rx_ctx->skb;
2622 np->get_rx_ctx->skb = NULL;
2623
2624 /* look at what we actually got: */
2625 if (np->desc_ver == DESC_VER_1) {
2626 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2627 len = flags & LEN_MASK_V1;
2628 if (unlikely(flags & NV_RX_ERROR)) {
2629 if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2630 len = nv_getlen(dev, skb->data, len);
2631 if (len < 0) {
2632 dev->stats.rx_errors++;
2633 dev_kfree_skb(skb);
2634 goto next_pkt;
2635 }
2636 }
2637 /* framing errors are soft errors */
2638 else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2639 if (flags & NV_RX_SUBSTRACT1)
2640 len--;
2641 }
2642 /* the rest are hard errors */
2643 else {
2644 if (flags & NV_RX_MISSEDFRAME)
2645 dev->stats.rx_missed_errors++;
2646 if (flags & NV_RX_CRCERR)
2647 dev->stats.rx_crc_errors++;
2648 if (flags & NV_RX_OVERFLOW)
2649 dev->stats.rx_over_errors++;
2650 dev->stats.rx_errors++;
2651 dev_kfree_skb(skb);
2652 goto next_pkt;
2653 }
2654 }
2655 } else {
2656 dev_kfree_skb(skb);
2657 goto next_pkt;
2658 }
2659 } else {
2660 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2661 len = flags & LEN_MASK_V2;
2662 if (unlikely(flags & NV_RX2_ERROR)) {
2663 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2664 len = nv_getlen(dev, skb->data, len);
2665 if (len < 0) {
2666 dev->stats.rx_errors++;
2667 dev_kfree_skb(skb);
2668 goto next_pkt;
2669 }
2670 }
2671 /* framing errors are soft errors */
2672 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2673 if (flags & NV_RX2_SUBSTRACT1)
2674 len--;
2675 }
2676 /* the rest are hard errors */
2677 else {
2678 if (flags & NV_RX2_CRCERR)
2679 dev->stats.rx_crc_errors++;
2680 if (flags & NV_RX2_OVERFLOW)
2681 dev->stats.rx_over_errors++;
2682 dev->stats.rx_errors++;
2683 dev_kfree_skb(skb);
2684 goto next_pkt;
2685 }
2686 }
2687 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2688 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2689 skb->ip_summed = CHECKSUM_UNNECESSARY;
2690 } else {
2691 dev_kfree_skb(skb);
2692 goto next_pkt;
2693 }
2694 }
2695 /* got a valid packet - forward it to the network core */
2696 skb_put(skb, len);
2697 skb->protocol = eth_type_trans(skb, dev);
2698 napi_gro_receive(&np->napi, skb);
2699 dev->stats.rx_packets++;
2700 dev->stats.rx_bytes += len;
2701 next_pkt:
2702 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2703 np->get_rx.orig = np->first_rx.orig;
2704 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2705 np->get_rx_ctx = np->first_rx_ctx;
2706
2707 rx_work++;
2708 }
2709
2710 return rx_work;
2711 }
2712
2713 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2714 {
2715 struct fe_priv *np = netdev_priv(dev);
2716 u32 flags;
2717 u32 vlanflags = 0;
2718 int rx_work = 0;
2719 struct sk_buff *skb;
2720 int len;
2721
2722 while ((np->get_rx.ex != np->put_rx.ex) &&
2723 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2724 (rx_work < limit)) {
2725
2726 /*
2727 * the packet is for us - immediately tear down the pci mapping.
2728 * TODO: check if a prefetch of the first cacheline improves
2729 * the performance.
2730 */
2731 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2732 np->get_rx_ctx->dma_len,
2733 PCI_DMA_FROMDEVICE);
2734 skb = np->get_rx_ctx->skb;
2735 np->get_rx_ctx->skb = NULL;
2736
2737 /* look at what we actually got: */
2738 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2739 len = flags & LEN_MASK_V2;
2740 if (unlikely(flags & NV_RX2_ERROR)) {
2741 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2742 len = nv_getlen(dev, skb->data, len);
2743 if (len < 0) {
2744 dev_kfree_skb(skb);
2745 goto next_pkt;
2746 }
2747 }
2748 /* framing errors are soft errors */
2749 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2750 if (flags & NV_RX2_SUBSTRACT1)
2751 len--;
2752 }
2753 /* the rest are hard errors */
2754 else {
2755 dev_kfree_skb(skb);
2756 goto next_pkt;
2757 }
2758 }
2759
2760 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2761 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2762 skb->ip_summed = CHECKSUM_UNNECESSARY;
2763
2764 /* got a valid packet - forward it to the network core */
2765 skb_put(skb, len);
2766 skb->protocol = eth_type_trans(skb, dev);
2767 prefetch(skb->data);
2768
2769 if (likely(!np->vlangrp)) {
2770 napi_gro_receive(&np->napi, skb);
2771 } else {
2772 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2773 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2774 vlan_gro_receive(&np->napi, np->vlangrp,
2775 vlanflags & NV_RX3_VLAN_TAG_MASK, skb);
2776 } else {
2777 napi_gro_receive(&np->napi, skb);
2778 }
2779 }
2780
2781 dev->stats.rx_packets++;
2782 dev->stats.rx_bytes += len;
2783 } else {
2784 dev_kfree_skb(skb);
2785 }
2786 next_pkt:
2787 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2788 np->get_rx.ex = np->first_rx.ex;
2789 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2790 np->get_rx_ctx = np->first_rx_ctx;
2791
2792 rx_work++;
2793 }
2794
2795 return rx_work;
2796 }
2797
2798 static void set_bufsize(struct net_device *dev)
2799 {
2800 struct fe_priv *np = netdev_priv(dev);
2801
2802 if (dev->mtu <= ETH_DATA_LEN)
2803 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2804 else
2805 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2806 }
2807
2808 /*
2809 * nv_change_mtu: dev->change_mtu function
2810 * Called with dev_base_lock held for read.
2811 */
2812 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2813 {
2814 struct fe_priv *np = netdev_priv(dev);
2815 int old_mtu;
2816
2817 if (new_mtu < 64 || new_mtu > np->pkt_limit)
2818 return -EINVAL;
2819
2820 old_mtu = dev->mtu;
2821 dev->mtu = new_mtu;
2822
2823 /* return early if the buffer sizes will not change */
2824 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2825 return 0;
2826 if (old_mtu == new_mtu)
2827 return 0;
2828
2829 /* synchronized against open : rtnl_lock() held by caller */
2830 if (netif_running(dev)) {
2831 u8 __iomem *base = get_hwbase(dev);
2832 /*
2833 * It seems that the nic preloads valid ring entries into an
2834 * internal buffer. The procedure for flushing everything is
2835 * guessed, there is probably a simpler approach.
2836 * Changing the MTU is a rare event, it shouldn't matter.
2837 */
2838 nv_disable_irq(dev);
2839 nv_napi_disable(dev);
2840 netif_tx_lock_bh(dev);
2841 netif_addr_lock(dev);
2842 spin_lock(&np->lock);
2843 /* stop engines */
2844 nv_stop_rxtx(dev);
2845 nv_txrx_reset(dev);
2846 /* drain rx queue */
2847 nv_drain_rxtx(dev);
2848 /* reinit driver view of the rx queue */
2849 set_bufsize(dev);
2850 if (nv_init_ring(dev)) {
2851 if (!np->in_shutdown)
2852 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2853 }
2854 /* reinit nic view of the rx queue */
2855 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2856 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2857 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2858 base + NvRegRingSizes);
2859 pci_push(base);
2860 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2861 pci_push(base);
2862
2863 /* restart rx engine */
2864 nv_start_rxtx(dev);
2865 spin_unlock(&np->lock);
2866 netif_addr_unlock(dev);
2867 netif_tx_unlock_bh(dev);
2868 nv_napi_enable(dev);
2869 nv_enable_irq(dev);
2870 }
2871 return 0;
2872 }
2873
2874 static void nv_copy_mac_to_hw(struct net_device *dev)
2875 {
2876 u8 __iomem *base = get_hwbase(dev);
2877 u32 mac[2];
2878
2879 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2880 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2881 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2882
2883 writel(mac[0], base + NvRegMacAddrA);
2884 writel(mac[1], base + NvRegMacAddrB);
2885 }
2886
2887 /*
2888 * nv_set_mac_address: dev->set_mac_address function
2889 * Called with rtnl_lock() held.
2890 */
2891 static int nv_set_mac_address(struct net_device *dev, void *addr)
2892 {
2893 struct fe_priv *np = netdev_priv(dev);
2894 struct sockaddr *macaddr = (struct sockaddr *)addr;
2895
2896 if (!is_valid_ether_addr(macaddr->sa_data))
2897 return -EADDRNOTAVAIL;
2898
2899 /* synchronized against open : rtnl_lock() held by caller */
2900 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2901
2902 if (netif_running(dev)) {
2903 netif_tx_lock_bh(dev);
2904 netif_addr_lock(dev);
2905 spin_lock_irq(&np->lock);
2906
2907 /* stop rx engine */
2908 nv_stop_rx(dev);
2909
2910 /* set mac address */
2911 nv_copy_mac_to_hw(dev);
2912
2913 /* restart rx engine */
2914 nv_start_rx(dev);
2915 spin_unlock_irq(&np->lock);
2916 netif_addr_unlock(dev);
2917 netif_tx_unlock_bh(dev);
2918 } else {
2919 nv_copy_mac_to_hw(dev);
2920 }
2921 return 0;
2922 }
2923
2924 /*
2925 * nv_set_multicast: dev->set_multicast function
2926 * Called with netif_tx_lock held.
2927 */
2928 static void nv_set_multicast(struct net_device *dev)
2929 {
2930 struct fe_priv *np = netdev_priv(dev);
2931 u8 __iomem *base = get_hwbase(dev);
2932 u32 addr[2];
2933 u32 mask[2];
2934 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2935
2936 memset(addr, 0, sizeof(addr));
2937 memset(mask, 0, sizeof(mask));
2938
2939 if (dev->flags & IFF_PROMISC) {
2940 pff |= NVREG_PFF_PROMISC;
2941 } else {
2942 pff |= NVREG_PFF_MYADDR;
2943
2944 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
2945 u32 alwaysOff[2];
2946 u32 alwaysOn[2];
2947
2948 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2949 if (dev->flags & IFF_ALLMULTI) {
2950 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2951 } else {
2952 struct netdev_hw_addr *ha;
2953
2954 netdev_for_each_mc_addr(ha, dev) {
2955 unsigned char *addr = ha->addr;
2956 u32 a, b;
2957
2958 a = le32_to_cpu(*(__le32 *) addr);
2959 b = le16_to_cpu(*(__le16 *) (&addr[4]));
2960 alwaysOn[0] &= a;
2961 alwaysOff[0] &= ~a;
2962 alwaysOn[1] &= b;
2963 alwaysOff[1] &= ~b;
2964 }
2965 }
2966 addr[0] = alwaysOn[0];
2967 addr[1] = alwaysOn[1];
2968 mask[0] = alwaysOn[0] | alwaysOff[0];
2969 mask[1] = alwaysOn[1] | alwaysOff[1];
2970 } else {
2971 mask[0] = NVREG_MCASTMASKA_NONE;
2972 mask[1] = NVREG_MCASTMASKB_NONE;
2973 }
2974 }
2975 addr[0] |= NVREG_MCASTADDRA_FORCE;
2976 pff |= NVREG_PFF_ALWAYS;
2977 spin_lock_irq(&np->lock);
2978 nv_stop_rx(dev);
2979 writel(addr[0], base + NvRegMulticastAddrA);
2980 writel(addr[1], base + NvRegMulticastAddrB);
2981 writel(mask[0], base + NvRegMulticastMaskA);
2982 writel(mask[1], base + NvRegMulticastMaskB);
2983 writel(pff, base + NvRegPacketFilterFlags);
2984 nv_start_rx(dev);
2985 spin_unlock_irq(&np->lock);
2986 }
2987
2988 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2989 {
2990 struct fe_priv *np = netdev_priv(dev);
2991 u8 __iomem *base = get_hwbase(dev);
2992
2993 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2994
2995 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2996 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2997 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2998 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2999 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3000 } else {
3001 writel(pff, base + NvRegPacketFilterFlags);
3002 }
3003 }
3004 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3005 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3006 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3007 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3008 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3009 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3010 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3011 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3012 /* limit the number of tx pause frames to a default of 8 */
3013 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3014 }
3015 writel(pause_enable, base + NvRegTxPauseFrame);
3016 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3017 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3018 } else {
3019 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3020 writel(regmisc, base + NvRegMisc1);
3021 }
3022 }
3023 }
3024
3025 /**
3026 * nv_update_linkspeed: Setup the MAC according to the link partner
3027 * @dev: Network device to be configured
3028 *
3029 * The function queries the PHY and checks if there is a link partner.
3030 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3031 * set to 10 MBit HD.
3032 *
3033 * The function returns 0 if there is no link partner and 1 if there is
3034 * a good link partner.
3035 */
3036 static int nv_update_linkspeed(struct net_device *dev)
3037 {
3038 struct fe_priv *np = netdev_priv(dev);
3039 u8 __iomem *base = get_hwbase(dev);
3040 int adv = 0;
3041 int lpa = 0;
3042 int adv_lpa, adv_pause, lpa_pause;
3043 int newls = np->linkspeed;
3044 int newdup = np->duplex;
3045 int mii_status;
3046 int retval = 0;
3047 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3048 u32 txrxFlags = 0;
3049 u32 phy_exp;
3050
3051 /* BMSR_LSTATUS is latched, read it twice:
3052 * we want the current value.
3053 */
3054 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3055 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3056
3057 if (!(mii_status & BMSR_LSTATUS)) {
3058 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3059 newdup = 0;
3060 retval = 0;
3061 goto set_speed;
3062 }
3063
3064 if (np->autoneg == 0) {
3065 if (np->fixed_mode & LPA_100FULL) {
3066 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3067 newdup = 1;
3068 } else if (np->fixed_mode & LPA_100HALF) {
3069 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3070 newdup = 0;
3071 } else if (np->fixed_mode & LPA_10FULL) {
3072 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3073 newdup = 1;
3074 } else {
3075 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3076 newdup = 0;
3077 }
3078 retval = 1;
3079 goto set_speed;
3080 }
3081 /* check auto negotiation is complete */
3082 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3083 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3084 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3085 newdup = 0;
3086 retval = 0;
3087 goto set_speed;
3088 }
3089
3090 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3091 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3092
3093 retval = 1;
3094 if (np->gigabit == PHY_GIGABIT) {
3095 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3096 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3097
3098 if ((control_1000 & ADVERTISE_1000FULL) &&
3099 (status_1000 & LPA_1000FULL)) {
3100 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3101 newdup = 1;
3102 goto set_speed;
3103 }
3104 }
3105
3106 /* FIXME: handle parallel detection properly */
3107 adv_lpa = lpa & adv;
3108 if (adv_lpa & LPA_100FULL) {
3109 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3110 newdup = 1;
3111 } else if (adv_lpa & LPA_100HALF) {
3112 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3113 newdup = 0;
3114 } else if (adv_lpa & LPA_10FULL) {
3115 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3116 newdup = 1;
3117 } else if (adv_lpa & LPA_10HALF) {
3118 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3119 newdup = 0;
3120 } else {
3121 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3122 newdup = 0;
3123 }
3124
3125 set_speed:
3126 if (np->duplex == newdup && np->linkspeed == newls)
3127 return retval;
3128
3129 np->duplex = newdup;
3130 np->linkspeed = newls;
3131
3132 /* The transmitter and receiver must be restarted for safe update */
3133 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3134 txrxFlags |= NV_RESTART_TX;
3135 nv_stop_tx(dev);
3136 }
3137 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3138 txrxFlags |= NV_RESTART_RX;
3139 nv_stop_rx(dev);
3140 }
3141
3142 if (np->gigabit == PHY_GIGABIT) {
3143 phyreg = readl(base + NvRegSlotTime);
3144 phyreg &= ~(0x3FF00);
3145 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3146 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3147 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3148 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3149 phyreg |= NVREG_SLOTTIME_1000_FULL;
3150 writel(phyreg, base + NvRegSlotTime);
3151 }
3152
3153 phyreg = readl(base + NvRegPhyInterface);
3154 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3155 if (np->duplex == 0)
3156 phyreg |= PHY_HALF;
3157 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3158 phyreg |= PHY_100;
3159 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3160 phyreg |= PHY_1000;
3161 writel(phyreg, base + NvRegPhyInterface);
3162
3163 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3164 if (phyreg & PHY_RGMII) {
3165 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3166 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3167 } else {
3168 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3169 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3170 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3171 else
3172 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3173 } else {
3174 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3175 }
3176 }
3177 } else {
3178 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3179 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3180 else
3181 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3182 }
3183 writel(txreg, base + NvRegTxDeferral);
3184
3185 if (np->desc_ver == DESC_VER_1) {
3186 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3187 } else {
3188 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3189 txreg = NVREG_TX_WM_DESC2_3_1000;
3190 else
3191 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3192 }
3193 writel(txreg, base + NvRegTxWatermark);
3194
3195 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3196 base + NvRegMisc1);
3197 pci_push(base);
3198 writel(np->linkspeed, base + NvRegLinkSpeed);
3199 pci_push(base);
3200
3201 pause_flags = 0;
3202 /* setup pause frame */
3203 if (np->duplex != 0) {
3204 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3205 adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3206 lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
3207
3208 switch (adv_pause) {
3209 case ADVERTISE_PAUSE_CAP:
3210 if (lpa_pause & LPA_PAUSE_CAP) {
3211 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3212 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3213 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3214 }
3215 break;
3216 case ADVERTISE_PAUSE_ASYM:
3217 if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
3218 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3219 break;
3220 case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3221 if (lpa_pause & LPA_PAUSE_CAP) {
3222 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3223 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3224 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3225 }
3226 if (lpa_pause == LPA_PAUSE_ASYM)
3227 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3228 break;
3229 }
3230 } else {
3231 pause_flags = np->pause_flags;
3232 }
3233 }
3234 nv_update_pause(dev, pause_flags);
3235
3236 if (txrxFlags & NV_RESTART_TX)
3237 nv_start_tx(dev);
3238 if (txrxFlags & NV_RESTART_RX)
3239 nv_start_rx(dev);
3240
3241 return retval;
3242 }
3243
3244 static void nv_linkchange(struct net_device *dev)
3245 {
3246 if (nv_update_linkspeed(dev)) {
3247 if (!netif_carrier_ok(dev)) {
3248 netif_carrier_on(dev);
3249 netdev_info(dev, "link up\n");
3250 nv_txrx_gate(dev, false);
3251 nv_start_rx(dev);
3252 }
3253 } else {
3254 if (netif_carrier_ok(dev)) {
3255 netif_carrier_off(dev);
3256 netdev_info(dev, "link down\n");
3257 nv_txrx_gate(dev, true);
3258 nv_stop_rx(dev);
3259 }
3260 }
3261 }
3262
3263 static void nv_link_irq(struct net_device *dev)
3264 {
3265 u8 __iomem *base = get_hwbase(dev);
3266 u32 miistat;
3267
3268 miistat = readl(base + NvRegMIIStatus);
3269 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3270
3271 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3272 nv_linkchange(dev);
3273 }
3274
3275 static void nv_msi_workaround(struct fe_priv *np)
3276 {
3277
3278 /* Need to toggle the msi irq mask within the ethernet device,
3279 * otherwise, future interrupts will not be detected.
3280 */
3281 if (np->msi_flags & NV_MSI_ENABLED) {
3282 u8 __iomem *base = np->base;
3283
3284 writel(0, base + NvRegMSIIrqMask);
3285 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3286 }
3287 }
3288
3289 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3290 {
3291 struct fe_priv *np = netdev_priv(dev);
3292
3293 if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3294 if (total_work > NV_DYNAMIC_THRESHOLD) {
3295 /* transition to poll based interrupts */
3296 np->quiet_count = 0;
3297 if (np->irqmask != NVREG_IRQMASK_CPU) {
3298 np->irqmask = NVREG_IRQMASK_CPU;
3299 return 1;
3300 }
3301 } else {
3302 if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3303 np->quiet_count++;
3304 } else {
3305 /* reached a period of low activity, switch
3306 to per tx/rx packet interrupts */
3307 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3308 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3309 return 1;
3310 }
3311 }
3312 }
3313 }
3314 return 0;
3315 }
3316
3317 static irqreturn_t nv_nic_irq(int foo, void *data)
3318 {
3319 struct net_device *dev = (struct net_device *) data;
3320 struct fe_priv *np = netdev_priv(dev);
3321 u8 __iomem *base = get_hwbase(dev);
3322
3323 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3324 np->events = readl(base + NvRegIrqStatus);
3325 writel(np->events, base + NvRegIrqStatus);
3326 } else {
3327 np->events = readl(base + NvRegMSIXIrqStatus);
3328 writel(np->events, base + NvRegMSIXIrqStatus);
3329 }
3330 if (!(np->events & np->irqmask))
3331 return IRQ_NONE;
3332
3333 nv_msi_workaround(np);
3334
3335 if (napi_schedule_prep(&np->napi)) {
3336 /*
3337 * Disable further irq's (msix not enabled with napi)
3338 */
3339 writel(0, base + NvRegIrqMask);
3340 __napi_schedule(&np->napi);
3341 }
3342
3343 return IRQ_HANDLED;
3344 }
3345
3346 /**
3347 * All _optimized functions are used to help increase performance
3348 * (reduce CPU and increase throughput). They use descripter version 3,
3349 * compiler directives, and reduce memory accesses.
3350 */
3351 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3352 {
3353 struct net_device *dev = (struct net_device *) data;
3354 struct fe_priv *np = netdev_priv(dev);
3355 u8 __iomem *base = get_hwbase(dev);
3356
3357 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3358 np->events = readl(base + NvRegIrqStatus);
3359 writel(np->events, base + NvRegIrqStatus);
3360 } else {
3361 np->events = readl(base + NvRegMSIXIrqStatus);
3362 writel(np->events, base + NvRegMSIXIrqStatus);
3363 }
3364 if (!(np->events & np->irqmask))
3365 return IRQ_NONE;
3366
3367 nv_msi_workaround(np);
3368
3369 if (napi_schedule_prep(&np->napi)) {
3370 /*
3371 * Disable further irq's (msix not enabled with napi)
3372 */
3373 writel(0, base + NvRegIrqMask);
3374 __napi_schedule(&np->napi);
3375 }
3376
3377 return IRQ_HANDLED;
3378 }
3379
3380 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3381 {
3382 struct net_device *dev = (struct net_device *) data;
3383 struct fe_priv *np = netdev_priv(dev);
3384 u8 __iomem *base = get_hwbase(dev);
3385 u32 events;
3386 int i;
3387 unsigned long flags;
3388
3389 for (i = 0;; i++) {
3390 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3391 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3392 if (!(events & np->irqmask))
3393 break;
3394
3395 spin_lock_irqsave(&np->lock, flags);
3396 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3397 spin_unlock_irqrestore(&np->lock, flags);
3398
3399 if (unlikely(i > max_interrupt_work)) {
3400 spin_lock_irqsave(&np->lock, flags);
3401 /* disable interrupts on the nic */
3402 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3403 pci_push(base);
3404
3405 if (!np->in_shutdown) {
3406 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3407 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3408 }
3409 spin_unlock_irqrestore(&np->lock, flags);
3410 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3411 __func__, i);
3412 break;
3413 }
3414
3415 }
3416
3417 return IRQ_RETVAL(i);
3418 }
3419
3420 static int nv_napi_poll(struct napi_struct *napi, int budget)
3421 {
3422 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3423 struct net_device *dev = np->dev;
3424 u8 __iomem *base = get_hwbase(dev);
3425 unsigned long flags;
3426 int retcode;
3427 int rx_count, tx_work = 0, rx_work = 0;
3428
3429 do {
3430 if (!nv_optimized(np)) {
3431 spin_lock_irqsave(&np->lock, flags);
3432 tx_work += nv_tx_done(dev, np->tx_ring_size);
3433 spin_unlock_irqrestore(&np->lock, flags);
3434
3435 rx_count = nv_rx_process(dev, budget - rx_work);
3436 retcode = nv_alloc_rx(dev);
3437 } else {
3438 spin_lock_irqsave(&np->lock, flags);
3439 tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3440 spin_unlock_irqrestore(&np->lock, flags);
3441
3442 rx_count = nv_rx_process_optimized(dev,
3443 budget - rx_work);
3444 retcode = nv_alloc_rx_optimized(dev);
3445 }
3446 } while (retcode == 0 &&
3447 rx_count > 0 && (rx_work += rx_count) < budget);
3448
3449 if (retcode) {
3450 spin_lock_irqsave(&np->lock, flags);
3451 if (!np->in_shutdown)
3452 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3453 spin_unlock_irqrestore(&np->lock, flags);
3454 }
3455
3456 nv_change_interrupt_mode(dev, tx_work + rx_work);
3457
3458 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3459 spin_lock_irqsave(&np->lock, flags);
3460 nv_link_irq(dev);
3461 spin_unlock_irqrestore(&np->lock, flags);
3462 }
3463 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3464 spin_lock_irqsave(&np->lock, flags);
3465 nv_linkchange(dev);
3466 spin_unlock_irqrestore(&np->lock, flags);
3467 np->link_timeout = jiffies + LINK_TIMEOUT;
3468 }
3469 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3470 spin_lock_irqsave(&np->lock, flags);
3471 if (!np->in_shutdown) {
3472 np->nic_poll_irq = np->irqmask;
3473 np->recover_error = 1;
3474 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3475 }
3476 spin_unlock_irqrestore(&np->lock, flags);
3477 napi_complete(napi);
3478 return rx_work;
3479 }
3480
3481 if (rx_work < budget) {
3482 /* re-enable interrupts
3483 (msix not enabled in napi) */
3484 napi_complete(napi);
3485
3486 writel(np->irqmask, base + NvRegIrqMask);
3487 }
3488 return rx_work;
3489 }
3490
3491 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3492 {
3493 struct net_device *dev = (struct net_device *) data;
3494 struct fe_priv *np = netdev_priv(dev);
3495 u8 __iomem *base = get_hwbase(dev);
3496 u32 events;
3497 int i;
3498 unsigned long flags;
3499
3500 for (i = 0;; i++) {
3501 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3502 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3503 if (!(events & np->irqmask))
3504 break;
3505
3506 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3507 if (unlikely(nv_alloc_rx_optimized(dev))) {
3508 spin_lock_irqsave(&np->lock, flags);
3509 if (!np->in_shutdown)
3510 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3511 spin_unlock_irqrestore(&np->lock, flags);
3512 }
3513 }
3514
3515 if (unlikely(i > max_interrupt_work)) {
3516 spin_lock_irqsave(&np->lock, flags);
3517 /* disable interrupts on the nic */
3518 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3519 pci_push(base);
3520
3521 if (!np->in_shutdown) {
3522 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3523 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3524 }
3525 spin_unlock_irqrestore(&np->lock, flags);
3526 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3527 __func__, i);
3528 break;
3529 }
3530 }
3531
3532 return IRQ_RETVAL(i);
3533 }
3534
3535 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3536 {
3537 struct net_device *dev = (struct net_device *) data;
3538 struct fe_priv *np = netdev_priv(dev);
3539 u8 __iomem *base = get_hwbase(dev);
3540 u32 events;
3541 int i;
3542 unsigned long flags;
3543
3544 for (i = 0;; i++) {
3545 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3546 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3547 if (!(events & np->irqmask))
3548 break;
3549
3550 /* check tx in case we reached max loop limit in tx isr */
3551 spin_lock_irqsave(&np->lock, flags);
3552 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3553 spin_unlock_irqrestore(&np->lock, flags);
3554
3555 if (events & NVREG_IRQ_LINK) {
3556 spin_lock_irqsave(&np->lock, flags);
3557 nv_link_irq(dev);
3558 spin_unlock_irqrestore(&np->lock, flags);
3559 }
3560 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3561 spin_lock_irqsave(&np->lock, flags);
3562 nv_linkchange(dev);
3563 spin_unlock_irqrestore(&np->lock, flags);
3564 np->link_timeout = jiffies + LINK_TIMEOUT;
3565 }
3566 if (events & NVREG_IRQ_RECOVER_ERROR) {
3567 spin_lock_irq(&np->lock);
3568 /* disable interrupts on the nic */
3569 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3570 pci_push(base);
3571
3572 if (!np->in_shutdown) {
3573 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3574 np->recover_error = 1;
3575 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3576 }
3577 spin_unlock_irq(&np->lock);
3578 break;
3579 }
3580 if (unlikely(i > max_interrupt_work)) {
3581 spin_lock_irqsave(&np->lock, flags);
3582 /* disable interrupts on the nic */
3583 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3584 pci_push(base);
3585
3586 if (!np->in_shutdown) {
3587 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3588 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3589 }
3590 spin_unlock_irqrestore(&np->lock, flags);
3591 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3592 __func__, i);
3593 break;
3594 }
3595
3596 }
3597
3598 return IRQ_RETVAL(i);
3599 }
3600
3601 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3602 {
3603 struct net_device *dev = (struct net_device *) data;
3604 struct fe_priv *np = netdev_priv(dev);
3605 u8 __iomem *base = get_hwbase(dev);
3606 u32 events;
3607
3608 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3609 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3610 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3611 } else {
3612 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3613 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3614 }
3615 pci_push(base);
3616 if (!(events & NVREG_IRQ_TIMER))
3617 return IRQ_RETVAL(0);
3618
3619 nv_msi_workaround(np);
3620
3621 spin_lock(&np->lock);
3622 np->intr_test = 1;
3623 spin_unlock(&np->lock);
3624
3625 return IRQ_RETVAL(1);
3626 }
3627
3628 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3629 {
3630 u8 __iomem *base = get_hwbase(dev);
3631 int i;
3632 u32 msixmap = 0;
3633
3634 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3635 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3636 * the remaining 8 interrupts.
3637 */
3638 for (i = 0; i < 8; i++) {
3639 if ((irqmask >> i) & 0x1)
3640 msixmap |= vector << (i << 2);
3641 }
3642 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3643
3644 msixmap = 0;
3645 for (i = 0; i < 8; i++) {
3646 if ((irqmask >> (i + 8)) & 0x1)
3647 msixmap |= vector << (i << 2);
3648 }
3649 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3650 }
3651
3652 static int nv_request_irq(struct net_device *dev, int intr_test)
3653 {
3654 struct fe_priv *np = get_nvpriv(dev);
3655 u8 __iomem *base = get_hwbase(dev);
3656 int ret = 1;
3657 int i;
3658 irqreturn_t (*handler)(int foo, void *data);
3659
3660 if (intr_test) {
3661 handler = nv_nic_irq_test;
3662 } else {
3663 if (nv_optimized(np))
3664 handler = nv_nic_irq_optimized;
3665 else
3666 handler = nv_nic_irq;
3667 }
3668
3669 if (np->msi_flags & NV_MSI_X_CAPABLE) {
3670 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3671 np->msi_x_entry[i].entry = i;
3672 ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK));
3673 if (ret == 0) {
3674 np->msi_flags |= NV_MSI_X_ENABLED;
3675 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3676 /* Request irq for rx handling */
3677 sprintf(np->name_rx, "%s-rx", dev->name);
3678 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3679 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3680 netdev_info(dev,
3681 "request_irq failed for rx %d\n",
3682 ret);
3683 pci_disable_msix(np->pci_dev);
3684 np->msi_flags &= ~NV_MSI_X_ENABLED;
3685 goto out_err;
3686 }
3687 /* Request irq for tx handling */
3688 sprintf(np->name_tx, "%s-tx", dev->name);
3689 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3690 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3691 netdev_info(dev,
3692 "request_irq failed for tx %d\n",
3693 ret);
3694 pci_disable_msix(np->pci_dev);
3695 np->msi_flags &= ~NV_MSI_X_ENABLED;
3696 goto out_free_rx;
3697 }
3698 /* Request irq for link and timer handling */
3699 sprintf(np->name_other, "%s-other", dev->name);
3700 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3701 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3702 netdev_info(dev,
3703 "request_irq failed for link %d\n",
3704 ret);
3705 pci_disable_msix(np->pci_dev);
3706 np->msi_flags &= ~NV_MSI_X_ENABLED;
3707 goto out_free_tx;
3708 }
3709 /* map interrupts to their respective vector */
3710 writel(0, base + NvRegMSIXMap0);
3711 writel(0, base + NvRegMSIXMap1);
3712 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3713 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3714 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3715 } else {
3716 /* Request irq for all interrupts */
3717 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3718 netdev_info(dev,
3719 "request_irq failed %d\n",
3720 ret);
3721 pci_disable_msix(np->pci_dev);
3722 np->msi_flags &= ~NV_MSI_X_ENABLED;
3723 goto out_err;
3724 }
3725
3726 /* map interrupts to vector 0 */
3727 writel(0, base + NvRegMSIXMap0);
3728 writel(0, base + NvRegMSIXMap1);
3729 }
3730 }
3731 }
3732 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3733 ret = pci_enable_msi(np->pci_dev);
3734 if (ret == 0) {
3735 np->msi_flags |= NV_MSI_ENABLED;
3736 dev->irq = np->pci_dev->irq;
3737 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3738 netdev_info(dev, "request_irq failed %d\n",
3739 ret);
3740 pci_disable_msi(np->pci_dev);
3741 np->msi_flags &= ~NV_MSI_ENABLED;
3742 dev->irq = np->pci_dev->irq;
3743 goto out_err;
3744 }
3745
3746 /* map interrupts to vector 0 */
3747 writel(0, base + NvRegMSIMap0);
3748 writel(0, base + NvRegMSIMap1);
3749 /* enable msi vector 0 */
3750 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3751 }
3752 }
3753 if (ret != 0) {
3754 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3755 goto out_err;
3756
3757 }
3758
3759 return 0;
3760 out_free_tx:
3761 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3762 out_free_rx:
3763 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3764 out_err:
3765 return 1;
3766 }
3767
3768 static void nv_free_irq(struct net_device *dev)
3769 {
3770 struct fe_priv *np = get_nvpriv(dev);
3771 int i;
3772
3773 if (np->msi_flags & NV_MSI_X_ENABLED) {
3774 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3775 free_irq(np->msi_x_entry[i].vector, dev);
3776 pci_disable_msix(np->pci_dev);
3777 np->msi_flags &= ~NV_MSI_X_ENABLED;
3778 } else {
3779 free_irq(np->pci_dev->irq, dev);
3780 if (np->msi_flags & NV_MSI_ENABLED) {
3781 pci_disable_msi(np->pci_dev);
3782 np->msi_flags &= ~NV_MSI_ENABLED;
3783 }
3784 }
3785 }
3786
3787 static void nv_do_nic_poll(unsigned long data)
3788 {
3789 struct net_device *dev = (struct net_device *) data;
3790 struct fe_priv *np = netdev_priv(dev);
3791 u8 __iomem *base = get_hwbase(dev);
3792 u32 mask = 0;
3793
3794 /*
3795 * First disable irq(s) and then
3796 * reenable interrupts on the nic, we have to do this before calling
3797 * nv_nic_irq because that may decide to do otherwise
3798 */
3799
3800 if (!using_multi_irqs(dev)) {
3801 if (np->msi_flags & NV_MSI_X_ENABLED)
3802 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3803 else
3804 disable_irq_lockdep(np->pci_dev->irq);
3805 mask = np->irqmask;
3806 } else {
3807 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3808 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3809 mask |= NVREG_IRQ_RX_ALL;
3810 }
3811 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3812 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3813 mask |= NVREG_IRQ_TX_ALL;
3814 }
3815 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3816 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3817 mask |= NVREG_IRQ_OTHER;
3818 }
3819 }
3820 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3821
3822 if (np->recover_error) {
3823 np->recover_error = 0;
3824 netdev_info(dev, "MAC in recoverable error state\n");
3825 if (netif_running(dev)) {
3826 netif_tx_lock_bh(dev);
3827 netif_addr_lock(dev);
3828 spin_lock(&np->lock);
3829 /* stop engines */
3830 nv_stop_rxtx(dev);
3831 if (np->driver_data & DEV_HAS_POWER_CNTRL)
3832 nv_mac_reset(dev);
3833 nv_txrx_reset(dev);
3834 /* drain rx queue */
3835 nv_drain_rxtx(dev);
3836 /* reinit driver view of the rx queue */
3837 set_bufsize(dev);
3838 if (nv_init_ring(dev)) {
3839 if (!np->in_shutdown)
3840 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3841 }
3842 /* reinit nic view of the rx queue */
3843 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3844 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3845 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3846 base + NvRegRingSizes);
3847 pci_push(base);
3848 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3849 pci_push(base);
3850 /* clear interrupts */
3851 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3852 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3853 else
3854 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3855
3856 /* restart rx engine */
3857 nv_start_rxtx(dev);
3858 spin_unlock(&np->lock);
3859 netif_addr_unlock(dev);
3860 netif_tx_unlock_bh(dev);
3861 }
3862 }
3863
3864 writel(mask, base + NvRegIrqMask);
3865 pci_push(base);
3866
3867 if (!using_multi_irqs(dev)) {
3868 np->nic_poll_irq = 0;
3869 if (nv_optimized(np))
3870 nv_nic_irq_optimized(0, dev);
3871 else
3872 nv_nic_irq(0, dev);
3873 if (np->msi_flags & NV_MSI_X_ENABLED)
3874 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3875 else
3876 enable_irq_lockdep(np->pci_dev->irq);
3877 } else {
3878 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3879 np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
3880 nv_nic_irq_rx(0, dev);
3881 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3882 }
3883 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3884 np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
3885 nv_nic_irq_tx(0, dev);
3886 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3887 }
3888 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3889 np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
3890 nv_nic_irq_other(0, dev);
3891 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3892 }
3893 }
3894
3895 }
3896
3897 #ifdef CONFIG_NET_POLL_CONTROLLER
3898 static void nv_poll_controller(struct net_device *dev)
3899 {
3900 nv_do_nic_poll((unsigned long) dev);
3901 }
3902 #endif
3903
3904 static void nv_do_stats_poll(unsigned long data)
3905 {
3906 struct net_device *dev = (struct net_device *) data;
3907 struct fe_priv *np = netdev_priv(dev);
3908
3909 nv_get_hw_stats(dev);
3910
3911 if (!np->in_shutdown)
3912 mod_timer(&np->stats_poll,
3913 round_jiffies(jiffies + STATS_INTERVAL));
3914 }
3915
3916 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3917 {
3918 struct fe_priv *np = netdev_priv(dev);
3919 strcpy(info->driver, DRV_NAME);
3920 strcpy(info->version, FORCEDETH_VERSION);
3921 strcpy(info->bus_info, pci_name(np->pci_dev));
3922 }
3923
3924 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3925 {
3926 struct fe_priv *np = netdev_priv(dev);
3927 wolinfo->supported = WAKE_MAGIC;
3928
3929 spin_lock_irq(&np->lock);
3930 if (np->wolenabled)
3931 wolinfo->wolopts = WAKE_MAGIC;
3932 spin_unlock_irq(&np->lock);
3933 }
3934
3935 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3936 {
3937 struct fe_priv *np = netdev_priv(dev);
3938 u8 __iomem *base = get_hwbase(dev);
3939 u32 flags = 0;
3940
3941 if (wolinfo->wolopts == 0) {
3942 np->wolenabled = 0;
3943 } else if (wolinfo->wolopts & WAKE_MAGIC) {
3944 np->wolenabled = 1;
3945 flags = NVREG_WAKEUPFLAGS_ENABLE;
3946 }
3947 if (netif_running(dev)) {
3948 spin_lock_irq(&np->lock);
3949 writel(flags, base + NvRegWakeUpFlags);
3950 spin_unlock_irq(&np->lock);
3951 }
3952 device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
3953 return 0;
3954 }
3955
3956 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3957 {
3958 struct fe_priv *np = netdev_priv(dev);
3959 int adv;
3960
3961 spin_lock_irq(&np->lock);
3962 ecmd->port = PORT_MII;
3963 if (!netif_running(dev)) {
3964 /* We do not track link speed / duplex setting if the
3965 * interface is disabled. Force a link check */
3966 if (nv_update_linkspeed(dev)) {
3967 if (!netif_carrier_ok(dev))
3968 netif_carrier_on(dev);
3969 } else {
3970 if (netif_carrier_ok(dev))
3971 netif_carrier_off(dev);
3972 }
3973 }
3974
3975 if (netif_carrier_ok(dev)) {
3976 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3977 case NVREG_LINKSPEED_10:
3978 ecmd->speed = SPEED_10;
3979 break;
3980 case NVREG_LINKSPEED_100:
3981 ecmd->speed = SPEED_100;
3982 break;
3983 case NVREG_LINKSPEED_1000:
3984 ecmd->speed = SPEED_1000;
3985 break;
3986 }
3987 ecmd->duplex = DUPLEX_HALF;
3988 if (np->duplex)
3989 ecmd->duplex = DUPLEX_FULL;
3990 } else {
3991 ecmd->speed = -1;
3992 ecmd->duplex = -1;
3993 }
3994
3995 ecmd->autoneg = np->autoneg;
3996
3997 ecmd->advertising = ADVERTISED_MII;
3998 if (np->autoneg) {
3999 ecmd->advertising |= ADVERTISED_Autoneg;
4000 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4001 if (adv & ADVERTISE_10HALF)
4002 ecmd->advertising |= ADVERTISED_10baseT_Half;
4003 if (adv & ADVERTISE_10FULL)
4004 ecmd->advertising |= ADVERTISED_10baseT_Full;
4005 if (adv & ADVERTISE_100HALF)
4006 ecmd->advertising |= ADVERTISED_100baseT_Half;
4007 if (adv & ADVERTISE_100FULL)
4008 ecmd->advertising |= ADVERTISED_100baseT_Full;
4009 if (np->gigabit == PHY_GIGABIT) {
4010 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4011 if (adv & ADVERTISE_1000FULL)
4012 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4013 }
4014 }
4015 ecmd->supported = (SUPPORTED_Autoneg |
4016 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4017 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4018 SUPPORTED_MII);
4019 if (np->gigabit == PHY_GIGABIT)
4020 ecmd->supported |= SUPPORTED_1000baseT_Full;
4021
4022 ecmd->phy_address = np->phyaddr;
4023 ecmd->transceiver = XCVR_EXTERNAL;
4024
4025 /* ignore maxtxpkt, maxrxpkt for now */
4026 spin_unlock_irq(&np->lock);
4027 return 0;
4028 }
4029
4030 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4031 {
4032 struct fe_priv *np = netdev_priv(dev);
4033
4034 if (ecmd->port != PORT_MII)
4035 return -EINVAL;
4036 if (ecmd->transceiver != XCVR_EXTERNAL)
4037 return -EINVAL;
4038 if (ecmd->phy_address != np->phyaddr) {
4039 /* TODO: support switching between multiple phys. Should be
4040 * trivial, but not enabled due to lack of test hardware. */
4041 return -EINVAL;
4042 }
4043 if (ecmd->autoneg == AUTONEG_ENABLE) {
4044 u32 mask;
4045
4046 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4047 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4048 if (np->gigabit == PHY_GIGABIT)
4049 mask |= ADVERTISED_1000baseT_Full;
4050
4051 if ((ecmd->advertising & mask) == 0)
4052 return -EINVAL;
4053
4054 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4055 /* Note: autonegotiation disable, speed 1000 intentionally
4056 * forbidden - noone should need that. */
4057
4058 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4059 return -EINVAL;
4060 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4061 return -EINVAL;
4062 } else {
4063 return -EINVAL;
4064 }
4065
4066 netif_carrier_off(dev);
4067 if (netif_running(dev)) {
4068 unsigned long flags;
4069
4070 nv_disable_irq(dev);
4071 netif_tx_lock_bh(dev);
4072 netif_addr_lock(dev);
4073 /* with plain spinlock lockdep complains */
4074 spin_lock_irqsave(&np->lock, flags);
4075 /* stop engines */
4076 /* FIXME:
4077 * this can take some time, and interrupts are disabled
4078 * due to spin_lock_irqsave, but let's hope no daemon
4079 * is going to change the settings very often...
4080 * Worst case:
4081 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4082 * + some minor delays, which is up to a second approximately
4083 */
4084 nv_stop_rxtx(dev);
4085 spin_unlock_irqrestore(&np->lock, flags);
4086 netif_addr_unlock(dev);
4087 netif_tx_unlock_bh(dev);
4088 }
4089
4090 if (ecmd->autoneg == AUTONEG_ENABLE) {
4091 int adv, bmcr;
4092
4093 np->autoneg = 1;
4094
4095 /* advertise only what has been requested */
4096 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4097 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4098 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4099 adv |= ADVERTISE_10HALF;
4100 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4101 adv |= ADVERTISE_10FULL;
4102 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4103 adv |= ADVERTISE_100HALF;
4104 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4105 adv |= ADVERTISE_100FULL;
4106 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4107 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4108 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4109 adv |= ADVERTISE_PAUSE_ASYM;
4110 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4111
4112 if (np->gigabit == PHY_GIGABIT) {
4113 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4114 adv &= ~ADVERTISE_1000FULL;
4115 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4116 adv |= ADVERTISE_1000FULL;
4117 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4118 }
4119
4120 if (netif_running(dev))
4121 netdev_info(dev, "link down\n");
4122 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4123 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4124 bmcr |= BMCR_ANENABLE;
4125 /* reset the phy in order for settings to stick,
4126 * and cause autoneg to start */
4127 if (phy_reset(dev, bmcr)) {
4128 netdev_info(dev, "phy reset failed\n");
4129 return -EINVAL;
4130 }
4131 } else {
4132 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4133 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4134 }
4135 } else {
4136 int adv, bmcr;
4137
4138 np->autoneg = 0;
4139
4140 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4141 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4142 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4143 adv |= ADVERTISE_10HALF;
4144 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4145 adv |= ADVERTISE_10FULL;
4146 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4147 adv |= ADVERTISE_100HALF;
4148 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4149 adv |= ADVERTISE_100FULL;
4150 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4151 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4152 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4153 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4154 }
4155 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4156 adv |= ADVERTISE_PAUSE_ASYM;
4157 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4158 }
4159 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4160 np->fixed_mode = adv;
4161
4162 if (np->gigabit == PHY_GIGABIT) {
4163 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4164 adv &= ~ADVERTISE_1000FULL;
4165 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4166 }
4167
4168 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4169 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4170 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4171 bmcr |= BMCR_FULLDPLX;
4172 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4173 bmcr |= BMCR_SPEED100;
4174 if (np->phy_oui == PHY_OUI_MARVELL) {
4175 /* reset the phy in order for forced mode settings to stick */
4176 if (phy_reset(dev, bmcr)) {
4177 netdev_info(dev, "phy reset failed\n");
4178 return -EINVAL;
4179 }
4180 } else {
4181 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4182 if (netif_running(dev)) {
4183 /* Wait a bit and then reconfigure the nic. */
4184 udelay(10);
4185 nv_linkchange(dev);
4186 }
4187 }
4188 }
4189
4190 if (netif_running(dev)) {
4191 nv_start_rxtx(dev);
4192 nv_enable_irq(dev);
4193 }
4194
4195 return 0;
4196 }
4197
4198 #define FORCEDETH_REGS_VER 1
4199
4200 static int nv_get_regs_len(struct net_device *dev)
4201 {
4202 struct fe_priv *np = netdev_priv(dev);
4203 return np->register_size;
4204 }
4205
4206 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4207 {
4208 struct fe_priv *np = netdev_priv(dev);
4209 u8 __iomem *base = get_hwbase(dev);
4210 u32 *rbuf = buf;
4211 int i;
4212
4213 regs->version = FORCEDETH_REGS_VER;
4214 spin_lock_irq(&np->lock);
4215 for (i = 0; i <= np->register_size/sizeof(u32); i++)
4216 rbuf[i] = readl(base + i*sizeof(u32));
4217 spin_unlock_irq(&np->lock);
4218 }
4219
4220 static int nv_nway_reset(struct net_device *dev)
4221 {
4222 struct fe_priv *np = netdev_priv(dev);
4223 int ret;
4224
4225 if (np->autoneg) {
4226 int bmcr;
4227
4228 netif_carrier_off(dev);
4229 if (netif_running(dev)) {
4230 nv_disable_irq(dev);
4231 netif_tx_lock_bh(dev);
4232 netif_addr_lock(dev);
4233 spin_lock(&np->lock);
4234 /* stop engines */
4235 nv_stop_rxtx(dev);
4236 spin_unlock(&np->lock);
4237 netif_addr_unlock(dev);
4238 netif_tx_unlock_bh(dev);
4239 netdev_info(dev, "link down\n");
4240 }
4241
4242 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4243 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4244 bmcr |= BMCR_ANENABLE;
4245 /* reset the phy in order for settings to stick*/
4246 if (phy_reset(dev, bmcr)) {
4247 netdev_info(dev, "phy reset failed\n");
4248 return -EINVAL;
4249 }
4250 } else {
4251 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4252 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4253 }
4254
4255 if (netif_running(dev)) {
4256 nv_start_rxtx(dev);
4257 nv_enable_irq(dev);
4258 }
4259 ret = 0;
4260 } else {
4261 ret = -EINVAL;
4262 }
4263
4264 return ret;
4265 }
4266
4267 static int nv_set_tso(struct net_device *dev, u32 value)
4268 {
4269 struct fe_priv *np = netdev_priv(dev);
4270
4271 if ((np->driver_data & DEV_HAS_CHECKSUM))
4272 return ethtool_op_set_tso(dev, value);
4273 else
4274 return -EOPNOTSUPP;
4275 }
4276
4277 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4278 {
4279 struct fe_priv *np = netdev_priv(dev);
4280
4281 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4282 ring->rx_mini_max_pending = 0;
4283 ring->rx_jumbo_max_pending = 0;
4284 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4285
4286 ring->rx_pending = np->rx_ring_size;
4287 ring->rx_mini_pending = 0;
4288 ring->rx_jumbo_pending = 0;
4289 ring->tx_pending = np->tx_ring_size;
4290 }
4291
4292 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4293 {
4294 struct fe_priv *np = netdev_priv(dev);
4295 u8 __iomem *base = get_hwbase(dev);
4296 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4297 dma_addr_t ring_addr;
4298
4299 if (ring->rx_pending < RX_RING_MIN ||
4300 ring->tx_pending < TX_RING_MIN ||
4301 ring->rx_mini_pending != 0 ||
4302 ring->rx_jumbo_pending != 0 ||
4303 (np->desc_ver == DESC_VER_1 &&
4304 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4305 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4306 (np->desc_ver != DESC_VER_1 &&
4307 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4308 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4309 return -EINVAL;
4310 }
4311
4312 /* allocate new rings */
4313 if (!nv_optimized(np)) {
4314 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4315 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4316 &ring_addr);
4317 } else {
4318 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4319 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4320 &ring_addr);
4321 }
4322 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4323 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4324 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4325 /* fall back to old rings */
4326 if (!nv_optimized(np)) {
4327 if (rxtx_ring)
4328 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4329 rxtx_ring, ring_addr);
4330 } else {
4331 if (rxtx_ring)
4332 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4333 rxtx_ring, ring_addr);
4334 }
4335
4336 kfree(rx_skbuff);
4337 kfree(tx_skbuff);
4338 goto exit;
4339 }
4340
4341 if (netif_running(dev)) {
4342 nv_disable_irq(dev);
4343 nv_napi_disable(dev);
4344 netif_tx_lock_bh(dev);
4345 netif_addr_lock(dev);
4346 spin_lock(&np->lock);
4347 /* stop engines */
4348 nv_stop_rxtx(dev);
4349 nv_txrx_reset(dev);
4350 /* drain queues */
4351 nv_drain_rxtx(dev);
4352 /* delete queues */
4353 free_rings(dev);
4354 }
4355
4356 /* set new values */
4357 np->rx_ring_size = ring->rx_pending;
4358 np->tx_ring_size = ring->tx_pending;
4359
4360 if (!nv_optimized(np)) {
4361 np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
4362 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4363 } else {
4364 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
4365 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4366 }
4367 np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4368 np->tx_skb = (struct nv_skb_map *)tx_skbuff;
4369 np->ring_addr = ring_addr;
4370
4371 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4372 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4373
4374 if (netif_running(dev)) {
4375 /* reinit driver view of the queues */
4376 set_bufsize(dev);
4377 if (nv_init_ring(dev)) {
4378 if (!np->in_shutdown)
4379 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4380 }
4381
4382 /* reinit nic view of the queues */
4383 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4384 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4385 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4386 base + NvRegRingSizes);
4387 pci_push(base);
4388 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4389 pci_push(base);
4390
4391 /* restart engines */
4392 nv_start_rxtx(dev);
4393 spin_unlock(&np->lock);
4394 netif_addr_unlock(dev);
4395 netif_tx_unlock_bh(dev);
4396 nv_napi_enable(dev);
4397 nv_enable_irq(dev);
4398 }
4399 return 0;
4400 exit:
4401 return -ENOMEM;
4402 }
4403
4404 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4405 {
4406 struct fe_priv *np = netdev_priv(dev);
4407
4408 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4409 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4410 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4411 }
4412
4413 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4414 {
4415 struct fe_priv *np = netdev_priv(dev);
4416 int adv, bmcr;
4417
4418 if ((!np->autoneg && np->duplex == 0) ||
4419 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4420 netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
4421 return -EINVAL;
4422 }
4423 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4424 netdev_info(dev, "hardware does not support tx pause frames\n");
4425 return -EINVAL;
4426 }
4427
4428 netif_carrier_off(dev);
4429 if (netif_running(dev)) {
4430 nv_disable_irq(dev);
4431 netif_tx_lock_bh(dev);
4432 netif_addr_lock(dev);
4433 spin_lock(&np->lock);
4434 /* stop engines */
4435 nv_stop_rxtx(dev);
4436 spin_unlock(&np->lock);
4437 netif_addr_unlock(dev);
4438 netif_tx_unlock_bh(dev);
4439 }
4440
4441 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4442 if (pause->rx_pause)
4443 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4444 if (pause->tx_pause)
4445 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4446
4447 if (np->autoneg && pause->autoneg) {
4448 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4449
4450 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4451 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4452 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4453 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4454 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4455 adv |= ADVERTISE_PAUSE_ASYM;
4456 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4457
4458 if (netif_running(dev))
4459 netdev_info(dev, "link down\n");
4460 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4461 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4462 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4463 } else {
4464 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4465 if (pause->rx_pause)
4466 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4467 if (pause->tx_pause)
4468 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4469
4470 if (!netif_running(dev))
4471 nv_update_linkspeed(dev);
4472 else
4473 nv_update_pause(dev, np->pause_flags);
4474 }
4475
4476 if (netif_running(dev)) {
4477 nv_start_rxtx(dev);
4478 nv_enable_irq(dev);
4479 }
4480 return 0;
4481 }
4482
4483 static u32 nv_get_rx_csum(struct net_device *dev)
4484 {
4485 struct fe_priv *np = netdev_priv(dev);
4486 return np->rx_csum != 0;
4487 }
4488
4489 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4490 {
4491 struct fe_priv *np = netdev_priv(dev);
4492 u8 __iomem *base = get_hwbase(dev);
4493 int retcode = 0;
4494
4495 if (np->driver_data & DEV_HAS_CHECKSUM) {
4496 if (data) {
4497 np->rx_csum = 1;
4498 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4499 } else {
4500 np->rx_csum = 0;
4501 /* vlan is dependent on rx checksum offload */
4502 if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4503 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4504 }
4505 if (netif_running(dev)) {
4506 spin_lock_irq(&np->lock);
4507 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4508 spin_unlock_irq(&np->lock);
4509 }
4510 } else {
4511 return -EINVAL;
4512 }
4513
4514 return retcode;
4515 }
4516
4517 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4518 {
4519 struct fe_priv *np = netdev_priv(dev);
4520
4521 if (np->driver_data & DEV_HAS_CHECKSUM)
4522 return ethtool_op_set_tx_csum(dev, data);
4523 else
4524 return -EOPNOTSUPP;
4525 }
4526
4527 static int nv_set_sg(struct net_device *dev, u32 data)
4528 {
4529 struct fe_priv *np = netdev_priv(dev);
4530
4531 if (np->driver_data & DEV_HAS_CHECKSUM)
4532 return ethtool_op_set_sg(dev, data);
4533 else
4534 return -EOPNOTSUPP;
4535 }
4536
4537 static int nv_get_sset_count(struct net_device *dev, int sset)
4538 {
4539 struct fe_priv *np = netdev_priv(dev);
4540
4541 switch (sset) {
4542 case ETH_SS_TEST:
4543 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4544 return NV_TEST_COUNT_EXTENDED;
4545 else
4546 return NV_TEST_COUNT_BASE;
4547 case ETH_SS_STATS:
4548 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4549 return NV_DEV_STATISTICS_V3_COUNT;
4550 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4551 return NV_DEV_STATISTICS_V2_COUNT;
4552 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4553 return NV_DEV_STATISTICS_V1_COUNT;
4554 else
4555 return 0;
4556 default:
4557 return -EOPNOTSUPP;
4558 }
4559 }
4560
4561 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4562 {
4563 struct fe_priv *np = netdev_priv(dev);
4564
4565 /* update stats */
4566 nv_do_stats_poll((unsigned long)dev);
4567
4568 memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4569 }
4570
4571 static int nv_link_test(struct net_device *dev)
4572 {
4573 struct fe_priv *np = netdev_priv(dev);
4574 int mii_status;
4575
4576 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4577 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4578
4579 /* check phy link status */
4580 if (!(mii_status & BMSR_LSTATUS))
4581 return 0;
4582 else
4583 return 1;
4584 }
4585
4586 static int nv_register_test(struct net_device *dev)
4587 {
4588 u8 __iomem *base = get_hwbase(dev);
4589 int i = 0;
4590 u32 orig_read, new_read;
4591
4592 do {
4593 orig_read = readl(base + nv_registers_test[i].reg);
4594
4595 /* xor with mask to toggle bits */
4596 orig_read ^= nv_registers_test[i].mask;
4597
4598 writel(orig_read, base + nv_registers_test[i].reg);
4599
4600 new_read = readl(base + nv_registers_test[i].reg);
4601
4602 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4603 return 0;
4604
4605 /* restore original value */
4606 orig_read ^= nv_registers_test[i].mask;
4607 writel(orig_read, base + nv_registers_test[i].reg);
4608
4609 } while (nv_registers_test[++i].reg != 0);
4610
4611 return 1;
4612 }
4613
4614 static int nv_interrupt_test(struct net_device *dev)
4615 {
4616 struct fe_priv *np = netdev_priv(dev);
4617 u8 __iomem *base = get_hwbase(dev);
4618 int ret = 1;
4619 int testcnt;
4620 u32 save_msi_flags, save_poll_interval = 0;
4621
4622 if (netif_running(dev)) {
4623 /* free current irq */
4624 nv_free_irq(dev);
4625 save_poll_interval = readl(base+NvRegPollingInterval);
4626 }
4627
4628 /* flag to test interrupt handler */
4629 np->intr_test = 0;
4630
4631 /* setup test irq */
4632 save_msi_flags = np->msi_flags;
4633 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4634 np->msi_flags |= 0x001; /* setup 1 vector */
4635 if (nv_request_irq(dev, 1))
4636 return 0;
4637
4638 /* setup timer interrupt */
4639 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4640 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4641
4642 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4643
4644 /* wait for at least one interrupt */
4645 msleep(100);
4646
4647 spin_lock_irq(&np->lock);
4648
4649 /* flag should be set within ISR */
4650 testcnt = np->intr_test;
4651 if (!testcnt)
4652 ret = 2;
4653
4654 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4655 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4656 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4657 else
4658 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4659
4660 spin_unlock_irq(&np->lock);
4661
4662 nv_free_irq(dev);
4663
4664 np->msi_flags = save_msi_flags;
4665
4666 if (netif_running(dev)) {
4667 writel(save_poll_interval, base + NvRegPollingInterval);
4668 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4669 /* restore original irq */
4670 if (nv_request_irq(dev, 0))
4671 return 0;
4672 }
4673
4674 return ret;
4675 }
4676
4677 static int nv_loopback_test(struct net_device *dev)
4678 {
4679 struct fe_priv *np = netdev_priv(dev);
4680 u8 __iomem *base = get_hwbase(dev);
4681 struct sk_buff *tx_skb, *rx_skb;
4682 dma_addr_t test_dma_addr;
4683 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4684 u32 flags;
4685 int len, i, pkt_len;
4686 u8 *pkt_data;
4687 u32 filter_flags = 0;
4688 u32 misc1_flags = 0;
4689 int ret = 1;
4690
4691 if (netif_running(dev)) {
4692 nv_disable_irq(dev);
4693 filter_flags = readl(base + NvRegPacketFilterFlags);
4694 misc1_flags = readl(base + NvRegMisc1);
4695 } else {
4696 nv_txrx_reset(dev);
4697 }
4698
4699 /* reinit driver view of the rx queue */
4700 set_bufsize(dev);
4701 nv_init_ring(dev);
4702
4703 /* setup hardware for loopback */
4704 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4705 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4706
4707 /* reinit nic view of the rx queue */
4708 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4709 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4710 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4711 base + NvRegRingSizes);
4712 pci_push(base);
4713
4714 /* restart rx engine */
4715 nv_start_rxtx(dev);
4716
4717 /* setup packet for tx */
4718 pkt_len = ETH_DATA_LEN;
4719 tx_skb = dev_alloc_skb(pkt_len);
4720 if (!tx_skb) {
4721 netdev_err(dev, "dev_alloc_skb() failed during loopback test\n");
4722 ret = 0;
4723 goto out;
4724 }
4725 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4726 skb_tailroom(tx_skb),
4727 PCI_DMA_FROMDEVICE);
4728 pkt_data = skb_put(tx_skb, pkt_len);
4729 for (i = 0; i < pkt_len; i++)
4730 pkt_data[i] = (u8)(i & 0xff);
4731
4732 if (!nv_optimized(np)) {
4733 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4734 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4735 } else {
4736 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4737 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4738 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4739 }
4740 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4741 pci_push(get_hwbase(dev));
4742
4743 msleep(500);
4744
4745 /* check for rx of the packet */
4746 if (!nv_optimized(np)) {
4747 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4748 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4749
4750 } else {
4751 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4752 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4753 }
4754
4755 if (flags & NV_RX_AVAIL) {
4756 ret = 0;
4757 } else if (np->desc_ver == DESC_VER_1) {
4758 if (flags & NV_RX_ERROR)
4759 ret = 0;
4760 } else {
4761 if (flags & NV_RX2_ERROR)
4762 ret = 0;
4763 }
4764
4765 if (ret) {
4766 if (len != pkt_len) {
4767 ret = 0;
4768 } else {
4769 rx_skb = np->rx_skb[0].skb;
4770 for (i = 0; i < pkt_len; i++) {
4771 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4772 ret = 0;
4773 break;
4774 }
4775 }
4776 }
4777 }
4778
4779 pci_unmap_single(np->pci_dev, test_dma_addr,
4780 (skb_end_pointer(tx_skb) - tx_skb->data),
4781 PCI_DMA_TODEVICE);
4782 dev_kfree_skb_any(tx_skb);
4783 out:
4784 /* stop engines */
4785 nv_stop_rxtx(dev);
4786 nv_txrx_reset(dev);
4787 /* drain rx queue */
4788 nv_drain_rxtx(dev);
4789
4790 if (netif_running(dev)) {
4791 writel(misc1_flags, base + NvRegMisc1);
4792 writel(filter_flags, base + NvRegPacketFilterFlags);
4793 nv_enable_irq(dev);
4794 }
4795
4796 return ret;
4797 }
4798
4799 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4800 {
4801 struct fe_priv *np = netdev_priv(dev);
4802 u8 __iomem *base = get_hwbase(dev);
4803 int result;
4804 memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
4805
4806 if (!nv_link_test(dev)) {
4807 test->flags |= ETH_TEST_FL_FAILED;
4808 buffer[0] = 1;
4809 }
4810
4811 if (test->flags & ETH_TEST_FL_OFFLINE) {
4812 if (netif_running(dev)) {
4813 netif_stop_queue(dev);
4814 nv_napi_disable(dev);
4815 netif_tx_lock_bh(dev);
4816 netif_addr_lock(dev);
4817 spin_lock_irq(&np->lock);
4818 nv_disable_hw_interrupts(dev, np->irqmask);
4819 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4820 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4821 else
4822 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4823 /* stop engines */
4824 nv_stop_rxtx(dev);
4825 nv_txrx_reset(dev);
4826 /* drain rx queue */
4827 nv_drain_rxtx(dev);
4828 spin_unlock_irq(&np->lock);
4829 netif_addr_unlock(dev);
4830 netif_tx_unlock_bh(dev);
4831 }
4832
4833 if (!nv_register_test(dev)) {
4834 test->flags |= ETH_TEST_FL_FAILED;
4835 buffer[1] = 1;
4836 }
4837
4838 result = nv_interrupt_test(dev);
4839 if (result != 1) {
4840 test->flags |= ETH_TEST_FL_FAILED;
4841 buffer[2] = 1;
4842 }
4843 if (result == 0) {
4844 /* bail out */
4845 return;
4846 }
4847
4848 if (!nv_loopback_test(dev)) {
4849 test->flags |= ETH_TEST_FL_FAILED;
4850 buffer[3] = 1;
4851 }
4852
4853 if (netif_running(dev)) {
4854 /* reinit driver view of the rx queue */
4855 set_bufsize(dev);
4856 if (nv_init_ring(dev)) {
4857 if (!np->in_shutdown)
4858 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4859 }
4860 /* reinit nic view of the rx queue */
4861 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4862 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4863 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4864 base + NvRegRingSizes);
4865 pci_push(base);
4866 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4867 pci_push(base);
4868 /* restart rx engine */
4869 nv_start_rxtx(dev);
4870 netif_start_queue(dev);
4871 nv_napi_enable(dev);
4872 nv_enable_hw_interrupts(dev, np->irqmask);
4873 }
4874 }
4875 }
4876
4877 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4878 {
4879 switch (stringset) {
4880 case ETH_SS_STATS:
4881 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
4882 break;
4883 case ETH_SS_TEST:
4884 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
4885 break;
4886 }
4887 }
4888
4889 static const struct ethtool_ops ops = {
4890 .get_drvinfo = nv_get_drvinfo,
4891 .get_link = ethtool_op_get_link,
4892 .get_wol = nv_get_wol,
4893 .set_wol = nv_set_wol,
4894 .get_settings = nv_get_settings,
4895 .set_settings = nv_set_settings,
4896 .get_regs_len = nv_get_regs_len,
4897 .get_regs = nv_get_regs,
4898 .nway_reset = nv_nway_reset,
4899 .set_tso = nv_set_tso,
4900 .get_ringparam = nv_get_ringparam,
4901 .set_ringparam = nv_set_ringparam,
4902 .get_pauseparam = nv_get_pauseparam,
4903 .set_pauseparam = nv_set_pauseparam,
4904 .get_rx_csum = nv_get_rx_csum,
4905 .set_rx_csum = nv_set_rx_csum,
4906 .set_tx_csum = nv_set_tx_csum,
4907 .set_sg = nv_set_sg,
4908 .get_strings = nv_get_strings,
4909 .get_ethtool_stats = nv_get_ethtool_stats,
4910 .get_sset_count = nv_get_sset_count,
4911 .self_test = nv_self_test,
4912 };
4913
4914 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4915 {
4916 struct fe_priv *np = get_nvpriv(dev);
4917
4918 spin_lock_irq(&np->lock);
4919
4920 /* save vlan group */
4921 np->vlangrp = grp;
4922
4923 if (grp) {
4924 /* enable vlan on MAC */
4925 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4926 } else {
4927 /* disable vlan on MAC */
4928 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4929 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4930 }
4931
4932 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4933
4934 spin_unlock_irq(&np->lock);
4935 }
4936
4937 /* The mgmt unit and driver use a semaphore to access the phy during init */
4938 static int nv_mgmt_acquire_sema(struct net_device *dev)
4939 {
4940 struct fe_priv *np = netdev_priv(dev);
4941 u8 __iomem *base = get_hwbase(dev);
4942 int i;
4943 u32 tx_ctrl, mgmt_sema;
4944
4945 for (i = 0; i < 10; i++) {
4946 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4947 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4948 break;
4949 msleep(500);
4950 }
4951
4952 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4953 return 0;
4954
4955 for (i = 0; i < 2; i++) {
4956 tx_ctrl = readl(base + NvRegTransmitterControl);
4957 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4958 writel(tx_ctrl, base + NvRegTransmitterControl);
4959
4960 /* verify that semaphore was acquired */
4961 tx_ctrl = readl(base + NvRegTransmitterControl);
4962 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4963 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
4964 np->mgmt_sema = 1;
4965 return 1;
4966 } else
4967 udelay(50);
4968 }
4969
4970 return 0;
4971 }
4972
4973 static void nv_mgmt_release_sema(struct net_device *dev)
4974 {
4975 struct fe_priv *np = netdev_priv(dev);
4976 u8 __iomem *base = get_hwbase(dev);
4977 u32 tx_ctrl;
4978
4979 if (np->driver_data & DEV_HAS_MGMT_UNIT) {
4980 if (np->mgmt_sema) {
4981 tx_ctrl = readl(base + NvRegTransmitterControl);
4982 tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
4983 writel(tx_ctrl, base + NvRegTransmitterControl);
4984 }
4985 }
4986 }
4987
4988
4989 static int nv_mgmt_get_version(struct net_device *dev)
4990 {
4991 struct fe_priv *np = netdev_priv(dev);
4992 u8 __iomem *base = get_hwbase(dev);
4993 u32 data_ready = readl(base + NvRegTransmitterControl);
4994 u32 data_ready2 = 0;
4995 unsigned long start;
4996 int ready = 0;
4997
4998 writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
4999 writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5000 start = jiffies;
5001 while (time_before(jiffies, start + 5*HZ)) {
5002 data_ready2 = readl(base + NvRegTransmitterControl);
5003 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5004 ready = 1;
5005 break;
5006 }
5007 schedule_timeout_uninterruptible(1);
5008 }
5009
5010 if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5011 return 0;
5012
5013 np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5014
5015 return 1;
5016 }
5017
5018 static int nv_open(struct net_device *dev)
5019 {
5020 struct fe_priv *np = netdev_priv(dev);
5021 u8 __iomem *base = get_hwbase(dev);
5022 int ret = 1;
5023 int oom, i;
5024 u32 low;
5025
5026 /* power up phy */
5027 mii_rw(dev, np->phyaddr, MII_BMCR,
5028 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5029
5030 nv_txrx_gate(dev, false);
5031 /* erase previous misconfiguration */
5032 if (np->driver_data & DEV_HAS_POWER_CNTRL)
5033 nv_mac_reset(dev);
5034 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5035 writel(0, base + NvRegMulticastAddrB);
5036 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5037 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5038 writel(0, base + NvRegPacketFilterFlags);
5039
5040 writel(0, base + NvRegTransmitterControl);
5041 writel(0, base + NvRegReceiverControl);
5042
5043 writel(0, base + NvRegAdapterControl);
5044
5045 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5046 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
5047
5048 /* initialize descriptor rings */
5049 set_bufsize(dev);
5050 oom = nv_init_ring(dev);
5051
5052 writel(0, base + NvRegLinkSpeed);
5053 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5054 nv_txrx_reset(dev);
5055 writel(0, base + NvRegUnknownSetupReg6);
5056
5057 np->in_shutdown = 0;
5058
5059 /* give hw rings */
5060 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5061 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5062 base + NvRegRingSizes);
5063
5064 writel(np->linkspeed, base + NvRegLinkSpeed);
5065 if (np->desc_ver == DESC_VER_1)
5066 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5067 else
5068 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5069 writel(np->txrxctl_bits, base + NvRegTxRxControl);
5070 writel(np->vlanctl_bits, base + NvRegVlanControl);
5071 pci_push(base);
5072 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5073 if (reg_delay(dev, NvRegUnknownSetupReg5,
5074 NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5075 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
5076 netdev_info(dev,
5077 "%s: SetupReg5, Bit 31 remained off\n", __func__);
5078
5079 writel(0, base + NvRegMIIMask);
5080 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5081 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5082
5083 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5084 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5085 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5086 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5087
5088 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5089
5090 get_random_bytes(&low, sizeof(low));
5091 low &= NVREG_SLOTTIME_MASK;
5092 if (np->desc_ver == DESC_VER_1) {
5093 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5094 } else {
5095 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5096 /* setup legacy backoff */
5097 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5098 } else {
5099 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5100 nv_gear_backoff_reseed(dev);
5101 }
5102 }
5103 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5104 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5105 if (poll_interval == -1) {
5106 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5107 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5108 else
5109 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5110 } else
5111 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5112 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5113 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5114 base + NvRegAdapterControl);
5115 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5116 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5117 if (np->wolenabled)
5118 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5119
5120 i = readl(base + NvRegPowerState);
5121 if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
5122 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5123
5124 pci_push(base);
5125 udelay(10);
5126 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5127
5128 nv_disable_hw_interrupts(dev, np->irqmask);
5129 pci_push(base);
5130 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5131 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5132 pci_push(base);
5133
5134 if (nv_request_irq(dev, 0))
5135 goto out_drain;
5136
5137 /* ask for interrupts */
5138 nv_enable_hw_interrupts(dev, np->irqmask);
5139
5140 spin_lock_irq(&np->lock);
5141 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5142 writel(0, base + NvRegMulticastAddrB);
5143 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5144 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5145 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5146 /* One manual link speed update: Interrupts are enabled, future link
5147 * speed changes cause interrupts and are handled by nv_link_irq().
5148 */
5149 {
5150 u32 miistat;
5151 miistat = readl(base + NvRegMIIStatus);
5152 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5153 }
5154 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5155 * to init hw */
5156 np->linkspeed = 0;
5157 ret = nv_update_linkspeed(dev);
5158 nv_start_rxtx(dev);
5159 netif_start_queue(dev);
5160 nv_napi_enable(dev);
5161
5162 if (ret) {
5163 netif_carrier_on(dev);
5164 } else {
5165 netdev_info(dev, "no link during initialization\n");
5166 netif_carrier_off(dev);
5167 }
5168 if (oom)
5169 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5170
5171 /* start statistics timer */
5172 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5173 mod_timer(&np->stats_poll,
5174 round_jiffies(jiffies + STATS_INTERVAL));
5175
5176 spin_unlock_irq(&np->lock);
5177
5178 return 0;
5179 out_drain:
5180 nv_drain_rxtx(dev);
5181 return ret;
5182 }
5183
5184 static int nv_close(struct net_device *dev)
5185 {
5186 struct fe_priv *np = netdev_priv(dev);
5187 u8 __iomem *base;
5188
5189 spin_lock_irq(&np->lock);
5190 np->in_shutdown = 1;
5191 spin_unlock_irq(&np->lock);
5192 nv_napi_disable(dev);
5193 synchronize_irq(np->pci_dev->irq);
5194
5195 del_timer_sync(&np->oom_kick);
5196 del_timer_sync(&np->nic_poll);
5197 del_timer_sync(&np->stats_poll);
5198
5199 netif_stop_queue(dev);
5200 spin_lock_irq(&np->lock);
5201 nv_stop_rxtx(dev);
5202 nv_txrx_reset(dev);
5203
5204 /* disable interrupts on the nic or we will lock up */
5205 base = get_hwbase(dev);
5206 nv_disable_hw_interrupts(dev, np->irqmask);
5207 pci_push(base);
5208
5209 spin_unlock_irq(&np->lock);
5210
5211 nv_free_irq(dev);
5212
5213 nv_drain_rxtx(dev);
5214
5215 if (np->wolenabled || !phy_power_down) {
5216 nv_txrx_gate(dev, false);
5217 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5218 nv_start_rx(dev);
5219 } else {
5220 /* power down phy */
5221 mii_rw(dev, np->phyaddr, MII_BMCR,
5222 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5223 nv_txrx_gate(dev, true);
5224 }
5225
5226 /* FIXME: power down nic */
5227
5228 return 0;
5229 }
5230
5231 static const struct net_device_ops nv_netdev_ops = {
5232 .ndo_open = nv_open,
5233 .ndo_stop = nv_close,
5234 .ndo_get_stats = nv_get_stats,
5235 .ndo_start_xmit = nv_start_xmit,
5236 .ndo_tx_timeout = nv_tx_timeout,
5237 .ndo_change_mtu = nv_change_mtu,
5238 .ndo_validate_addr = eth_validate_addr,
5239 .ndo_set_mac_address = nv_set_mac_address,
5240 .ndo_set_multicast_list = nv_set_multicast,
5241 .ndo_vlan_rx_register = nv_vlan_rx_register,
5242 #ifdef CONFIG_NET_POLL_CONTROLLER
5243 .ndo_poll_controller = nv_poll_controller,
5244 #endif
5245 };
5246
5247 static const struct net_device_ops nv_netdev_ops_optimized = {
5248 .ndo_open = nv_open,
5249 .ndo_stop = nv_close,
5250 .ndo_get_stats = nv_get_stats,
5251 .ndo_start_xmit = nv_start_xmit_optimized,
5252 .ndo_tx_timeout = nv_tx_timeout,
5253 .ndo_change_mtu = nv_change_mtu,
5254 .ndo_validate_addr = eth_validate_addr,
5255 .ndo_set_mac_address = nv_set_mac_address,
5256 .ndo_set_multicast_list = nv_set_multicast,
5257 .ndo_vlan_rx_register = nv_vlan_rx_register,
5258 #ifdef CONFIG_NET_POLL_CONTROLLER
5259 .ndo_poll_controller = nv_poll_controller,
5260 #endif
5261 };
5262
5263 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5264 {
5265 struct net_device *dev;
5266 struct fe_priv *np;
5267 unsigned long addr;
5268 u8 __iomem *base;
5269 int err, i;
5270 u32 powerstate, txreg;
5271 u32 phystate_orig = 0, phystate;
5272 int phyinitialized = 0;
5273 static int printed_version;
5274
5275 if (!printed_version++)
5276 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5277 FORCEDETH_VERSION);
5278
5279 dev = alloc_etherdev(sizeof(struct fe_priv));
5280 err = -ENOMEM;
5281 if (!dev)
5282 goto out;
5283
5284 np = netdev_priv(dev);
5285 np->dev = dev;
5286 np->pci_dev = pci_dev;
5287 spin_lock_init(&np->lock);
5288 SET_NETDEV_DEV(dev, &pci_dev->dev);
5289
5290 init_timer(&np->oom_kick);
5291 np->oom_kick.data = (unsigned long) dev;
5292 np->oom_kick.function = nv_do_rx_refill; /* timer handler */
5293 init_timer(&np->nic_poll);
5294 np->nic_poll.data = (unsigned long) dev;
5295 np->nic_poll.function = nv_do_nic_poll; /* timer handler */
5296 init_timer(&np->stats_poll);
5297 np->stats_poll.data = (unsigned long) dev;
5298 np->stats_poll.function = nv_do_stats_poll; /* timer handler */
5299
5300 err = pci_enable_device(pci_dev);
5301 if (err)
5302 goto out_free;
5303
5304 pci_set_master(pci_dev);
5305
5306 err = pci_request_regions(pci_dev, DRV_NAME);
5307 if (err < 0)
5308 goto out_disable;
5309
5310 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5311 np->register_size = NV_PCI_REGSZ_VER3;
5312 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5313 np->register_size = NV_PCI_REGSZ_VER2;
5314 else
5315 np->register_size = NV_PCI_REGSZ_VER1;
5316
5317 err = -EINVAL;
5318 addr = 0;
5319 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5320 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5321 pci_resource_len(pci_dev, i) >= np->register_size) {
5322 addr = pci_resource_start(pci_dev, i);
5323 break;
5324 }
5325 }
5326 if (i == DEVICE_COUNT_RESOURCE) {
5327 dev_info(&pci_dev->dev, "Couldn't find register window\n");
5328 goto out_relreg;
5329 }
5330
5331 /* copy of driver data */
5332 np->driver_data = id->driver_data;
5333 /* copy of device id */
5334 np->device_id = id->device;
5335
5336 /* handle different descriptor versions */
5337 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5338 /* packet format 3: supports 40-bit addressing */
5339 np->desc_ver = DESC_VER_3;
5340 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5341 if (dma_64bit) {
5342 if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5343 dev_info(&pci_dev->dev,
5344 "64-bit DMA failed, using 32-bit addressing\n");
5345 else
5346 dev->features |= NETIF_F_HIGHDMA;
5347 if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5348 dev_info(&pci_dev->dev,
5349 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5350 }
5351 }
5352 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5353 /* packet format 2: supports jumbo frames */
5354 np->desc_ver = DESC_VER_2;
5355 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5356 } else {
5357 /* original packet format */
5358 np->desc_ver = DESC_VER_1;
5359 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5360 }
5361
5362 np->pkt_limit = NV_PKTLIMIT_1;
5363 if (id->driver_data & DEV_HAS_LARGEDESC)
5364 np->pkt_limit = NV_PKTLIMIT_2;
5365
5366 if (id->driver_data & DEV_HAS_CHECKSUM) {
5367 np->rx_csum = 1;
5368 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5369 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
5370 dev->features |= NETIF_F_TSO;
5371 dev->features |= NETIF_F_GRO;
5372 }
5373
5374 np->vlanctl_bits = 0;
5375 if (id->driver_data & DEV_HAS_VLAN) {
5376 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5377 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5378 }
5379
5380 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5381 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5382 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5383 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5384 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5385 }
5386
5387
5388 err = -ENOMEM;
5389 np->base = ioremap(addr, np->register_size);
5390 if (!np->base)
5391 goto out_relreg;
5392 dev->base_addr = (unsigned long)np->base;
5393
5394 dev->irq = pci_dev->irq;
5395
5396 np->rx_ring_size = RX_RING_DEFAULT;
5397 np->tx_ring_size = TX_RING_DEFAULT;
5398
5399 if (!nv_optimized(np)) {
5400 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5401 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5402 &np->ring_addr);
5403 if (!np->rx_ring.orig)
5404 goto out_unmap;
5405 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5406 } else {
5407 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5408 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5409 &np->ring_addr);
5410 if (!np->rx_ring.ex)
5411 goto out_unmap;
5412 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5413 }
5414 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5415 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5416 if (!np->rx_skb || !np->tx_skb)
5417 goto out_freering;
5418
5419 if (!nv_optimized(np))
5420 dev->netdev_ops = &nv_netdev_ops;
5421 else
5422 dev->netdev_ops = &nv_netdev_ops_optimized;
5423
5424 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5425 SET_ETHTOOL_OPS(dev, &ops);
5426 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5427
5428 pci_set_drvdata(pci_dev, dev);
5429
5430 /* read the mac address */
5431 base = get_hwbase(dev);
5432 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5433 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5434
5435 /* check the workaround bit for correct mac address order */
5436 txreg = readl(base + NvRegTransmitPoll);
5437 if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5438 /* mac address is already in correct order */
5439 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5440 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5441 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5442 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5443 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5444 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5445 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5446 /* mac address is already in correct order */
5447 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5448 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5449 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5450 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5451 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5452 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5453 /*
5454 * Set orig mac address back to the reversed version.
5455 * This flag will be cleared during low power transition.
5456 * Therefore, we should always put back the reversed address.
5457 */
5458 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5459 (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5460 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5461 } else {
5462 /* need to reverse mac address to correct order */
5463 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5464 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5465 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5466 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5467 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5468 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
5469 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5470 dev_dbg(&pci_dev->dev,
5471 "%s: set workaround bit for reversed mac addr\n",
5472 __func__);
5473 }
5474 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5475
5476 if (!is_valid_ether_addr(dev->perm_addr)) {
5477 /*
5478 * Bad mac address. At least one bios sets the mac address
5479 * to 01:23:45:67:89:ab
5480 */
5481 dev_err(&pci_dev->dev,
5482 "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
5483 dev->dev_addr);
5484 random_ether_addr(dev->dev_addr);
5485 dev_err(&pci_dev->dev,
5486 "Using random MAC address: %pM\n", dev->dev_addr);
5487 }
5488
5489 /* set mac address */
5490 nv_copy_mac_to_hw(dev);
5491
5492 /* disable WOL */
5493 writel(0, base + NvRegWakeUpFlags);
5494 np->wolenabled = 0;
5495 device_set_wakeup_enable(&pci_dev->dev, false);
5496
5497 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5498
5499 /* take phy and nic out of low power mode */
5500 powerstate = readl(base + NvRegPowerState2);
5501 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5502 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5503 pci_dev->revision >= 0xA3)
5504 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5505 writel(powerstate, base + NvRegPowerState2);
5506 }
5507
5508 if (np->desc_ver == DESC_VER_1)
5509 np->tx_flags = NV_TX_VALID;
5510 else
5511 np->tx_flags = NV_TX2_VALID;
5512
5513 np->msi_flags = 0;
5514 if ((id->driver_data & DEV_HAS_MSI) && msi)
5515 np->msi_flags |= NV_MSI_CAPABLE;
5516
5517 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5518 /* msix has had reported issues when modifying irqmask
5519 as in the case of napi, therefore, disable for now
5520 */
5521 #if 0
5522 np->msi_flags |= NV_MSI_X_CAPABLE;
5523 #endif
5524 }
5525
5526 if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5527 np->irqmask = NVREG_IRQMASK_CPU;
5528 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5529 np->msi_flags |= 0x0001;
5530 } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5531 !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5532 /* start off in throughput mode */
5533 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5534 /* remove support for msix mode */
5535 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5536 } else {
5537 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5538 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5539 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5540 np->msi_flags |= 0x0003;
5541 }
5542
5543 if (id->driver_data & DEV_NEED_TIMERIRQ)
5544 np->irqmask |= NVREG_IRQ_TIMER;
5545 if (id->driver_data & DEV_NEED_LINKTIMER) {
5546 np->need_linktimer = 1;
5547 np->link_timeout = jiffies + LINK_TIMEOUT;
5548 } else {
5549 np->need_linktimer = 0;
5550 }
5551
5552 /* Limit the number of tx's outstanding for hw bug */
5553 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5554 np->tx_limit = 1;
5555 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
5556 pci_dev->revision >= 0xA2)
5557 np->tx_limit = 0;
5558 }
5559
5560 /* clear phy state and temporarily halt phy interrupts */
5561 writel(0, base + NvRegMIIMask);
5562 phystate = readl(base + NvRegAdapterControl);
5563 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5564 phystate_orig = 1;
5565 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5566 writel(phystate, base + NvRegAdapterControl);
5567 }
5568 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5569
5570 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5571 /* management unit running on the mac? */
5572 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5573 (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5574 nv_mgmt_acquire_sema(dev) &&
5575 nv_mgmt_get_version(dev)) {
5576 np->mac_in_use = 1;
5577 if (np->mgmt_version > 0)
5578 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5579 /* management unit setup the phy already? */
5580 if (np->mac_in_use &&
5581 ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5582 NVREG_XMITCTL_SYNC_PHY_INIT)) {
5583 /* phy is inited by mgmt unit */
5584 phyinitialized = 1;
5585 } else {
5586 /* we need to init the phy */
5587 }
5588 }
5589 }
5590
5591 /* find a suitable phy */
5592 for (i = 1; i <= 32; i++) {
5593 int id1, id2;
5594 int phyaddr = i & 0x1F;
5595
5596 spin_lock_irq(&np->lock);
5597 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5598 spin_unlock_irq(&np->lock);
5599 if (id1 < 0 || id1 == 0xffff)
5600 continue;
5601 spin_lock_irq(&np->lock);
5602 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5603 spin_unlock_irq(&np->lock);
5604 if (id2 < 0 || id2 == 0xffff)
5605 continue;
5606
5607 np->phy_model = id2 & PHYID2_MODEL_MASK;
5608 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5609 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5610 np->phyaddr = phyaddr;
5611 np->phy_oui = id1 | id2;
5612
5613 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5614 if (np->phy_oui == PHY_OUI_REALTEK2)
5615 np->phy_oui = PHY_OUI_REALTEK;
5616 /* Setup phy revision for Realtek */
5617 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5618 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5619
5620 break;
5621 }
5622 if (i == 33) {
5623 dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n");
5624 goto out_error;
5625 }
5626
5627 if (!phyinitialized) {
5628 /* reset it */
5629 phy_init(dev);
5630 } else {
5631 /* see if it is a gigabit phy */
5632 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5633 if (mii_status & PHY_GIGABIT)
5634 np->gigabit = PHY_GIGABIT;
5635 }
5636
5637 /* set default link speed settings */
5638 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5639 np->duplex = 0;
5640 np->autoneg = 1;
5641
5642 err = register_netdev(dev);
5643 if (err) {
5644 dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err);
5645 goto out_error;
5646 }
5647
5648 dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
5649 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
5650
5651 dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5652 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5653 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
5654 "csum " : "",
5655 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5656 "vlan " : "",
5657 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5658 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5659 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5660 np->gigabit == PHY_GIGABIT ? "gbit " : "",
5661 np->need_linktimer ? "lnktim " : "",
5662 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5663 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5664 np->desc_ver);
5665
5666 return 0;
5667
5668 out_error:
5669 if (phystate_orig)
5670 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5671 pci_set_drvdata(pci_dev, NULL);
5672 out_freering:
5673 free_rings(dev);
5674 out_unmap:
5675 iounmap(get_hwbase(dev));
5676 out_relreg:
5677 pci_release_regions(pci_dev);
5678 out_disable:
5679 pci_disable_device(pci_dev);
5680 out_free:
5681 free_netdev(dev);
5682 out:
5683 return err;
5684 }
5685
5686 static void nv_restore_phy(struct net_device *dev)
5687 {
5688 struct fe_priv *np = netdev_priv(dev);
5689 u16 phy_reserved, mii_control;
5690
5691 if (np->phy_oui == PHY_OUI_REALTEK &&
5692 np->phy_model == PHY_MODEL_REALTEK_8201 &&
5693 phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5694 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5695 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5696 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5697 phy_reserved |= PHY_REALTEK_INIT8;
5698 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5699 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5700
5701 /* restart auto negotiation */
5702 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5703 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5704 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5705 }
5706 }
5707
5708 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
5709 {
5710 struct net_device *dev = pci_get_drvdata(pci_dev);
5711 struct fe_priv *np = netdev_priv(dev);
5712 u8 __iomem *base = get_hwbase(dev);
5713
5714 /* special op: write back the misordered MAC address - otherwise
5715 * the next nv_probe would see a wrong address.
5716 */
5717 writel(np->orig_mac[0], base + NvRegMacAddrA);
5718 writel(np->orig_mac[1], base + NvRegMacAddrB);
5719 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5720 base + NvRegTransmitPoll);
5721 }
5722
5723 static void __devexit nv_remove(struct pci_dev *pci_dev)
5724 {
5725 struct net_device *dev = pci_get_drvdata(pci_dev);
5726
5727 unregister_netdev(dev);
5728
5729 nv_restore_mac_addr(pci_dev);
5730
5731 /* restore any phy related changes */
5732 nv_restore_phy(dev);
5733
5734 nv_mgmt_release_sema(dev);
5735
5736 /* free all structures */
5737 free_rings(dev);
5738 iounmap(get_hwbase(dev));
5739 pci_release_regions(pci_dev);
5740 pci_disable_device(pci_dev);
5741 free_netdev(dev);
5742 pci_set_drvdata(pci_dev, NULL);
5743 }
5744
5745 #ifdef CONFIG_PM
5746 static int nv_suspend(struct device *device)
5747 {
5748 struct pci_dev *pdev = to_pci_dev(device);
5749 struct net_device *dev = pci_get_drvdata(pdev);
5750 struct fe_priv *np = netdev_priv(dev);
5751 u8 __iomem *base = get_hwbase(dev);
5752 int i;
5753
5754 if (netif_running(dev)) {
5755 /* Gross. */
5756 nv_close(dev);
5757 }
5758 netif_device_detach(dev);
5759
5760 /* save non-pci configuration space */
5761 for (i = 0; i <= np->register_size/sizeof(u32); i++)
5762 np->saved_config_space[i] = readl(base + i*sizeof(u32));
5763
5764 return 0;
5765 }
5766
5767 static int nv_resume(struct device *device)
5768 {
5769 struct pci_dev *pdev = to_pci_dev(device);
5770 struct net_device *dev = pci_get_drvdata(pdev);
5771 struct fe_priv *np = netdev_priv(dev);
5772 u8 __iomem *base = get_hwbase(dev);
5773 int i, rc = 0;
5774
5775 /* restore non-pci configuration space */
5776 for (i = 0; i <= np->register_size/sizeof(u32); i++)
5777 writel(np->saved_config_space[i], base+i*sizeof(u32));
5778
5779 if (np->driver_data & DEV_NEED_MSI_FIX)
5780 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
5781
5782 /* restore phy state, including autoneg */
5783 phy_init(dev);
5784
5785 netif_device_attach(dev);
5786 if (netif_running(dev)) {
5787 rc = nv_open(dev);
5788 nv_set_multicast(dev);
5789 }
5790 return rc;
5791 }
5792
5793 static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
5794 #define NV_PM_OPS (&nv_pm_ops)
5795
5796 static void nv_shutdown(struct pci_dev *pdev)
5797 {
5798 struct net_device *dev = pci_get_drvdata(pdev);
5799 struct fe_priv *np = netdev_priv(dev);
5800
5801 if (netif_running(dev))
5802 nv_close(dev);
5803
5804 /*
5805 * Restore the MAC so a kernel started by kexec won't get confused.
5806 * If we really go for poweroff, we must not restore the MAC,
5807 * otherwise the MAC for WOL will be reversed at least on some boards.
5808 */
5809 if (system_state != SYSTEM_POWER_OFF)
5810 nv_restore_mac_addr(pdev);
5811
5812 pci_disable_device(pdev);
5813 /*
5814 * Apparently it is not possible to reinitialise from D3 hot,
5815 * only put the device into D3 if we really go for poweroff.
5816 */
5817 if (system_state == SYSTEM_POWER_OFF) {
5818 pci_wake_from_d3(pdev, np->wolenabled);
5819 pci_set_power_state(pdev, PCI_D3hot);
5820 }
5821 }
5822 #else
5823 #define NV_PM_OPS NULL
5824 #define nv_shutdown NULL
5825 #endif /* CONFIG_PM */
5826
5827 static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
5828 { /* nForce Ethernet Controller */
5829 PCI_DEVICE(0x10DE, 0x01C3),
5830 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5831 },
5832 { /* nForce2 Ethernet Controller */
5833 PCI_DEVICE(0x10DE, 0x0066),
5834 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5835 },
5836 { /* nForce3 Ethernet Controller */
5837 PCI_DEVICE(0x10DE, 0x00D6),
5838 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5839 },
5840 { /* nForce3 Ethernet Controller */
5841 PCI_DEVICE(0x10DE, 0x0086),
5842 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5843 },
5844 { /* nForce3 Ethernet Controller */
5845 PCI_DEVICE(0x10DE, 0x008C),
5846 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5847 },
5848 { /* nForce3 Ethernet Controller */
5849 PCI_DEVICE(0x10DE, 0x00E6),
5850 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5851 },
5852 { /* nForce3 Ethernet Controller */
5853 PCI_DEVICE(0x10DE, 0x00DF),
5854 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5855 },
5856 { /* CK804 Ethernet Controller */
5857 PCI_DEVICE(0x10DE, 0x0056),
5858 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5859 },
5860 { /* CK804 Ethernet Controller */
5861 PCI_DEVICE(0x10DE, 0x0057),
5862 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5863 },
5864 { /* MCP04 Ethernet Controller */
5865 PCI_DEVICE(0x10DE, 0x0037),
5866 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5867 },
5868 { /* MCP04 Ethernet Controller */
5869 PCI_DEVICE(0x10DE, 0x0038),
5870 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5871 },
5872 { /* MCP51 Ethernet Controller */
5873 PCI_DEVICE(0x10DE, 0x0268),
5874 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
5875 },
5876 { /* MCP51 Ethernet Controller */
5877 PCI_DEVICE(0x10DE, 0x0269),
5878 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
5879 },
5880 { /* MCP55 Ethernet Controller */
5881 PCI_DEVICE(0x10DE, 0x0372),
5882 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
5883 },
5884 { /* MCP55 Ethernet Controller */
5885 PCI_DEVICE(0x10DE, 0x0373),
5886 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
5887 },
5888 { /* MCP61 Ethernet Controller */
5889 PCI_DEVICE(0x10DE, 0x03E5),
5890 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5891 },
5892 { /* MCP61 Ethernet Controller */
5893 PCI_DEVICE(0x10DE, 0x03E6),
5894 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5895 },
5896 { /* MCP61 Ethernet Controller */
5897 PCI_DEVICE(0x10DE, 0x03EE),
5898 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5899 },
5900 { /* MCP61 Ethernet Controller */
5901 PCI_DEVICE(0x10DE, 0x03EF),
5902 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5903 },
5904 { /* MCP65 Ethernet Controller */
5905 PCI_DEVICE(0x10DE, 0x0450),
5906 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5907 },
5908 { /* MCP65 Ethernet Controller */
5909 PCI_DEVICE(0x10DE, 0x0451),
5910 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5911 },
5912 { /* MCP65 Ethernet Controller */
5913 PCI_DEVICE(0x10DE, 0x0452),
5914 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5915 },
5916 { /* MCP65 Ethernet Controller */
5917 PCI_DEVICE(0x10DE, 0x0453),
5918 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5919 },
5920 { /* MCP67 Ethernet Controller */
5921 PCI_DEVICE(0x10DE, 0x054C),
5922 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5923 },
5924 { /* MCP67 Ethernet Controller */
5925 PCI_DEVICE(0x10DE, 0x054D),
5926 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5927 },
5928 { /* MCP67 Ethernet Controller */
5929 PCI_DEVICE(0x10DE, 0x054E),
5930 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5931 },
5932 { /* MCP67 Ethernet Controller */
5933 PCI_DEVICE(0x10DE, 0x054F),
5934 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5935 },
5936 { /* MCP73 Ethernet Controller */
5937 PCI_DEVICE(0x10DE, 0x07DC),
5938 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5939 },
5940 { /* MCP73 Ethernet Controller */
5941 PCI_DEVICE(0x10DE, 0x07DD),
5942 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5943 },
5944 { /* MCP73 Ethernet Controller */
5945 PCI_DEVICE(0x10DE, 0x07DE),
5946 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5947 },
5948 { /* MCP73 Ethernet Controller */
5949 PCI_DEVICE(0x10DE, 0x07DF),
5950 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5951 },
5952 { /* MCP77 Ethernet Controller */
5953 PCI_DEVICE(0x10DE, 0x0760),
5954 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5955 },
5956 { /* MCP77 Ethernet Controller */
5957 PCI_DEVICE(0x10DE, 0x0761),
5958 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5959 },
5960 { /* MCP77 Ethernet Controller */
5961 PCI_DEVICE(0x10DE, 0x0762),
5962 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5963 },
5964 { /* MCP77 Ethernet Controller */
5965 PCI_DEVICE(0x10DE, 0x0763),
5966 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5967 },
5968 { /* MCP79 Ethernet Controller */
5969 PCI_DEVICE(0x10DE, 0x0AB0),
5970 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5971 },
5972 { /* MCP79 Ethernet Controller */
5973 PCI_DEVICE(0x10DE, 0x0AB1),
5974 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5975 },
5976 { /* MCP79 Ethernet Controller */
5977 PCI_DEVICE(0x10DE, 0x0AB2),
5978 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5979 },
5980 { /* MCP79 Ethernet Controller */
5981 PCI_DEVICE(0x10DE, 0x0AB3),
5982 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5983 },
5984 { /* MCP89 Ethernet Controller */
5985 PCI_DEVICE(0x10DE, 0x0D7D),
5986 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
5987 },
5988 {0,},
5989 };
5990
5991 static struct pci_driver driver = {
5992 .name = DRV_NAME,
5993 .id_table = pci_tbl,
5994 .probe = nv_probe,
5995 .remove = __devexit_p(nv_remove),
5996 .shutdown = nv_shutdown,
5997 .driver.pm = NV_PM_OPS,
5998 };
5999
6000 static int __init init_nic(void)
6001 {
6002 return pci_register_driver(&driver);
6003 }
6004
6005 static void __exit exit_nic(void)
6006 {
6007 pci_unregister_driver(&driver);
6008 }
6009
6010 module_param(max_interrupt_work, int, 0);
6011 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6012 module_param(optimization_mode, int, 0);
6013 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6014 module_param(poll_interval, int, 0);
6015 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6016 module_param(msi, int, 0);
6017 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6018 module_param(msix, int, 0);
6019 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6020 module_param(dma_64bit, int, 0);
6021 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6022 module_param(phy_cross, int, 0);
6023 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6024 module_param(phy_power_down, int, 0);
6025 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6026
6027 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6028 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6029 MODULE_LICENSE("GPL");
6030
6031 MODULE_DEVICE_TABLE(pci, pci_tbl);
6032
6033 module_init(init_nic);
6034 module_exit(exit_nic);
x86 "subsystem" repository