2 * RDC R6040 Fast Ethernet MAC support
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Florian Fainelli <florian@openwrt.org>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/version.h>
28 #include <linux/moduleparam.h>
29 #include <linux/string.h>
30 #include <linux/timer.h>
31 #include <linux/errno.h>
32 #include <linux/ioport.h>
33 #include <linux/slab.h>
34 #include <linux/interrupt.h>
35 #include <linux/pci.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/skbuff.h>
39 #include <linux/init.h>
40 #include <linux/delay.h>
41 #include <linux/mii.h>
42 #include <linux/ethtool.h>
43 #include <linux/crc32.h>
44 #include <linux/spinlock.h>
45 #include <linux/bitops.h>
47 #include <linux/irq.h>
48 #include <linux/uaccess.h>
50 #include <asm/processor.h>
52 #define DRV_NAME "r6040"
53 #define DRV_VERSION "0.16"
54 #define DRV_RELDATE "10Nov2007"
56 /* PHY CHIP Address */
57 #define PHY1_ADDR 1 /* For MAC1 */
58 #define PHY2_ADDR 2 /* For MAC2 */
59 #define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
60 #define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
62 /* Time in jiffies before concluding the transmitter is hung. */
63 #define TX_TIMEOUT (6000 * HZ / 1000)
65 /* RDC MAC I/O Size */
66 #define R6040_IO_SIZE 256
72 #define MCR0 0x00 /* Control register 0 */
73 #define MCR1 0x04 /* Control register 1 */
74 #define MAC_RST 0x0001 /* Reset the MAC */
75 #define MBCR 0x08 /* Bus control */
76 #define MT_ICR 0x0C /* TX interrupt control */
77 #define MR_ICR 0x10 /* RX interrupt control */
78 #define MTPR 0x14 /* TX poll command register */
79 #define MR_BSR 0x18 /* RX buffer size */
80 #define MR_DCR 0x1A /* RX descriptor control */
81 #define MLSR 0x1C /* Last status */
82 #define MMDIO 0x20 /* MDIO control register */
83 #define MDIO_WRITE 0x4000 /* MDIO write */
84 #define MDIO_READ 0x2000 /* MDIO read */
85 #define MMRD 0x24 /* MDIO read data register */
86 #define MMWD 0x28 /* MDIO write data register */
87 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
88 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
89 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
90 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
91 #define MISR 0x3C /* Status register */
92 #define MIER 0x40 /* INT enable register */
93 #define MSK_INT 0x0000 /* Mask off interrupts */
94 #define RX_FINISH 0x0001 /* RX finished */
95 #define RX_NO_DESC 0x0002 /* No RX descriptor available */
96 #define RX_FIFO_FULL 0x0004 /* RX FIFO full */
97 #define RX_EARLY 0x0008 /* RX early */
98 #define TX_FINISH 0x0010 /* TX finished */
99 #define TX_EARLY 0x0080 /* TX early */
100 #define EVENT_OVRFL 0x0100 /* Event counter overflow */
101 #define LINK_CHANGED 0x0200 /* PHY link changed */
102 #define ME_CISR 0x44 /* Event counter INT status */
103 #define ME_CIER 0x48 /* Event counter INT enable */
104 #define MR_CNT 0x50 /* Successfully received packet counter */
105 #define ME_CNT0 0x52 /* Event counter 0 */
106 #define ME_CNT1 0x54 /* Event counter 1 */
107 #define ME_CNT2 0x56 /* Event counter 2 */
108 #define ME_CNT3 0x58 /* Event counter 3 */
109 #define MT_CNT 0x5A /* Successfully transmit packet counter */
110 #define ME_CNT4 0x5C /* Event counter 4 */
111 #define MP_CNT 0x5E /* Pause frame counter register */
112 #define MAR0 0x60 /* Hash table 0 */
113 #define MAR1 0x62 /* Hash table 1 */
114 #define MAR2 0x64 /* Hash table 2 */
115 #define MAR3 0x66 /* Hash table 3 */
116 #define MID_0L 0x68 /* Multicast address MID0 Low */
117 #define MID_0M 0x6A /* Multicast address MID0 Medium */
118 #define MID_0H 0x6C /* Multicast address MID0 High */
119 #define MID_1L 0x70 /* MID1 Low */
120 #define MID_1M 0x72 /* MID1 Medium */
121 #define MID_1H 0x74 /* MID1 High */
122 #define MID_2L 0x78 /* MID2 Low */
123 #define MID_2M 0x7A /* MID2 Medium */
124 #define MID_2H 0x7C /* MID2 High */
125 #define MID_3L 0x80 /* MID3 Low */
126 #define MID_3M 0x82 /* MID3 Medium */
127 #define MID_3H 0x84 /* MID3 High */
128 #define PHY_CC 0x88 /* PHY status change configuration register */
129 #define PHY_ST 0x8A /* PHY status register */
130 #define MAC_SM 0xAC /* MAC status machine */
131 #define MAC_ID 0xBE /* Identifier register */
133 #define TX_DCNT 0x80 /* TX descriptor count */
134 #define RX_DCNT 0x80 /* RX descriptor count */
135 #define MAX_BUF_SIZE 0x600
136 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
137 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
138 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
139 #define MCAST_MAX 4 /* Max number multicast addresses to filter */
142 #define ICPLUS_PHY_ID 0x0243
144 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
145 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
146 "Florian Fainelli <florian@openwrt.org>");
147 MODULE_LICENSE("GPL");
148 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
150 /* RX and TX interrupts that we handle */
151 #define RX_INT (RX_FINISH)
152 #define TX_INT (TX_FINISH)
153 #define INT_MASK (RX_INT | TX_INT)
155 struct r6040_descriptor
{
156 u16 status
, len
; /* 0-3 */
157 __le32 buf
; /* 4-7 */
158 __le32 ndesc
; /* 8-B */
160 char *vbufp
; /* 10-13 */
161 struct r6040_descriptor
*vndescp
; /* 14-17 */
162 struct sk_buff
*skb_ptr
; /* 18-1B */
163 u32 rev2
; /* 1C-1F */
164 } __attribute__((aligned(32)));
166 struct r6040_private
{
167 spinlock_t lock
; /* driver lock */
168 struct timer_list timer
;
169 struct pci_dev
*pdev
;
170 struct r6040_descriptor
*rx_insert_ptr
;
171 struct r6040_descriptor
*rx_remove_ptr
;
172 struct r6040_descriptor
*tx_insert_ptr
;
173 struct r6040_descriptor
*tx_remove_ptr
;
174 struct r6040_descriptor
*rx_ring
;
175 struct r6040_descriptor
*tx_ring
;
176 dma_addr_t rx_ring_dma
;
177 dma_addr_t tx_ring_dma
;
178 u16 tx_free_desc
, rx_free_desc
, phy_addr
, phy_mode
;
181 struct net_device
*dev
;
182 struct mii_if_info mii_if
;
183 struct napi_struct napi
;
187 static char version
[] __devinitdata
= KERN_INFO DRV_NAME
188 ": RDC R6040 NAPI net driver,"
189 "version "DRV_VERSION
" (" DRV_RELDATE
")\n";
191 static int phy_table
[] = { PHY1_ADDR
, PHY2_ADDR
};
193 /* Read a word data from PHY Chip */
194 static int r6040_phy_read(void __iomem
*ioaddr
, int phy_addr
, int reg
)
199 iowrite16(MDIO_READ
+ reg
+ (phy_addr
<< 8), ioaddr
+ MMDIO
);
200 /* Wait for the read bit to be cleared */
202 cmd
= ioread16(ioaddr
+ MMDIO
);
207 return ioread16(ioaddr
+ MMRD
);
210 /* Write a word data from PHY Chip */
211 static void r6040_phy_write(void __iomem
*ioaddr
, int phy_addr
, int reg
, u16 val
)
216 iowrite16(val
, ioaddr
+ MMWD
);
217 /* Write the command to the MDIO bus */
218 iowrite16(MDIO_WRITE
+ reg
+ (phy_addr
<< 8), ioaddr
+ MMDIO
);
219 /* Wait for the write bit to be cleared */
221 cmd
= ioread16(ioaddr
+ MMDIO
);
222 if (cmd
& MDIO_WRITE
)
227 static int r6040_mdio_read(struct net_device
*dev
, int mii_id
, int reg
)
229 struct r6040_private
*lp
= netdev_priv(dev
);
230 void __iomem
*ioaddr
= lp
->base
;
232 return (r6040_phy_read(ioaddr
, lp
->phy_addr
, reg
));
235 static void r6040_mdio_write(struct net_device
*dev
, int mii_id
, int reg
, int val
)
237 struct r6040_private
*lp
= netdev_priv(dev
);
238 void __iomem
*ioaddr
= lp
->base
;
240 r6040_phy_write(ioaddr
, lp
->phy_addr
, reg
, val
);
243 static void r6040_free_txbufs(struct net_device
*dev
)
245 struct r6040_private
*lp
= netdev_priv(dev
);
248 for (i
= 0; i
< TX_DCNT
; i
++) {
249 if (lp
->tx_insert_ptr
->skb_ptr
) {
250 pci_unmap_single(lp
->pdev
,
251 le32_to_cpu(lp
->tx_insert_ptr
->buf
),
252 MAX_BUF_SIZE
, PCI_DMA_TODEVICE
);
253 dev_kfree_skb(lp
->tx_insert_ptr
->skb_ptr
);
254 lp
->rx_insert_ptr
->skb_ptr
= NULL
;
256 lp
->tx_insert_ptr
= lp
->tx_insert_ptr
->vndescp
;
260 static void r6040_free_rxbufs(struct net_device
*dev
)
262 struct r6040_private
*lp
= netdev_priv(dev
);
265 for (i
= 0; i
< RX_DCNT
; i
++) {
266 if (lp
->rx_insert_ptr
->skb_ptr
) {
267 pci_unmap_single(lp
->pdev
,
268 le32_to_cpu(lp
->rx_insert_ptr
->buf
),
269 MAX_BUF_SIZE
, PCI_DMA_FROMDEVICE
);
270 dev_kfree_skb(lp
->rx_insert_ptr
->skb_ptr
);
271 lp
->rx_insert_ptr
->skb_ptr
= NULL
;
273 lp
->rx_insert_ptr
= lp
->rx_insert_ptr
->vndescp
;
277 static void r6040_init_ring_desc(struct r6040_descriptor
*desc_ring
,
278 dma_addr_t desc_dma
, int size
)
280 struct r6040_descriptor
*desc
= desc_ring
;
281 dma_addr_t mapping
= desc_dma
;
284 mapping
+= sizeof(*desc
);
285 desc
->ndesc
= cpu_to_le32(mapping
);
286 desc
->vndescp
= desc
+ 1;
290 desc
->ndesc
= cpu_to_le32(desc_dma
);
291 desc
->vndescp
= desc_ring
;
294 /* Allocate skb buffer for rx descriptor */
295 static void r6040_rx_buf_alloc(struct r6040_private
*lp
, struct net_device
*dev
)
297 struct r6040_descriptor
*descptr
;
299 descptr
= lp
->rx_insert_ptr
;
300 while (lp
->rx_free_desc
< RX_DCNT
) {
301 descptr
->skb_ptr
= netdev_alloc_skb(dev
, MAX_BUF_SIZE
);
303 if (!descptr
->skb_ptr
)
305 descptr
->buf
= cpu_to_le32(pci_map_single(lp
->pdev
,
306 descptr
->skb_ptr
->data
,
307 MAX_BUF_SIZE
, PCI_DMA_FROMDEVICE
));
308 descptr
->status
= 0x8000;
309 descptr
= descptr
->vndescp
;
312 lp
->rx_insert_ptr
= descptr
;
315 static void r6040_init_txbufs(struct net_device
*dev
)
317 struct r6040_private
*lp
= netdev_priv(dev
);
319 lp
->tx_free_desc
= TX_DCNT
;
321 lp
->tx_remove_ptr
= lp
->tx_insert_ptr
= lp
->tx_ring
;
322 r6040_init_ring_desc(lp
->tx_ring
, lp
->tx_ring_dma
, TX_DCNT
);
325 static int r6040_alloc_rxbufs(struct net_device
*dev
)
327 struct r6040_private
*lp
= netdev_priv(dev
);
328 struct r6040_descriptor
*desc
;
332 lp
->rx_remove_ptr
= lp
->rx_insert_ptr
= lp
->rx_ring
;
333 r6040_init_ring_desc(lp
->rx_ring
, lp
->rx_ring_dma
, RX_DCNT
);
335 /* Allocate skbs for the rx descriptors */
338 skb
= netdev_alloc_skb(dev
, MAX_BUF_SIZE
);
340 printk(KERN_ERR
"%s: failed to alloc skb for rx\n", dev
->name
);
345 desc
->buf
= cpu_to_le32(pci_map_single(lp
->pdev
,
347 MAX_BUF_SIZE
, PCI_DMA_FROMDEVICE
));
348 desc
->status
= 0x8000;
349 desc
= desc
->vndescp
;
350 } while (desc
!= lp
->rx_ring
);
355 /* Deallocate all previously allocated skbs */
356 r6040_free_rxbufs(dev
);
360 static void r6040_init_mac_regs(struct net_device
*dev
)
362 struct r6040_private
*lp
= netdev_priv(dev
);
363 void __iomem
*ioaddr
= lp
->base
;
367 /* Mask Off Interrupt */
368 iowrite16(MSK_INT
, ioaddr
+ MIER
);
371 iowrite16(MAC_RST
, ioaddr
+ MCR1
);
373 cmd
= ioread16(ioaddr
+ MCR1
);
377 /* Reset internal state machine */
378 iowrite16(2, ioaddr
+ MAC_SM
);
379 iowrite16(0, ioaddr
+ MAC_SM
);
382 /* MAC Bus Control Register */
383 iowrite16(MBCR_DEFAULT
, ioaddr
+ MBCR
);
385 /* Buffer Size Register */
386 iowrite16(MAX_BUF_SIZE
, ioaddr
+ MR_BSR
);
388 /* Write TX ring start address */
389 iowrite16(lp
->tx_ring_dma
, ioaddr
+ MTD_SA0
);
390 iowrite16(lp
->tx_ring_dma
>> 16, ioaddr
+ MTD_SA1
);
392 /* Write RX ring start address */
393 iowrite16(lp
->rx_ring_dma
, ioaddr
+ MRD_SA0
);
394 iowrite16(lp
->rx_ring_dma
>> 16, ioaddr
+ MRD_SA1
);
396 /* Set interrupt waiting time and packet numbers */
397 iowrite16(0x0F06, ioaddr
+ MT_ICR
);
398 iowrite16(0x0F06, ioaddr
+ MR_ICR
);
400 /* Enable interrupts */
401 iowrite16(INT_MASK
, ioaddr
+ MIER
);
403 /* Enable TX and RX */
404 iowrite16(lp
->mcr0
| 0x0002, ioaddr
);
406 /* Let TX poll the descriptors
407 * we may got called by r6040_tx_timeout which has left
408 * some unsent tx buffers */
409 iowrite16(0x01, ioaddr
+ MTPR
);
412 static void r6040_tx_timeout(struct net_device
*dev
)
414 struct r6040_private
*priv
= netdev_priv(dev
);
415 void __iomem
*ioaddr
= priv
->base
;
417 printk(KERN_WARNING
"%s: transmit timed out, int enable %4.4x "
418 "status %4.4x, PHY status %4.4x\n",
419 dev
->name
, ioread16(ioaddr
+ MIER
),
420 ioread16(ioaddr
+ MISR
),
421 r6040_mdio_read(dev
, priv
->mii_if
.phy_id
, MII_BMSR
));
423 dev
->stats
.tx_errors
++;
425 /* Reset MAC and re-init all registers */
426 r6040_init_mac_regs(dev
);
429 static struct net_device_stats
*r6040_get_stats(struct net_device
*dev
)
431 struct r6040_private
*priv
= netdev_priv(dev
);
432 void __iomem
*ioaddr
= priv
->base
;
435 spin_lock_irqsave(&priv
->lock
, flags
);
436 dev
->stats
.rx_crc_errors
+= ioread8(ioaddr
+ ME_CNT1
);
437 dev
->stats
.multicast
+= ioread8(ioaddr
+ ME_CNT0
);
438 spin_unlock_irqrestore(&priv
->lock
, flags
);
443 /* Stop RDC MAC and Free the allocated resource */
444 static void r6040_down(struct net_device
*dev
)
446 struct r6040_private
*lp
= netdev_priv(dev
);
447 void __iomem
*ioaddr
= lp
->base
;
448 struct pci_dev
*pdev
= lp
->pdev
;
454 iowrite16(MSK_INT
, ioaddr
+ MIER
); /* Mask Off Interrupt */
455 iowrite16(MAC_RST
, ioaddr
+ MCR1
); /* Reset RDC MAC */
457 cmd
= ioread16(ioaddr
+ MCR1
);
462 /* Restore MAC Address to MIDx */
463 adrp
= (u16
*) dev
->dev_addr
;
464 iowrite16(adrp
[0], ioaddr
+ MID_0L
);
465 iowrite16(adrp
[1], ioaddr
+ MID_0M
);
466 iowrite16(adrp
[2], ioaddr
+ MID_0H
);
467 free_irq(dev
->irq
, dev
);
470 r6040_free_rxbufs(dev
);
473 r6040_free_txbufs(dev
);
475 /* Free Descriptor memory */
476 pci_free_consistent(pdev
, RX_DESC_SIZE
, lp
->rx_ring
, lp
->rx_ring_dma
);
477 pci_free_consistent(pdev
, TX_DESC_SIZE
, lp
->tx_ring
, lp
->tx_ring_dma
);
480 static int r6040_close(struct net_device
*dev
)
482 struct r6040_private
*lp
= netdev_priv(dev
);
485 del_timer_sync(&lp
->timer
);
487 spin_lock_irq(&lp
->lock
);
488 netif_stop_queue(dev
);
490 spin_unlock_irq(&lp
->lock
);
495 /* Status of PHY CHIP */
496 static int r6040_phy_mode_chk(struct net_device
*dev
)
498 struct r6040_private
*lp
= netdev_priv(dev
);
499 void __iomem
*ioaddr
= lp
->base
;
502 /* PHY Link Status Check */
503 phy_dat
= r6040_phy_read(ioaddr
, lp
->phy_addr
, 1);
504 if (!(phy_dat
& 0x4))
505 phy_dat
= 0x8000; /* Link Failed, full duplex */
507 /* PHY Chip Auto-Negotiation Status */
508 phy_dat
= r6040_phy_read(ioaddr
, lp
->phy_addr
, 1);
509 if (phy_dat
& 0x0020) {
510 /* Auto Negotiation Mode */
511 phy_dat
= r6040_phy_read(ioaddr
, lp
->phy_addr
, 5);
512 phy_dat
&= r6040_phy_read(ioaddr
, lp
->phy_addr
, 4);
514 /* Force full duplex */
520 phy_dat
= r6040_phy_read(ioaddr
, lp
->phy_addr
, 0);
530 static void r6040_set_carrier(struct mii_if_info
*mii
)
532 if (r6040_phy_mode_chk(mii
->dev
)) {
533 /* autoneg is off: Link is always assumed to be up */
534 if (!netif_carrier_ok(mii
->dev
))
535 netif_carrier_on(mii
->dev
);
537 r6040_phy_mode_chk(mii
->dev
);
540 static int r6040_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
542 struct r6040_private
*lp
= netdev_priv(dev
);
543 struct mii_ioctl_data
*data
= if_mii(rq
);
546 if (!netif_running(dev
))
548 spin_lock_irq(&lp
->lock
);
549 rc
= generic_mii_ioctl(&lp
->mii_if
, data
, cmd
, NULL
);
550 spin_unlock_irq(&lp
->lock
);
551 r6040_set_carrier(&lp
->mii_if
);
555 static int r6040_rx(struct net_device
*dev
, int limit
)
557 struct r6040_private
*priv
= netdev_priv(dev
);
559 void __iomem
*ioaddr
= priv
->base
;
562 for (count
= 0; count
< limit
; ++count
) {
563 struct r6040_descriptor
*descptr
= priv
->rx_remove_ptr
;
564 struct sk_buff
*skb_ptr
;
566 descptr
= priv
->rx_remove_ptr
;
568 /* Check for errors */
569 err
= ioread16(ioaddr
+ MLSR
);
571 dev
->stats
.rx_errors
++;
572 /* RX FIFO over-run */
574 dev
->stats
.rx_fifo_errors
++;
575 /* RX descriptor unavailable */
577 dev
->stats
.rx_frame_errors
++;
578 /* Received packet with length over buffer lenght */
580 dev
->stats
.rx_over_errors
++;
581 /* Received packet with too long or short */
582 if (err
& (0x0010 | 0x0008))
583 dev
->stats
.rx_length_errors
++;
584 /* Received packet with CRC errors */
586 spin_lock(&priv
->lock
);
587 dev
->stats
.rx_crc_errors
++;
588 spin_unlock(&priv
->lock
);
591 while (priv
->rx_free_desc
) {
593 if (descptr
->status
& 0x8000)
595 skb_ptr
= descptr
->skb_ptr
;
597 printk(KERN_ERR
"%s: Inconsistent RX"
598 "descriptor chain\n",
602 descptr
->skb_ptr
= NULL
;
603 skb_ptr
->dev
= priv
->dev
;
604 /* Do not count the CRC */
605 skb_put(skb_ptr
, descptr
->len
- 4);
606 pci_unmap_single(priv
->pdev
, le32_to_cpu(descptr
->buf
),
607 MAX_BUF_SIZE
, PCI_DMA_FROMDEVICE
);
608 skb_ptr
->protocol
= eth_type_trans(skb_ptr
, priv
->dev
);
609 /* Send to upper layer */
610 netif_receive_skb(skb_ptr
);
611 dev
->last_rx
= jiffies
;
612 dev
->stats
.rx_packets
++;
613 dev
->stats
.rx_bytes
+= descptr
->len
;
614 /* To next descriptor */
615 descptr
= descptr
->vndescp
;
616 priv
->rx_free_desc
--;
618 priv
->rx_remove_ptr
= descptr
;
620 /* Allocate new RX buffer */
621 if (priv
->rx_free_desc
< RX_DCNT
)
622 r6040_rx_buf_alloc(priv
, priv
->dev
);
627 static void r6040_tx(struct net_device
*dev
)
629 struct r6040_private
*priv
= netdev_priv(dev
);
630 struct r6040_descriptor
*descptr
;
631 void __iomem
*ioaddr
= priv
->base
;
632 struct sk_buff
*skb_ptr
;
635 spin_lock(&priv
->lock
);
636 descptr
= priv
->tx_remove_ptr
;
637 while (priv
->tx_free_desc
< TX_DCNT
) {
638 /* Check for errors */
639 err
= ioread16(ioaddr
+ MLSR
);
642 dev
->stats
.rx_fifo_errors
++;
643 if (err
& (0x2000 | 0x4000))
644 dev
->stats
.tx_carrier_errors
++;
646 if (descptr
->status
& 0x8000)
647 break; /* Not complete */
648 skb_ptr
= descptr
->skb_ptr
;
649 pci_unmap_single(priv
->pdev
, le32_to_cpu(descptr
->buf
),
650 skb_ptr
->len
, PCI_DMA_TODEVICE
);
652 dev_kfree_skb_irq(skb_ptr
);
653 descptr
->skb_ptr
= NULL
;
654 /* To next descriptor */
655 descptr
= descptr
->vndescp
;
656 priv
->tx_free_desc
++;
658 priv
->tx_remove_ptr
= descptr
;
660 if (priv
->tx_free_desc
)
661 netif_wake_queue(dev
);
662 spin_unlock(&priv
->lock
);
665 static int r6040_poll(struct napi_struct
*napi
, int budget
)
667 struct r6040_private
*priv
=
668 container_of(napi
, struct r6040_private
, napi
);
669 struct net_device
*dev
= priv
->dev
;
670 void __iomem
*ioaddr
= priv
->base
;
673 work_done
= r6040_rx(dev
, budget
);
675 if (work_done
< budget
) {
676 netif_rx_complete(dev
, napi
);
677 /* Enable RX interrupt */
678 iowrite16(ioread16(ioaddr
+ MIER
) | RX_INT
, ioaddr
+ MIER
);
683 /* The RDC interrupt handler. */
684 static irqreturn_t
r6040_interrupt(int irq
, void *dev_id
)
686 struct net_device
*dev
= dev_id
;
687 struct r6040_private
*lp
= netdev_priv(dev
);
688 void __iomem
*ioaddr
= lp
->base
;
691 /* Mask off RDC MAC interrupt */
692 iowrite16(MSK_INT
, ioaddr
+ MIER
);
693 /* Read MISR status and clear */
694 status
= ioread16(ioaddr
+ MISR
);
696 if (status
== 0x0000 || status
== 0xffff)
699 /* RX interrupt request */
701 /* Mask off RX interrupt */
702 iowrite16(ioread16(ioaddr
+ MIER
) & ~RX_INT
, ioaddr
+ MIER
);
703 netif_rx_schedule(dev
, &lp
->napi
);
706 /* TX interrupt request */
713 #ifdef CONFIG_NET_POLL_CONTROLLER
714 static void r6040_poll_controller(struct net_device
*dev
)
716 disable_irq(dev
->irq
);
717 r6040_interrupt(dev
->irq
, dev
);
718 enable_irq(dev
->irq
);
723 static int r6040_up(struct net_device
*dev
)
725 struct r6040_private
*lp
= netdev_priv(dev
);
726 void __iomem
*ioaddr
= lp
->base
;
729 /* Initialise and alloc RX/TX buffers */
730 r6040_init_txbufs(dev
);
731 ret
= r6040_alloc_rxbufs(dev
);
735 /* Read the PHY ID */
736 lp
->switch_sig
= r6040_phy_read(ioaddr
, 0, 2);
738 if (lp
->switch_sig
== ICPLUS_PHY_ID
) {
739 r6040_phy_write(ioaddr
, 29, 31, 0x175C); /* Enable registers */
740 lp
->phy_mode
= 0x8000;
743 r6040_phy_write(ioaddr
, lp
->phy_addr
, 4, PHY_CAP
);
744 r6040_phy_write(ioaddr
, lp
->phy_addr
, 0, PHY_MODE
);
746 if (PHY_MODE
== 0x3100)
747 lp
->phy_mode
= r6040_phy_mode_chk(dev
);
749 lp
->phy_mode
= (PHY_MODE
& 0x0100) ? 0x8000:0x0;
752 /* Set duplex mode */
753 lp
->mcr0
|= lp
->phy_mode
;
755 /* improve performance (by RDC guys) */
756 r6040_phy_write(ioaddr
, 30, 17, (r6040_phy_read(ioaddr
, 30, 17) | 0x4000));
757 r6040_phy_write(ioaddr
, 30, 17, ~((~r6040_phy_read(ioaddr
, 30, 17)) | 0x2000));
758 r6040_phy_write(ioaddr
, 0, 19, 0x0000);
759 r6040_phy_write(ioaddr
, 0, 30, 0x01F0);
761 /* Initialize all MAC registers */
762 r6040_init_mac_regs(dev
);
768 A periodic timer routine
769 Polling PHY Chip Link Status
771 static void r6040_timer(unsigned long data
)
773 struct net_device
*dev
= (struct net_device
*)data
;
774 struct r6040_private
*lp
= netdev_priv(dev
);
775 void __iomem
*ioaddr
= lp
->base
;
778 /* Polling PHY Chip Status */
779 if (PHY_MODE
== 0x3100)
780 phy_mode
= r6040_phy_mode_chk(dev
);
782 phy_mode
= (PHY_MODE
& 0x0100) ? 0x8000:0x0;
784 if (phy_mode
!= lp
->phy_mode
) {
785 lp
->phy_mode
= phy_mode
;
786 lp
->mcr0
= (lp
->mcr0
& 0x7fff) | phy_mode
;
787 iowrite16(lp
->mcr0
, ioaddr
);
788 printk(KERN_INFO
"Link Change %x \n", ioread16(ioaddr
));
791 /* Timer active again */
792 mod_timer(&lp
->timer
, round_jiffies(jiffies
+ HZ
));
795 /* Read/set MAC address routines */
796 static void r6040_mac_address(struct net_device
*dev
)
798 struct r6040_private
*lp
= netdev_priv(dev
);
799 void __iomem
*ioaddr
= lp
->base
;
802 /* MAC operation register */
803 iowrite16(0x01, ioaddr
+ MCR1
); /* Reset MAC */
804 iowrite16(2, ioaddr
+ MAC_SM
); /* Reset internal state machine */
805 iowrite16(0, ioaddr
+ MAC_SM
);
808 /* Restore MAC Address */
809 adrp
= (u16
*) dev
->dev_addr
;
810 iowrite16(adrp
[0], ioaddr
+ MID_0L
);
811 iowrite16(adrp
[1], ioaddr
+ MID_0M
);
812 iowrite16(adrp
[2], ioaddr
+ MID_0H
);
815 static int r6040_open(struct net_device
*dev
)
817 struct r6040_private
*lp
= netdev_priv(dev
);
820 /* Request IRQ and Register interrupt handler */
821 ret
= request_irq(dev
->irq
, &r6040_interrupt
,
822 IRQF_SHARED
, dev
->name
, dev
);
826 /* Set MAC address */
827 r6040_mac_address(dev
);
829 /* Allocate Descriptor memory */
831 pci_alloc_consistent(lp
->pdev
, RX_DESC_SIZE
, &lp
->rx_ring_dma
);
836 pci_alloc_consistent(lp
->pdev
, TX_DESC_SIZE
, &lp
->tx_ring_dma
);
838 pci_free_consistent(lp
->pdev
, RX_DESC_SIZE
, lp
->rx_ring
,
845 pci_free_consistent(lp
->pdev
, TX_DESC_SIZE
, lp
->tx_ring
,
847 pci_free_consistent(lp
->pdev
, RX_DESC_SIZE
, lp
->rx_ring
,
852 napi_enable(&lp
->napi
);
853 netif_start_queue(dev
);
855 /* set and active a timer process */
856 setup_timer(&lp
->timer
, r6040_timer
, (unsigned long) dev
);
857 if (lp
->switch_sig
!= ICPLUS_PHY_ID
)
858 mod_timer(&lp
->timer
, jiffies
+ HZ
);
862 static int r6040_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
864 struct r6040_private
*lp
= netdev_priv(dev
);
865 struct r6040_descriptor
*descptr
;
866 void __iomem
*ioaddr
= lp
->base
;
868 int ret
= NETDEV_TX_OK
;
870 /* Critical Section */
871 spin_lock_irqsave(&lp
->lock
, flags
);
873 /* TX resource check */
874 if (!lp
->tx_free_desc
) {
875 spin_unlock_irqrestore(&lp
->lock
, flags
);
876 netif_stop_queue(dev
);
877 printk(KERN_ERR DRV_NAME
": no tx descriptor\n");
878 ret
= NETDEV_TX_BUSY
;
882 /* Statistic Counter */
883 dev
->stats
.tx_packets
++;
884 dev
->stats
.tx_bytes
+= skb
->len
;
885 /* Set TX descriptor & Transmit it */
887 descptr
= lp
->tx_insert_ptr
;
891 descptr
->len
= skb
->len
;
893 descptr
->skb_ptr
= skb
;
894 descptr
->buf
= cpu_to_le32(pci_map_single(lp
->pdev
,
895 skb
->data
, skb
->len
, PCI_DMA_TODEVICE
));
896 descptr
->status
= 0x8000;
897 /* Trigger the MAC to check the TX descriptor */
898 iowrite16(0x01, ioaddr
+ MTPR
);
899 lp
->tx_insert_ptr
= descptr
->vndescp
;
901 /* If no tx resource, stop */
902 if (!lp
->tx_free_desc
)
903 netif_stop_queue(dev
);
905 dev
->trans_start
= jiffies
;
906 spin_unlock_irqrestore(&lp
->lock
, flags
);
910 static void r6040_multicast_list(struct net_device
*dev
)
912 struct r6040_private
*lp
= netdev_priv(dev
);
913 void __iomem
*ioaddr
= lp
->base
;
917 struct dev_mc_list
*dmi
= dev
->mc_list
;
921 adrp
= (u16
*)dev
->dev_addr
;
922 iowrite16(adrp
[0], ioaddr
+ MID_0L
);
923 iowrite16(adrp
[1], ioaddr
+ MID_0M
);
924 iowrite16(adrp
[2], ioaddr
+ MID_0H
);
926 /* Promiscous Mode */
927 spin_lock_irqsave(&lp
->lock
, flags
);
929 /* Clear AMCP & PROM bits */
930 reg
= ioread16(ioaddr
) & ~0x0120;
931 if (dev
->flags
& IFF_PROMISC
) {
935 /* Too many multicast addresses
936 * accept all traffic */
937 else if ((dev
->mc_count
> MCAST_MAX
)
938 || (dev
->flags
& IFF_ALLMULTI
))
941 iowrite16(reg
, ioaddr
);
942 spin_unlock_irqrestore(&lp
->lock
, flags
);
944 /* Build the hash table */
945 if (dev
->mc_count
> MCAST_MAX
) {
949 for (i
= 0; i
< 4; i
++)
952 for (i
= 0; i
< dev
->mc_count
; i
++) {
953 char *addrs
= dmi
->dmi_addr
;
960 crc
= ether_crc_le(6, addrs
);
962 hash_table
[crc
>> 4] |= 1 << (15 - (crc
& 0xf));
964 /* Write the index of the hash table */
965 for (i
= 0; i
< 4; i
++)
966 iowrite16(hash_table
[i
] << 14, ioaddr
+ MCR1
);
967 /* Fill the MAC hash tables with their values */
968 iowrite16(hash_table
[0], ioaddr
+ MAR0
);
969 iowrite16(hash_table
[1], ioaddr
+ MAR1
);
970 iowrite16(hash_table
[2], ioaddr
+ MAR2
);
971 iowrite16(hash_table
[3], ioaddr
+ MAR3
);
973 /* Multicast Address 1~4 case */
974 for (i
= 0, dmi
; (i
< dev
->mc_count
) && (i
< MCAST_MAX
); i
++) {
975 adrp
= (u16
*)dmi
->dmi_addr
;
976 iowrite16(adrp
[0], ioaddr
+ MID_1L
+ 8*i
);
977 iowrite16(adrp
[1], ioaddr
+ MID_1M
+ 8*i
);
978 iowrite16(adrp
[2], ioaddr
+ MID_1H
+ 8*i
);
981 for (i
= dev
->mc_count
; i
< MCAST_MAX
; i
++) {
982 iowrite16(0xffff, ioaddr
+ MID_0L
+ 8*i
);
983 iowrite16(0xffff, ioaddr
+ MID_0M
+ 8*i
);
984 iowrite16(0xffff, ioaddr
+ MID_0H
+ 8*i
);
988 static void netdev_get_drvinfo(struct net_device
*dev
,
989 struct ethtool_drvinfo
*info
)
991 struct r6040_private
*rp
= netdev_priv(dev
);
993 strcpy(info
->driver
, DRV_NAME
);
994 strcpy(info
->version
, DRV_VERSION
);
995 strcpy(info
->bus_info
, pci_name(rp
->pdev
));
998 static int netdev_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1000 struct r6040_private
*rp
= netdev_priv(dev
);
1003 spin_lock_irq(&rp
->lock
);
1004 rc
= mii_ethtool_gset(&rp
->mii_if
, cmd
);
1005 spin_unlock_irq(&rp
->lock
);
1010 static int netdev_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1012 struct r6040_private
*rp
= netdev_priv(dev
);
1015 spin_lock_irq(&rp
->lock
);
1016 rc
= mii_ethtool_sset(&rp
->mii_if
, cmd
);
1017 spin_unlock_irq(&rp
->lock
);
1018 r6040_set_carrier(&rp
->mii_if
);
1023 static u32
netdev_get_link(struct net_device
*dev
)
1025 struct r6040_private
*rp
= netdev_priv(dev
);
1027 return mii_link_ok(&rp
->mii_if
);
1030 static struct ethtool_ops netdev_ethtool_ops
= {
1031 .get_drvinfo
= netdev_get_drvinfo
,
1032 .get_settings
= netdev_get_settings
,
1033 .set_settings
= netdev_set_settings
,
1034 .get_link
= netdev_get_link
,
1037 static int __devinit
r6040_init_one(struct pci_dev
*pdev
,
1038 const struct pci_device_id
*ent
)
1040 struct net_device
*dev
;
1041 struct r6040_private
*lp
;
1042 void __iomem
*ioaddr
;
1043 int err
, io_size
= R6040_IO_SIZE
;
1044 static int card_idx
= -1;
1049 printk(KERN_INFO
"%s\n", version
);
1051 err
= pci_enable_device(pdev
);
1055 /* this should always be supported */
1056 if (pci_set_dma_mask(pdev
, DMA_32BIT_MASK
)) {
1057 printk(KERN_ERR DRV_NAME
"32-bit PCI DMA addresses"
1058 "not supported by the card\n");
1061 if (pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
)) {
1062 printk(KERN_ERR DRV_NAME
"32-bit PCI DMA addresses"
1063 "not supported by the card\n");
1068 if (pci_resource_len(pdev
, 0) < io_size
) {
1069 printk(KERN_ERR
"Insufficient PCI resources, aborting\n");
1073 pioaddr
= pci_resource_start(pdev
, 0); /* IO map base address */
1074 pci_set_master(pdev
);
1076 dev
= alloc_etherdev(sizeof(struct r6040_private
));
1078 printk(KERN_ERR
"Failed to allocate etherdev\n");
1081 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1082 lp
= netdev_priv(dev
);
1086 if (pci_request_regions(pdev
, DRV_NAME
)) {
1087 printk(KERN_ERR DRV_NAME
": Failed to request PCI regions\n");
1089 goto err_out_disable
;
1092 ioaddr
= pci_iomap(pdev
, bar
, io_size
);
1094 printk(KERN_ERR
"ioremap failed for device %s\n",
1099 /* Init system & device */
1101 dev
->irq
= pdev
->irq
;
1103 spin_lock_init(&lp
->lock
);
1104 pci_set_drvdata(pdev
, dev
);
1106 /* Set MAC address */
1109 adrp
= (u16
*)dev
->dev_addr
;
1110 adrp
[0] = ioread16(ioaddr
+ MID_0L
);
1111 adrp
[1] = ioread16(ioaddr
+ MID_0M
);
1112 adrp
[2] = ioread16(ioaddr
+ MID_0H
);
1114 /* Link new device into r6040_root_dev */
1117 /* Init RDC private data */
1119 lp
->phy_addr
= phy_table
[card_idx
];
1122 /* The RDC-specific entries in the device structure. */
1123 dev
->open
= &r6040_open
;
1124 dev
->hard_start_xmit
= &r6040_start_xmit
;
1125 dev
->stop
= &r6040_close
;
1126 dev
->get_stats
= r6040_get_stats
;
1127 dev
->set_multicast_list
= &r6040_multicast_list
;
1128 dev
->do_ioctl
= &r6040_ioctl
;
1129 dev
->ethtool_ops
= &netdev_ethtool_ops
;
1130 dev
->tx_timeout
= &r6040_tx_timeout
;
1131 dev
->watchdog_timeo
= TX_TIMEOUT
;
1132 #ifdef CONFIG_NET_POLL_CONTROLLER
1133 dev
->poll_controller
= r6040_poll_controller
;
1135 netif_napi_add(dev
, &lp
->napi
, r6040_poll
, 64);
1136 lp
->mii_if
.dev
= dev
;
1137 lp
->mii_if
.mdio_read
= r6040_mdio_read
;
1138 lp
->mii_if
.mdio_write
= r6040_mdio_write
;
1139 lp
->mii_if
.phy_id
= lp
->phy_addr
;
1140 lp
->mii_if
.phy_id_mask
= 0x1f;
1141 lp
->mii_if
.reg_num_mask
= 0x1f;
1143 /* Register net device. After this dev->name assign */
1144 err
= register_netdev(dev
);
1146 printk(KERN_ERR DRV_NAME
": Failed to register net device\n");
1152 pci_release_regions(pdev
);
1154 pci_disable_device(pdev
);
1155 pci_set_drvdata(pdev
, NULL
);
1161 static void __devexit
r6040_remove_one(struct pci_dev
*pdev
)
1163 struct net_device
*dev
= pci_get_drvdata(pdev
);
1165 unregister_netdev(dev
);
1166 pci_release_regions(pdev
);
1168 pci_disable_device(pdev
);
1169 pci_set_drvdata(pdev
, NULL
);
1173 static struct pci_device_id r6040_pci_tbl
[] = {
1174 { PCI_DEVICE(PCI_VENDOR_ID_RDC
, 0x6040) },
1177 MODULE_DEVICE_TABLE(pci
, r6040_pci_tbl
);
1179 static struct pci_driver r6040_driver
= {
1181 .id_table
= r6040_pci_tbl
,
1182 .probe
= r6040_init_one
,
1183 .remove
= __devexit_p(r6040_remove_one
),
1187 static int __init
r6040_init(void)
1189 return pci_register_driver(&r6040_driver
);
1193 static void __exit
r6040_cleanup(void)
1195 pci_unregister_driver(&r6040_driver
);
1198 module_init(r6040_init
);
1199 module_exit(r6040_cleanup
);