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switch fat to ->s_d_op, close exportfs races there
[linux-2.6/x86.git] / arch / arm / mach-s5pv310 / clock.c
blob58c9d33f36fec8caef7150a929e94800f97b8b04
1 /* linux/arch/arm/mach-s5pv310/clock.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/err.h>
15 #include <linux/io.h>
16
17 #include <plat/cpu-freq.h>
18 #include <plat/clock.h>
19 #include <plat/cpu.h>
20 #include <plat/pll.h>
21 #include <plat/s5p-clock.h>
22 #include <plat/clock-clksrc.h>
23
24 #include <mach/map.h>
25 #include <mach/regs-clock.h>
26
27 static struct clk clk_sclk_hdmi27m = {
28 .name = "sclk_hdmi27m",
29 .id = -1,
30 .rate = 27000000,
31 };
32
33 static struct clk clk_sclk_hdmiphy = {
34 .name = "sclk_hdmiphy",
35 .id = -1,
36 };
37
38 static struct clk clk_sclk_usbphy0 = {
39 .name = "sclk_usbphy0",
40 .id = -1,
41 .rate = 27000000,
42 };
43
44 static struct clk clk_sclk_usbphy1 = {
45 .name = "sclk_usbphy1",
46 .id = -1,
47 };
48
49 static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable)
50 {
51 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
52 }
53
54 static int s5pv310_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
55 {
56 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
57 }
58
59 static int s5pv310_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
60 {
61 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
62 }
63
64 static int s5pv310_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
65 {
66 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
67 }
68
69 static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
70 {
71 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
72 }
73
74 static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
75 {
76 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
77 }
78
79 static int s5pv310_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
80 {
81 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
82 }
83
84 static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable)
85 {
86 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
87 }
88
89 static int s5pv310_clk_ip_image_ctrl(struct clk *clk, int enable)
90 {
91 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
92 }
93
94 static int s5pv310_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
95 {
96 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
97 }
98
99 static int s5pv310_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
100 {
101 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
102 }
103
104 static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable)
105 {
106 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
107 }
108
109 static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
110 {
111 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
112 }
113
114 static int s5pv310_clk_ip_perir_ctrl(struct clk *clk, int enable)
115 {
116 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
117 }
118
119 /* Core list of CMU_CPU side */
120
121 static struct clksrc_clk clk_mout_apll = {
122 .clk = {
123 .name = "mout_apll",
124 .id = -1,
125 },
126 .sources = &clk_src_apll,
127 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
128 };
129
130 static struct clksrc_clk clk_sclk_apll = {
131 .clk = {
132 .name = "sclk_apll",
133 .id = -1,
134 .parent = &clk_mout_apll.clk,
135 },
136 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
137 };
138
139 static struct clksrc_clk clk_mout_epll = {
140 .clk = {
141 .name = "mout_epll",
142 .id = -1,
143 },
144 .sources = &clk_src_epll,
145 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
146 };
147
148 static struct clksrc_clk clk_mout_mpll = {
149 .clk = {
150 .name = "mout_mpll",
151 .id = -1,
152 },
153 .sources = &clk_src_mpll,
154 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
155 };
156
157 static struct clk *clkset_moutcore_list[] = {
158 [0] = &clk_mout_apll.clk,
159 [1] = &clk_mout_mpll.clk,
160 };
161
162 static struct clksrc_sources clkset_moutcore = {
163 .sources = clkset_moutcore_list,
164 .nr_sources = ARRAY_SIZE(clkset_moutcore_list),
165 };
166
167 static struct clksrc_clk clk_moutcore = {
168 .clk = {
169 .name = "moutcore",
170 .id = -1,
171 },
172 .sources = &clkset_moutcore,
173 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
174 };
175
176 static struct clksrc_clk clk_coreclk = {
177 .clk = {
178 .name = "core_clk",
179 .id = -1,
180 .parent = &clk_moutcore.clk,
181 },
182 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
183 };
184
185 static struct clksrc_clk clk_armclk = {
186 .clk = {
187 .name = "armclk",
188 .id = -1,
189 .parent = &clk_coreclk.clk,
190 },
191 };
192
193 static struct clksrc_clk clk_aclk_corem0 = {
194 .clk = {
195 .name = "aclk_corem0",
196 .id = -1,
197 .parent = &clk_coreclk.clk,
198 },
199 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
200 };
201
202 static struct clksrc_clk clk_aclk_cores = {
203 .clk = {
204 .name = "aclk_cores",
205 .id = -1,
206 .parent = &clk_coreclk.clk,
207 },
208 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
209 };
210
211 static struct clksrc_clk clk_aclk_corem1 = {
212 .clk = {
213 .name = "aclk_corem1",
214 .id = -1,
215 .parent = &clk_coreclk.clk,
216 },
217 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
218 };
219
220 static struct clksrc_clk clk_periphclk = {
221 .clk = {
222 .name = "periphclk",
223 .id = -1,
224 .parent = &clk_coreclk.clk,
225 },
226 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
227 };
228
229 /* Core list of CMU_CORE side */
230
231 static struct clk *clkset_corebus_list[] = {
232 [0] = &clk_mout_mpll.clk,
233 [1] = &clk_sclk_apll.clk,
234 };
235
236 static struct clksrc_sources clkset_mout_corebus = {
237 .sources = clkset_corebus_list,
238 .nr_sources = ARRAY_SIZE(clkset_corebus_list),
239 };
240
241 static struct clksrc_clk clk_mout_corebus = {
242 .clk = {
243 .name = "mout_corebus",
244 .id = -1,
245 },
246 .sources = &clkset_mout_corebus,
247 .reg_src = { .reg = S5P_CLKSRC_CORE, .shift = 4, .size = 1 },
248 };
249
250 static struct clksrc_clk clk_sclk_dmc = {
251 .clk = {
252 .name = "sclk_dmc",
253 .id = -1,
254 .parent = &clk_mout_corebus.clk,
255 },
256 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 12, .size = 3 },
257 };
258
259 static struct clksrc_clk clk_aclk_cored = {
260 .clk = {
261 .name = "aclk_cored",
262 .id = -1,
263 .parent = &clk_sclk_dmc.clk,
264 },
265 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 16, .size = 3 },
266 };
267
268 static struct clksrc_clk clk_aclk_corep = {
269 .clk = {
270 .name = "aclk_corep",
271 .id = -1,
272 .parent = &clk_aclk_cored.clk,
273 },
274 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 20, .size = 3 },
275 };
276
277 static struct clksrc_clk clk_aclk_acp = {
278 .clk = {
279 .name = "aclk_acp",
280 .id = -1,
281 .parent = &clk_mout_corebus.clk,
282 },
283 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 0, .size = 3 },
284 };
285
286 static struct clksrc_clk clk_pclk_acp = {
287 .clk = {
288 .name = "pclk_acp",
289 .id = -1,
290 .parent = &clk_aclk_acp.clk,
291 },
292 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 4, .size = 3 },
293 };
294
295 /* Core list of CMU_TOP side */
296
297 static struct clk *clkset_aclk_top_list[] = {
298 [0] = &clk_mout_mpll.clk,
299 [1] = &clk_sclk_apll.clk,
300 };
301
302 static struct clksrc_sources clkset_aclk = {
303 .sources = clkset_aclk_top_list,
304 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
305 };
306
307 static struct clksrc_clk clk_aclk_200 = {
308 .clk = {
309 .name = "aclk_200",
310 .id = -1,
311 },
312 .sources = &clkset_aclk,
313 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
314 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
315 };
316
317 static struct clksrc_clk clk_aclk_100 = {
318 .clk = {
319 .name = "aclk_100",
320 .id = -1,
321 },
322 .sources = &clkset_aclk,
323 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
324 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
325 };
326
327 static struct clksrc_clk clk_aclk_160 = {
328 .clk = {
329 .name = "aclk_160",
330 .id = -1,
331 },
332 .sources = &clkset_aclk,
333 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
334 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
335 };
336
337 static struct clksrc_clk clk_aclk_133 = {
338 .clk = {
339 .name = "aclk_133",
340 .id = -1,
341 },
342 .sources = &clkset_aclk,
343 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
344 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
345 };
346
347 static struct clk *clkset_vpllsrc_list[] = {
348 [0] = &clk_fin_vpll,
349 [1] = &clk_sclk_hdmi27m,
350 };
351
352 static struct clksrc_sources clkset_vpllsrc = {
353 .sources = clkset_vpllsrc_list,
354 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
355 };
356
357 static struct clksrc_clk clk_vpllsrc = {
358 .clk = {
359 .name = "vpll_src",
360 .id = -1,
361 .enable = s5pv310_clksrc_mask_top_ctrl,
362 .ctrlbit = (1 << 0),
363 },
364 .sources = &clkset_vpllsrc,
365 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
366 };
367
368 static struct clk *clkset_sclk_vpll_list[] = {
369 [0] = &clk_vpllsrc.clk,
370 [1] = &clk_fout_vpll,
371 };
372
373 static struct clksrc_sources clkset_sclk_vpll = {
374 .sources = clkset_sclk_vpll_list,
375 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
376 };
377
378 static struct clksrc_clk clk_sclk_vpll = {
379 .clk = {
380 .name = "sclk_vpll",
381 .id = -1,
382 },
383 .sources = &clkset_sclk_vpll,
384 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
385 };
386
387 static struct clk init_clocks_disable[] = {
388 {
389 .name = "timers",
390 .id = -1,
391 .parent = &clk_aclk_100.clk,
392 .enable = s5pv310_clk_ip_peril_ctrl,
393 .ctrlbit = (1<<24),
394 }, {
395 .name = "csis",
396 .id = 0,
397 .enable = s5pv310_clk_ip_cam_ctrl,
398 .ctrlbit = (1 << 4),
399 }, {
400 .name = "csis",
401 .id = 1,
402 .enable = s5pv310_clk_ip_cam_ctrl,
403 .ctrlbit = (1 << 5),
404 }, {
405 .name = "fimc",
406 .id = 0,
407 .enable = s5pv310_clk_ip_cam_ctrl,
408 .ctrlbit = (1 << 0),
409 }, {
410 .name = "fimc",
411 .id = 1,
412 .enable = s5pv310_clk_ip_cam_ctrl,
413 .ctrlbit = (1 << 1),
414 }, {
415 .name = "fimc",
416 .id = 2,
417 .enable = s5pv310_clk_ip_cam_ctrl,
418 .ctrlbit = (1 << 2),
419 }, {
420 .name = "fimc",
421 .id = 3,
422 .enable = s5pv310_clk_ip_cam_ctrl,
423 .ctrlbit = (1 << 3),
424 }, {
425 .name = "fimd",
426 .id = 0,
427 .enable = s5pv310_clk_ip_lcd0_ctrl,
428 .ctrlbit = (1 << 0),
429 }, {
430 .name = "fimd",
431 .id = 1,
432 .enable = s5pv310_clk_ip_lcd1_ctrl,
433 .ctrlbit = (1 << 0),
434 }, {
435 .name = "hsmmc",
436 .id = 0,
437 .parent = &clk_aclk_133.clk,
438 .enable = s5pv310_clk_ip_fsys_ctrl,
439 .ctrlbit = (1 << 5),
440 }, {
441 .name = "hsmmc",
442 .id = 1,
443 .parent = &clk_aclk_133.clk,
444 .enable = s5pv310_clk_ip_fsys_ctrl,
445 .ctrlbit = (1 << 6),
446 }, {
447 .name = "hsmmc",
448 .id = 2,
449 .parent = &clk_aclk_133.clk,
450 .enable = s5pv310_clk_ip_fsys_ctrl,
451 .ctrlbit = (1 << 7),
452 }, {
453 .name = "hsmmc",
454 .id = 3,
455 .parent = &clk_aclk_133.clk,
456 .enable = s5pv310_clk_ip_fsys_ctrl,
457 .ctrlbit = (1 << 8),
458 }, {
459 .name = "hsmmc",
460 .id = 4,
461 .parent = &clk_aclk_133.clk,
462 .enable = s5pv310_clk_ip_fsys_ctrl,
463 .ctrlbit = (1 << 9),
464 }, {
465 .name = "sata",
466 .id = -1,
467 .enable = s5pv310_clk_ip_fsys_ctrl,
468 .ctrlbit = (1 << 10),
469 }, {
470 .name = "adc",
471 .id = -1,
472 .enable = s5pv310_clk_ip_peril_ctrl,
473 .ctrlbit = (1 << 15),
474 }, {
475 .name = "rtc",
476 .id = -1,
477 .enable = s5pv310_clk_ip_perir_ctrl,
478 .ctrlbit = (1 << 15),
479 }, {
480 .name = "watchdog",
481 .id = -1,
482 .enable = s5pv310_clk_ip_perir_ctrl,
483 .ctrlbit = (1 << 14),
484 }, {
485 .name = "usbhost",
486 .id = -1,
487 .enable = s5pv310_clk_ip_fsys_ctrl ,
488 .ctrlbit = (1 << 12),
489 }, {
490 .name = "otg",
491 .id = -1,
492 .enable = s5pv310_clk_ip_fsys_ctrl,
493 .ctrlbit = (1 << 13),
494 }, {
495 .name = "spi",
496 .id = 0,
497 .enable = s5pv310_clk_ip_peril_ctrl,
498 .ctrlbit = (1 << 16),
499 }, {
500 .name = "spi",
501 .id = 1,
502 .enable = s5pv310_clk_ip_peril_ctrl,
503 .ctrlbit = (1 << 17),
504 }, {
505 .name = "spi",
506 .id = 2,
507 .enable = s5pv310_clk_ip_peril_ctrl,
508 .ctrlbit = (1 << 18),
509 }, {
510 .name = "fimg2d",
511 .id = -1,
512 .enable = s5pv310_clk_ip_image_ctrl,
513 .ctrlbit = (1 << 0),
514 }, {
515 .name = "i2c",
516 .id = 0,
517 .parent = &clk_aclk_100.clk,
518 .enable = s5pv310_clk_ip_peril_ctrl,
519 .ctrlbit = (1 << 6),
520 }, {
521 .name = "i2c",
522 .id = 1,
523 .parent = &clk_aclk_100.clk,
524 .enable = s5pv310_clk_ip_peril_ctrl,
525 .ctrlbit = (1 << 7),
526 }, {
527 .name = "i2c",
528 .id = 2,
529 .parent = &clk_aclk_100.clk,
530 .enable = s5pv310_clk_ip_peril_ctrl,
531 .ctrlbit = (1 << 8),
532 }, {
533 .name = "i2c",
534 .id = 3,
535 .parent = &clk_aclk_100.clk,
536 .enable = s5pv310_clk_ip_peril_ctrl,
537 .ctrlbit = (1 << 9),
538 }, {
539 .name = "i2c",
540 .id = 4,
541 .parent = &clk_aclk_100.clk,
542 .enable = s5pv310_clk_ip_peril_ctrl,
543 .ctrlbit = (1 << 10),
544 }, {
545 .name = "i2c",
546 .id = 5,
547 .parent = &clk_aclk_100.clk,
548 .enable = s5pv310_clk_ip_peril_ctrl,
549 .ctrlbit = (1 << 11),
550 }, {
551 .name = "i2c",
552 .id = 6,
553 .parent = &clk_aclk_100.clk,
554 .enable = s5pv310_clk_ip_peril_ctrl,
555 .ctrlbit = (1 << 12),
556 }, {
557 .name = "i2c",
558 .id = 7,
559 .parent = &clk_aclk_100.clk,
560 .enable = s5pv310_clk_ip_peril_ctrl,
561 .ctrlbit = (1 << 13),
562 },
563 };
564
565 static struct clk init_clocks[] = {
566 {
567 .name = "uart",
568 .id = 0,
569 .enable = s5pv310_clk_ip_peril_ctrl,
570 .ctrlbit = (1 << 0),
571 }, {
572 .name = "uart",
573 .id = 1,
574 .enable = s5pv310_clk_ip_peril_ctrl,
575 .ctrlbit = (1 << 1),
576 }, {
577 .name = "uart",
578 .id = 2,
579 .enable = s5pv310_clk_ip_peril_ctrl,
580 .ctrlbit = (1 << 2),
581 }, {
582 .name = "uart",
583 .id = 3,
584 .enable = s5pv310_clk_ip_peril_ctrl,
585 .ctrlbit = (1 << 3),
586 }, {
587 .name = "uart",
588 .id = 4,
589 .enable = s5pv310_clk_ip_peril_ctrl,
590 .ctrlbit = (1 << 4),
591 }, {
592 .name = "uart",
593 .id = 5,
594 .enable = s5pv310_clk_ip_peril_ctrl,
595 .ctrlbit = (1 << 5),
596 }
597 };
598
599 static struct clk *clkset_group_list[] = {
600 [0] = &clk_ext_xtal_mux,
601 [1] = &clk_xusbxti,
602 [2] = &clk_sclk_hdmi27m,
603 [3] = &clk_sclk_usbphy0,
604 [4] = &clk_sclk_usbphy1,
605 [5] = &clk_sclk_hdmiphy,
606 [6] = &clk_mout_mpll.clk,
607 [7] = &clk_mout_epll.clk,
608 [8] = &clk_sclk_vpll.clk,
609 };
610
611 static struct clksrc_sources clkset_group = {
612 .sources = clkset_group_list,
613 .nr_sources = ARRAY_SIZE(clkset_group_list),
614 };
615
616 static struct clk *clkset_mout_g2d0_list[] = {
617 [0] = &clk_mout_mpll.clk,
618 [1] = &clk_sclk_apll.clk,
619 };
620
621 static struct clksrc_sources clkset_mout_g2d0 = {
622 .sources = clkset_mout_g2d0_list,
623 .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
624 };
625
626 static struct clksrc_clk clk_mout_g2d0 = {
627 .clk = {
628 .name = "mout_g2d0",
629 .id = -1,
630 },
631 .sources = &clkset_mout_g2d0,
632 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
633 };
634
635 static struct clk *clkset_mout_g2d1_list[] = {
636 [0] = &clk_mout_epll.clk,
637 [1] = &clk_sclk_vpll.clk,
638 };
639
640 static struct clksrc_sources clkset_mout_g2d1 = {
641 .sources = clkset_mout_g2d1_list,
642 .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
643 };
644
645 static struct clksrc_clk clk_mout_g2d1 = {
646 .clk = {
647 .name = "mout_g2d1",
648 .id = -1,
649 },
650 .sources = &clkset_mout_g2d1,
651 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
652 };
653
654 static struct clk *clkset_mout_g2d_list[] = {
655 [0] = &clk_mout_g2d0.clk,
656 [1] = &clk_mout_g2d1.clk,
657 };
658
659 static struct clksrc_sources clkset_mout_g2d = {
660 .sources = clkset_mout_g2d_list,
661 .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
662 };
663
664 static struct clksrc_clk clk_dout_mmc0 = {
665 .clk = {
666 .name = "dout_mmc0",
667 .id = -1,
668 },
669 .sources = &clkset_group,
670 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
671 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
672 };
673
674 static struct clksrc_clk clk_dout_mmc1 = {
675 .clk = {
676 .name = "dout_mmc1",
677 .id = -1,
678 },
679 .sources = &clkset_group,
680 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
681 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
682 };
683
684 static struct clksrc_clk clk_dout_mmc2 = {
685 .clk = {
686 .name = "dout_mmc2",
687 .id = -1,
688 },
689 .sources = &clkset_group,
690 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
691 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
692 };
693
694 static struct clksrc_clk clk_dout_mmc3 = {
695 .clk = {
696 .name = "dout_mmc3",
697 .id = -1,
698 },
699 .sources = &clkset_group,
700 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
701 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
702 };
703
704 static struct clksrc_clk clk_dout_mmc4 = {
705 .clk = {
706 .name = "dout_mmc4",
707 .id = -1,
708 },
709 .sources = &clkset_group,
710 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
711 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
712 };
713
714 static struct clksrc_clk clksrcs[] = {
715 {
716 .clk = {
717 .name = "uclk1",
718 .id = 0,
719 .enable = s5pv310_clksrc_mask_peril0_ctrl,
720 .ctrlbit = (1 << 0),
721 },
722 .sources = &clkset_group,
723 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
724 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
725 }, {
726 .clk = {
727 .name = "uclk1",
728 .id = 1,
729 .enable = s5pv310_clksrc_mask_peril0_ctrl,
730 .ctrlbit = (1 << 4),
731 },
732 .sources = &clkset_group,
733 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
734 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
735 }, {
736 .clk = {
737 .name = "uclk1",
738 .id = 2,
739 .enable = s5pv310_clksrc_mask_peril0_ctrl,
740 .ctrlbit = (1 << 8),
741 },
742 .sources = &clkset_group,
743 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
744 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
745 }, {
746 .clk = {
747 .name = "uclk1",
748 .id = 3,
749 .enable = s5pv310_clksrc_mask_peril0_ctrl,
750 .ctrlbit = (1 << 12),
751 },
752 .sources = &clkset_group,
753 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
754 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
755 }, {
756 .clk = {
757 .name = "sclk_pwm",
758 .id = -1,
759 .enable = s5pv310_clksrc_mask_peril0_ctrl,
760 .ctrlbit = (1 << 24),
761 },
762 .sources = &clkset_group,
763 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
764 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
765 }, {
766 .clk = {
767 .name = "sclk_csis",
768 .id = 0,
769 .enable = s5pv310_clksrc_mask_cam_ctrl,
770 .ctrlbit = (1 << 24),
771 },
772 .sources = &clkset_group,
773 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
774 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
775 }, {
776 .clk = {
777 .name = "sclk_csis",
778 .id = 1,
779 .enable = s5pv310_clksrc_mask_cam_ctrl,
780 .ctrlbit = (1 << 28),
781 },
782 .sources = &clkset_group,
783 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
784 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
785 }, {
786 .clk = {
787 .name = "sclk_cam",
788 .id = 0,
789 .enable = s5pv310_clksrc_mask_cam_ctrl,
790 .ctrlbit = (1 << 16),
791 },
792 .sources = &clkset_group,
793 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
794 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
795 }, {
796 .clk = {
797 .name = "sclk_cam",
798 .id = 1,
799 .enable = s5pv310_clksrc_mask_cam_ctrl,
800 .ctrlbit = (1 << 20),
801 },
802 .sources = &clkset_group,
803 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
804 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
805 }, {
806 .clk = {
807 .name = "sclk_fimc",
808 .id = 0,
809 .enable = s5pv310_clksrc_mask_cam_ctrl,
810 .ctrlbit = (1 << 0),
811 },
812 .sources = &clkset_group,
813 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
814 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
815 }, {
816 .clk = {
817 .name = "sclk_fimc",
818 .id = 1,
819 .enable = s5pv310_clksrc_mask_cam_ctrl,
820 .ctrlbit = (1 << 4),
821 },
822 .sources = &clkset_group,
823 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
824 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
825 }, {
826 .clk = {
827 .name = "sclk_fimc",
828 .id = 2,
829 .enable = s5pv310_clksrc_mask_cam_ctrl,
830 .ctrlbit = (1 << 8),
831 },
832 .sources = &clkset_group,
833 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
834 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
835 }, {
836 .clk = {
837 .name = "sclk_fimc",
838 .id = 3,
839 .enable = s5pv310_clksrc_mask_cam_ctrl,
840 .ctrlbit = (1 << 12),
841 },
842 .sources = &clkset_group,
843 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
844 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
845 }, {
846 .clk = {
847 .name = "sclk_fimd",
848 .id = 0,
849 .enable = s5pv310_clksrc_mask_lcd0_ctrl,
850 .ctrlbit = (1 << 0),
851 },
852 .sources = &clkset_group,
853 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
854 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
855 }, {
856 .clk = {
857 .name = "sclk_fimd",
858 .id = 1,
859 .enable = s5pv310_clksrc_mask_lcd1_ctrl,
860 .ctrlbit = (1 << 0),
861 },
862 .sources = &clkset_group,
863 .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
864 .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
865 }, {
866 .clk = {
867 .name = "sclk_sata",
868 .id = -1,
869 .enable = s5pv310_clksrc_mask_fsys_ctrl,
870 .ctrlbit = (1 << 24),
871 },
872 .sources = &clkset_mout_corebus,
873 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
874 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
875 }, {
876 .clk = {
877 .name = "sclk_spi",
878 .id = 0,
879 .enable = s5pv310_clksrc_mask_peril1_ctrl,
880 .ctrlbit = (1 << 16),
881 },
882 .sources = &clkset_group,
883 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
884 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
885 }, {
886 .clk = {
887 .name = "sclk_spi",
888 .id = 1,
889 .enable = s5pv310_clksrc_mask_peril1_ctrl,
890 .ctrlbit = (1 << 20),
891 },
892 .sources = &clkset_group,
893 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
894 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
895 }, {
896 .clk = {
897 .name = "sclk_spi",
898 .id = 2,
899 .enable = s5pv310_clksrc_mask_peril1_ctrl,
900 .ctrlbit = (1 << 24),
901 },
902 .sources = &clkset_group,
903 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
904 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
905 }, {
906 .clk = {
907 .name = "sclk_fimg2d",
908 .id = -1,
909 },
910 .sources = &clkset_mout_g2d,
911 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
912 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
913 }, {
914 .clk = {
915 .name = "sclk_mmc",
916 .id = 0,
917 .parent = &clk_dout_mmc0.clk,
918 .enable = s5pv310_clksrc_mask_fsys_ctrl,
919 .ctrlbit = (1 << 0),
920 },
921 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
922 }, {
923 .clk = {
924 .name = "sclk_mmc",
925 .id = 1,
926 .parent = &clk_dout_mmc1.clk,
927 .enable = s5pv310_clksrc_mask_fsys_ctrl,
928 .ctrlbit = (1 << 4),
929 },
930 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
931 }, {
932 .clk = {
933 .name = "sclk_mmc",
934 .id = 2,
935 .parent = &clk_dout_mmc2.clk,
936 .enable = s5pv310_clksrc_mask_fsys_ctrl,
937 .ctrlbit = (1 << 8),
938 },
939 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
940 }, {
941 .clk = {
942 .name = "sclk_mmc",
943 .id = 3,
944 .parent = &clk_dout_mmc3.clk,
945 .enable = s5pv310_clksrc_mask_fsys_ctrl,
946 .ctrlbit = (1 << 12),
947 },
948 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
949 }, {
950 .clk = {
951 .name = "sclk_mmc",
952 .id = 4,
953 .parent = &clk_dout_mmc4.clk,
954 .enable = s5pv310_clksrc_mask_fsys_ctrl,
955 .ctrlbit = (1 << 16),
956 },
957 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
958 }
959 };
960
961 /* Clock initialization code */
962 static struct clksrc_clk *sysclks[] = {
963 &clk_mout_apll,
964 &clk_sclk_apll,
965 &clk_mout_epll,
966 &clk_mout_mpll,
967 &clk_moutcore,
968 &clk_coreclk,
969 &clk_armclk,
970 &clk_aclk_corem0,
971 &clk_aclk_cores,
972 &clk_aclk_corem1,
973 &clk_periphclk,
974 &clk_mout_corebus,
975 &clk_sclk_dmc,
976 &clk_aclk_cored,
977 &clk_aclk_corep,
978 &clk_aclk_acp,
979 &clk_pclk_acp,
980 &clk_vpllsrc,
981 &clk_sclk_vpll,
982 &clk_aclk_200,
983 &clk_aclk_100,
984 &clk_aclk_160,
985 &clk_aclk_133,
986 &clk_dout_mmc0,
987 &clk_dout_mmc1,
988 &clk_dout_mmc2,
989 &clk_dout_mmc3,
990 &clk_dout_mmc4,
991 };
992
993 void __init_or_cpufreq s5pv310_setup_clocks(void)
994 {
995 struct clk *xtal_clk;
996 unsigned long apll;
997 unsigned long mpll;
998 unsigned long epll;
999 unsigned long vpll;
1000 unsigned long vpllsrc;
1001 unsigned long xtal;
1002 unsigned long armclk;
1003 unsigned long sclk_dmc;
1004 unsigned long aclk_200;
1005 unsigned long aclk_100;
1006 unsigned long aclk_160;
1007 unsigned long aclk_133;
1008 unsigned int ptr;
1009
1010 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1011
1012 xtal_clk = clk_get(NULL, "xtal");
1013 BUG_ON(IS_ERR(xtal_clk));
1014
1015 xtal = clk_get_rate(xtal_clk);
1016 clk_put(xtal_clk);
1017
1018 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1019
1020 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
1021 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
1022 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1023 __raw_readl(S5P_EPLL_CON1), pll_4600);
1024
1025 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1026 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1027 __raw_readl(S5P_VPLL_CON1), pll_4650);
1028
1029 clk_fout_apll.rate = apll;
1030 clk_fout_mpll.rate = mpll;
1031 clk_fout_epll.rate = epll;
1032 clk_fout_vpll.rate = vpll;
1033
1034 printk(KERN_INFO "S5PV310: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1035 apll, mpll, epll, vpll);
1036
1037 armclk = clk_get_rate(&clk_armclk.clk);
1038 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1039
1040 aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1041 aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1042 aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1043 aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1044
1045 printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1046 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1047 armclk, sclk_dmc, aclk_200,
1048 aclk_100, aclk_160, aclk_133);
1049
1050 clk_f.rate = armclk;
1051 clk_h.rate = sclk_dmc;
1052 clk_p.rate = aclk_100;
1053
1054 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1055 s3c_set_clksrc(&clksrcs[ptr], true);
1056 }
1057
1058 static struct clk *clks[] __initdata = {
1059 /* Nothing here yet */
1060 };
1061
1062 void __init s5pv310_register_clocks(void)
1063 {
1064 struct clk *clkp;
1065 int ret;
1066 int ptr;
1067
1068 ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1069 if (ret > 0)
1070 printk(KERN_ERR "Failed to register %u clocks\n", ret);
1071
1072 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1073 s3c_register_clksrc(sysclks[ptr], 1);
1074
1075 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1076 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1077
1078 clkp = init_clocks_disable;
1079 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
1080 ret = s3c24xx_register_clock(clkp);
1081 if (ret < 0) {
1082 printk(KERN_ERR "Failed to register clock %s (%d)\n",
1083 clkp->name, ret);
1084 }
1085 (clkp->enable)(clkp, 0);
1086 }
1087
1088 s3c_pwmclk_init();
1089 }
x86 "subsystem" repository