arch/arm/mach-pxa/pxa27x.c

   1 /*
   2  *  linux/arch/arm/mach-pxa/pxa27x.c
   3  *
   4  *  Author:     Nicolas Pitre
   5  *  Created:    Nov 05, 2002
   6  *  Copyright:  MontaVista Software Inc.
   7  *
   8  * Code specific to PXA27x aka Bulverde.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/suspend.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/sysdev.h>
  20 #include <linux/io.h>
  21
  22 #include <asm/mach/map.h>
  23 #include <mach/hardware.h>
  24 #include <asm/irq.h>
  25 #include <mach/irqs.h>
  26 #include <mach/gpio.h>
  27 #include <mach/pxa27x.h>
  28 #include <mach/reset.h>
  29 #include <mach/ohci.h>
  30 #include <mach/pm.h>
  31 #include <mach/dma.h>
  32 #include <mach/smemc.h>
  33
  34 #include <plat/i2c.h>
  35
  36 #include "generic.h"
  37 #include "devices.h"
  38 #include "clock.h"
  39
  40 void pxa27x_clear_otgph(void)
  41 {
  42         if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
  43                 PSSR |= PSSR_OTGPH;
  44 }
  45 EXPORT_SYMBOL(pxa27x_clear_otgph);
  46
  47 static unsigned long ac97_reset_config[] = {
  48         GPIO113_GPIO,
  49         GPIO113_AC97_nRESET,
  50         GPIO95_GPIO,
  51         GPIO95_AC97_nRESET,
  52 };
  53
  54 void pxa27x_assert_ac97reset(int reset_gpio, int on)
  55 {
  56         if (reset_gpio == 113)
  57                 pxa2xx_mfp_config(on ? &ac97_reset_config[0] :
  58                                        &ac97_reset_config[1], 1);
  59
  60         if (reset_gpio == 95)
  61                 pxa2xx_mfp_config(on ? &ac97_reset_config[2] :
  62                                        &ac97_reset_config[3], 1);
  63 }
  64 EXPORT_SYMBOL_GPL(pxa27x_assert_ac97reset);
  65
  66 /* Crystal clock: 13MHz */
  67 #define BASE_CLK        13000000
  68
  69 /*
  70  * Get the clock frequency as reflected by CCSR and the turbo flag.
  71  * We assume these values have been applied via a fcs.
  72  * If info is not 0 we also display the current settings.
  73  */
  74 unsigned int pxa27x_get_clk_frequency_khz(int info)
  75 {
  76         unsigned long ccsr, clkcfg;
  77         unsigned int l, L, m, M, n2, N, S;
  78         int cccr_a, t, ht, b;
  79
  80         ccsr = CCSR;
  81         cccr_a = CCCR & (1 << 25);
  82
  83         /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
  84         asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
  85         t  = clkcfg & (1 << 0);
  86         ht = clkcfg & (1 << 2);
  87         b  = clkcfg & (1 << 3);
  88
  89         l  = ccsr & 0x1f;
  90         n2 = (ccsr>>7) & 0xf;
  91         m  = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
  92
  93         L  = l * BASE_CLK;
  94         N  = (L * n2) / 2;
  95         M  = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
  96         S  = (b) ? L : (L/2);
  97
  98         if (info) {
  99                 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
 100                         L / 1000000, (L % 1000000) / 10000, l );
 101                 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
 102                         N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
 103                         (t) ? "" : "in" );
 104                 printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
 105                         M / 1000000, (M % 1000000) / 10000, m );
 106                 printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
 107                         S / 1000000, (S % 1000000) / 10000 );
 108         }
 109
 110         return (t) ? (N/1000) : (L/1000);
 111 }
 112
 113 /*
 114  * Return the current mem clock frequency as reflected by CCCR[A], B, and L
 115  */
 116 static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
 117 {
 118         unsigned long ccsr, clkcfg;
 119         unsigned int l, L, m, M;
 120         int cccr_a, b;
 121
 122         ccsr = CCSR;
 123         cccr_a = CCCR & (1 << 25);
 124
 125         /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
 126         asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
 127         b = clkcfg & (1 << 3);
 128
 129         l = ccsr & 0x1f;
 130         m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
 131
 132         L = l * BASE_CLK;
 133         M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
 134
 135         return M;
 136 }
 137
 138 static const struct clkops clk_pxa27x_mem_ops = {
 139         .enable         = clk_dummy_enable,
 140         .disable        = clk_dummy_disable,
 141         .getrate        = clk_pxa27x_mem_getrate,
 142 };
 143
 144 /*
 145  * Return the current LCD clock frequency in units of 10kHz as
 146  */
 147 static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
 148 {
 149         unsigned long ccsr;
 150         unsigned int l, L, k, K;
 151
 152         ccsr = CCSR;
 153
 154         l = ccsr & 0x1f;
 155         k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
 156
 157         L = l * BASE_CLK;
 158         K = L / k;
 159
 160         return (K / 10000);
 161 }
 162
 163 static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
 164 {
 165         return pxa27x_get_lcdclk_frequency_10khz() * 10000;
 166 }
 167
 168 static const struct clkops clk_pxa27x_lcd_ops = {
 169         .enable         = clk_pxa2xx_cken_enable,
 170         .disable        = clk_pxa2xx_cken_disable,
 171         .getrate        = clk_pxa27x_lcd_getrate,
 172 };
 173
 174 static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
 175 static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
 176 static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1);
 177 static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0);
 178 static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0);
 179 static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5);
 180 static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0);
 181 static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0);
 182 static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
 183 static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
 184 static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
 185 static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
 186 static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
 187 static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
 188 static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
 189 static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
 190 static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0);
 191 static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
 192 static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0);
 193 static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0);
 194 static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
 195 static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0);
 196 static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0);
 197
 198 static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
 199 static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
 200 static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0);
 201
 202 static struct clk_lookup pxa27x_clkregs[] = {
 203         INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
 204         INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
 205         INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
 206         INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
 207         INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
 208         INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
 209         INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
 210         INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
 211         INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
 212         INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
 213         INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
 214         INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
 215         INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
 216         INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
 217         INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
 218         INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
 219         INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
 220         INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
 221         INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
 222         INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
 223         INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
 224         INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
 225         INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
 226         INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
 227         INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
 228         INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
 229         INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
 230 };
 231
 232 #ifdef CONFIG_PM
 233
 234 #define SAVE(x)         sleep_save[SLEEP_SAVE_##x] = x
 235 #define RESTORE(x)      x = sleep_save[SLEEP_SAVE_##x]
 236
 237 /*
 238  * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
 239  */
 240 static unsigned int pwrmode = PWRMODE_SLEEP;
 241
 242 int __init pxa27x_set_pwrmode(unsigned int mode)
 243 {
 244         switch (mode) {
 245         case PWRMODE_SLEEP:
 246         case PWRMODE_DEEPSLEEP:
 247                 pwrmode = mode;
 248                 return 0;
 249         }
 250
 251         return -EINVAL;
 252 }
 253
 254 /*
 255  * List of global PXA peripheral registers to preserve.
 256  * More ones like CP and general purpose register values are preserved
 257  * with the stack pointer in sleep.S.
 258  */
 259 enum {
 260         SLEEP_SAVE_PSTR,
 261         SLEEP_SAVE_MDREFR,
 262         SLEEP_SAVE_PCFR,
 263         SLEEP_SAVE_COUNT
 264 };
 265
 266 void pxa27x_cpu_pm_save(unsigned long *sleep_save)
 267 {
 268         sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
 269         SAVE(PCFR);
 270
 271         SAVE(PSTR);
 272 }
 273
 274 void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
 275 {
 276         __raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
 277         RESTORE(PCFR);
 278
 279         PSSR = PSSR_RDH | PSSR_PH;
 280
 281         RESTORE(PSTR);
 282 }
 283
 284 void pxa27x_cpu_pm_enter(suspend_state_t state)
 285 {
 286         extern void pxa_cpu_standby(void);
 287
 288         /* ensure voltage-change sequencer not initiated, which hangs */
 289         PCFR &= ~PCFR_FVC;
 290
 291         /* Clear edge-detect status register. */
 292         PEDR = 0xDF12FE1B;
 293
 294         /* Clear reset status */
 295         RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
 296
 297         switch (state) {
 298         case PM_SUSPEND_STANDBY:
 299                 pxa_cpu_standby();
 300                 break;
 301         case PM_SUSPEND_MEM:
 302                 pxa27x_cpu_suspend(pwrmode);
 303                 break;
 304         }
 305 }
 306
 307 static int pxa27x_cpu_pm_valid(suspend_state_t state)
 308 {
 309         return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
 310 }
 311
 312 static int pxa27x_cpu_pm_prepare(void)
 313 {
 314         /* set resume return address */
 315         PSPR = virt_to_phys(pxa_cpu_resume);
 316         return 0;
 317 }
 318
 319 static void pxa27x_cpu_pm_finish(void)
 320 {
 321         /* ensure not to come back here if it wasn't intended */
 322         PSPR = 0;
 323 }
 324
 325 static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
 326         .save_count     = SLEEP_SAVE_COUNT,
 327         .save           = pxa27x_cpu_pm_save,
 328         .restore        = pxa27x_cpu_pm_restore,
 329         .valid          = pxa27x_cpu_pm_valid,
 330         .enter          = pxa27x_cpu_pm_enter,
 331         .prepare        = pxa27x_cpu_pm_prepare,
 332         .finish         = pxa27x_cpu_pm_finish,
 333 };
 334
 335 static void __init pxa27x_init_pm(void)
 336 {
 337         pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
 338 }
 339 #else
 340 static inline void pxa27x_init_pm(void) {}
 341 #endif
 342
 343 /* PXA27x:  Various gpios can issue wakeup events.  This logic only
 344  * handles the simple cases, not the WEMUX2 and WEMUX3 options
 345  */
 346 static int pxa27x_set_wake(unsigned int irq, unsigned int on)
 347 {
 348         int gpio = IRQ_TO_GPIO(irq);
 349         uint32_t mask;
 350
 351         if (gpio >= 0 && gpio < 128)
 352                 return gpio_set_wake(gpio, on);
 353
 354         if (irq == IRQ_KEYPAD)
 355                 return keypad_set_wake(on);
 356
 357         switch (irq) {
 358         case IRQ_RTCAlrm:
 359                 mask = PWER_RTC;
 360                 break;
 361         case IRQ_USB:
 362                 mask = 1u << 26;
 363                 break;
 364         default:
 365                 return -EINVAL;
 366         }
 367
 368         if (on)
 369                 PWER |= mask;
 370         else
 371                 PWER &=~mask;
 372
 373         return 0;
 374 }
 375
 376 void __init pxa27x_init_irq(void)
 377 {
 378         pxa_init_irq(34, pxa27x_set_wake);
 379         pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake);
 380 }
 381
 382 static struct map_desc pxa27x_io_desc[] __initdata = {
 383         {       /* Mem Ctl */
 384                 .virtual        = SMEMC_VIRT,
 385                 .pfn            = __phys_to_pfn(PXA2XX_SMEMC_BASE),
 386                 .length         = 0x00200000,
 387                 .type           = MT_DEVICE
 388         }, {    /* IMem ctl */
 389                 .virtual        =  0xfe000000,
 390                 .pfn            = __phys_to_pfn(0x58000000),
 391                 .length         = 0x00100000,
 392                 .type           = MT_DEVICE
 393         },
 394 };
 395
 396 void __init pxa27x_map_io(void)
 397 {
 398         pxa_map_io();
 399         iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc));
 400         pxa27x_get_clk_frequency_khz(1);
 401 }
 402
 403 /*
 404  * device registration specific to PXA27x.
 405  */
 406 void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 407 {
 408         local_irq_disable();
 409         PCFR |= PCFR_PI2CEN;
 410         local_irq_enable();
 411         pxa_register_device(&pxa27x_device_i2c_power, info);
 412 }
 413
 414 static struct platform_device *devices[] __initdata = {
 415         &pxa27x_device_udc,
 416         &pxa_device_pmu,
 417         &pxa_device_i2s,
 418         &pxa_device_asoc_ssp1,
 419         &pxa_device_asoc_ssp2,
 420         &pxa_device_asoc_ssp3,
 421         &pxa_device_asoc_platform,
 422         &sa1100_device_rtc,
 423         &pxa_device_rtc,
 424         &pxa27x_device_ssp1,
 425         &pxa27x_device_ssp2,
 426         &pxa27x_device_ssp3,
 427         &pxa27x_device_pwm0,
 428         &pxa27x_device_pwm1,
 429 };
 430
 431 static struct sys_device pxa27x_sysdev[] = {
 432         {
 433                 .cls    = &pxa_irq_sysclass,
 434         }, {
 435                 .cls    = &pxa2xx_mfp_sysclass,
 436         }, {
 437                 .cls    = &pxa_gpio_sysclass,
 438         }, {
 439                 .cls    = &pxa2xx_clock_sysclass,
 440         }
 441 };
 442
 443 static int __init pxa27x_init(void)
 444 {
 445         int i, ret = 0;
 446
 447         if (cpu_is_pxa27x()) {
 448
 449                 reset_status = RCSR;
 450
 451                 clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
 452
 453                 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
 454                         return ret;
 455
 456                 pxa27x_init_pm();
 457
 458                 for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) {
 459                         ret = sysdev_register(&pxa27x_sysdev[i]);
 460                         if (ret)
 461                                 pr_err("failed to register sysdev[%d]\n", i);
 462                 }
 463
 464                 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
 465         }
 466
 467         return ret;
 468 }
 469
 470 postcore_initcall(pxa27x_init);