drivers/scsi/sata_sis.c

   1 /*
   2  *  sata_sis.c - Silicon Integrated Systems SATA
   3  *
   4  *  Maintained by:  Uwe Koziolek
   5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6  *                  on emails.
   7  *
   8  *  Copyright 2004 Uwe Koziolek
   9  *
  10  *
  11  *  This program is free software; you can redistribute it and/or modify
  12  *  it under the terms of the GNU General Public License as published by
  13  *  the Free Software Foundation; either version 2, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful,
  17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *  GNU General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License
  22  *  along with this program; see the file COPYING.  If not, write to
  23  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  24  *
  25  *
  26  *  libata documentation is available via 'make {ps|pdf}docs',
  27  *  as Documentation/DocBook/libata.*
  28  *
  29  *  Hardware documentation available under NDA.
  30  *
  31  */
  32
  33 #include <linux/config.h>
  34 #include <linux/kernel.h>
  35 #include <linux/module.h>
  36 #include <linux/pci.h>
  37 #include <linux/init.h>
  38 #include <linux/blkdev.h>
  39 #include <linux/delay.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/device.h>
  42 #include "scsi.h"
  43 #include <scsi/scsi_host.h>
  44 #include <linux/libata.h>
  45
  46 #define DRV_NAME        "sata_sis"
  47 #define DRV_VERSION     "0.5"
  48
  49 enum {
  50         sis_180                 = 0,
  51         SIS_SCR_PCI_BAR         = 5,
  52
  53         /* PCI configuration registers */
  54         SIS_GENCTL              = 0x54, /* IDE General Control register */
  55         SIS_SCR_BASE            = 0xc0, /* sata0 phy SCR registers */
  56         SIS180_SATA1_OFS        = 0x10, /* offset from sata0->sata1 phy regs */
  57         SIS182_SATA1_OFS        = 0x20, /* offset from sata0->sata1 phy regs */
  58         SIS_PMR                 = 0x90, /* port mapping register */
  59         SIS_PMR_COMBINED        = 0x30,
  60
  61         /* random bits */
  62         SIS_FLAG_CFGSCR         = (1 << 30), /* host flag: SCRs via PCI cfg */
  63
  64         GENCTL_IOMAPPED_SCR     = (1 << 26), /* if set, SCRs are in IO space */
  65 };
  66
  67 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
  68 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg);
  69 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
  70
  71 static struct pci_device_id sis_pci_tbl[] = {
  72         { PCI_VENDOR_ID_SI, 0x180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
  73         { PCI_VENDOR_ID_SI, 0x181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
  74         { PCI_VENDOR_ID_SI, 0x182, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
  75         { }     /* terminate list */
  76 };
  77
  78
  79 static struct pci_driver sis_pci_driver = {
  80         .name                   = DRV_NAME,
  81         .id_table               = sis_pci_tbl,
  82         .probe                  = sis_init_one,
  83         .remove                 = ata_pci_remove_one,
  84 };
  85
  86 static Scsi_Host_Template sis_sht = {
  87         .module                 = THIS_MODULE,
  88         .name                   = DRV_NAME,
  89         .ioctl                  = ata_scsi_ioctl,
  90         .queuecommand           = ata_scsi_queuecmd,
  91         .eh_strategy_handler    = ata_scsi_error,
  92         .can_queue              = ATA_DEF_QUEUE,
  93         .this_id                = ATA_SHT_THIS_ID,
  94         .sg_tablesize           = ATA_MAX_PRD,
  95         .max_sectors            = ATA_MAX_SECTORS,
  96         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
  97         .emulated               = ATA_SHT_EMULATED,
  98         .use_clustering         = ATA_SHT_USE_CLUSTERING,
  99         .proc_name              = DRV_NAME,
 100         .dma_boundary           = ATA_DMA_BOUNDARY,
 101         .slave_configure        = ata_scsi_slave_config,
 102         .bios_param             = ata_std_bios_param,
 103         .ordered_flush          = 1,
 104 };
 105
 106 static const struct ata_port_operations sis_ops = {
 107         .port_disable           = ata_port_disable,
 108         .tf_load                = ata_tf_load,
 109         .tf_read                = ata_tf_read,
 110         .check_status           = ata_check_status,
 111         .exec_command           = ata_exec_command,
 112         .dev_select             = ata_std_dev_select,
 113         .phy_reset              = sata_phy_reset,
 114         .bmdma_setup            = ata_bmdma_setup,
 115         .bmdma_start            = ata_bmdma_start,
 116         .bmdma_stop             = ata_bmdma_stop,
 117         .bmdma_status           = ata_bmdma_status,
 118         .qc_prep                = ata_qc_prep,
 119         .qc_issue               = ata_qc_issue_prot,
 120         .eng_timeout            = ata_eng_timeout,
 121         .irq_handler            = ata_interrupt,
 122         .irq_clear              = ata_bmdma_irq_clear,
 123         .scr_read               = sis_scr_read,
 124         .scr_write              = sis_scr_write,
 125         .port_start             = ata_port_start,
 126         .port_stop              = ata_port_stop,
 127         .host_stop              = ata_host_stop,
 128 };
 129
 130 static struct ata_port_info sis_port_info = {
 131         .sht            = &sis_sht,
 132         .host_flags     = ATA_FLAG_SATA | ATA_FLAG_SATA_RESET |
 133                           ATA_FLAG_NO_LEGACY,
 134         .pio_mask       = 0x1f,
 135         .mwdma_mask     = 0x7,
 136         .udma_mask      = 0x7f,
 137         .port_ops       = &sis_ops,
 138 };
 139
 140
 141 MODULE_AUTHOR("Uwe Koziolek");
 142 MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
 143 MODULE_LICENSE("GPL");
 144 MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
 145 MODULE_VERSION(DRV_VERSION);
 146
 147 static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg, int device)
 148 {
 149         unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
 150
 151         if (port_no)  {
 152                 if (device == 0x182)
 153                         addr += SIS182_SATA1_OFS;
 154                 else
 155                         addr += SIS180_SATA1_OFS;
 156         }
 157
 158         return addr;
 159 }
 160
 161 static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
 162 {
 163         struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
 164         unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg, pdev->device);
 165         u32 val, val2 = 0;
 166         u8 pmr;
 167
 168         if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
 169                 return 0xffffffff;
 170
 171         pci_read_config_byte(pdev, SIS_PMR, &pmr);
 172
 173         pci_read_config_dword(pdev, cfg_addr, &val);
 174
 175         if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
 176                 pci_read_config_dword(pdev, cfg_addr+0x10, &val2);
 177
 178         return val|val2;
 179 }
 180
 181 static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val)
 182 {
 183         struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
 184         unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, scr, pdev->device);
 185         u8 pmr;
 186
 187         if (scr == SCR_ERROR) /* doesn't exist in PCI cfg space */
 188                 return;
 189
 190         pci_read_config_byte(pdev, SIS_PMR, &pmr);
 191
 192         pci_write_config_dword(pdev, cfg_addr, val);
 193
 194         if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
 195                 pci_write_config_dword(pdev, cfg_addr+0x10, val);
 196 }
 197
 198 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
 199 {
 200         struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
 201         u32 val, val2 = 0;
 202         u8 pmr;
 203
 204         if (sc_reg > SCR_CONTROL)
 205                 return 0xffffffffU;
 206
 207         if (ap->flags & SIS_FLAG_CFGSCR)
 208                 return sis_scr_cfg_read(ap, sc_reg);
 209
 210         pci_read_config_byte(pdev, SIS_PMR, &pmr);
 211
 212         val = inl(ap->ioaddr.scr_addr + (sc_reg * 4));
 213
 214         if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
 215                 val2 = inl(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10);
 216
 217         return val | val2;
 218 }
 219
 220 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
 221 {
 222         struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
 223         u8 pmr;
 224
 225         if (sc_reg > SCR_CONTROL)
 226                 return;
 227
 228         pci_read_config_byte(pdev, SIS_PMR, &pmr);
 229
 230         if (ap->flags & SIS_FLAG_CFGSCR)
 231                 sis_scr_cfg_write(ap, sc_reg, val);
 232         else {
 233                 outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
 234                 if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
 235                         outl(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
 236         }
 237 }
 238
 239 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
 240 {
 241         static int printed_version;
 242         struct ata_probe_ent *probe_ent = NULL;
 243         int rc;
 244         u32 genctl;
 245         struct ata_port_info *ppi;
 246         int pci_dev_busy = 0;
 247         u8 pmr;
 248         u8 port2_start;
 249
 250         if (!printed_version++)
 251                 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
 252
 253         rc = pci_enable_device(pdev);
 254         if (rc)
 255                 return rc;
 256
 257         rc = pci_request_regions(pdev, DRV_NAME);
 258         if (rc) {
 259                 pci_dev_busy = 1;
 260                 goto err_out;
 261         }
 262
 263         rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
 264         if (rc)
 265                 goto err_out_regions;
 266         rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
 267         if (rc)
 268                 goto err_out_regions;
 269
 270         ppi = &sis_port_info;
 271         probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
 272         if (!probe_ent) {
 273                 rc = -ENOMEM;
 274                 goto err_out_regions;
 275         }
 276
 277         /* check and see if the SCRs are in IO space or PCI cfg space */
 278         pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
 279         if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
 280                 probe_ent->host_flags |= SIS_FLAG_CFGSCR;
 281
 282         /* if hardware thinks SCRs are in IO space, but there are
 283          * no IO resources assigned, change to PCI cfg space.
 284          */
 285         if ((!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) &&
 286             ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
 287              (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
 288                 genctl &= ~GENCTL_IOMAPPED_SCR;
 289                 pci_write_config_dword(pdev, SIS_GENCTL, genctl);
 290                 probe_ent->host_flags |= SIS_FLAG_CFGSCR;
 291         }
 292
 293         pci_read_config_byte(pdev, SIS_PMR, &pmr);
 294         if (ent->device != 0x182) {
 295                 if ((pmr & SIS_PMR_COMBINED) == 0) {
 296                         dev_printk(KERN_INFO, &pdev->dev,
 297                                    "Detected SiS 180/181 chipset in SATA mode\n");
 298                         port2_start = 64;
 299                 }
 300                 else {
 301                         dev_printk(KERN_INFO, &pdev->dev,
 302                                    "Detected SiS 180/181 chipset in combined mode\n");
 303                         port2_start=0;
 304                 }
 305         }
 306         else {
 307                 dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182 chipset\n");
 308                 port2_start = 0x20;
 309         }
 310
 311         if (!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) {
 312                 probe_ent->port[0].scr_addr =
 313                         pci_resource_start(pdev, SIS_SCR_PCI_BAR);
 314                 probe_ent->port[1].scr_addr =
 315                         pci_resource_start(pdev, SIS_SCR_PCI_BAR) + port2_start;
 316         }
 317
 318         pci_set_master(pdev);
 319         pci_intx(pdev, 1);
 320
 321         /* FIXME: check ata_device_add return value */
 322         ata_device_add(probe_ent);
 323         kfree(probe_ent);
 324
 325         return 0;
 326
 327 err_out_regions:
 328         pci_release_regions(pdev);
 329
 330 err_out:
 331         if (!pci_dev_busy)
 332                 pci_disable_device(pdev);
 333         return rc;
 334
 335 }
 336
 337 static int __init sis_init(void)
 338 {
 339         return pci_module_init(&sis_pci_driver);
 340 }
 341
 342 static void __exit sis_exit(void)
 343 {
 344         pci_unregister_driver(&sis_pci_driver);
 345 }
 346
 347 module_init(sis_init);
 348 module_exit(sis_exit);
 349