2 # DMA engine configuration
6 bool "DMA Engine support"
9 DMA engines can do asynchronous data transfers without
10 involving the host CPU. Currently, this framework can be
11 used to offload memory copies in the network stack and
12 RAID operations in the MD driver. This menu only presents
13 DMA Device drivers supported by the configured arch, it may
14 be empty in some cases.
20 config ASYNC_TX_DISABLE_CHANNEL_SWITCH
24 tristate "Intel I/OAT DMA support"
28 select ASYNC_TX_DISABLE_CHANNEL_SWITCH
29 select ASYNC_TX_DISABLE_PQ_VAL_DMA
30 select ASYNC_TX_DISABLE_XOR_VAL_DMA
32 Enable support for the Intel(R) I/OAT DMA engine present
33 in recent Intel Xeon chipsets.
35 Say Y here if you have such a chipset.
40 tristate "Intel IOP ADMA support"
41 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
44 Enable support for the Intel(R) IOP Series RAID engines.
47 tristate "Synopsys DesignWare AHB DMA support"
50 default y if CPU_AT32AP7000
52 Support the Synopsys DesignWare AHB DMA controller. This
53 can be integrated in chips such as the Atmel AT32ap7000.
56 tristate "Atmel AHB DMA support"
57 depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
60 Support the Atmel AHB DMA controller. This can be integrated in
61 chips such as the Atmel AT91SAM9RL.
64 tristate "Freescale Elo and Elo Plus DMA support"
68 Enable support for the Freescale Elo and Elo Plus DMA controllers.
69 The Elo is the DMA controller on some 82xx and 83xx parts, and the
70 Elo Plus is the DMA controller on 85xx and 86xx parts.
73 bool "Marvell XOR engine support"
77 Enable support for the Marvell XOR engine.
80 bool "MX3x Image Processing Unit support"
85 If you plan to use the Image Processing unit in the i.MX3x, say
86 Y here. If unsure, select Y.
89 int "Number of dynamically mapped interrupts for IPU"
94 Out of 137 interrupt sources on i.MX31 IPU only very few are used.
95 To avoid bloating the irq_desc[] array we allocate a sufficient
96 number of IRQ slots and map them dynamically to specific sources.
99 tristate "Toshiba TXx9 SoC DMA support"
100 depends on MACH_TX49XX || MACH_TX39XX
103 Support the TXx9 SoC internal DMA controller. This can be
104 integrated in chips such as the Toshiba TX4927/38/39.
107 tristate "Renesas SuperH DMAC support"
108 depends on SUPERH && SH_DMA
109 depends on !SH_DMA_API
112 Enable support for the Renesas SuperH DMA controllers.
115 bool "ST-Ericsson COH901318 DMA support"
119 Enable support for ST-Ericsson COH 901 318 DMA.
121 config AMCC_PPC440SPE_ADMA
122 tristate "AMCC PPC440SPe ADMA support"
123 depends on 440SPe || 440SP
125 select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
127 Enable support for the AMCC PPC440SPe RAID engines.
129 config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
135 comment "DMA Clients"
136 depends on DMA_ENGINE
139 bool "Network: TCP receive copy offload"
140 depends on DMA_ENGINE && NET
141 default (INTEL_IOATDMA || FSL_DMA)
143 This enables the use of DMA engines in the network stack to
144 offload receive copy-to-user operations, freeing CPU cycles.
146 Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
150 bool "Async_tx: Offload support for the async_tx api"
151 depends on DMA_ENGINE
153 This allows the async_tx api to take advantage of offload engines for
154 memcpy, memset, xor, and raid6 p+q operations. If your platform has
155 a dma engine that can perform raid operations and you have enabled
161 tristate "DMA Test client"
162 depends on DMA_ENGINE
164 Simple DMA test client. Say N unless you're debugging a