drivers/video/geode/lxfb.h

   1 #ifndef _LXFB_H_
   2 #define _LXFB_H_
   3
   4 #include <linux/fb.h>
   5
   6 #define GP_REG_COUNT    (0x7c / 4)
   7 #define DC_REG_COUNT    (0xf0 / 4)
   8 #define VP_REG_COUNT    (0x158 / 8)
   9 #define FP_REG_COUNT    (0x60 / 8)
  10
  11 #define DC_PAL_COUNT    0x104
  12 #define DC_HFILT_COUNT  0x100
  13 #define DC_VFILT_COUNT  0x100
  14 #define VP_COEFF_SIZE   0x1000
  15
  16 #define OUTPUT_CRT   0x01
  17 #define OUTPUT_PANEL 0x02
  18
  19 struct lxfb_par {
  20         int output;
  21
  22         void __iomem *gp_regs;
  23         void __iomem *dc_regs;
  24         void __iomem *vp_regs;
  25 #ifdef CONFIG_PM
  26         int powered_down;
  27
  28         /* register state, for power mgmt functionality */
  29         struct {
  30                 uint64_t padsel;
  31                 uint64_t dotpll;
  32                 uint64_t dfglcfg;
  33                 uint64_t dcspare;
  34         } msr;
  35
  36         uint32_t gp[GP_REG_COUNT];
  37         uint32_t dc[DC_REG_COUNT];
  38         uint64_t vp[VP_REG_COUNT];
  39         uint64_t fp[FP_REG_COUNT];
  40
  41         uint32_t pal[DC_PAL_COUNT];
  42         uint32_t hcoeff[DC_HFILT_COUNT * 2];
  43         uint32_t vcoeff[DC_VFILT_COUNT];
  44         uint32_t vp_coeff[VP_COEFF_SIZE / 4];
  45 #endif
  46 };
  47
  48 static inline unsigned int lx_get_pitch(unsigned int xres, int bpp)
  49 {
  50         return (((xres * (bpp >> 3)) + 7) & ~7);
  51 }
  52
  53 void lx_set_mode(struct fb_info *);
  54 unsigned int lx_framebuffer_size(void);
  55 int lx_blank_display(struct fb_info *, int);
  56 void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int,
  57                         unsigned int, unsigned int);
  58
  59 #ifdef CONFIG_PM
  60 int lx_powerdown(struct fb_info *info);
  61 int lx_powerup(struct fb_info *info);
  62 #endif
  63
  64
  65 /* Graphics Processor registers (table 6-29 from the data book) */
  66 enum gp_registers {
  67         GP_DST_OFFSET = 0,
  68         GP_SRC_OFFSET,
  69         GP_STRIDE,
  70         GP_WID_HEIGHT,
  71
  72         GP_SRC_COLOR_FG,
  73         GP_SRC_COLOR_BG,
  74         GP_PAT_COLOR_0,
  75         GP_PAT_COLOR_1,
  76
  77         GP_PAT_COLOR_2,
  78         GP_PAT_COLOR_3,
  79         GP_PAT_COLOR_4,
  80         GP_PAT_COLOR_5,
  81
  82         GP_PAT_DATA_0,
  83         GP_PAT_DATA_1,
  84         GP_RASTER_MODE,
  85         GP_VECTOR_MODE,
  86
  87         GP_BLT_MODE,
  88         GP_BLT_STATUS,
  89         GP_HST_SRC,
  90         GP_BASE_OFFSET,
  91
  92         GP_CMD_TOP,
  93         GP_CMD_BOT,
  94         GP_CMD_READ,
  95         GP_CMD_WRITE,
  96
  97         GP_CH3_OFFSET,
  98         GP_CH3_MODE_STR,
  99         GP_CH3_WIDHI,
 100         GP_CH3_HSRC,
 101
 102         GP_LUT_INDEX,
 103         GP_LUT_DATA,
 104         GP_INT_CNTRL, /* 0x78 */
 105 };
 106
 107 #define GP_BLT_STATUS_CE                (1 << 4)        /* cmd buf empty */
 108 #define GP_BLT_STATUS_PB                (1 << 0)        /* primative busy */
 109
 110
 111 /* Display Controller registers (table 6-47 from the data book) */
 112 enum dc_registers {
 113         DC_UNLOCK = 0,
 114         DC_GENERAL_CFG,
 115         DC_DISPLAY_CFG,
 116         DC_ARB_CFG,
 117
 118         DC_FB_ST_OFFSET,
 119         DC_CB_ST_OFFSET,
 120         DC_CURS_ST_OFFSET,
 121         DC_RSVD_0,
 122
 123         DC_VID_Y_ST_OFFSET,
 124         DC_VID_U_ST_OFFSET,
 125         DC_VID_V_ST_OFFSET,
 126         DC_DV_TOP,
 127
 128         DC_LINE_SIZE,
 129         DC_GFX_PITCH,
 130         DC_VID_YUV_PITCH,
 131         DC_RSVD_1,
 132
 133         DC_H_ACTIVE_TIMING,
 134         DC_H_BLANK_TIMING,
 135         DC_H_SYNC_TIMING,
 136         DC_RSVD_2,
 137
 138         DC_V_ACTIVE_TIMING,
 139         DC_V_BLANK_TIMING,
 140         DC_V_SYNC_TIMING,
 141         DC_FB_ACTIVE,
 142
 143         DC_CURSOR_X,
 144         DC_CURSOR_Y,
 145         DC_RSVD_3,
 146         DC_LINE_CNT,
 147
 148         DC_PAL_ADDRESS,
 149         DC_PAL_DATA,
 150         DC_DFIFO_DIAG,
 151         DC_CFIFO_DIAG,
 152
 153         DC_VID_DS_DELTA,
 154         DC_GLIU0_MEM_OFFSET,
 155         DC_DV_CTL,
 156         DC_DV_ACCESS,
 157
 158         DC_GFX_SCALE,
 159         DC_IRQ_FILT_CTL,
 160         DC_FILT_COEFF1,
 161         DC_FILT_COEFF2,
 162
 163         DC_VBI_EVEN_CTL,
 164         DC_VBI_ODD_CTL,
 165         DC_VBI_HOR,
 166         DC_VBI_LN_ODD,
 167
 168         DC_VBI_LN_EVEN,
 169         DC_VBI_PITCH,
 170         DC_CLR_KEY,
 171         DC_CLR_KEY_MASK,
 172
 173         DC_CLR_KEY_X,
 174         DC_CLR_KEY_Y,
 175         DC_IRQ,
 176         DC_RSVD_4,
 177
 178         DC_RSVD_5,
 179         DC_GENLK_CTL,
 180         DC_VID_EVEN_Y_ST_OFFSET,
 181         DC_VID_EVEN_U_ST_OFFSET,
 182
 183         DC_VID_EVEN_V_ST_OFFSET,
 184         DC_V_ACTIVE_EVEN_TIMING,
 185         DC_V_BLANK_EVEN_TIMING,
 186         DC_V_SYNC_EVEN_TIMING,  /* 0xec */
 187 };
 188
 189 #define DC_UNLOCK_LOCK                  0x00000000
 190 #define DC_UNLOCK_UNLOCK                0x00004758      /* magic value */
 191
 192 #define DC_GENERAL_CFG_FDTY             (1 << 17)
 193 #define DC_GENERAL_CFG_DFHPEL_SHIFT     (12)
 194 #define DC_GENERAL_CFG_DFHPSL_SHIFT     (8)
 195 #define DC_GENERAL_CFG_VGAE             (1 << 7)
 196 #define DC_GENERAL_CFG_DECE             (1 << 6)
 197 #define DC_GENERAL_CFG_CMPE             (1 << 5)
 198 #define DC_GENERAL_CFG_VIDE             (1 << 3)
 199 #define DC_GENERAL_CFG_DFLE             (1 << 0)
 200
 201 #define DC_DISPLAY_CFG_VISL             (1 << 27)
 202 #define DC_DISPLAY_CFG_PALB             (1 << 25)
 203 #define DC_DISPLAY_CFG_DCEN             (1 << 24)
 204 #define DC_DISPLAY_CFG_DISP_MODE_24BPP  (1 << 9)
 205 #define DC_DISPLAY_CFG_DISP_MODE_16BPP  (1 << 8)
 206 #define DC_DISPLAY_CFG_DISP_MODE_8BPP   (0)
 207 #define DC_DISPLAY_CFG_TRUP             (1 << 6)
 208 #define DC_DISPLAY_CFG_VDEN             (1 << 4)
 209 #define DC_DISPLAY_CFG_GDEN             (1 << 3)
 210 #define DC_DISPLAY_CFG_TGEN             (1 << 0)
 211
 212 #define DC_DV_TOP_DV_TOP_EN             (1 << 0)
 213
 214 #define DC_DV_CTL_DV_LINE_SIZE          ((1 << 10) | (1 << 11))
 215 #define DC_DV_CTL_DV_LINE_SIZE_1K       (0)
 216 #define DC_DV_CTL_DV_LINE_SIZE_2K       (1 << 10)
 217 #define DC_DV_CTL_DV_LINE_SIZE_4K       (1 << 11)
 218 #define DC_DV_CTL_DV_LINE_SIZE_8K       ((1 << 10) | (1 << 11))
 219 #define DC_DV_CTL_CLEAR_DV_RAM          (1 << 0)
 220
 221 #define DC_IRQ_FILT_CTL_H_FILT_SEL      (1 << 10)
 222
 223 #define DC_CLR_KEY_CLR_KEY_EN           (1 << 24)
 224
 225 #define DC_IRQ_VIP_VSYNC_IRQ_STATUS     (1 << 21)       /* undocumented? */
 226 #define DC_IRQ_STATUS                   (1 << 20)       /* undocumented? */
 227 #define DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK  (1 << 1)
 228 #define DC_IRQ_MASK                     (1 << 0)
 229
 230 #define DC_GENLK_CTL_FLICK_SEL_MASK     (0x0F << 28)
 231 #define DC_GENLK_CTL_ALPHA_FLICK_EN     (1 << 25)
 232 #define DC_GENLK_CTL_FLICK_EN           (1 << 24)
 233 #define DC_GENLK_CTL_GENLK_EN           (1 << 18)
 234
 235
 236 /*
 237  * Video Processor registers (table 6-71).
 238  * There is space for 64 bit values, but we never use more than the
 239  * lower 32 bits.  The actual register save/restore code only bothers
 240  * to restore those 32 bits.
 241  */
 242 enum vp_registers {
 243         VP_VCFG = 0,
 244         VP_DCFG,
 245
 246         VP_VX,
 247         VP_VY,
 248
 249         VP_SCL,
 250         VP_VCK,
 251
 252         VP_VCM,
 253         VP_PAR,
 254
 255         VP_PDR,
 256         VP_SLR,
 257
 258         VP_MISC,
 259         VP_CCS,
 260
 261         VP_VYS,
 262         VP_VXS,
 263
 264         VP_RSVD_0,
 265         VP_VDC,
 266
 267         VP_RSVD_1,
 268         VP_CRC,
 269
 270         VP_CRC32,
 271         VP_VDE,
 272
 273         VP_CCK,
 274         VP_CCM,
 275
 276         VP_CC1,
 277         VP_CC2,
 278
 279         VP_A1X,
 280         VP_A1Y,
 281
 282         VP_A1C,
 283         VP_A1T,
 284
 285         VP_A2X,
 286         VP_A2Y,
 287
 288         VP_A2C,
 289         VP_A2T,
 290
 291         VP_A3X,
 292         VP_A3Y,
 293
 294         VP_A3C,
 295         VP_A3T,
 296
 297         VP_VRR,
 298         VP_AWT,
 299
 300         VP_VTM,
 301         VP_VYE,
 302
 303         VP_A1YE,
 304         VP_A2YE,
 305
 306         VP_A3YE,        /* 0x150 */
 307
 308         VP_VCR = 0x1000, /* 0x1000 - 0x1fff */
 309 };
 310
 311 #define VP_VCFG_VID_EN                  (1 << 0)
 312
 313 #define VP_DCFG_GV_GAM                  (1 << 21)
 314 #define VP_DCFG_PWR_SEQ_DELAY           ((1 << 17) | (1 << 18) | (1 << 19))
 315 #define VP_DCFG_PWR_SEQ_DELAY_DEFAULT   (1 << 19)       /* undocumented */
 316 #define VP_DCFG_CRT_SYNC_SKW            ((1 << 14) | (1 << 15) | (1 << 16))
 317 #define VP_DCFG_CRT_SYNC_SKW_DEFAULT    (1 << 16)
 318 #define VP_DCFG_CRT_VSYNC_POL           (1 << 9)
 319 #define VP_DCFG_CRT_HSYNC_POL           (1 << 8)
 320 #define VP_DCFG_DAC_BL_EN               (1 << 3)
 321 #define VP_DCFG_VSYNC_EN                (1 << 2)
 322 #define VP_DCFG_HSYNC_EN                (1 << 1)
 323 #define VP_DCFG_CRT_EN                  (1 << 0)
 324
 325 #define VP_MISC_APWRDN                  (1 << 11)
 326 #define VP_MISC_DACPWRDN                (1 << 10)
 327 #define VP_MISC_BYP_BOTH                (1 << 0)
 328
 329
 330 /*
 331  * Flat Panel registers (table 6-71).
 332  * Also 64 bit registers; see above note about 32-bit handling.
 333  */
 334
 335 /* we're actually in the VP register space, starting at address 0x400 */
 336 #define VP_FP_START     0x400
 337
 338 enum fp_registers {
 339         FP_PT1 = 0,
 340         FP_PT2,
 341
 342         FP_PM,
 343         FP_DFC,
 344
 345         FP_RSVD_0,
 346         FP_RSVD_1,
 347
 348         FP_RSVD_2,
 349         FP_RSVD_3,
 350
 351         FP_RSVD_4,
 352         FP_DCA,
 353
 354         FP_DMD,
 355         FP_CRC, /* 0x458 */
 356 };
 357
 358 #define FP_PT2_SCRC                     (1 << 27)       /* shfclk free */
 359
 360 #define FP_PM_P                         (1 << 24)       /* panel power ctl */
 361 #define FP_PM_PANEL_PWR_UP              (1 << 3)        /* r/o */
 362 #define FP_PM_PANEL_PWR_DOWN            (1 << 2)        /* r/o */
 363 #define FP_PM_PANEL_OFF                 (1 << 1)        /* r/o */
 364 #define FP_PM_PANEL_ON                  (1 << 0)        /* r/o */
 365
 366 #define FP_DFC_BC                       ((1 << 4) | (1 << 5) | (1 << 6))
 367
 368
 369 /* register access functions */
 370
 371 static inline uint32_t read_gp(struct lxfb_par *par, int reg)
 372 {
 373         return readl(par->gp_regs + 4*reg);
 374 }
 375
 376 static inline void write_gp(struct lxfb_par *par, int reg, uint32_t val)
 377 {
 378         writel(val, par->gp_regs + 4*reg);
 379 }
 380
 381 static inline uint32_t read_dc(struct lxfb_par *par, int reg)
 382 {
 383         return readl(par->dc_regs + 4*reg);
 384 }
 385
 386 static inline void write_dc(struct lxfb_par *par, int reg, uint32_t val)
 387 {
 388         writel(val, par->dc_regs + 4*reg);
 389 }
 390
 391 static inline uint32_t read_vp(struct lxfb_par *par, int reg)
 392 {
 393         return readl(par->vp_regs + 8*reg);
 394 }
 395
 396 static inline void write_vp(struct lxfb_par *par, int reg, uint32_t val)
 397 {
 398         writel(val, par->vp_regs + 8*reg);
 399 }
 400
 401 static inline uint32_t read_fp(struct lxfb_par *par, int reg)
 402 {
 403         return readl(par->vp_regs + 8*reg + VP_FP_START);
 404 }
 405
 406 static inline void write_fp(struct lxfb_par *par, int reg, uint32_t val)
 407 {
 408         writel(val, par->vp_regs + 8*reg + VP_FP_START);
 409 }
 410
 411
 412 /* MSRs are defined in asm/geode.h; their bitfields are here */
 413
 414 #define MSR_GLCP_DOTPLL_LOCK            (1 << 25)       /* r/o */
 415 #define MSR_GLCP_DOTPLL_HALFPIX         (1 << 24)
 416 #define MSR_GLCP_DOTPLL_BYPASS          (1 << 15)
 417 #define MSR_GLCP_DOTPLL_DOTRESET        (1 << 0)
 418
 419 /* note: this is actually the VP's GLD_MSR_CONFIG */
 420 #define MSR_LX_GLD_MSR_CONFIG_FMT       ((1 << 3) | (1 << 4) | (1 << 5))
 421 #define MSR_LX_GLD_MSR_CONFIG_FMT_FP    (1 << 3)
 422 #define MSR_LX_GLD_MSR_CONFIG_FMT_CRT   (0)
 423 #define MSR_LX_GLD_MSR_CONFIG_FPC       (1 << 15)       /* FP *and* CRT */
 424
 425 #define MSR_LX_MSR_PADSEL_TFT_SEL_LOW   0xDFFFFFFF      /* ??? */
 426 #define MSR_LX_MSR_PADSEL_TFT_SEL_HIGH  0x0000003F      /* ??? */
 427
 428 #define MSR_LX_SPARE_MSR_DIS_CFIFO_HGO  (1 << 11)       /* undocumented */
 429 #define MSR_LX_SPARE_MSR_VFIFO_ARB_SEL  (1 << 10)       /* undocumented */
 430 #define MSR_LX_SPARE_MSR_WM_LPEN_OVRD   (1 << 9)        /* undocumented */
 431 #define MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M (1 << 8)        /* undocumented */
 432 #define MSR_LX_SPARE_MSR_DIS_INIT_V_PRI (1 << 7)        /* undocumented */
 433 #define MSR_LX_SPARE_MSR_DIS_VIFO_WM    (1 << 6)
 434 #define MSR_LX_SPARE_MSR_DIS_CWD_CHECK  (1 << 5)        /* undocumented */
 435 #define MSR_LX_SPARE_MSR_PIX8_PAN_FIX   (1 << 4)        /* undocumented */
 436 #define MSR_LX_SPARE_MSR_FIRST_REQ_MASK (1 << 1)        /* undocumented */
 437
 438 #endif