ACPICA: Add function to handle PM1 control registers
[linux-2.6/x86.git] / drivers / acpi / acpica / hwregs.c
blobedc627c9fc0d5e3340e3a61d762c2b59471f6999
2 /*******************************************************************************
4 * Module Name: hwregs - Read/write access functions for the various ACPI
5 * control and status registers.
7 ******************************************************************************/
9 /*
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46 #include <acpi/acpi.h>
47 #include "accommon.h"
48 #include "acnamesp.h"
49 #include "acevents.h"
51 #define _COMPONENT ACPI_HARDWARE
52 ACPI_MODULE_NAME("hwregs")
54 /* Local Prototypes */
55 static acpi_status
56 acpi_hw_read_multiple(u32 *value,
57 struct acpi_generic_address *register_a,
58 struct acpi_generic_address *register_b);
60 static acpi_status
61 acpi_hw_write_multiple(u32 value,
62 struct acpi_generic_address *register_a,
63 struct acpi_generic_address *register_b);
65 /*******************************************************************************
67 * FUNCTION: acpi_hw_clear_acpi_status
69 * PARAMETERS: None
71 * RETURN: Status
73 * DESCRIPTION: Clears all fixed and general purpose status bits
75 ******************************************************************************/
77 acpi_status acpi_hw_clear_acpi_status(void)
79 acpi_status status;
80 acpi_cpu_flags lock_flags = 0;
82 ACPI_FUNCTION_TRACE(hw_clear_acpi_status);
84 ACPI_DEBUG_PRINT((ACPI_DB_IO, "About to write %04X to %0llX\n",
85 ACPI_BITMASK_ALL_FIXED_STATUS,
86 acpi_gbl_xpm1a_status.address));
88 lock_flags = acpi_os_acquire_lock(acpi_gbl_hardware_lock);
90 /* Clear the fixed events in PM1 A/B */
92 status = acpi_hw_register_write(ACPI_REGISTER_PM1_STATUS,
93 ACPI_BITMASK_ALL_FIXED_STATUS);
94 if (ACPI_FAILURE(status)) {
95 goto unlock_and_exit;
98 /* Clear the GPE Bits in all GPE registers in all GPE blocks */
100 status = acpi_ev_walk_gpe_list(acpi_hw_clear_gpe_block, NULL);
102 unlock_and_exit:
103 acpi_os_release_lock(acpi_gbl_hardware_lock, lock_flags);
104 return_ACPI_STATUS(status);
107 /*******************************************************************************
109 * FUNCTION: acpi_hw_get_register_bit_mask
111 * PARAMETERS: register_id - Index of ACPI Register to access
113 * RETURN: The bitmask to be used when accessing the register
115 * DESCRIPTION: Map register_id into a register bitmask.
117 ******************************************************************************/
119 struct acpi_bit_register_info *acpi_hw_get_bit_register_info(u32 register_id)
121 ACPI_FUNCTION_ENTRY();
123 if (register_id > ACPI_BITREG_MAX) {
124 ACPI_ERROR((AE_INFO, "Invalid BitRegister ID: %X",
125 register_id));
126 return (NULL);
129 return (&acpi_gbl_bit_register_info[register_id]);
132 /******************************************************************************
134 * FUNCTION: acpi_hw_write_pm1_control
136 * PARAMETERS: pm1a_control - Value to be written to PM1A control
137 * pm1b_control - Value to be written to PM1B control
139 * RETURN: Status
141 * DESCRIPTION: Write the PM1 A/B control registers. These registers are
142 * different than than the PM1 A/B status and enable registers
143 * in that different values can be written to the A/B registers.
144 * Most notably, the SLP_TYP bits can be different, as per the
145 * values returned from the _Sx predefined methods.
147 ******************************************************************************/
149 acpi_status acpi_hw_write_pm1_control(u32 pm1a_control, u32 pm1b_control)
151 acpi_status status;
153 ACPI_FUNCTION_TRACE(hw_write_pm1_control);
155 status = acpi_write(pm1a_control, &acpi_gbl_FADT.xpm1a_control_block);
156 if (ACPI_FAILURE(status)) {
157 return_ACPI_STATUS(status);
160 if (acpi_gbl_FADT.xpm1b_control_block.address) {
161 status =
162 acpi_write(pm1b_control,
163 &acpi_gbl_FADT.xpm1b_control_block);
165 return_ACPI_STATUS(status);
168 /******************************************************************************
170 * FUNCTION: acpi_hw_register_read
172 * PARAMETERS: register_id - ACPI Register ID
173 * return_value - Where the register value is returned
175 * RETURN: Status and the value read.
177 * DESCRIPTION: Read from the specified ACPI register
179 ******************************************************************************/
180 acpi_status
181 acpi_hw_register_read(u32 register_id, u32 * return_value)
183 u32 value = 0;
184 acpi_status status;
186 ACPI_FUNCTION_TRACE(hw_register_read);
188 switch (register_id) {
189 case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
191 status = acpi_hw_read_multiple(&value,
192 &acpi_gbl_xpm1a_status,
193 &acpi_gbl_xpm1b_status);
194 break;
196 case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */
198 status = acpi_hw_read_multiple(&value,
199 &acpi_gbl_xpm1a_enable,
200 &acpi_gbl_xpm1b_enable);
201 break;
203 case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
205 status = acpi_hw_read_multiple(&value,
206 &acpi_gbl_FADT.
207 xpm1a_control_block,
208 &acpi_gbl_FADT.
209 xpm1b_control_block);
210 break;
212 case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
214 status = acpi_read(&value, &acpi_gbl_FADT.xpm2_control_block);
215 break;
217 case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
219 status = acpi_read(&value, &acpi_gbl_FADT.xpm_timer_block);
220 break;
222 case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
224 status =
225 acpi_os_read_port(acpi_gbl_FADT.smi_command, &value, 8);
226 break;
228 default:
229 ACPI_ERROR((AE_INFO, "Unknown Register ID: %X", register_id));
230 status = AE_BAD_PARAMETER;
231 break;
234 if (ACPI_SUCCESS(status)) {
235 *return_value = value;
238 return_ACPI_STATUS(status);
241 /******************************************************************************
243 * FUNCTION: acpi_hw_register_write
245 * PARAMETERS: register_id - ACPI Register ID
246 * Value - The value to write
248 * RETURN: Status
250 * DESCRIPTION: Write to the specified ACPI register
252 * NOTE: In accordance with the ACPI specification, this function automatically
253 * preserves the value of the following bits, meaning that these bits cannot be
254 * changed via this interface:
256 * PM1_CONTROL[0] = SCI_EN
257 * PM1_CONTROL[9]
258 * PM1_STATUS[11]
260 * ACPI References:
261 * 1) Hardware Ignored Bits: When software writes to a register with ignored
262 * bit fields, it preserves the ignored bit fields
263 * 2) SCI_EN: OSPM always preserves this bit position
265 ******************************************************************************/
267 acpi_status acpi_hw_register_write(u32 register_id, u32 value)
269 acpi_status status;
270 u32 read_value;
272 ACPI_FUNCTION_TRACE(hw_register_write);
274 switch (register_id) {
275 case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
277 /* Perform a read first to preserve certain bits (per ACPI spec) */
279 status = acpi_hw_read_multiple(&read_value,
280 &acpi_gbl_xpm1a_status,
281 &acpi_gbl_xpm1b_status);
282 if (ACPI_FAILURE(status)) {
283 goto exit;
286 /* Insert the bits to be preserved */
288 ACPI_INSERT_BITS(value, ACPI_PM1_STATUS_PRESERVED_BITS,
289 read_value);
291 /* Now we can write the data */
293 status = acpi_hw_write_multiple(value,
294 &acpi_gbl_xpm1a_status,
295 &acpi_gbl_xpm1b_status);
296 break;
298 case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access */
300 status = acpi_hw_write_multiple(value,
301 &acpi_gbl_xpm1a_enable,
302 &acpi_gbl_xpm1b_enable);
303 break;
305 case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
308 * Perform a read first to preserve certain bits (per ACPI spec)
309 * Note: This includes SCI_EN, we never want to change this bit
311 status = acpi_hw_read_multiple(&read_value,
312 &acpi_gbl_FADT.
313 xpm1a_control_block,
314 &acpi_gbl_FADT.
315 xpm1b_control_block);
316 if (ACPI_FAILURE(status)) {
317 goto exit;
320 /* Insert the bits to be preserved */
322 ACPI_INSERT_BITS(value, ACPI_PM1_CONTROL_PRESERVED_BITS,
323 read_value);
325 /* Now we can write the data */
327 status = acpi_hw_write_multiple(value,
328 &acpi_gbl_FADT.
329 xpm1a_control_block,
330 &acpi_gbl_FADT.
331 xpm1b_control_block);
332 break;
334 case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
336 status = acpi_write(value, &acpi_gbl_FADT.xpm2_control_block);
337 break;
339 case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
341 status = acpi_write(value, &acpi_gbl_FADT.xpm_timer_block);
342 break;
344 case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
346 /* SMI_CMD is currently always in IO space */
348 status =
349 acpi_os_write_port(acpi_gbl_FADT.smi_command, value, 8);
350 break;
352 default:
353 ACPI_ERROR((AE_INFO, "Unknown Register ID: %X", register_id));
354 status = AE_BAD_PARAMETER;
355 break;
358 exit:
359 return_ACPI_STATUS(status);
362 /******************************************************************************
364 * FUNCTION: acpi_hw_read_multiple
366 * PARAMETERS: Value - Where the register value is returned
367 * register_a - First ACPI register (required)
368 * register_b - Second ACPI register (optional)
370 * RETURN: Status
372 * DESCRIPTION: Read from the specified two-part ACPI register (such as PM1 A/B)
374 ******************************************************************************/
376 static acpi_status
377 acpi_hw_read_multiple(u32 *value,
378 struct acpi_generic_address *register_a,
379 struct acpi_generic_address *register_b)
381 u32 value_a = 0;
382 u32 value_b = 0;
383 acpi_status status;
385 /* The first register is always required */
387 status = acpi_read(&value_a, register_a);
388 if (ACPI_FAILURE(status)) {
389 return (status);
392 /* Second register is optional */
394 if (register_b->address) {
395 status = acpi_read(&value_b, register_b);
396 if (ACPI_FAILURE(status)) {
397 return (status);
402 * OR the two return values together. No shifting or masking is necessary,
403 * because of how the PM1 registers are defined in the ACPI specification:
405 * "Although the bits can be split between the two register blocks (each
406 * register block has a unique pointer within the FADT), the bit positions
407 * are maintained. The register block with unimplemented bits (that is,
408 * those implemented in the other register block) always returns zeros,
409 * and writes have no side effects"
411 *value = (value_a | value_b);
412 return (AE_OK);
415 /******************************************************************************
417 * FUNCTION: acpi_hw_write_multiple
419 * PARAMETERS: Value - The value to write
420 * register_a - First ACPI register (required)
421 * register_b - Second ACPI register (optional)
423 * RETURN: Status
425 * DESCRIPTION: Write to the specified two-part ACPI register (such as PM1 A/B)
427 ******************************************************************************/
429 static acpi_status
430 acpi_hw_write_multiple(u32 value,
431 struct acpi_generic_address *register_a,
432 struct acpi_generic_address *register_b)
434 acpi_status status;
436 /* The first register is always required */
438 status = acpi_write(value, register_a);
439 if (ACPI_FAILURE(status)) {
440 return (status);
444 * Second register is optional
446 * No bit shifting or clearing is necessary, because of how the PM1
447 * registers are defined in the ACPI specification:
449 * "Although the bits can be split between the two register blocks (each
450 * register block has a unique pointer within the FADT), the bit positions
451 * are maintained. The register block with unimplemented bits (that is,
452 * those implemented in the other register block) always returns zeros,
453 * and writes have no side effects"
455 if (register_b->address) {
456 status = acpi_write(value, register_b);
459 return (status);