3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_mac.c - All code and routines pertaining to the MAC
13 *------------------------------------------------------------------------------
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
22 * Copyright © 2005 Agere Systems Inc.
23 * All rights reserved.
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
43 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
47 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
51 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
58 #include "et131x_version.h"
59 #include "et131x_defs.h"
61 #include <linux/init.h>
62 #include <linux/module.h>
63 #include <linux/types.h>
64 #include <linux/kernel.h>
66 #include <linux/sched.h>
67 #include <linux/ptrace.h>
68 #include <linux/slab.h>
69 #include <linux/ctype.h>
70 #include <linux/string.h>
71 #include <linux/timer.h>
72 #include <linux/interrupt.h>
74 #include <linux/delay.h>
76 #include <linux/bitops.h>
77 #include <linux/pci.h>
78 #include <asm/system.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/if_arp.h>
84 #include <linux/ioport.h>
85 #include <linux/crc32.h>
87 #include "et1310_phy.h"
88 #include "et1310_pm.h"
89 #include "et1310_jagcore.h"
90 #include "et1310_mac.h"
92 #include "et131x_adapter.h"
93 #include "et131x_initpci.h"
96 * ConfigMacRegs1 - Initialize the first part of MAC regs
97 * @pAdpater: pointer to our adapter structure
99 void ConfigMACRegs1(struct et131x_adapter
*etdev
)
101 struct _MAC_t __iomem
*pMac
= &etdev
->regs
->mac
;
102 MAC_STATION_ADDR1_t station1
;
103 MAC_STATION_ADDR2_t station2
;
106 MII_MGMT_CFG_t mii_mgmt_cfg
;
108 /* First we need to reset everything. Write to MAC configuration
109 * register 1 to perform reset.
111 writel(0xC00F0000, &pMac
->cfg1
.value
);
113 /* Next lets configure the MAC Inter-packet gap register */
114 ipg
= 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */
115 ipg
|= 0x50 << 8; /* ifg enforce 0x50 */
116 writel(ipg
, &pMac
->ipg
);
118 /* Next lets configure the MAC Half Duplex register */
119 hfdp
.bits
.alt_beb_trunc
= 0xA;
120 hfdp
.bits
.alt_beb_enable
= 0x0;
121 hfdp
.bits
.bp_no_backoff
= 0x0;
122 hfdp
.bits
.no_backoff
= 0x0;
123 hfdp
.bits
.excess_defer
= 0x1;
124 hfdp
.bits
.rexmit_max
= 0xF;
125 hfdp
.bits
.coll_window
= 0x37; /* 55d */
126 writel(hfdp
.value
, &pMac
->hfdp
.value
);
128 /* Next lets configure the MAC Interface Control register */
129 writel(0, &pMac
->if_ctrl
.value
);
131 /* Let's move on to setting up the mii management configuration */
132 mii_mgmt_cfg
.bits
.reset_mii_mgmt
= 0;
133 mii_mgmt_cfg
.bits
.scan_auto_incremt
= 0;
134 mii_mgmt_cfg
.bits
.preamble_suppress
= 0;
135 mii_mgmt_cfg
.bits
.mgmt_clk_reset
= 0x7;
136 writel(mii_mgmt_cfg
.value
, &pMac
->mii_mgmt_cfg
.value
);
138 /* Next lets configure the MAC Station Address register. These
139 * values are read from the EEPROM during initialization and stored
140 * in the adapter structure. We write what is stored in the adapter
141 * structure to the MAC Station Address registers high and low. This
142 * station address is used for generating and checking pause control
145 station2
.bits
.Octet1
= etdev
->CurrentAddress
[0];
146 station2
.bits
.Octet2
= etdev
->CurrentAddress
[1];
147 station1
.bits
.Octet3
= etdev
->CurrentAddress
[2];
148 station1
.bits
.Octet4
= etdev
->CurrentAddress
[3];
149 station1
.bits
.Octet5
= etdev
->CurrentAddress
[4];
150 station1
.bits
.Octet6
= etdev
->CurrentAddress
[5];
151 writel(station1
.value
, &pMac
->station_addr_1
.value
);
152 writel(station2
.value
, &pMac
->station_addr_2
.value
);
154 /* Max ethernet packet in bytes that will passed by the mac without
155 * being truncated. Allow the MAC to pass 4 more than our max packet
156 * size. This is 4 for the Ethernet CRC.
158 * Packets larger than (RegistryJumboPacket) that do not contain a
159 * VLAN ID will be dropped by the Rx function.
161 writel(etdev
->RegistryJumboPacket
+ 4, &pMac
->max_fm_len
.value
);
163 /* clear out MAC config reset */
164 writel(0, &pMac
->cfg1
.value
);
168 * ConfigMacRegs2 - Initialize the second part of MAC regs
169 * @pAdpater: pointer to our adapter structure
171 void ConfigMACRegs2(struct et131x_adapter
*etdev
)
174 struct _MAC_t __iomem
*pMac
= &etdev
->regs
->mac
;
177 MAC_IF_CTRL_t ifctrl
;
180 ctl
.value
= readl(&etdev
->regs
->txmac
.ctl
.value
);
181 cfg1
.value
= readl(&pMac
->cfg1
.value
);
182 cfg2
.value
= readl(&pMac
->cfg2
.value
);
183 ifctrl
.value
= readl(&pMac
->if_ctrl
.value
);
185 if (etdev
->linkspeed
== TRUEPHY_SPEED_1000MBPS
) {
186 cfg2
.bits
.if_mode
= 0x2;
187 ifctrl
.bits
.phy_mode
= 0x0;
189 cfg2
.bits
.if_mode
= 0x1;
190 ifctrl
.bits
.phy_mode
= 0x1;
193 /* We need to enable Rx/Tx */
194 cfg1
.bits
.rx_enable
= 0x1;
195 cfg1
.bits
.tx_enable
= 0x1;
197 /* Set up flow control */
198 cfg1
.bits
.tx_flow
= 0x1;
200 if ((etdev
->FlowControl
== RxOnly
) ||
201 (etdev
->FlowControl
== Both
)) {
202 cfg1
.bits
.rx_flow
= 0x1;
204 cfg1
.bits
.rx_flow
= 0x0;
207 /* Initialize loop back to off */
208 cfg1
.bits
.loop_back
= 0;
210 writel(cfg1
.value
, &pMac
->cfg1
.value
);
212 /* Now we need to initialize the MAC Configuration 2 register */
213 cfg2
.bits
.preamble_len
= 0x7;
214 cfg2
.bits
.huge_frame
= 0x0;
215 /* LENGTH FIELD CHECKING bit4: Set this bit to cause the MAC to check
216 * the frame's length field to ensure it matches the actual data
217 * field length. Clear this bit if no length field checking is
218 * desired. Its default is 0.
220 cfg2
.bits
.len_check
= 0x1;
222 cfg2
.bits
.pad_crc
= 0x1;
223 cfg2
.bits
.crc_enable
= 0x1;
225 /* 1 - full duplex, 0 - half-duplex */
226 cfg2
.bits
.full_duplex
= etdev
->duplex_mode
;
227 ifctrl
.bits
.ghd_mode
= !etdev
->duplex_mode
;
229 writel(ifctrl
.value
, &pMac
->if_ctrl
.value
);
230 writel(cfg2
.value
, &pMac
->cfg2
.value
);
235 cfg1
.value
= readl(&pMac
->cfg1
.value
);
236 } while ((!cfg1
.bits
.syncd_rx_en
|| !cfg1
.bits
.syncd_tx_en
) &&
240 dev_warn(&etdev
->pdev
->dev
,
241 "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
246 ctl
.bits
.txmac_en
= 0x1;
247 ctl
.bits
.fc_disable
= 0x1;
248 writel(ctl
.value
, &etdev
->regs
->txmac
.ctl
.value
);
250 /* Ready to start the RXDMA/TXDMA engine */
251 if (etdev
->Flags
& fMP_ADAPTER_LOWER_POWER
) {
252 et131x_rx_dma_enable(etdev
);
253 et131x_tx_dma_enable(etdev
);
257 void ConfigRxMacRegs(struct et131x_adapter
*etdev
)
259 struct _RXMAC_t __iomem
*pRxMac
= &etdev
->regs
->rxmac
;
260 RXMAC_WOL_SA_LO_t sa_lo
;
261 RXMAC_WOL_SA_HI_t sa_hi
;
262 RXMAC_PF_CTRL_t pf_ctrl
= { 0 };
264 /* Disable the MAC while it is being configured (also disable WOL) */
265 writel(0x8, &pRxMac
->ctrl
.value
);
267 /* Initialize WOL to disabled. */
268 writel(0, &pRxMac
->crc0
.value
);
269 writel(0, &pRxMac
->crc12
.value
);
270 writel(0, &pRxMac
->crc34
.value
);
272 /* We need to set the WOL mask0 - mask4 next. We initialize it to
273 * its default Values of 0x00000000 because there are not WOL masks
276 writel(0, &pRxMac
->mask0_word0
);
277 writel(0, &pRxMac
->mask0_word1
);
278 writel(0, &pRxMac
->mask0_word2
);
279 writel(0, &pRxMac
->mask0_word3
);
281 writel(0, &pRxMac
->mask1_word0
);
282 writel(0, &pRxMac
->mask1_word1
);
283 writel(0, &pRxMac
->mask1_word2
);
284 writel(0, &pRxMac
->mask1_word3
);
286 writel(0, &pRxMac
->mask2_word0
);
287 writel(0, &pRxMac
->mask2_word1
);
288 writel(0, &pRxMac
->mask2_word2
);
289 writel(0, &pRxMac
->mask2_word3
);
291 writel(0, &pRxMac
->mask3_word0
);
292 writel(0, &pRxMac
->mask3_word1
);
293 writel(0, &pRxMac
->mask3_word2
);
294 writel(0, &pRxMac
->mask3_word3
);
296 writel(0, &pRxMac
->mask4_word0
);
297 writel(0, &pRxMac
->mask4_word1
);
298 writel(0, &pRxMac
->mask4_word2
);
299 writel(0, &pRxMac
->mask4_word3
);
301 /* Lets setup the WOL Source Address */
302 sa_lo
.bits
.sa3
= etdev
->CurrentAddress
[2];
303 sa_lo
.bits
.sa4
= etdev
->CurrentAddress
[3];
304 sa_lo
.bits
.sa5
= etdev
->CurrentAddress
[4];
305 sa_lo
.bits
.sa6
= etdev
->CurrentAddress
[5];
306 writel(sa_lo
.value
, &pRxMac
->sa_lo
.value
);
308 sa_hi
.bits
.sa1
= etdev
->CurrentAddress
[0];
309 sa_hi
.bits
.sa2
= etdev
->CurrentAddress
[1];
310 writel(sa_hi
.value
, &pRxMac
->sa_hi
.value
);
312 /* Disable all Packet Filtering */
313 writel(0, &pRxMac
->pf_ctrl
.value
);
315 /* Let's initialize the Unicast Packet filtering address */
316 if (etdev
->PacketFilter
& ET131X_PACKET_TYPE_DIRECTED
) {
317 SetupDeviceForUnicast(etdev
);
318 pf_ctrl
.bits
.filter_uni_en
= 1;
320 writel(0, &pRxMac
->uni_pf_addr1
.value
);
321 writel(0, &pRxMac
->uni_pf_addr2
.value
);
322 writel(0, &pRxMac
->uni_pf_addr3
.value
);
325 /* Let's initialize the Multicast hash */
326 if (etdev
->PacketFilter
& ET131X_PACKET_TYPE_ALL_MULTICAST
) {
327 pf_ctrl
.bits
.filter_multi_en
= 0;
329 pf_ctrl
.bits
.filter_multi_en
= 1;
330 SetupDeviceForMulticast(etdev
);
333 /* Runt packet filtering. Didn't work in version A silicon. */
334 pf_ctrl
.bits
.min_pkt_size
= NIC_MIN_PACKET_SIZE
+ 4;
335 pf_ctrl
.bits
.filter_frag_en
= 1;
337 if (etdev
->RegistryJumboPacket
> 8192) {
338 RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg
;
340 /* In order to transmit jumbo packets greater than 8k, the
341 * FIFO between RxMAC and RxDMA needs to be reduced in size
342 * to (16k - Jumbo packet size). In order to implement this,
343 * we must use "cut through" mode in the RxMAC, which chops
344 * packets down into segments which are (max_size * 16). In
345 * this case we selected 256 bytes, since this is the size of
346 * the PCI-Express TLP's that the 1310 uses.
348 mcif_ctrl_max_seg
.bits
.seg_en
= 0x1;
349 mcif_ctrl_max_seg
.bits
.fc_en
= 0x0;
350 mcif_ctrl_max_seg
.bits
.max_size
= 0x10;
352 writel(mcif_ctrl_max_seg
.value
,
353 &pRxMac
->mcif_ctrl_max_seg
.value
);
355 writel(0, &pRxMac
->mcif_ctrl_max_seg
.value
);
358 /* Initialize the MCIF water marks */
359 writel(0, &pRxMac
->mcif_water_mark
.value
);
361 /* Initialize the MIF control */
362 writel(0, &pRxMac
->mif_ctrl
.value
);
364 /* Initialize the Space Available Register */
365 writel(0, &pRxMac
->space_avail
.value
);
367 /* Initialize the the mif_ctrl register
368 * bit 3: Receive code error. One or more nibbles were signaled as
369 * errors during the reception of the packet. Clear this
370 * bit in Gigabit, set it in 100Mbit. This was derived
371 * experimentally at UNH.
372 * bit 4: Receive CRC error. The packet's CRC did not match the
373 * internally generated CRC.
374 * bit 5: Receive length check error. Indicates that frame length
375 * field value in the packet does not match the actual data
376 * byte length and is not a type field.
377 * bit 16: Receive frame truncated.
378 * bit 17: Drop packet enable
380 if (etdev
->linkspeed
== TRUEPHY_SPEED_100MBPS
)
381 writel(0x30038, &pRxMac
->mif_ctrl
.value
);
383 writel(0x30030, &pRxMac
->mif_ctrl
.value
);
385 /* Finally we initialize RxMac to be enabled & WOL disabled. Packet
386 * filter is always enabled since it is where the runt packets are
387 * supposed to be dropped. For version A silicon, runt packet
388 * dropping doesn't work, so it is disabled in the pf_ctrl register,
389 * but we still leave the packet filter on.
391 writel(pf_ctrl
.value
, &pRxMac
->pf_ctrl
.value
);
392 writel(0x9, &pRxMac
->ctrl
.value
);
395 void ConfigTxMacRegs(struct et131x_adapter
*etdev
)
397 struct _TXMAC_t __iomem
*pTxMac
= &etdev
->regs
->txmac
;
398 TXMAC_CF_PARAM_t Local
;
400 /* We need to update the Control Frame Parameters
401 * cfpt - control frame pause timer set to 64 (0x40)
402 * cfep - control frame extended pause timer set to 0x0
404 if (etdev
->FlowControl
== None
) {
405 writel(0, &pTxMac
->cf_param
.value
);
407 Local
.bits
.cfpt
= 0x40;
408 Local
.bits
.cfep
= 0x0;
409 writel(Local
.value
, &pTxMac
->cf_param
.value
);
413 void ConfigMacStatRegs(struct et131x_adapter
*etdev
)
415 struct _MAC_STAT_t __iomem
*pDevMacStat
=
416 &etdev
->regs
->macStat
;
418 /* Next we need to initialize all the MAC_STAT registers to zero on
421 writel(0, &pDevMacStat
->RFcs
);
422 writel(0, &pDevMacStat
->RAln
);
423 writel(0, &pDevMacStat
->RFlr
);
424 writel(0, &pDevMacStat
->RDrp
);
425 writel(0, &pDevMacStat
->RCde
);
426 writel(0, &pDevMacStat
->ROvr
);
427 writel(0, &pDevMacStat
->RFrg
);
429 writel(0, &pDevMacStat
->TScl
);
430 writel(0, &pDevMacStat
->TDfr
);
431 writel(0, &pDevMacStat
->TMcl
);
432 writel(0, &pDevMacStat
->TLcl
);
433 writel(0, &pDevMacStat
->TNcl
);
434 writel(0, &pDevMacStat
->TOvr
);
435 writel(0, &pDevMacStat
->TUnd
);
437 /* Unmask any counters that we want to track the overflow of.
438 * Initially this will be all counters. It may become clear later
439 * that we do not need to track all counters.
442 MAC_STAT_REG_1_t Carry1M
= { 0xffffffff };
444 Carry1M
.bits
.rdrp
= 0;
445 Carry1M
.bits
.rjbr
= 1;
446 Carry1M
.bits
.rfrg
= 0;
447 Carry1M
.bits
.rovr
= 0;
448 Carry1M
.bits
.rund
= 1;
449 Carry1M
.bits
.rcse
= 1;
450 Carry1M
.bits
.rcde
= 0;
451 Carry1M
.bits
.rflr
= 0;
452 Carry1M
.bits
.raln
= 0;
453 Carry1M
.bits
.rxuo
= 1;
454 Carry1M
.bits
.rxpf
= 1;
455 Carry1M
.bits
.rxcf
= 1;
456 Carry1M
.bits
.rbca
= 1;
457 Carry1M
.bits
.rmca
= 1;
458 Carry1M
.bits
.rfcs
= 0;
459 Carry1M
.bits
.rpkt
= 1;
460 Carry1M
.bits
.rbyt
= 1;
461 Carry1M
.bits
.trmgv
= 1;
462 Carry1M
.bits
.trmax
= 1;
463 Carry1M
.bits
.tr1k
= 1;
464 Carry1M
.bits
.tr511
= 1;
465 Carry1M
.bits
.tr255
= 1;
466 Carry1M
.bits
.tr127
= 1;
467 Carry1M
.bits
.tr64
= 1;
469 writel(Carry1M
.value
, &pDevMacStat
->Carry1M
.value
);
473 MAC_STAT_REG_2_t Carry2M
= { 0xffffffff };
475 Carry2M
.bits
.tdrp
= 1;
476 Carry2M
.bits
.tpfh
= 1;
477 Carry2M
.bits
.tncl
= 0;
478 Carry2M
.bits
.txcl
= 1;
479 Carry2M
.bits
.tlcl
= 0;
480 Carry2M
.bits
.tmcl
= 0;
481 Carry2M
.bits
.tscl
= 0;
482 Carry2M
.bits
.tedf
= 1;
483 Carry2M
.bits
.tdfr
= 0;
484 Carry2M
.bits
.txpf
= 1;
485 Carry2M
.bits
.tbca
= 1;
486 Carry2M
.bits
.tmca
= 1;
487 Carry2M
.bits
.tpkt
= 1;
488 Carry2M
.bits
.tbyt
= 1;
489 Carry2M
.bits
.tfrg
= 1;
490 Carry2M
.bits
.tund
= 0;
491 Carry2M
.bits
.tovr
= 0;
492 Carry2M
.bits
.txcf
= 1;
493 Carry2M
.bits
.tfcs
= 1;
494 Carry2M
.bits
.tjbr
= 1;
496 writel(Carry2M
.value
, &pDevMacStat
->Carry2M
.value
);
500 void ConfigFlowControl(struct et131x_adapter
*etdev
)
502 if (etdev
->duplex_mode
== 0) {
503 etdev
->FlowControl
= None
;
505 char RemotePause
, RemoteAsyncPause
;
507 ET1310_PhyAccessMiBit(etdev
,
508 TRUEPHY_BIT_READ
, 5, 10, &RemotePause
);
509 ET1310_PhyAccessMiBit(etdev
,
510 TRUEPHY_BIT_READ
, 5, 11,
513 if ((RemotePause
== TRUEPHY_BIT_SET
) &&
514 (RemoteAsyncPause
== TRUEPHY_BIT_SET
)) {
515 etdev
->FlowControl
= etdev
->RegistryFlowControl
;
516 } else if ((RemotePause
== TRUEPHY_BIT_SET
) &&
517 (RemoteAsyncPause
== TRUEPHY_BIT_CLEAR
)) {
518 if (etdev
->RegistryFlowControl
== Both
)
519 etdev
->FlowControl
= Both
;
521 etdev
->FlowControl
= None
;
522 } else if ((RemotePause
== TRUEPHY_BIT_CLEAR
) &&
523 (RemoteAsyncPause
== TRUEPHY_BIT_CLEAR
)) {
524 etdev
->FlowControl
= None
;
525 } else {/* if (RemotePause == TRUEPHY_CLEAR_BIT &&
526 RemoteAsyncPause == TRUEPHY_SET_BIT) */
527 if (etdev
->RegistryFlowControl
== Both
)
528 etdev
->FlowControl
= RxOnly
;
530 etdev
->FlowControl
= None
;
536 * UpdateMacStatHostCounters - Update the local copy of the statistics
537 * @etdev: pointer to the adapter structure
539 void UpdateMacStatHostCounters(struct et131x_adapter
*etdev
)
541 struct _ce_stats_t
*stats
= &etdev
->Stats
;
542 struct _MAC_STAT_t __iomem
*pDevMacStat
=
543 &etdev
->regs
->macStat
;
545 stats
->collisions
+= readl(&pDevMacStat
->TNcl
);
546 stats
->first_collision
+= readl(&pDevMacStat
->TScl
);
547 stats
->tx_deferred
+= readl(&pDevMacStat
->TDfr
);
548 stats
->excessive_collisions
+= readl(&pDevMacStat
->TMcl
);
549 stats
->late_collisions
+= readl(&pDevMacStat
->TLcl
);
550 stats
->tx_uflo
+= readl(&pDevMacStat
->TUnd
);
551 stats
->max_pkt_error
+= readl(&pDevMacStat
->TOvr
);
553 stats
->alignment_err
+= readl(&pDevMacStat
->RAln
);
554 stats
->crc_err
+= readl(&pDevMacStat
->RCde
);
555 stats
->norcvbuf
+= readl(&pDevMacStat
->RDrp
);
556 stats
->rx_ov_flow
+= readl(&pDevMacStat
->ROvr
);
557 stats
->code_violations
+= readl(&pDevMacStat
->RFcs
);
558 stats
->length_err
+= readl(&pDevMacStat
->RFlr
);
560 stats
->other_errors
+= readl(&pDevMacStat
->RFrg
);
564 * HandleMacStatInterrupt
565 * @etdev: pointer to the adapter structure
567 * One of the MACSTAT counters has wrapped. Update the local copy of
568 * the statistics held in the adapter structure, checking the "wrap"
569 * bit for each counter.
571 void HandleMacStatInterrupt(struct et131x_adapter
*etdev
)
573 MAC_STAT_REG_1_t Carry1
;
574 MAC_STAT_REG_2_t Carry2
;
576 /* Read the interrupt bits from the register(s). These are Clear On
579 Carry1
.value
= readl(&etdev
->regs
->macStat
.Carry1
.value
);
580 Carry2
.value
= readl(&etdev
->regs
->macStat
.Carry2
.value
);
582 writel(Carry1
.value
, &etdev
->regs
->macStat
.Carry1
.value
);
583 writel(Carry2
.value
, &etdev
->regs
->macStat
.Carry2
.value
);
585 /* We need to do update the host copy of all the MAC_STAT counters.
586 * For each counter, check it's overflow bit. If the overflow bit is
587 * set, then increment the host version of the count by one complete
588 * revolution of the counter. This routine is called when the counter
589 * block indicates that one of the counters has wrapped.
591 if (Carry1
.bits
.rfcs
)
592 etdev
->Stats
.code_violations
+= COUNTER_WRAP_16_BIT
;
593 if (Carry1
.bits
.raln
)
594 etdev
->Stats
.alignment_err
+= COUNTER_WRAP_12_BIT
;
595 if (Carry1
.bits
.rflr
)
596 etdev
->Stats
.length_err
+= COUNTER_WRAP_16_BIT
;
597 if (Carry1
.bits
.rfrg
)
598 etdev
->Stats
.other_errors
+= COUNTER_WRAP_16_BIT
;
599 if (Carry1
.bits
.rcde
)
600 etdev
->Stats
.crc_err
+= COUNTER_WRAP_16_BIT
;
601 if (Carry1
.bits
.rovr
)
602 etdev
->Stats
.rx_ov_flow
+= COUNTER_WRAP_16_BIT
;
603 if (Carry1
.bits
.rdrp
)
604 etdev
->Stats
.norcvbuf
+= COUNTER_WRAP_16_BIT
;
605 if (Carry2
.bits
.tovr
)
606 etdev
->Stats
.max_pkt_error
+= COUNTER_WRAP_12_BIT
;
607 if (Carry2
.bits
.tund
)
608 etdev
->Stats
.tx_uflo
+= COUNTER_WRAP_12_BIT
;
609 if (Carry2
.bits
.tscl
)
610 etdev
->Stats
.first_collision
+= COUNTER_WRAP_12_BIT
;
611 if (Carry2
.bits
.tdfr
)
612 etdev
->Stats
.tx_deferred
+= COUNTER_WRAP_12_BIT
;
613 if (Carry2
.bits
.tmcl
)
614 etdev
->Stats
.excessive_collisions
+= COUNTER_WRAP_12_BIT
;
615 if (Carry2
.bits
.tlcl
)
616 etdev
->Stats
.late_collisions
+= COUNTER_WRAP_12_BIT
;
617 if (Carry2
.bits
.tncl
)
618 etdev
->Stats
.collisions
+= COUNTER_WRAP_12_BIT
;
621 void SetupDeviceForMulticast(struct et131x_adapter
*etdev
)
623 struct _RXMAC_t __iomem
*rxmac
= &etdev
->regs
->rxmac
;
632 /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
633 * the multi-cast LIST. If it is NOT specified, (and "ALL" is not
634 * specified) then we should pass NO multi-cast addresses to the
637 if (etdev
->PacketFilter
& ET131X_PACKET_TYPE_MULTICAST
) {
638 /* Loop through our multicast array and set up the device */
639 for (nIndex
= 0; nIndex
< etdev
->MCAddressCount
; nIndex
++) {
640 result
= ether_crc(6, etdev
->MCList
[nIndex
]);
642 result
= (result
& 0x3F800000) >> 23;
645 hash1
|= (1 << result
);
646 } else if ((31 < result
) && (result
< 64)) {
648 hash2
|= (1 << result
);
649 } else if ((63 < result
) && (result
< 96)) {
651 hash3
|= (1 << result
);
654 hash4
|= (1 << result
);
659 /* Write out the new hash to the device */
660 pm_csr
= readl(&etdev
->regs
->global
.pm_csr
);
661 if ((pm_csr
& ET_PM_PHY_SW_COMA
) == 0) {
662 writel(hash1
, &rxmac
->multi_hash1
);
663 writel(hash2
, &rxmac
->multi_hash2
);
664 writel(hash3
, &rxmac
->multi_hash3
);
665 writel(hash4
, &rxmac
->multi_hash4
);
669 void SetupDeviceForUnicast(struct et131x_adapter
*etdev
)
671 struct _RXMAC_t __iomem
*rxmac
= &etdev
->regs
->rxmac
;
672 RXMAC_UNI_PF_ADDR1_t uni_pf1
;
673 RXMAC_UNI_PF_ADDR2_t uni_pf2
;
674 RXMAC_UNI_PF_ADDR3_t uni_pf3
;
677 /* Set up unicast packet filter reg 3 to be the first two octets of
678 * the MAC address for both address
680 * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
681 * MAC address for second address
683 * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
684 * MAC address for first address
686 uni_pf3
.bits
.addr1_1
= etdev
->CurrentAddress
[0];
687 uni_pf3
.bits
.addr1_2
= etdev
->CurrentAddress
[1];
688 uni_pf3
.bits
.addr2_1
= etdev
->CurrentAddress
[0];
689 uni_pf3
.bits
.addr2_2
= etdev
->CurrentAddress
[1];
691 uni_pf2
.bits
.addr2_3
= etdev
->CurrentAddress
[2];
692 uni_pf2
.bits
.addr2_4
= etdev
->CurrentAddress
[3];
693 uni_pf2
.bits
.addr2_5
= etdev
->CurrentAddress
[4];
694 uni_pf2
.bits
.addr2_6
= etdev
->CurrentAddress
[5];
696 uni_pf1
.bits
.addr1_3
= etdev
->CurrentAddress
[2];
697 uni_pf1
.bits
.addr1_4
= etdev
->CurrentAddress
[3];
698 uni_pf1
.bits
.addr1_5
= etdev
->CurrentAddress
[4];
699 uni_pf1
.bits
.addr1_6
= etdev
->CurrentAddress
[5];
701 pm_csr
= readl(&etdev
->regs
->global
.pm_csr
);
702 if ((pm_csr
& ET_PM_PHY_SW_COMA
) == 0) {
703 writel(uni_pf1
.value
, &rxmac
->uni_pf_addr1
.value
);
704 writel(uni_pf2
.value
, &rxmac
->uni_pf_addr2
.value
);
705 writel(uni_pf3
.value
, &rxmac
->uni_pf_addr3
.value
);