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powerpc: Fix data-corrupting bug in __futex_atomic_op
[linux-2.6/x86.git] / drivers / net / bnx2.c
blobad446db8e1861bb5a5c2813ba14856cd490b8510
1 /* bnx2.c: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004-2009 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15
16 #include <linux/kernel.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/vmalloc.h>
22 #include <linux/interrupt.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/bitops.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32 #include <linux/delay.h>
33 #include <asm/byteorder.h>
34 #include <asm/page.h>
35 #include <linux/time.h>
36 #include <linux/ethtool.h>
37 #include <linux/mii.h>
38 #include <linux/if_vlan.h>
39 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
40 #define BCM_VLAN 1
41 #endif
42 #include <net/ip.h>
43 #include <net/tcp.h>
44 #include <net/checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/zlib.h>
50 #include <linux/log2.h>
51
52 #include "bnx2.h"
53 #include "bnx2_fw.h"
54 #include "bnx2_fw2.h"
55
56 #define FW_BUF_SIZE 0x10000
57
58 #define DRV_MODULE_NAME "bnx2"
59 #define PFX DRV_MODULE_NAME ": "
60 #define DRV_MODULE_VERSION "1.9.3"
61 #define DRV_MODULE_RELDATE "March 17, 2009"
62
63 #define RUN_AT(x) (jiffies + (x))
64
65 /* Time in jiffies before concluding the transmitter is hung. */
66 #define TX_TIMEOUT (5*HZ)
67
68 static char version[] __devinitdata =
69 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
70
71 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
72 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
73 MODULE_LICENSE("GPL");
74 MODULE_VERSION(DRV_MODULE_VERSION);
75
76 static int disable_msi = 0;
77
78 module_param(disable_msi, int, 0);
79 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
80
81 typedef enum {
82 BCM5706 = 0,
83 NC370T,
84 NC370I,
85 BCM5706S,
86 NC370F,
87 BCM5708,
88 BCM5708S,
89 BCM5709,
90 BCM5709S,
91 BCM5716,
92 BCM5716S,
93 } board_t;
94
95 /* indexed by board_t, above */
96 static struct {
97 char *name;
98 } board_info[] __devinitdata = {
99 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
100 { "HP NC370T Multifunction Gigabit Server Adapter" },
101 { "HP NC370i Multifunction Gigabit Server Adapter" },
102 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
103 { "HP NC370F Multifunction Gigabit Server Adapter" },
104 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
105 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
106 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
107 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
108 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
109 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
110 };
111
112 static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
113 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
114 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
115 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
116 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
117 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
119 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
121 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
122 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
123 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
125 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
127 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
129 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
131 { PCI_VENDOR_ID_BROADCOM, 0x163b,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
133 { PCI_VENDOR_ID_BROADCOM, 0x163c,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
135 { 0, }
136 };
137
138 static struct flash_spec flash_table[] =
139 {
140 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
141 #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
142 /* Slow EEPROM */
143 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
144 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
145 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
146 "EEPROM - slow"},
147 /* Expansion entry 0001 */
148 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
149 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
150 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
151 "Entry 0001"},
152 /* Saifun SA25F010 (non-buffered flash) */
153 /* strap, cfg1, & write1 need updates */
154 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
155 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
156 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
157 "Non-buffered flash (128kB)"},
158 /* Saifun SA25F020 (non-buffered flash) */
159 /* strap, cfg1, & write1 need updates */
160 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
161 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
162 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
163 "Non-buffered flash (256kB)"},
164 /* Expansion entry 0100 */
165 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
166 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
167 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
168 "Entry 0100"},
169 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
170 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
171 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
172 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
173 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
174 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
175 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
176 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
177 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
178 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
179 /* Saifun SA25F005 (non-buffered flash) */
180 /* strap, cfg1, & write1 need updates */
181 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
182 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
183 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
184 "Non-buffered flash (64kB)"},
185 /* Fast EEPROM */
186 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
187 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
188 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
189 "EEPROM - fast"},
190 /* Expansion entry 1001 */
191 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
192 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
193 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
194 "Entry 1001"},
195 /* Expansion entry 1010 */
196 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
197 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
198 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
199 "Entry 1010"},
200 /* ATMEL AT45DB011B (buffered flash) */
201 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
202 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
203 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
204 "Buffered flash (128kB)"},
205 /* Expansion entry 1100 */
206 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
207 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
208 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
209 "Entry 1100"},
210 /* Expansion entry 1101 */
211 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
212 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
213 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
214 "Entry 1101"},
215 /* Ateml Expansion entry 1110 */
216 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
217 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
218 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
219 "Entry 1110 (Atmel)"},
220 /* ATMEL AT45DB021B (buffered flash) */
221 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
222 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
223 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
224 "Buffered flash (256kB)"},
225 };
226
227 static struct flash_spec flash_5709 = {
228 .flags = BNX2_NV_BUFFERED,
229 .page_bits = BCM5709_FLASH_PAGE_BITS,
230 .page_size = BCM5709_FLASH_PAGE_SIZE,
231 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
232 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
233 .name = "5709 Buffered flash (256kB)",
234 };
235
236 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
237
238 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
239 {
240 u32 diff;
241
242 smp_mb();
243
244 /* The ring uses 256 indices for 255 entries, one of them
245 * needs to be skipped.
246 */
247 diff = txr->tx_prod - txr->tx_cons;
248 if (unlikely(diff >= TX_DESC_CNT)) {
249 diff &= 0xffff;
250 if (diff == TX_DESC_CNT)
251 diff = MAX_TX_DESC_CNT;
252 }
253 return (bp->tx_ring_size - diff);
254 }
255
256 static u32
257 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
258 {
259 u32 val;
260
261 spin_lock_bh(&bp->indirect_lock);
262 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
263 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
264 spin_unlock_bh(&bp->indirect_lock);
265 return val;
266 }
267
268 static void
269 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
270 {
271 spin_lock_bh(&bp->indirect_lock);
272 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
273 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
274 spin_unlock_bh(&bp->indirect_lock);
275 }
276
277 static void
278 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
279 {
280 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
281 }
282
283 static u32
284 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
285 {
286 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
287 }
288
289 static void
290 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
291 {
292 offset += cid_addr;
293 spin_lock_bh(&bp->indirect_lock);
294 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
295 int i;
296
297 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
298 REG_WR(bp, BNX2_CTX_CTX_CTRL,
299 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
300 for (i = 0; i < 5; i++) {
301 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
302 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
303 break;
304 udelay(5);
305 }
306 } else {
307 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
308 REG_WR(bp, BNX2_CTX_DATA, val);
309 }
310 spin_unlock_bh(&bp->indirect_lock);
311 }
312
313 static int
314 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
315 {
316 u32 val1;
317 int i, ret;
318
319 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
320 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
321 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
322
323 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
324 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
325
326 udelay(40);
327 }
328
329 val1 = (bp->phy_addr << 21) | (reg << 16) |
330 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
331 BNX2_EMAC_MDIO_COMM_START_BUSY;
332 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
333
334 for (i = 0; i < 50; i++) {
335 udelay(10);
336
337 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
338 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
339 udelay(5);
340
341 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
342 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
343
344 break;
345 }
346 }
347
348 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
349 *val = 0x0;
350 ret = -EBUSY;
351 }
352 else {
353 *val = val1;
354 ret = 0;
355 }
356
357 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
358 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
359 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
360
361 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
362 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
363
364 udelay(40);
365 }
366
367 return ret;
368 }
369
370 static int
371 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
372 {
373 u32 val1;
374 int i, ret;
375
376 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
377 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
378 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
379
380 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
381 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
382
383 udelay(40);
384 }
385
386 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
387 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
388 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
389 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
390
391 for (i = 0; i < 50; i++) {
392 udelay(10);
393
394 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
395 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
396 udelay(5);
397 break;
398 }
399 }
400
401 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
402 ret = -EBUSY;
403 else
404 ret = 0;
405
406 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
407 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
408 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
409
410 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
411 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
412
413 udelay(40);
414 }
415
416 return ret;
417 }
418
419 static void
420 bnx2_disable_int(struct bnx2 *bp)
421 {
422 int i;
423 struct bnx2_napi *bnapi;
424
425 for (i = 0; i < bp->irq_nvecs; i++) {
426 bnapi = &bp->bnx2_napi[i];
427 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
428 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
429 }
430 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
431 }
432
433 static void
434 bnx2_enable_int(struct bnx2 *bp)
435 {
436 int i;
437 struct bnx2_napi *bnapi;
438
439 for (i = 0; i < bp->irq_nvecs; i++) {
440 bnapi = &bp->bnx2_napi[i];
441
442 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
443 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
444 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
445 bnapi->last_status_idx);
446
447 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
448 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
449 bnapi->last_status_idx);
450 }
451 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
452 }
453
454 static void
455 bnx2_disable_int_sync(struct bnx2 *bp)
456 {
457 int i;
458
459 atomic_inc(&bp->intr_sem);
460 bnx2_disable_int(bp);
461 for (i = 0; i < bp->irq_nvecs; i++)
462 synchronize_irq(bp->irq_tbl[i].vector);
463 }
464
465 static void
466 bnx2_napi_disable(struct bnx2 *bp)
467 {
468 int i;
469
470 for (i = 0; i < bp->irq_nvecs; i++)
471 napi_disable(&bp->bnx2_napi[i].napi);
472 }
473
474 static void
475 bnx2_napi_enable(struct bnx2 *bp)
476 {
477 int i;
478
479 for (i = 0; i < bp->irq_nvecs; i++)
480 napi_enable(&bp->bnx2_napi[i].napi);
481 }
482
483 static void
484 bnx2_netif_stop(struct bnx2 *bp)
485 {
486 bnx2_disable_int_sync(bp);
487 if (netif_running(bp->dev)) {
488 bnx2_napi_disable(bp);
489 netif_tx_disable(bp->dev);
490 bp->dev->trans_start = jiffies; /* prevent tx timeout */
491 }
492 }
493
494 static void
495 bnx2_netif_start(struct bnx2 *bp)
496 {
497 if (atomic_dec_and_test(&bp->intr_sem)) {
498 if (netif_running(bp->dev)) {
499 netif_tx_wake_all_queues(bp->dev);
500 bnx2_napi_enable(bp);
501 bnx2_enable_int(bp);
502 }
503 }
504 }
505
506 static void
507 bnx2_free_tx_mem(struct bnx2 *bp)
508 {
509 int i;
510
511 for (i = 0; i < bp->num_tx_rings; i++) {
512 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
513 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
514
515 if (txr->tx_desc_ring) {
516 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
517 txr->tx_desc_ring,
518 txr->tx_desc_mapping);
519 txr->tx_desc_ring = NULL;
520 }
521 kfree(txr->tx_buf_ring);
522 txr->tx_buf_ring = NULL;
523 }
524 }
525
526 static void
527 bnx2_free_rx_mem(struct bnx2 *bp)
528 {
529 int i;
530
531 for (i = 0; i < bp->num_rx_rings; i++) {
532 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
533 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
534 int j;
535
536 for (j = 0; j < bp->rx_max_ring; j++) {
537 if (rxr->rx_desc_ring[j])
538 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
539 rxr->rx_desc_ring[j],
540 rxr->rx_desc_mapping[j]);
541 rxr->rx_desc_ring[j] = NULL;
542 }
543 if (rxr->rx_buf_ring)
544 vfree(rxr->rx_buf_ring);
545 rxr->rx_buf_ring = NULL;
546
547 for (j = 0; j < bp->rx_max_pg_ring; j++) {
548 if (rxr->rx_pg_desc_ring[j])
549 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
550 rxr->rx_pg_desc_ring[j],
551 rxr->rx_pg_desc_mapping[j]);
552 rxr->rx_pg_desc_ring[j] = NULL;
553 }
554 if (rxr->rx_pg_ring)
555 vfree(rxr->rx_pg_ring);
556 rxr->rx_pg_ring = NULL;
557 }
558 }
559
560 static int
561 bnx2_alloc_tx_mem(struct bnx2 *bp)
562 {
563 int i;
564
565 for (i = 0; i < bp->num_tx_rings; i++) {
566 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
567 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
568
569 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
570 if (txr->tx_buf_ring == NULL)
571 return -ENOMEM;
572
573 txr->tx_desc_ring =
574 pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
575 &txr->tx_desc_mapping);
576 if (txr->tx_desc_ring == NULL)
577 return -ENOMEM;
578 }
579 return 0;
580 }
581
582 static int
583 bnx2_alloc_rx_mem(struct bnx2 *bp)
584 {
585 int i;
586
587 for (i = 0; i < bp->num_rx_rings; i++) {
588 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
589 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
590 int j;
591
592 rxr->rx_buf_ring =
593 vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
594 if (rxr->rx_buf_ring == NULL)
595 return -ENOMEM;
596
597 memset(rxr->rx_buf_ring, 0,
598 SW_RXBD_RING_SIZE * bp->rx_max_ring);
599
600 for (j = 0; j < bp->rx_max_ring; j++) {
601 rxr->rx_desc_ring[j] =
602 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
603 &rxr->rx_desc_mapping[j]);
604 if (rxr->rx_desc_ring[j] == NULL)
605 return -ENOMEM;
606
607 }
608
609 if (bp->rx_pg_ring_size) {
610 rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
611 bp->rx_max_pg_ring);
612 if (rxr->rx_pg_ring == NULL)
613 return -ENOMEM;
614
615 memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
616 bp->rx_max_pg_ring);
617 }
618
619 for (j = 0; j < bp->rx_max_pg_ring; j++) {
620 rxr->rx_pg_desc_ring[j] =
621 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
622 &rxr->rx_pg_desc_mapping[j]);
623 if (rxr->rx_pg_desc_ring[j] == NULL)
624 return -ENOMEM;
625
626 }
627 }
628 return 0;
629 }
630
631 static void
632 bnx2_free_mem(struct bnx2 *bp)
633 {
634 int i;
635 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
636
637 bnx2_free_tx_mem(bp);
638 bnx2_free_rx_mem(bp);
639
640 for (i = 0; i < bp->ctx_pages; i++) {
641 if (bp->ctx_blk[i]) {
642 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
643 bp->ctx_blk[i],
644 bp->ctx_blk_mapping[i]);
645 bp->ctx_blk[i] = NULL;
646 }
647 }
648 if (bnapi->status_blk.msi) {
649 pci_free_consistent(bp->pdev, bp->status_stats_size,
650 bnapi->status_blk.msi,
651 bp->status_blk_mapping);
652 bnapi->status_blk.msi = NULL;
653 bp->stats_blk = NULL;
654 }
655 }
656
657 static int
658 bnx2_alloc_mem(struct bnx2 *bp)
659 {
660 int i, status_blk_size, err;
661 struct bnx2_napi *bnapi;
662 void *status_blk;
663
664 /* Combine status and statistics blocks into one allocation. */
665 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
666 if (bp->flags & BNX2_FLAG_MSIX_CAP)
667 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
668 BNX2_SBLK_MSIX_ALIGN_SIZE);
669 bp->status_stats_size = status_blk_size +
670 sizeof(struct statistics_block);
671
672 status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
673 &bp->status_blk_mapping);
674 if (status_blk == NULL)
675 goto alloc_mem_err;
676
677 memset(status_blk, 0, bp->status_stats_size);
678
679 bnapi = &bp->bnx2_napi[0];
680 bnapi->status_blk.msi = status_blk;
681 bnapi->hw_tx_cons_ptr =
682 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
683 bnapi->hw_rx_cons_ptr =
684 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
685 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
686 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
687 struct status_block_msix *sblk;
688
689 bnapi = &bp->bnx2_napi[i];
690
691 sblk = (void *) (status_blk +
692 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
693 bnapi->status_blk.msix = sblk;
694 bnapi->hw_tx_cons_ptr =
695 &sblk->status_tx_quick_consumer_index;
696 bnapi->hw_rx_cons_ptr =
697 &sblk->status_rx_quick_consumer_index;
698 bnapi->int_num = i << 24;
699 }
700 }
701
702 bp->stats_blk = status_blk + status_blk_size;
703
704 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
705
706 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
707 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
708 if (bp->ctx_pages == 0)
709 bp->ctx_pages = 1;
710 for (i = 0; i < bp->ctx_pages; i++) {
711 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
712 BCM_PAGE_SIZE,
713 &bp->ctx_blk_mapping[i]);
714 if (bp->ctx_blk[i] == NULL)
715 goto alloc_mem_err;
716 }
717 }
718
719 err = bnx2_alloc_rx_mem(bp);
720 if (err)
721 goto alloc_mem_err;
722
723 err = bnx2_alloc_tx_mem(bp);
724 if (err)
725 goto alloc_mem_err;
726
727 return 0;
728
729 alloc_mem_err:
730 bnx2_free_mem(bp);
731 return -ENOMEM;
732 }
733
734 static void
735 bnx2_report_fw_link(struct bnx2 *bp)
736 {
737 u32 fw_link_status = 0;
738
739 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
740 return;
741
742 if (bp->link_up) {
743 u32 bmsr;
744
745 switch (bp->line_speed) {
746 case SPEED_10:
747 if (bp->duplex == DUPLEX_HALF)
748 fw_link_status = BNX2_LINK_STATUS_10HALF;
749 else
750 fw_link_status = BNX2_LINK_STATUS_10FULL;
751 break;
752 case SPEED_100:
753 if (bp->duplex == DUPLEX_HALF)
754 fw_link_status = BNX2_LINK_STATUS_100HALF;
755 else
756 fw_link_status = BNX2_LINK_STATUS_100FULL;
757 break;
758 case SPEED_1000:
759 if (bp->duplex == DUPLEX_HALF)
760 fw_link_status = BNX2_LINK_STATUS_1000HALF;
761 else
762 fw_link_status = BNX2_LINK_STATUS_1000FULL;
763 break;
764 case SPEED_2500:
765 if (bp->duplex == DUPLEX_HALF)
766 fw_link_status = BNX2_LINK_STATUS_2500HALF;
767 else
768 fw_link_status = BNX2_LINK_STATUS_2500FULL;
769 break;
770 }
771
772 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
773
774 if (bp->autoneg) {
775 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
776
777 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
778 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
779
780 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
781 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
782 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
783 else
784 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
785 }
786 }
787 else
788 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
789
790 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
791 }
792
793 static char *
794 bnx2_xceiver_str(struct bnx2 *bp)
795 {
796 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
797 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
798 "Copper"));
799 }
800
801 static void
802 bnx2_report_link(struct bnx2 *bp)
803 {
804 if (bp->link_up) {
805 netif_carrier_on(bp->dev);
806 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
807 bnx2_xceiver_str(bp));
808
809 printk("%d Mbps ", bp->line_speed);
810
811 if (bp->duplex == DUPLEX_FULL)
812 printk("full duplex");
813 else
814 printk("half duplex");
815
816 if (bp->flow_ctrl) {
817 if (bp->flow_ctrl & FLOW_CTRL_RX) {
818 printk(", receive ");
819 if (bp->flow_ctrl & FLOW_CTRL_TX)
820 printk("& transmit ");
821 }
822 else {
823 printk(", transmit ");
824 }
825 printk("flow control ON");
826 }
827 printk("\n");
828 }
829 else {
830 netif_carrier_off(bp->dev);
831 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
832 bnx2_xceiver_str(bp));
833 }
834
835 bnx2_report_fw_link(bp);
836 }
837
838 static void
839 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
840 {
841 u32 local_adv, remote_adv;
842
843 bp->flow_ctrl = 0;
844 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
845 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
846
847 if (bp->duplex == DUPLEX_FULL) {
848 bp->flow_ctrl = bp->req_flow_ctrl;
849 }
850 return;
851 }
852
853 if (bp->duplex != DUPLEX_FULL) {
854 return;
855 }
856
857 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
858 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
859 u32 val;
860
861 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
862 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
863 bp->flow_ctrl |= FLOW_CTRL_TX;
864 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
865 bp->flow_ctrl |= FLOW_CTRL_RX;
866 return;
867 }
868
869 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
870 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
871
872 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
873 u32 new_local_adv = 0;
874 u32 new_remote_adv = 0;
875
876 if (local_adv & ADVERTISE_1000XPAUSE)
877 new_local_adv |= ADVERTISE_PAUSE_CAP;
878 if (local_adv & ADVERTISE_1000XPSE_ASYM)
879 new_local_adv |= ADVERTISE_PAUSE_ASYM;
880 if (remote_adv & ADVERTISE_1000XPAUSE)
881 new_remote_adv |= ADVERTISE_PAUSE_CAP;
882 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
883 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
884
885 local_adv = new_local_adv;
886 remote_adv = new_remote_adv;
887 }
888
889 /* See Table 28B-3 of 802.3ab-1999 spec. */
890 if (local_adv & ADVERTISE_PAUSE_CAP) {
891 if(local_adv & ADVERTISE_PAUSE_ASYM) {
892 if (remote_adv & ADVERTISE_PAUSE_CAP) {
893 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
894 }
895 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
896 bp->flow_ctrl = FLOW_CTRL_RX;
897 }
898 }
899 else {
900 if (remote_adv & ADVERTISE_PAUSE_CAP) {
901 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
902 }
903 }
904 }
905 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
906 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
907 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
908
909 bp->flow_ctrl = FLOW_CTRL_TX;
910 }
911 }
912 }
913
914 static int
915 bnx2_5709s_linkup(struct bnx2 *bp)
916 {
917 u32 val, speed;
918
919 bp->link_up = 1;
920
921 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
922 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
923 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
924
925 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
926 bp->line_speed = bp->req_line_speed;
927 bp->duplex = bp->req_duplex;
928 return 0;
929 }
930 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
931 switch (speed) {
932 case MII_BNX2_GP_TOP_AN_SPEED_10:
933 bp->line_speed = SPEED_10;
934 break;
935 case MII_BNX2_GP_TOP_AN_SPEED_100:
936 bp->line_speed = SPEED_100;
937 break;
938 case MII_BNX2_GP_TOP_AN_SPEED_1G:
939 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
940 bp->line_speed = SPEED_1000;
941 break;
942 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
943 bp->line_speed = SPEED_2500;
944 break;
945 }
946 if (val & MII_BNX2_GP_TOP_AN_FD)
947 bp->duplex = DUPLEX_FULL;
948 else
949 bp->duplex = DUPLEX_HALF;
950 return 0;
951 }
952
953 static int
954 bnx2_5708s_linkup(struct bnx2 *bp)
955 {
956 u32 val;
957
958 bp->link_up = 1;
959 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
960 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
961 case BCM5708S_1000X_STAT1_SPEED_10:
962 bp->line_speed = SPEED_10;
963 break;
964 case BCM5708S_1000X_STAT1_SPEED_100:
965 bp->line_speed = SPEED_100;
966 break;
967 case BCM5708S_1000X_STAT1_SPEED_1G:
968 bp->line_speed = SPEED_1000;
969 break;
970 case BCM5708S_1000X_STAT1_SPEED_2G5:
971 bp->line_speed = SPEED_2500;
972 break;
973 }
974 if (val & BCM5708S_1000X_STAT1_FD)
975 bp->duplex = DUPLEX_FULL;
976 else
977 bp->duplex = DUPLEX_HALF;
978
979 return 0;
980 }
981
982 static int
983 bnx2_5706s_linkup(struct bnx2 *bp)
984 {
985 u32 bmcr, local_adv, remote_adv, common;
986
987 bp->link_up = 1;
988 bp->line_speed = SPEED_1000;
989
990 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
991 if (bmcr & BMCR_FULLDPLX) {
992 bp->duplex = DUPLEX_FULL;
993 }
994 else {
995 bp->duplex = DUPLEX_HALF;
996 }
997
998 if (!(bmcr & BMCR_ANENABLE)) {
999 return 0;
1000 }
1001
1002 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1003 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1004
1005 common = local_adv & remote_adv;
1006 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1007
1008 if (common & ADVERTISE_1000XFULL) {
1009 bp->duplex = DUPLEX_FULL;
1010 }
1011 else {
1012 bp->duplex = DUPLEX_HALF;
1013 }
1014 }
1015
1016 return 0;
1017 }
1018
1019 static int
1020 bnx2_copper_linkup(struct bnx2 *bp)
1021 {
1022 u32 bmcr;
1023
1024 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1025 if (bmcr & BMCR_ANENABLE) {
1026 u32 local_adv, remote_adv, common;
1027
1028 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1029 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1030
1031 common = local_adv & (remote_adv >> 2);
1032 if (common & ADVERTISE_1000FULL) {
1033 bp->line_speed = SPEED_1000;
1034 bp->duplex = DUPLEX_FULL;
1035 }
1036 else if (common & ADVERTISE_1000HALF) {
1037 bp->line_speed = SPEED_1000;
1038 bp->duplex = DUPLEX_HALF;
1039 }
1040 else {
1041 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1042 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1043
1044 common = local_adv & remote_adv;
1045 if (common & ADVERTISE_100FULL) {
1046 bp->line_speed = SPEED_100;
1047 bp->duplex = DUPLEX_FULL;
1048 }
1049 else if (common & ADVERTISE_100HALF) {
1050 bp->line_speed = SPEED_100;
1051 bp->duplex = DUPLEX_HALF;
1052 }
1053 else if (common & ADVERTISE_10FULL) {
1054 bp->line_speed = SPEED_10;
1055 bp->duplex = DUPLEX_FULL;
1056 }
1057 else if (common & ADVERTISE_10HALF) {
1058 bp->line_speed = SPEED_10;
1059 bp->duplex = DUPLEX_HALF;
1060 }
1061 else {
1062 bp->line_speed = 0;
1063 bp->link_up = 0;
1064 }
1065 }
1066 }
1067 else {
1068 if (bmcr & BMCR_SPEED100) {
1069 bp->line_speed = SPEED_100;
1070 }
1071 else {
1072 bp->line_speed = SPEED_10;
1073 }
1074 if (bmcr & BMCR_FULLDPLX) {
1075 bp->duplex = DUPLEX_FULL;
1076 }
1077 else {
1078 bp->duplex = DUPLEX_HALF;
1079 }
1080 }
1081
1082 return 0;
1083 }
1084
1085 static void
1086 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1087 {
1088 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1089
1090 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1091 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1092 val |= 0x02 << 8;
1093
1094 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1095 u32 lo_water, hi_water;
1096
1097 if (bp->flow_ctrl & FLOW_CTRL_TX)
1098 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1099 else
1100 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1101 if (lo_water >= bp->rx_ring_size)
1102 lo_water = 0;
1103
1104 hi_water = bp->rx_ring_size / 4;
1105
1106 if (hi_water <= lo_water)
1107 lo_water = 0;
1108
1109 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1110 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1111
1112 if (hi_water > 0xf)
1113 hi_water = 0xf;
1114 else if (hi_water == 0)
1115 lo_water = 0;
1116 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1117 }
1118 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1119 }
1120
1121 static void
1122 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1123 {
1124 int i;
1125 u32 cid;
1126
1127 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1128 if (i == 1)
1129 cid = RX_RSS_CID;
1130 bnx2_init_rx_context(bp, cid);
1131 }
1132 }
1133
1134 static void
1135 bnx2_set_mac_link(struct bnx2 *bp)
1136 {
1137 u32 val;
1138
1139 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1140 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1141 (bp->duplex == DUPLEX_HALF)) {
1142 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1143 }
1144
1145 /* Configure the EMAC mode register. */
1146 val = REG_RD(bp, BNX2_EMAC_MODE);
1147
1148 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1149 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1150 BNX2_EMAC_MODE_25G_MODE);
1151
1152 if (bp->link_up) {
1153 switch (bp->line_speed) {
1154 case SPEED_10:
1155 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1156 val |= BNX2_EMAC_MODE_PORT_MII_10M;
1157 break;
1158 }
1159 /* fall through */
1160 case SPEED_100:
1161 val |= BNX2_EMAC_MODE_PORT_MII;
1162 break;
1163 case SPEED_2500:
1164 val |= BNX2_EMAC_MODE_25G_MODE;
1165 /* fall through */
1166 case SPEED_1000:
1167 val |= BNX2_EMAC_MODE_PORT_GMII;
1168 break;
1169 }
1170 }
1171 else {
1172 val |= BNX2_EMAC_MODE_PORT_GMII;
1173 }
1174
1175 /* Set the MAC to operate in the appropriate duplex mode. */
1176 if (bp->duplex == DUPLEX_HALF)
1177 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1178 REG_WR(bp, BNX2_EMAC_MODE, val);
1179
1180 /* Enable/disable rx PAUSE. */
1181 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1182
1183 if (bp->flow_ctrl & FLOW_CTRL_RX)
1184 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1185 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1186
1187 /* Enable/disable tx PAUSE. */
1188 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1189 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1190
1191 if (bp->flow_ctrl & FLOW_CTRL_TX)
1192 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1193 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1194
1195 /* Acknowledge the interrupt. */
1196 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1197
1198 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1199 bnx2_init_all_rx_contexts(bp);
1200 }
1201
1202 static void
1203 bnx2_enable_bmsr1(struct bnx2 *bp)
1204 {
1205 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1206 (CHIP_NUM(bp) == CHIP_NUM_5709))
1207 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1208 MII_BNX2_BLK_ADDR_GP_STATUS);
1209 }
1210
1211 static void
1212 bnx2_disable_bmsr1(struct bnx2 *bp)
1213 {
1214 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1215 (CHIP_NUM(bp) == CHIP_NUM_5709))
1216 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1217 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1218 }
1219
1220 static int
1221 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1222 {
1223 u32 up1;
1224 int ret = 1;
1225
1226 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1227 return 0;
1228
1229 if (bp->autoneg & AUTONEG_SPEED)
1230 bp->advertising |= ADVERTISED_2500baseX_Full;
1231
1232 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1233 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1234
1235 bnx2_read_phy(bp, bp->mii_up1, &up1);
1236 if (!(up1 & BCM5708S_UP1_2G5)) {
1237 up1 |= BCM5708S_UP1_2G5;
1238 bnx2_write_phy(bp, bp->mii_up1, up1);
1239 ret = 0;
1240 }
1241
1242 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1243 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1244 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1245
1246 return ret;
1247 }
1248
1249 static int
1250 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1251 {
1252 u32 up1;
1253 int ret = 0;
1254
1255 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1256 return 0;
1257
1258 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1259 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1260
1261 bnx2_read_phy(bp, bp->mii_up1, &up1);
1262 if (up1 & BCM5708S_UP1_2G5) {
1263 up1 &= ~BCM5708S_UP1_2G5;
1264 bnx2_write_phy(bp, bp->mii_up1, up1);
1265 ret = 1;
1266 }
1267
1268 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1269 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1270 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1271
1272 return ret;
1273 }
1274
1275 static void
1276 bnx2_enable_forced_2g5(struct bnx2 *bp)
1277 {
1278 u32 bmcr;
1279
1280 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1281 return;
1282
1283 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1284 u32 val;
1285
1286 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1287 MII_BNX2_BLK_ADDR_SERDES_DIG);
1288 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1289 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1290 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1291 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1292
1293 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1294 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1295 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1296
1297 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1298 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1299 bmcr |= BCM5708S_BMCR_FORCE_2500;
1300 }
1301
1302 if (bp->autoneg & AUTONEG_SPEED) {
1303 bmcr &= ~BMCR_ANENABLE;
1304 if (bp->req_duplex == DUPLEX_FULL)
1305 bmcr |= BMCR_FULLDPLX;
1306 }
1307 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1308 }
1309
1310 static void
1311 bnx2_disable_forced_2g5(struct bnx2 *bp)
1312 {
1313 u32 bmcr;
1314
1315 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1316 return;
1317
1318 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1319 u32 val;
1320
1321 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1322 MII_BNX2_BLK_ADDR_SERDES_DIG);
1323 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1324 val &= ~MII_BNX2_SD_MISC1_FORCE;
1325 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1326
1327 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1328 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1329 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1330
1331 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1332 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1333 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1334 }
1335
1336 if (bp->autoneg & AUTONEG_SPEED)
1337 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1338 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1339 }
1340
1341 static void
1342 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1343 {
1344 u32 val;
1345
1346 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1347 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1348 if (start)
1349 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1350 else
1351 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1352 }
1353
1354 static int
1355 bnx2_set_link(struct bnx2 *bp)
1356 {
1357 u32 bmsr;
1358 u8 link_up;
1359
1360 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1361 bp->link_up = 1;
1362 return 0;
1363 }
1364
1365 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1366 return 0;
1367
1368 link_up = bp->link_up;
1369
1370 bnx2_enable_bmsr1(bp);
1371 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1372 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1373 bnx2_disable_bmsr1(bp);
1374
1375 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1376 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1377 u32 val, an_dbg;
1378
1379 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1380 bnx2_5706s_force_link_dn(bp, 0);
1381 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1382 }
1383 val = REG_RD(bp, BNX2_EMAC_STATUS);
1384
1385 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1386 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1387 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1388
1389 if ((val & BNX2_EMAC_STATUS_LINK) &&
1390 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1391 bmsr |= BMSR_LSTATUS;
1392 else
1393 bmsr &= ~BMSR_LSTATUS;
1394 }
1395
1396 if (bmsr & BMSR_LSTATUS) {
1397 bp->link_up = 1;
1398
1399 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1400 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1401 bnx2_5706s_linkup(bp);
1402 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1403 bnx2_5708s_linkup(bp);
1404 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1405 bnx2_5709s_linkup(bp);
1406 }
1407 else {
1408 bnx2_copper_linkup(bp);
1409 }
1410 bnx2_resolve_flow_ctrl(bp);
1411 }
1412 else {
1413 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1414 (bp->autoneg & AUTONEG_SPEED))
1415 bnx2_disable_forced_2g5(bp);
1416
1417 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1418 u32 bmcr;
1419
1420 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1421 bmcr |= BMCR_ANENABLE;
1422 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1423
1424 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1425 }
1426 bp->link_up = 0;
1427 }
1428
1429 if (bp->link_up != link_up) {
1430 bnx2_report_link(bp);
1431 }
1432
1433 bnx2_set_mac_link(bp);
1434
1435 return 0;
1436 }
1437
1438 static int
1439 bnx2_reset_phy(struct bnx2 *bp)
1440 {
1441 int i;
1442 u32 reg;
1443
1444 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1445
1446 #define PHY_RESET_MAX_WAIT 100
1447 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1448 udelay(10);
1449
1450 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1451 if (!(reg & BMCR_RESET)) {
1452 udelay(20);
1453 break;
1454 }
1455 }
1456 if (i == PHY_RESET_MAX_WAIT) {
1457 return -EBUSY;
1458 }
1459 return 0;
1460 }
1461
1462 static u32
1463 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1464 {
1465 u32 adv = 0;
1466
1467 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1468 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1469
1470 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1471 adv = ADVERTISE_1000XPAUSE;
1472 }
1473 else {
1474 adv = ADVERTISE_PAUSE_CAP;
1475 }
1476 }
1477 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1478 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1479 adv = ADVERTISE_1000XPSE_ASYM;
1480 }
1481 else {
1482 adv = ADVERTISE_PAUSE_ASYM;
1483 }
1484 }
1485 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1486 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1487 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1488 }
1489 else {
1490 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1491 }
1492 }
1493 return adv;
1494 }
1495
1496 static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1497
1498 static int
1499 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1500 __releases(&bp->phy_lock)
1501 __acquires(&bp->phy_lock)
1502 {
1503 u32 speed_arg = 0, pause_adv;
1504
1505 pause_adv = bnx2_phy_get_pause_adv(bp);
1506
1507 if (bp->autoneg & AUTONEG_SPEED) {
1508 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1509 if (bp->advertising & ADVERTISED_10baseT_Half)
1510 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1511 if (bp->advertising & ADVERTISED_10baseT_Full)
1512 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1513 if (bp->advertising & ADVERTISED_100baseT_Half)
1514 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1515 if (bp->advertising & ADVERTISED_100baseT_Full)
1516 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1517 if (bp->advertising & ADVERTISED_1000baseT_Full)
1518 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1519 if (bp->advertising & ADVERTISED_2500baseX_Full)
1520 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1521 } else {
1522 if (bp->req_line_speed == SPEED_2500)
1523 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1524 else if (bp->req_line_speed == SPEED_1000)
1525 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1526 else if (bp->req_line_speed == SPEED_100) {
1527 if (bp->req_duplex == DUPLEX_FULL)
1528 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1529 else
1530 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1531 } else if (bp->req_line_speed == SPEED_10) {
1532 if (bp->req_duplex == DUPLEX_FULL)
1533 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1534 else
1535 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1536 }
1537 }
1538
1539 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1540 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1541 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1542 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1543
1544 if (port == PORT_TP)
1545 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1546 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1547
1548 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1549
1550 spin_unlock_bh(&bp->phy_lock);
1551 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1552 spin_lock_bh(&bp->phy_lock);
1553
1554 return 0;
1555 }
1556
1557 static int
1558 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1559 __releases(&bp->phy_lock)
1560 __acquires(&bp->phy_lock)
1561 {
1562 u32 adv, bmcr;
1563 u32 new_adv = 0;
1564
1565 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1566 return (bnx2_setup_remote_phy(bp, port));
1567
1568 if (!(bp->autoneg & AUTONEG_SPEED)) {
1569 u32 new_bmcr;
1570 int force_link_down = 0;
1571
1572 if (bp->req_line_speed == SPEED_2500) {
1573 if (!bnx2_test_and_enable_2g5(bp))
1574 force_link_down = 1;
1575 } else if (bp->req_line_speed == SPEED_1000) {
1576 if (bnx2_test_and_disable_2g5(bp))
1577 force_link_down = 1;
1578 }
1579 bnx2_read_phy(bp, bp->mii_adv, &adv);
1580 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1581
1582 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1583 new_bmcr = bmcr & ~BMCR_ANENABLE;
1584 new_bmcr |= BMCR_SPEED1000;
1585
1586 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1587 if (bp->req_line_speed == SPEED_2500)
1588 bnx2_enable_forced_2g5(bp);
1589 else if (bp->req_line_speed == SPEED_1000) {
1590 bnx2_disable_forced_2g5(bp);
1591 new_bmcr &= ~0x2000;
1592 }
1593
1594 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1595 if (bp->req_line_speed == SPEED_2500)
1596 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1597 else
1598 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1599 }
1600
1601 if (bp->req_duplex == DUPLEX_FULL) {
1602 adv |= ADVERTISE_1000XFULL;
1603 new_bmcr |= BMCR_FULLDPLX;
1604 }
1605 else {
1606 adv |= ADVERTISE_1000XHALF;
1607 new_bmcr &= ~BMCR_FULLDPLX;
1608 }
1609 if ((new_bmcr != bmcr) || (force_link_down)) {
1610 /* Force a link down visible on the other side */
1611 if (bp->link_up) {
1612 bnx2_write_phy(bp, bp->mii_adv, adv &
1613 ~(ADVERTISE_1000XFULL |
1614 ADVERTISE_1000XHALF));
1615 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1616 BMCR_ANRESTART | BMCR_ANENABLE);
1617
1618 bp->link_up = 0;
1619 netif_carrier_off(bp->dev);
1620 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1621 bnx2_report_link(bp);
1622 }
1623 bnx2_write_phy(bp, bp->mii_adv, adv);
1624 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1625 } else {
1626 bnx2_resolve_flow_ctrl(bp);
1627 bnx2_set_mac_link(bp);
1628 }
1629 return 0;
1630 }
1631
1632 bnx2_test_and_enable_2g5(bp);
1633
1634 if (bp->advertising & ADVERTISED_1000baseT_Full)
1635 new_adv |= ADVERTISE_1000XFULL;
1636
1637 new_adv |= bnx2_phy_get_pause_adv(bp);
1638
1639 bnx2_read_phy(bp, bp->mii_adv, &adv);
1640 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1641
1642 bp->serdes_an_pending = 0;
1643 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1644 /* Force a link down visible on the other side */
1645 if (bp->link_up) {
1646 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1647 spin_unlock_bh(&bp->phy_lock);
1648 msleep(20);
1649 spin_lock_bh(&bp->phy_lock);
1650 }
1651
1652 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1653 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1654 BMCR_ANENABLE);
1655 /* Speed up link-up time when the link partner
1656 * does not autonegotiate which is very common
1657 * in blade servers. Some blade servers use
1658 * IPMI for kerboard input and it's important
1659 * to minimize link disruptions. Autoneg. involves
1660 * exchanging base pages plus 3 next pages and
1661 * normally completes in about 120 msec.
1662 */
1663 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1664 bp->serdes_an_pending = 1;
1665 mod_timer(&bp->timer, jiffies + bp->current_interval);
1666 } else {
1667 bnx2_resolve_flow_ctrl(bp);
1668 bnx2_set_mac_link(bp);
1669 }
1670
1671 return 0;
1672 }
1673
1674 #define ETHTOOL_ALL_FIBRE_SPEED \
1675 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
1676 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1677 (ADVERTISED_1000baseT_Full)
1678
1679 #define ETHTOOL_ALL_COPPER_SPEED \
1680 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1681 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1682 ADVERTISED_1000baseT_Full)
1683
1684 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1685 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1686
1687 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1688
1689 static void
1690 bnx2_set_default_remote_link(struct bnx2 *bp)
1691 {
1692 u32 link;
1693
1694 if (bp->phy_port == PORT_TP)
1695 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1696 else
1697 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1698
1699 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1700 bp->req_line_speed = 0;
1701 bp->autoneg |= AUTONEG_SPEED;
1702 bp->advertising = ADVERTISED_Autoneg;
1703 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1704 bp->advertising |= ADVERTISED_10baseT_Half;
1705 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1706 bp->advertising |= ADVERTISED_10baseT_Full;
1707 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1708 bp->advertising |= ADVERTISED_100baseT_Half;
1709 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1710 bp->advertising |= ADVERTISED_100baseT_Full;
1711 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1712 bp->advertising |= ADVERTISED_1000baseT_Full;
1713 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1714 bp->advertising |= ADVERTISED_2500baseX_Full;
1715 } else {
1716 bp->autoneg = 0;
1717 bp->advertising = 0;
1718 bp->req_duplex = DUPLEX_FULL;
1719 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1720 bp->req_line_speed = SPEED_10;
1721 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1722 bp->req_duplex = DUPLEX_HALF;
1723 }
1724 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1725 bp->req_line_speed = SPEED_100;
1726 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1727 bp->req_duplex = DUPLEX_HALF;
1728 }
1729 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1730 bp->req_line_speed = SPEED_1000;
1731 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1732 bp->req_line_speed = SPEED_2500;
1733 }
1734 }
1735
1736 static void
1737 bnx2_set_default_link(struct bnx2 *bp)
1738 {
1739 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1740 bnx2_set_default_remote_link(bp);
1741 return;
1742 }
1743
1744 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1745 bp->req_line_speed = 0;
1746 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1747 u32 reg;
1748
1749 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1750
1751 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1752 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1753 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1754 bp->autoneg = 0;
1755 bp->req_line_speed = bp->line_speed = SPEED_1000;
1756 bp->req_duplex = DUPLEX_FULL;
1757 }
1758 } else
1759 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1760 }
1761
1762 static void
1763 bnx2_send_heart_beat(struct bnx2 *bp)
1764 {
1765 u32 msg;
1766 u32 addr;
1767
1768 spin_lock(&bp->indirect_lock);
1769 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1770 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1771 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1772 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1773 spin_unlock(&bp->indirect_lock);
1774 }
1775
1776 static void
1777 bnx2_remote_phy_event(struct bnx2 *bp)
1778 {
1779 u32 msg;
1780 u8 link_up = bp->link_up;
1781 u8 old_port;
1782
1783 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1784
1785 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1786 bnx2_send_heart_beat(bp);
1787
1788 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1789
1790 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1791 bp->link_up = 0;
1792 else {
1793 u32 speed;
1794
1795 bp->link_up = 1;
1796 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1797 bp->duplex = DUPLEX_FULL;
1798 switch (speed) {
1799 case BNX2_LINK_STATUS_10HALF:
1800 bp->duplex = DUPLEX_HALF;
1801 case BNX2_LINK_STATUS_10FULL:
1802 bp->line_speed = SPEED_10;
1803 break;
1804 case BNX2_LINK_STATUS_100HALF:
1805 bp->duplex = DUPLEX_HALF;
1806 case BNX2_LINK_STATUS_100BASE_T4:
1807 case BNX2_LINK_STATUS_100FULL:
1808 bp->line_speed = SPEED_100;
1809 break;
1810 case BNX2_LINK_STATUS_1000HALF:
1811 bp->duplex = DUPLEX_HALF;
1812 case BNX2_LINK_STATUS_1000FULL:
1813 bp->line_speed = SPEED_1000;
1814 break;
1815 case BNX2_LINK_STATUS_2500HALF:
1816 bp->duplex = DUPLEX_HALF;
1817 case BNX2_LINK_STATUS_2500FULL:
1818 bp->line_speed = SPEED_2500;
1819 break;
1820 default:
1821 bp->line_speed = 0;
1822 break;
1823 }
1824
1825 bp->flow_ctrl = 0;
1826 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1827 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1828 if (bp->duplex == DUPLEX_FULL)
1829 bp->flow_ctrl = bp->req_flow_ctrl;
1830 } else {
1831 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1832 bp->flow_ctrl |= FLOW_CTRL_TX;
1833 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1834 bp->flow_ctrl |= FLOW_CTRL_RX;
1835 }
1836
1837 old_port = bp->phy_port;
1838 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1839 bp->phy_port = PORT_FIBRE;
1840 else
1841 bp->phy_port = PORT_TP;
1842
1843 if (old_port != bp->phy_port)
1844 bnx2_set_default_link(bp);
1845
1846 }
1847 if (bp->link_up != link_up)
1848 bnx2_report_link(bp);
1849
1850 bnx2_set_mac_link(bp);
1851 }
1852
1853 static int
1854 bnx2_set_remote_link(struct bnx2 *bp)
1855 {
1856 u32 evt_code;
1857
1858 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
1859 switch (evt_code) {
1860 case BNX2_FW_EVT_CODE_LINK_EVENT:
1861 bnx2_remote_phy_event(bp);
1862 break;
1863 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1864 default:
1865 bnx2_send_heart_beat(bp);
1866 break;
1867 }
1868 return 0;
1869 }
1870
1871 static int
1872 bnx2_setup_copper_phy(struct bnx2 *bp)
1873 __releases(&bp->phy_lock)
1874 __acquires(&bp->phy_lock)
1875 {
1876 u32 bmcr;
1877 u32 new_bmcr;
1878
1879 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1880
1881 if (bp->autoneg & AUTONEG_SPEED) {
1882 u32 adv_reg, adv1000_reg;
1883 u32 new_adv_reg = 0;
1884 u32 new_adv1000_reg = 0;
1885
1886 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1887 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1888 ADVERTISE_PAUSE_ASYM);
1889
1890 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1891 adv1000_reg &= PHY_ALL_1000_SPEED;
1892
1893 if (bp->advertising & ADVERTISED_10baseT_Half)
1894 new_adv_reg |= ADVERTISE_10HALF;
1895 if (bp->advertising & ADVERTISED_10baseT_Full)
1896 new_adv_reg |= ADVERTISE_10FULL;
1897 if (bp->advertising & ADVERTISED_100baseT_Half)
1898 new_adv_reg |= ADVERTISE_100HALF;
1899 if (bp->advertising & ADVERTISED_100baseT_Full)
1900 new_adv_reg |= ADVERTISE_100FULL;
1901 if (bp->advertising & ADVERTISED_1000baseT_Full)
1902 new_adv1000_reg |= ADVERTISE_1000FULL;
1903
1904 new_adv_reg |= ADVERTISE_CSMA;
1905
1906 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1907
1908 if ((adv1000_reg != new_adv1000_reg) ||
1909 (adv_reg != new_adv_reg) ||
1910 ((bmcr & BMCR_ANENABLE) == 0)) {
1911
1912 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1913 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1914 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1915 BMCR_ANENABLE);
1916 }
1917 else if (bp->link_up) {
1918 /* Flow ctrl may have changed from auto to forced */
1919 /* or vice-versa. */
1920
1921 bnx2_resolve_flow_ctrl(bp);
1922 bnx2_set_mac_link(bp);
1923 }
1924 return 0;
1925 }
1926
1927 new_bmcr = 0;
1928 if (bp->req_line_speed == SPEED_100) {
1929 new_bmcr |= BMCR_SPEED100;
1930 }
1931 if (bp->req_duplex == DUPLEX_FULL) {
1932 new_bmcr |= BMCR_FULLDPLX;
1933 }
1934 if (new_bmcr != bmcr) {
1935 u32 bmsr;
1936
1937 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1938 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1939
1940 if (bmsr & BMSR_LSTATUS) {
1941 /* Force link down */
1942 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1943 spin_unlock_bh(&bp->phy_lock);
1944 msleep(50);
1945 spin_lock_bh(&bp->phy_lock);
1946
1947 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1948 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1949 }
1950
1951 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1952
1953 /* Normally, the new speed is setup after the link has
1954 * gone down and up again. In some cases, link will not go
1955 * down so we need to set up the new speed here.
1956 */
1957 if (bmsr & BMSR_LSTATUS) {
1958 bp->line_speed = bp->req_line_speed;
1959 bp->duplex = bp->req_duplex;
1960 bnx2_resolve_flow_ctrl(bp);
1961 bnx2_set_mac_link(bp);
1962 }
1963 } else {
1964 bnx2_resolve_flow_ctrl(bp);
1965 bnx2_set_mac_link(bp);
1966 }
1967 return 0;
1968 }
1969
1970 static int
1971 bnx2_setup_phy(struct bnx2 *bp, u8 port)
1972 __releases(&bp->phy_lock)
1973 __acquires(&bp->phy_lock)
1974 {
1975 if (bp->loopback == MAC_LOOPBACK)
1976 return 0;
1977
1978 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1979 return (bnx2_setup_serdes_phy(bp, port));
1980 }
1981 else {
1982 return (bnx2_setup_copper_phy(bp));
1983 }
1984 }
1985
1986 static int
1987 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
1988 {
1989 u32 val;
1990
1991 bp->mii_bmcr = MII_BMCR + 0x10;
1992 bp->mii_bmsr = MII_BMSR + 0x10;
1993 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1994 bp->mii_adv = MII_ADVERTISE + 0x10;
1995 bp->mii_lpa = MII_LPA + 0x10;
1996 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1997
1998 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1999 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2000
2001 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2002 if (reset_phy)
2003 bnx2_reset_phy(bp);
2004
2005 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2006
2007 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2008 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2009 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2010 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2011
2012 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2013 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2014 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2015 val |= BCM5708S_UP1_2G5;
2016 else
2017 val &= ~BCM5708S_UP1_2G5;
2018 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2019
2020 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2021 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2022 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2023 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2024
2025 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2026
2027 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2028 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2029 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2030
2031 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2032
2033 return 0;
2034 }
2035
2036 static int
2037 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2038 {
2039 u32 val;
2040
2041 if (reset_phy)
2042 bnx2_reset_phy(bp);
2043
2044 bp->mii_up1 = BCM5708S_UP1;
2045
2046 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2047 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2048 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2049
2050 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2051 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2052 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2053
2054 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2055 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2056 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2057
2058 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2059 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2060 val |= BCM5708S_UP1_2G5;
2061 bnx2_write_phy(bp, BCM5708S_UP1, val);
2062 }
2063
2064 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2065 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2066 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2067 /* increase tx signal amplitude */
2068 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2069 BCM5708S_BLK_ADDR_TX_MISC);
2070 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2071 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2072 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2073 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2074 }
2075
2076 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2077 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2078
2079 if (val) {
2080 u32 is_backplane;
2081
2082 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2083 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2084 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2085 BCM5708S_BLK_ADDR_TX_MISC);
2086 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2087 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2088 BCM5708S_BLK_ADDR_DIG);
2089 }
2090 }
2091 return 0;
2092 }
2093
2094 static int
2095 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2096 {
2097 if (reset_phy)
2098 bnx2_reset_phy(bp);
2099
2100 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2101
2102 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2103 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2104
2105 if (bp->dev->mtu > 1500) {
2106 u32 val;
2107
2108 /* Set extended packet length bit */
2109 bnx2_write_phy(bp, 0x18, 0x7);
2110 bnx2_read_phy(bp, 0x18, &val);
2111 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2112
2113 bnx2_write_phy(bp, 0x1c, 0x6c00);
2114 bnx2_read_phy(bp, 0x1c, &val);
2115 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2116 }
2117 else {
2118 u32 val;
2119
2120 bnx2_write_phy(bp, 0x18, 0x7);
2121 bnx2_read_phy(bp, 0x18, &val);
2122 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2123
2124 bnx2_write_phy(bp, 0x1c, 0x6c00);
2125 bnx2_read_phy(bp, 0x1c, &val);
2126 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2127 }
2128
2129 return 0;
2130 }
2131
2132 static int
2133 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2134 {
2135 u32 val;
2136
2137 if (reset_phy)
2138 bnx2_reset_phy(bp);
2139
2140 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2141 bnx2_write_phy(bp, 0x18, 0x0c00);
2142 bnx2_write_phy(bp, 0x17, 0x000a);
2143 bnx2_write_phy(bp, 0x15, 0x310b);
2144 bnx2_write_phy(bp, 0x17, 0x201f);
2145 bnx2_write_phy(bp, 0x15, 0x9506);
2146 bnx2_write_phy(bp, 0x17, 0x401f);
2147 bnx2_write_phy(bp, 0x15, 0x14e2);
2148 bnx2_write_phy(bp, 0x18, 0x0400);
2149 }
2150
2151 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2152 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2153 MII_BNX2_DSP_EXPAND_REG | 0x8);
2154 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2155 val &= ~(1 << 8);
2156 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2157 }
2158
2159 if (bp->dev->mtu > 1500) {
2160 /* Set extended packet length bit */
2161 bnx2_write_phy(bp, 0x18, 0x7);
2162 bnx2_read_phy(bp, 0x18, &val);
2163 bnx2_write_phy(bp, 0x18, val | 0x4000);
2164
2165 bnx2_read_phy(bp, 0x10, &val);
2166 bnx2_write_phy(bp, 0x10, val | 0x1);
2167 }
2168 else {
2169 bnx2_write_phy(bp, 0x18, 0x7);
2170 bnx2_read_phy(bp, 0x18, &val);
2171 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2172
2173 bnx2_read_phy(bp, 0x10, &val);
2174 bnx2_write_phy(bp, 0x10, val & ~0x1);
2175 }
2176
2177 /* ethernet@wirespeed */
2178 bnx2_write_phy(bp, 0x18, 0x7007);
2179 bnx2_read_phy(bp, 0x18, &val);
2180 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2181 return 0;
2182 }
2183
2184
2185 static int
2186 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2187 __releases(&bp->phy_lock)
2188 __acquires(&bp->phy_lock)
2189 {
2190 u32 val;
2191 int rc = 0;
2192
2193 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2194 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2195
2196 bp->mii_bmcr = MII_BMCR;
2197 bp->mii_bmsr = MII_BMSR;
2198 bp->mii_bmsr1 = MII_BMSR;
2199 bp->mii_adv = MII_ADVERTISE;
2200 bp->mii_lpa = MII_LPA;
2201
2202 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2203
2204 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2205 goto setup_phy;
2206
2207 bnx2_read_phy(bp, MII_PHYSID1, &val);
2208 bp->phy_id = val << 16;
2209 bnx2_read_phy(bp, MII_PHYSID2, &val);
2210 bp->phy_id |= val & 0xffff;
2211
2212 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2213 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2214 rc = bnx2_init_5706s_phy(bp, reset_phy);
2215 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2216 rc = bnx2_init_5708s_phy(bp, reset_phy);
2217 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2218 rc = bnx2_init_5709s_phy(bp, reset_phy);
2219 }
2220 else {
2221 rc = bnx2_init_copper_phy(bp, reset_phy);
2222 }
2223
2224 setup_phy:
2225 if (!rc)
2226 rc = bnx2_setup_phy(bp, bp->phy_port);
2227
2228 return rc;
2229 }
2230
2231 static int
2232 bnx2_set_mac_loopback(struct bnx2 *bp)
2233 {
2234 u32 mac_mode;
2235
2236 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2237 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2238 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2239 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2240 bp->link_up = 1;
2241 return 0;
2242 }
2243
2244 static int bnx2_test_link(struct bnx2 *);
2245
2246 static int
2247 bnx2_set_phy_loopback(struct bnx2 *bp)
2248 {
2249 u32 mac_mode;
2250 int rc, i;
2251
2252 spin_lock_bh(&bp->phy_lock);
2253 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2254 BMCR_SPEED1000);
2255 spin_unlock_bh(&bp->phy_lock);
2256 if (rc)
2257 return rc;
2258
2259 for (i = 0; i < 10; i++) {
2260 if (bnx2_test_link(bp) == 0)
2261 break;
2262 msleep(100);
2263 }
2264
2265 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2266 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2267 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2268 BNX2_EMAC_MODE_25G_MODE);
2269
2270 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2271 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2272 bp->link_up = 1;
2273 return 0;
2274 }
2275
2276 static int
2277 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2278 {
2279 int i;
2280 u32 val;
2281
2282 bp->fw_wr_seq++;
2283 msg_data |= bp->fw_wr_seq;
2284
2285 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2286
2287 if (!ack)
2288 return 0;
2289
2290 /* wait for an acknowledgement. */
2291 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
2292 msleep(10);
2293
2294 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2295
2296 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2297 break;
2298 }
2299 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2300 return 0;
2301
2302 /* If we timed out, inform the firmware that this is the case. */
2303 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2304 if (!silent)
2305 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2306 "%x\n", msg_data);
2307
2308 msg_data &= ~BNX2_DRV_MSG_CODE;
2309 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2310
2311 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2312
2313 return -EBUSY;
2314 }
2315
2316 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2317 return -EIO;
2318
2319 return 0;
2320 }
2321
2322 static int
2323 bnx2_init_5709_context(struct bnx2 *bp)
2324 {
2325 int i, ret = 0;
2326 u32 val;
2327
2328 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2329 val |= (BCM_PAGE_BITS - 8) << 16;
2330 REG_WR(bp, BNX2_CTX_COMMAND, val);
2331 for (i = 0; i < 10; i++) {
2332 val = REG_RD(bp, BNX2_CTX_COMMAND);
2333 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2334 break;
2335 udelay(2);
2336 }
2337 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2338 return -EBUSY;
2339
2340 for (i = 0; i < bp->ctx_pages; i++) {
2341 int j;
2342
2343 if (bp->ctx_blk[i])
2344 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2345 else
2346 return -ENOMEM;
2347
2348 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2349 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2350 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2351 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2352 (u64) bp->ctx_blk_mapping[i] >> 32);
2353 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2354 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2355 for (j = 0; j < 10; j++) {
2356
2357 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2358 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2359 break;
2360 udelay(5);
2361 }
2362 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2363 ret = -EBUSY;
2364 break;
2365 }
2366 }
2367 return ret;
2368 }
2369
2370 static void
2371 bnx2_init_context(struct bnx2 *bp)
2372 {
2373 u32 vcid;
2374
2375 vcid = 96;
2376 while (vcid) {
2377 u32 vcid_addr, pcid_addr, offset;
2378 int i;
2379
2380 vcid--;
2381
2382 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2383 u32 new_vcid;
2384
2385 vcid_addr = GET_PCID_ADDR(vcid);
2386 if (vcid & 0x8) {
2387 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2388 }
2389 else {
2390 new_vcid = vcid;
2391 }
2392 pcid_addr = GET_PCID_ADDR(new_vcid);
2393 }
2394 else {
2395 vcid_addr = GET_CID_ADDR(vcid);
2396 pcid_addr = vcid_addr;
2397 }
2398
2399 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2400 vcid_addr += (i << PHY_CTX_SHIFT);
2401 pcid_addr += (i << PHY_CTX_SHIFT);
2402
2403 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2404 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2405
2406 /* Zero out the context. */
2407 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2408 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2409 }
2410 }
2411 }
2412
2413 static int
2414 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2415 {
2416 u16 *good_mbuf;
2417 u32 good_mbuf_cnt;
2418 u32 val;
2419
2420 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2421 if (good_mbuf == NULL) {
2422 printk(KERN_ERR PFX "Failed to allocate memory in "
2423 "bnx2_alloc_bad_rbuf\n");
2424 return -ENOMEM;
2425 }
2426
2427 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2428 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2429
2430 good_mbuf_cnt = 0;
2431
2432 /* Allocate a bunch of mbufs and save the good ones in an array. */
2433 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2434 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2435 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2436 BNX2_RBUF_COMMAND_ALLOC_REQ);
2437
2438 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2439
2440 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2441
2442 /* The addresses with Bit 9 set are bad memory blocks. */
2443 if (!(val & (1 << 9))) {
2444 good_mbuf[good_mbuf_cnt] = (u16) val;
2445 good_mbuf_cnt++;
2446 }
2447
2448 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2449 }
2450
2451 /* Free the good ones back to the mbuf pool thus discarding
2452 * all the bad ones. */
2453 while (good_mbuf_cnt) {
2454 good_mbuf_cnt--;
2455
2456 val = good_mbuf[good_mbuf_cnt];
2457 val = (val << 9) | val | 1;
2458
2459 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2460 }
2461 kfree(good_mbuf);
2462 return 0;
2463 }
2464
2465 static void
2466 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2467 {
2468 u32 val;
2469
2470 val = (mac_addr[0] << 8) | mac_addr[1];
2471
2472 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2473
2474 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2475 (mac_addr[4] << 8) | mac_addr[5];
2476
2477 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2478 }
2479
2480 static inline int
2481 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2482 {
2483 dma_addr_t mapping;
2484 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2485 struct rx_bd *rxbd =
2486 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2487 struct page *page = alloc_page(GFP_ATOMIC);
2488
2489 if (!page)
2490 return -ENOMEM;
2491 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2492 PCI_DMA_FROMDEVICE);
2493 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2494 __free_page(page);
2495 return -EIO;
2496 }
2497
2498 rx_pg->page = page;
2499 pci_unmap_addr_set(rx_pg, mapping, mapping);
2500 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2501 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2502 return 0;
2503 }
2504
2505 static void
2506 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2507 {
2508 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2509 struct page *page = rx_pg->page;
2510
2511 if (!page)
2512 return;
2513
2514 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2515 PCI_DMA_FROMDEVICE);
2516
2517 __free_page(page);
2518 rx_pg->page = NULL;
2519 }
2520
2521 static inline int
2522 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2523 {
2524 struct sk_buff *skb;
2525 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2526 dma_addr_t mapping;
2527 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2528 unsigned long align;
2529
2530 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2531 if (skb == NULL) {
2532 return -ENOMEM;
2533 }
2534
2535 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2536 skb_reserve(skb, BNX2_RX_ALIGN - align);
2537
2538 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2539 PCI_DMA_FROMDEVICE);
2540 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2541 dev_kfree_skb(skb);
2542 return -EIO;
2543 }
2544
2545 rx_buf->skb = skb;
2546 pci_unmap_addr_set(rx_buf, mapping, mapping);
2547
2548 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2549 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2550
2551 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2552
2553 return 0;
2554 }
2555
2556 static int
2557 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2558 {
2559 struct status_block *sblk = bnapi->status_blk.msi;
2560 u32 new_link_state, old_link_state;
2561 int is_set = 1;
2562
2563 new_link_state = sblk->status_attn_bits & event;
2564 old_link_state = sblk->status_attn_bits_ack & event;
2565 if (new_link_state != old_link_state) {
2566 if (new_link_state)
2567 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2568 else
2569 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2570 } else
2571 is_set = 0;
2572
2573 return is_set;
2574 }
2575
2576 static void
2577 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2578 {
2579 spin_lock(&bp->phy_lock);
2580
2581 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2582 bnx2_set_link(bp);
2583 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2584 bnx2_set_remote_link(bp);
2585
2586 spin_unlock(&bp->phy_lock);
2587
2588 }
2589
2590 static inline u16
2591 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2592 {
2593 u16 cons;
2594
2595 /* Tell compiler that status block fields can change. */
2596 barrier();
2597 cons = *bnapi->hw_tx_cons_ptr;
2598 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2599 cons++;
2600 return cons;
2601 }
2602
2603 static int
2604 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2605 {
2606 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2607 u16 hw_cons, sw_cons, sw_ring_cons;
2608 int tx_pkt = 0, index;
2609 struct netdev_queue *txq;
2610
2611 index = (bnapi - bp->bnx2_napi);
2612 txq = netdev_get_tx_queue(bp->dev, index);
2613
2614 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2615 sw_cons = txr->tx_cons;
2616
2617 while (sw_cons != hw_cons) {
2618 struct sw_tx_bd *tx_buf;
2619 struct sk_buff *skb;
2620 int i, last;
2621
2622 sw_ring_cons = TX_RING_IDX(sw_cons);
2623
2624 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2625 skb = tx_buf->skb;
2626
2627 /* partial BD completions possible with TSO packets */
2628 if (skb_is_gso(skb)) {
2629 u16 last_idx, last_ring_idx;
2630
2631 last_idx = sw_cons +
2632 skb_shinfo(skb)->nr_frags + 1;
2633 last_ring_idx = sw_ring_cons +
2634 skb_shinfo(skb)->nr_frags + 1;
2635 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2636 last_idx++;
2637 }
2638 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2639 break;
2640 }
2641 }
2642
2643 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
2644
2645 tx_buf->skb = NULL;
2646 last = skb_shinfo(skb)->nr_frags;
2647
2648 for (i = 0; i < last; i++) {
2649 sw_cons = NEXT_TX_BD(sw_cons);
2650 }
2651
2652 sw_cons = NEXT_TX_BD(sw_cons);
2653
2654 dev_kfree_skb(skb);
2655 tx_pkt++;
2656 if (tx_pkt == budget)
2657 break;
2658
2659 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2660 }
2661
2662 txr->hw_tx_cons = hw_cons;
2663 txr->tx_cons = sw_cons;
2664
2665 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2666 * before checking for netif_tx_queue_stopped(). Without the
2667 * memory barrier, there is a small possibility that bnx2_start_xmit()
2668 * will miss it and cause the queue to be stopped forever.
2669 */
2670 smp_mb();
2671
2672 if (unlikely(netif_tx_queue_stopped(txq)) &&
2673 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2674 __netif_tx_lock(txq, smp_processor_id());
2675 if ((netif_tx_queue_stopped(txq)) &&
2676 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2677 netif_tx_wake_queue(txq);
2678 __netif_tx_unlock(txq);
2679 }
2680
2681 return tx_pkt;
2682 }
2683
2684 static void
2685 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2686 struct sk_buff *skb, int count)
2687 {
2688 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2689 struct rx_bd *cons_bd, *prod_bd;
2690 int i;
2691 u16 hw_prod, prod;
2692 u16 cons = rxr->rx_pg_cons;
2693
2694 cons_rx_pg = &rxr->rx_pg_ring[cons];
2695
2696 /* The caller was unable to allocate a new page to replace the
2697 * last one in the frags array, so we need to recycle that page
2698 * and then free the skb.
2699 */
2700 if (skb) {
2701 struct page *page;
2702 struct skb_shared_info *shinfo;
2703
2704 shinfo = skb_shinfo(skb);
2705 shinfo->nr_frags--;
2706 page = shinfo->frags[shinfo->nr_frags].page;
2707 shinfo->frags[shinfo->nr_frags].page = NULL;
2708
2709 cons_rx_pg->page = page;
2710 dev_kfree_skb(skb);
2711 }
2712
2713 hw_prod = rxr->rx_pg_prod;
2714
2715 for (i = 0; i < count; i++) {
2716 prod = RX_PG_RING_IDX(hw_prod);
2717
2718 prod_rx_pg = &rxr->rx_pg_ring[prod];
2719 cons_rx_pg = &rxr->rx_pg_ring[cons];
2720 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2721 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2722
2723 if (prod != cons) {
2724 prod_rx_pg->page = cons_rx_pg->page;
2725 cons_rx_pg->page = NULL;
2726 pci_unmap_addr_set(prod_rx_pg, mapping,
2727 pci_unmap_addr(cons_rx_pg, mapping));
2728
2729 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2730 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2731
2732 }
2733 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2734 hw_prod = NEXT_RX_BD(hw_prod);
2735 }
2736 rxr->rx_pg_prod = hw_prod;
2737 rxr->rx_pg_cons = cons;
2738 }
2739
2740 static inline void
2741 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2742 struct sk_buff *skb, u16 cons, u16 prod)
2743 {
2744 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2745 struct rx_bd *cons_bd, *prod_bd;
2746
2747 cons_rx_buf = &rxr->rx_buf_ring[cons];
2748 prod_rx_buf = &rxr->rx_buf_ring[prod];
2749
2750 pci_dma_sync_single_for_device(bp->pdev,
2751 pci_unmap_addr(cons_rx_buf, mapping),
2752 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2753
2754 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2755
2756 prod_rx_buf->skb = skb;
2757
2758 if (cons == prod)
2759 return;
2760
2761 pci_unmap_addr_set(prod_rx_buf, mapping,
2762 pci_unmap_addr(cons_rx_buf, mapping));
2763
2764 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2765 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2766 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2767 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2768 }
2769
2770 static int
2771 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2772 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2773 u32 ring_idx)
2774 {
2775 int err;
2776 u16 prod = ring_idx & 0xffff;
2777
2778 err = bnx2_alloc_rx_skb(bp, rxr, prod);
2779 if (unlikely(err)) {
2780 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2781 if (hdr_len) {
2782 unsigned int raw_len = len + 4;
2783 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2784
2785 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2786 }
2787 return err;
2788 }
2789
2790 skb_reserve(skb, BNX2_RX_OFFSET);
2791 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2792 PCI_DMA_FROMDEVICE);
2793
2794 if (hdr_len == 0) {
2795 skb_put(skb, len);
2796 return 0;
2797 } else {
2798 unsigned int i, frag_len, frag_size, pages;
2799 struct sw_pg *rx_pg;
2800 u16 pg_cons = rxr->rx_pg_cons;
2801 u16 pg_prod = rxr->rx_pg_prod;
2802
2803 frag_size = len + 4 - hdr_len;
2804 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2805 skb_put(skb, hdr_len);
2806
2807 for (i = 0; i < pages; i++) {
2808 dma_addr_t mapping_old;
2809
2810 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2811 if (unlikely(frag_len <= 4)) {
2812 unsigned int tail = 4 - frag_len;
2813
2814 rxr->rx_pg_cons = pg_cons;
2815 rxr->rx_pg_prod = pg_prod;
2816 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
2817 pages - i);
2818 skb->len -= tail;
2819 if (i == 0) {
2820 skb->tail -= tail;
2821 } else {
2822 skb_frag_t *frag =
2823 &skb_shinfo(skb)->frags[i - 1];
2824 frag->size -= tail;
2825 skb->data_len -= tail;
2826 skb->truesize -= tail;
2827 }
2828 return 0;
2829 }
2830 rx_pg = &rxr->rx_pg_ring[pg_cons];
2831
2832 /* Don't unmap yet. If we're unable to allocate a new
2833 * page, we need to recycle the page and the DMA addr.
2834 */
2835 mapping_old = pci_unmap_addr(rx_pg, mapping);
2836 if (i == pages - 1)
2837 frag_len -= 4;
2838
2839 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2840 rx_pg->page = NULL;
2841
2842 err = bnx2_alloc_rx_page(bp, rxr,
2843 RX_PG_RING_IDX(pg_prod));
2844 if (unlikely(err)) {
2845 rxr->rx_pg_cons = pg_cons;
2846 rxr->rx_pg_prod = pg_prod;
2847 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
2848 pages - i);
2849 return err;
2850 }
2851
2852 pci_unmap_page(bp->pdev, mapping_old,
2853 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2854
2855 frag_size -= frag_len;
2856 skb->data_len += frag_len;
2857 skb->truesize += frag_len;
2858 skb->len += frag_len;
2859
2860 pg_prod = NEXT_RX_BD(pg_prod);
2861 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2862 }
2863 rxr->rx_pg_prod = pg_prod;
2864 rxr->rx_pg_cons = pg_cons;
2865 }
2866 return 0;
2867 }
2868
2869 static inline u16
2870 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
2871 {
2872 u16 cons;
2873
2874 /* Tell compiler that status block fields can change. */
2875 barrier();
2876 cons = *bnapi->hw_rx_cons_ptr;
2877 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2878 cons++;
2879 return cons;
2880 }
2881
2882 static int
2883 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2884 {
2885 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
2886 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2887 struct l2_fhdr *rx_hdr;
2888 int rx_pkt = 0, pg_ring_used = 0;
2889
2890 hw_cons = bnx2_get_hw_rx_cons(bnapi);
2891 sw_cons = rxr->rx_cons;
2892 sw_prod = rxr->rx_prod;
2893
2894 /* Memory barrier necessary as speculative reads of the rx
2895 * buffer can be ahead of the index in the status block
2896 */
2897 rmb();
2898 while (sw_cons != hw_cons) {
2899 unsigned int len, hdr_len;
2900 u32 status;
2901 struct sw_bd *rx_buf;
2902 struct sk_buff *skb;
2903 dma_addr_t dma_addr;
2904 u16 vtag = 0;
2905 int hw_vlan __maybe_unused = 0;
2906
2907 sw_ring_cons = RX_RING_IDX(sw_cons);
2908 sw_ring_prod = RX_RING_IDX(sw_prod);
2909
2910 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
2911 skb = rx_buf->skb;
2912
2913 rx_buf->skb = NULL;
2914
2915 dma_addr = pci_unmap_addr(rx_buf, mapping);
2916
2917 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2918 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
2919 PCI_DMA_FROMDEVICE);
2920
2921 rx_hdr = (struct l2_fhdr *) skb->data;
2922 len = rx_hdr->l2_fhdr_pkt_len;
2923 status = rx_hdr->l2_fhdr_status;
2924
2925 hdr_len = 0;
2926 if (status & L2_FHDR_STATUS_SPLIT) {
2927 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2928 pg_ring_used = 1;
2929 } else if (len > bp->rx_jumbo_thresh) {
2930 hdr_len = bp->rx_jumbo_thresh;
2931 pg_ring_used = 1;
2932 }
2933
2934 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
2935 L2_FHDR_ERRORS_PHY_DECODE |
2936 L2_FHDR_ERRORS_ALIGNMENT |
2937 L2_FHDR_ERRORS_TOO_SHORT |
2938 L2_FHDR_ERRORS_GIANT_FRAME))) {
2939
2940 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2941 sw_ring_prod);
2942 if (pg_ring_used) {
2943 int pages;
2944
2945 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
2946
2947 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2948 }
2949 goto next_rx;
2950 }
2951
2952 len -= 4;
2953
2954 if (len <= bp->rx_copy_thresh) {
2955 struct sk_buff *new_skb;
2956
2957 new_skb = netdev_alloc_skb(bp->dev, len + 6);
2958 if (new_skb == NULL) {
2959 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2960 sw_ring_prod);
2961 goto next_rx;
2962 }
2963
2964 /* aligned copy */
2965 skb_copy_from_linear_data_offset(skb,
2966 BNX2_RX_OFFSET - 6,
2967 new_skb->data, len + 6);
2968 skb_reserve(new_skb, 6);
2969 skb_put(new_skb, len);
2970
2971 bnx2_reuse_rx_skb(bp, rxr, skb,
2972 sw_ring_cons, sw_ring_prod);
2973
2974 skb = new_skb;
2975 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
2976 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
2977 goto next_rx;
2978
2979 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
2980 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
2981 vtag = rx_hdr->l2_fhdr_vlan_tag;
2982 #ifdef BCM_VLAN
2983 if (bp->vlgrp)
2984 hw_vlan = 1;
2985 else
2986 #endif
2987 {
2988 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
2989 __skb_push(skb, 4);
2990
2991 memmove(ve, skb->data + 4, ETH_ALEN * 2);
2992 ve->h_vlan_proto = htons(ETH_P_8021Q);
2993 ve->h_vlan_TCI = htons(vtag);
2994 len += 4;
2995 }
2996 }
2997
2998 skb->protocol = eth_type_trans(skb, bp->dev);
2999
3000 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
3001 (ntohs(skb->protocol) != 0x8100)) {
3002
3003 dev_kfree_skb(skb);
3004 goto next_rx;
3005
3006 }
3007
3008 skb->ip_summed = CHECKSUM_NONE;
3009 if (bp->rx_csum &&
3010 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3011 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3012
3013 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3014 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
3015 skb->ip_summed = CHECKSUM_UNNECESSARY;
3016 }
3017
3018 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
3019
3020 #ifdef BCM_VLAN
3021 if (hw_vlan)
3022 vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
3023 else
3024 #endif
3025 netif_receive_skb(skb);
3026
3027 rx_pkt++;
3028
3029 next_rx:
3030 sw_cons = NEXT_RX_BD(sw_cons);
3031 sw_prod = NEXT_RX_BD(sw_prod);
3032
3033 if ((rx_pkt == budget))
3034 break;
3035
3036 /* Refresh hw_cons to see if there is new work */
3037 if (sw_cons == hw_cons) {
3038 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3039 rmb();
3040 }
3041 }
3042 rxr->rx_cons = sw_cons;
3043 rxr->rx_prod = sw_prod;
3044
3045 if (pg_ring_used)
3046 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3047
3048 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3049
3050 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3051
3052 mmiowb();
3053
3054 return rx_pkt;
3055
3056 }
3057
3058 /* MSI ISR - The only difference between this and the INTx ISR
3059 * is that the MSI interrupt is always serviced.
3060 */
3061 static irqreturn_t
3062 bnx2_msi(int irq, void *dev_instance)
3063 {
3064 struct bnx2_napi *bnapi = dev_instance;
3065 struct bnx2 *bp = bnapi->bp;
3066
3067 prefetch(bnapi->status_blk.msi);
3068 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3069 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3070 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3071
3072 /* Return here if interrupt is disabled. */
3073 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3074 return IRQ_HANDLED;
3075
3076 napi_schedule(&bnapi->napi);
3077
3078 return IRQ_HANDLED;
3079 }
3080
3081 static irqreturn_t
3082 bnx2_msi_1shot(int irq, void *dev_instance)
3083 {
3084 struct bnx2_napi *bnapi = dev_instance;
3085 struct bnx2 *bp = bnapi->bp;
3086
3087 prefetch(bnapi->status_blk.msi);
3088
3089 /* Return here if interrupt is disabled. */
3090 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3091 return IRQ_HANDLED;
3092
3093 napi_schedule(&bnapi->napi);
3094
3095 return IRQ_HANDLED;
3096 }
3097
3098 static irqreturn_t
3099 bnx2_interrupt(int irq, void *dev_instance)
3100 {
3101 struct bnx2_napi *bnapi = dev_instance;
3102 struct bnx2 *bp = bnapi->bp;
3103 struct status_block *sblk = bnapi->status_blk.msi;
3104
3105 /* When using INTx, it is possible for the interrupt to arrive
3106 * at the CPU before the status block posted prior to the
3107 * interrupt. Reading a register will flush the status block.
3108 * When using MSI, the MSI message will always complete after
3109 * the status block write.
3110 */
3111 if ((sblk->status_idx == bnapi->last_status_idx) &&
3112 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3113 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3114 return IRQ_NONE;
3115
3116 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3117 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3118 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3119
3120 /* Read back to deassert IRQ immediately to avoid too many
3121 * spurious interrupts.
3122 */
3123 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3124
3125 /* Return here if interrupt is shared and is disabled. */
3126 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3127 return IRQ_HANDLED;
3128
3129 if (napi_schedule_prep(&bnapi->napi)) {
3130 bnapi->last_status_idx = sblk->status_idx;
3131 __napi_schedule(&bnapi->napi);
3132 }
3133
3134 return IRQ_HANDLED;
3135 }
3136
3137 static inline int
3138 bnx2_has_fast_work(struct bnx2_napi *bnapi)
3139 {
3140 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3141 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3142
3143 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3144 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3145 return 1;
3146 return 0;
3147 }
3148
3149 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3150 STATUS_ATTN_BITS_TIMER_ABORT)
3151
3152 static inline int
3153 bnx2_has_work(struct bnx2_napi *bnapi)
3154 {
3155 struct status_block *sblk = bnapi->status_blk.msi;
3156
3157 if (bnx2_has_fast_work(bnapi))
3158 return 1;
3159
3160 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3161 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3162 return 1;
3163
3164 return 0;
3165 }
3166
3167 static void
3168 bnx2_chk_missed_msi(struct bnx2 *bp)
3169 {
3170 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3171 u32 msi_ctrl;
3172
3173 if (bnx2_has_work(bnapi)) {
3174 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3175 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3176 return;
3177
3178 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3179 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3180 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3181 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3182 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3183 }
3184 }
3185
3186 bp->idle_chk_status_idx = bnapi->last_status_idx;
3187 }
3188
3189 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3190 {
3191 struct status_block *sblk = bnapi->status_blk.msi;
3192 u32 status_attn_bits = sblk->status_attn_bits;
3193 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3194
3195 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3196 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3197
3198 bnx2_phy_int(bp, bnapi);
3199
3200 /* This is needed to take care of transient status
3201 * during link changes.
3202 */
3203 REG_WR(bp, BNX2_HC_COMMAND,
3204 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3205 REG_RD(bp, BNX2_HC_COMMAND);
3206 }
3207 }
3208
3209 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3210 int work_done, int budget)
3211 {
3212 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3213 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3214
3215 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3216 bnx2_tx_int(bp, bnapi, 0);
3217
3218 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3219 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3220
3221 return work_done;
3222 }
3223
3224 static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3225 {
3226 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3227 struct bnx2 *bp = bnapi->bp;
3228 int work_done = 0;
3229 struct status_block_msix *sblk = bnapi->status_blk.msix;
3230
3231 while (1) {
3232 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3233 if (unlikely(work_done >= budget))
3234 break;
3235
3236 bnapi->last_status_idx = sblk->status_idx;
3237 /* status idx must be read before checking for more work. */
3238 rmb();
3239 if (likely(!bnx2_has_fast_work(bnapi))) {
3240
3241 napi_complete(napi);
3242 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3243 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3244 bnapi->last_status_idx);
3245 break;
3246 }
3247 }
3248 return work_done;
3249 }
3250
3251 static int bnx2_poll(struct napi_struct *napi, int budget)
3252 {
3253 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3254 struct bnx2 *bp = bnapi->bp;
3255 int work_done = 0;
3256 struct status_block *sblk = bnapi->status_blk.msi;
3257
3258 while (1) {
3259 bnx2_poll_link(bp, bnapi);
3260
3261 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3262
3263 /* bnapi->last_status_idx is used below to tell the hw how
3264 * much work has been processed, so we must read it before
3265 * checking for more work.
3266 */
3267 bnapi->last_status_idx = sblk->status_idx;
3268
3269 if (unlikely(work_done >= budget))
3270 break;
3271
3272 rmb();
3273 if (likely(!bnx2_has_work(bnapi))) {
3274 napi_complete(napi);
3275 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3276 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3277 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3278 bnapi->last_status_idx);
3279 break;
3280 }
3281 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3282 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3283 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3284 bnapi->last_status_idx);
3285
3286 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3287 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3288 bnapi->last_status_idx);
3289 break;
3290 }
3291 }
3292
3293 return work_done;
3294 }
3295
3296 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3297 * from set_multicast.
3298 */
3299 static void
3300 bnx2_set_rx_mode(struct net_device *dev)
3301 {
3302 struct bnx2 *bp = netdev_priv(dev);
3303 u32 rx_mode, sort_mode;
3304 struct dev_addr_list *uc_ptr;
3305 int i;
3306
3307 if (!netif_running(dev))
3308 return;
3309
3310 spin_lock_bh(&bp->phy_lock);
3311
3312 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3313 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3314 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3315 #ifdef BCM_VLAN
3316 if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3317 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3318 #else
3319 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
3320 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3321 #endif
3322 if (dev->flags & IFF_PROMISC) {
3323 /* Promiscuous mode. */
3324 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3325 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3326 BNX2_RPM_SORT_USER0_PROM_VLAN;
3327 }
3328 else if (dev->flags & IFF_ALLMULTI) {
3329 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3330 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3331 0xffffffff);
3332 }
3333 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3334 }
3335 else {
3336 /* Accept one or more multicast(s). */
3337 struct dev_mc_list *mclist;
3338 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3339 u32 regidx;
3340 u32 bit;
3341 u32 crc;
3342
3343 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3344
3345 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3346 i++, mclist = mclist->next) {
3347
3348 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3349 bit = crc & 0xff;
3350 regidx = (bit & 0xe0) >> 5;
3351 bit &= 0x1f;
3352 mc_filter[regidx] |= (1 << bit);
3353 }
3354
3355 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3356 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3357 mc_filter[i]);
3358 }
3359
3360 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3361 }
3362
3363 uc_ptr = NULL;
3364 if (dev->uc_count > BNX2_MAX_UNICAST_ADDRESSES) {
3365 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3366 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3367 BNX2_RPM_SORT_USER0_PROM_VLAN;
3368 } else if (!(dev->flags & IFF_PROMISC)) {
3369 uc_ptr = dev->uc_list;
3370
3371 /* Add all entries into to the match filter list */
3372 for (i = 0; i < dev->uc_count; i++) {
3373 bnx2_set_mac_addr(bp, uc_ptr->da_addr,
3374 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3375 sort_mode |= (1 <<
3376 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3377 uc_ptr = uc_ptr->next;
3378 }
3379
3380 }
3381
3382 if (rx_mode != bp->rx_mode) {
3383 bp->rx_mode = rx_mode;
3384 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3385 }
3386
3387 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3388 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3389 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3390
3391 spin_unlock_bh(&bp->phy_lock);
3392 }
3393
3394 static void
3395 load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
3396 u32 rv2p_proc)
3397 {
3398 int i;
3399 u32 val;
3400
3401 if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) {
3402 val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]);
3403 val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK;
3404 val |= XI_RV2P_PROC2_BD_PAGE_SIZE;
3405 rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val);
3406 }
3407
3408 for (i = 0; i < rv2p_code_len; i += 8) {
3409 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
3410 rv2p_code++;
3411 REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
3412 rv2p_code++;
3413
3414 if (rv2p_proc == RV2P_PROC1) {
3415 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3416 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
3417 }
3418 else {
3419 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3420 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
3421 }
3422 }
3423
3424 /* Reset the processor, un-stall is done later. */
3425 if (rv2p_proc == RV2P_PROC1) {
3426 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3427 }
3428 else {
3429 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3430 }
3431 }
3432
3433 static int
3434 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, struct fw_info *fw)
3435 {
3436 u32 offset;
3437 u32 val;
3438 int rc;
3439
3440 /* Halt the CPU. */
3441 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3442 val |= cpu_reg->mode_value_halt;
3443 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3444 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3445
3446 /* Load the Text area. */
3447 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
3448 if (fw->gz_text) {
3449 int j;
3450
3451 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3452 fw->gz_text_len);
3453 if (rc < 0)
3454 return rc;
3455
3456 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
3457 bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
3458 }
3459 }
3460
3461 /* Load the Data area. */
3462 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3463 if (fw->data) {
3464 int j;
3465
3466 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
3467 bnx2_reg_wr_ind(bp, offset, fw->data[j]);
3468 }
3469 }
3470
3471 /* Load the SBSS area. */
3472 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
3473 if (fw->sbss_len) {
3474 int j;
3475
3476 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
3477 bnx2_reg_wr_ind(bp, offset, 0);
3478 }
3479 }
3480
3481 /* Load the BSS area. */
3482 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
3483 if (fw->bss_len) {
3484 int j;
3485
3486 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
3487 bnx2_reg_wr_ind(bp, offset, 0);
3488 }
3489 }
3490
3491 /* Load the Read-Only area. */
3492 offset = cpu_reg->spad_base +
3493 (fw->rodata_addr - cpu_reg->mips_view_base);
3494 if (fw->rodata) {
3495 int j;
3496
3497 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
3498 bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
3499 }
3500 }
3501
3502 /* Clear the pre-fetch instruction. */
3503 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3504 bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
3505
3506 /* Start the CPU. */
3507 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3508 val &= ~cpu_reg->mode_value_halt;
3509 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3510 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3511
3512 return 0;
3513 }
3514
3515 static int
3516 bnx2_init_cpus(struct bnx2 *bp)
3517 {
3518 struct fw_info *fw;
3519 int rc, rv2p_len;
3520 void *text, *rv2p;
3521
3522 /* Initialize the RV2P processor. */
3523 text = vmalloc(FW_BUF_SIZE);
3524 if (!text)
3525 return -ENOMEM;
3526 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3527 rv2p = bnx2_xi_rv2p_proc1;
3528 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3529 } else {
3530 rv2p = bnx2_rv2p_proc1;
3531 rv2p_len = sizeof(bnx2_rv2p_proc1);
3532 }
3533 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3534 if (rc < 0)
3535 goto init_cpu_err;
3536
3537 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
3538
3539 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3540 rv2p = bnx2_xi_rv2p_proc2;
3541 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3542 } else {
3543 rv2p = bnx2_rv2p_proc2;
3544 rv2p_len = sizeof(bnx2_rv2p_proc2);
3545 }
3546 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3547 if (rc < 0)
3548 goto init_cpu_err;
3549
3550 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
3551
3552 /* Initialize the RX Processor. */
3553 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3554 fw = &bnx2_rxp_fw_09;
3555 else
3556 fw = &bnx2_rxp_fw_06;
3557
3558 fw->text = text;
3559 rc = load_cpu_fw(bp, &cpu_reg_rxp, fw);
3560 if (rc)
3561 goto init_cpu_err;
3562
3563 /* Initialize the TX Processor. */
3564 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3565 fw = &bnx2_txp_fw_09;
3566 else
3567 fw = &bnx2_txp_fw_06;
3568
3569 fw->text = text;
3570 rc = load_cpu_fw(bp, &cpu_reg_txp, fw);
3571 if (rc)
3572 goto init_cpu_err;
3573
3574 /* Initialize the TX Patch-up Processor. */
3575 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3576 fw = &bnx2_tpat_fw_09;
3577 else
3578 fw = &bnx2_tpat_fw_06;
3579
3580 fw->text = text;
3581 rc = load_cpu_fw(bp, &cpu_reg_tpat, fw);
3582 if (rc)
3583 goto init_cpu_err;
3584
3585 /* Initialize the Completion Processor. */
3586 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3587 fw = &bnx2_com_fw_09;
3588 else
3589 fw = &bnx2_com_fw_06;
3590
3591 fw->text = text;
3592 rc = load_cpu_fw(bp, &cpu_reg_com, fw);
3593 if (rc)
3594 goto init_cpu_err;
3595
3596 /* Initialize the Command Processor. */
3597 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3598 fw = &bnx2_cp_fw_09;
3599 else
3600 fw = &bnx2_cp_fw_06;
3601
3602 fw->text = text;
3603 rc = load_cpu_fw(bp, &cpu_reg_cp, fw);
3604
3605 init_cpu_err:
3606 vfree(text);
3607 return rc;
3608 }
3609
3610 static int
3611 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3612 {
3613 u16 pmcsr;
3614
3615 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3616
3617 switch (state) {
3618 case PCI_D0: {
3619 u32 val;
3620
3621 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3622 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3623 PCI_PM_CTRL_PME_STATUS);
3624
3625 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3626 /* delay required during transition out of D3hot */
3627 msleep(20);
3628
3629 val = REG_RD(bp, BNX2_EMAC_MODE);
3630 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3631 val &= ~BNX2_EMAC_MODE_MPKT;
3632 REG_WR(bp, BNX2_EMAC_MODE, val);
3633
3634 val = REG_RD(bp, BNX2_RPM_CONFIG);
3635 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3636 REG_WR(bp, BNX2_RPM_CONFIG, val);
3637 break;
3638 }
3639 case PCI_D3hot: {
3640 int i;
3641 u32 val, wol_msg;
3642
3643 if (bp->wol) {
3644 u32 advertising;
3645 u8 autoneg;
3646
3647 autoneg = bp->autoneg;
3648 advertising = bp->advertising;
3649
3650 if (bp->phy_port == PORT_TP) {
3651 bp->autoneg = AUTONEG_SPEED;
3652 bp->advertising = ADVERTISED_10baseT_Half |
3653 ADVERTISED_10baseT_Full |
3654 ADVERTISED_100baseT_Half |
3655 ADVERTISED_100baseT_Full |
3656 ADVERTISED_Autoneg;
3657 }
3658
3659 spin_lock_bh(&bp->phy_lock);
3660 bnx2_setup_phy(bp, bp->phy_port);
3661 spin_unlock_bh(&bp->phy_lock);
3662
3663 bp->autoneg = autoneg;
3664 bp->advertising = advertising;
3665
3666 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3667
3668 val = REG_RD(bp, BNX2_EMAC_MODE);
3669
3670 /* Enable port mode. */
3671 val &= ~BNX2_EMAC_MODE_PORT;
3672 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3673 BNX2_EMAC_MODE_ACPI_RCVD |
3674 BNX2_EMAC_MODE_MPKT;
3675 if (bp->phy_port == PORT_TP)
3676 val |= BNX2_EMAC_MODE_PORT_MII;
3677 else {
3678 val |= BNX2_EMAC_MODE_PORT_GMII;
3679 if (bp->line_speed == SPEED_2500)
3680 val |= BNX2_EMAC_MODE_25G_MODE;
3681 }
3682
3683 REG_WR(bp, BNX2_EMAC_MODE, val);
3684
3685 /* receive all multicast */
3686 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3687 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3688 0xffffffff);
3689 }
3690 REG_WR(bp, BNX2_EMAC_RX_MODE,
3691 BNX2_EMAC_RX_MODE_SORT_MODE);
3692
3693 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3694 BNX2_RPM_SORT_USER0_MC_EN;
3695 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3696 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3697 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3698 BNX2_RPM_SORT_USER0_ENA);
3699
3700 /* Need to enable EMAC and RPM for WOL. */
3701 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3702 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3703 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3704 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3705
3706 val = REG_RD(bp, BNX2_RPM_CONFIG);
3707 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3708 REG_WR(bp, BNX2_RPM_CONFIG, val);
3709
3710 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3711 }
3712 else {
3713 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3714 }
3715
3716 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3717 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3718 1, 0);
3719
3720 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3721 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3722 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3723
3724 if (bp->wol)
3725 pmcsr |= 3;
3726 }
3727 else {
3728 pmcsr |= 3;
3729 }
3730 if (bp->wol) {
3731 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3732 }
3733 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3734 pmcsr);
3735
3736 /* No more memory access after this point until
3737 * device is brought back to D0.
3738 */
3739 udelay(50);
3740 break;
3741 }
3742 default:
3743 return -EINVAL;
3744 }
3745 return 0;
3746 }
3747
3748 static int
3749 bnx2_acquire_nvram_lock(struct bnx2 *bp)
3750 {
3751 u32 val;
3752 int j;
3753
3754 /* Request access to the flash interface. */
3755 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3756 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3757 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3758 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3759 break;
3760
3761 udelay(5);
3762 }
3763
3764 if (j >= NVRAM_TIMEOUT_COUNT)
3765 return -EBUSY;
3766
3767 return 0;
3768 }
3769
3770 static int
3771 bnx2_release_nvram_lock(struct bnx2 *bp)
3772 {
3773 int j;
3774 u32 val;
3775
3776 /* Relinquish nvram interface. */
3777 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3778
3779 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3780 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3781 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3782 break;
3783
3784 udelay(5);
3785 }
3786
3787 if (j >= NVRAM_TIMEOUT_COUNT)
3788 return -EBUSY;
3789
3790 return 0;
3791 }
3792
3793
3794 static int
3795 bnx2_enable_nvram_write(struct bnx2 *bp)
3796 {
3797 u32 val;
3798
3799 val = REG_RD(bp, BNX2_MISC_CFG);
3800 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3801
3802 if (bp->flash_info->flags & BNX2_NV_WREN) {
3803 int j;
3804
3805 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3806 REG_WR(bp, BNX2_NVM_COMMAND,
3807 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3808
3809 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3810 udelay(5);
3811
3812 val = REG_RD(bp, BNX2_NVM_COMMAND);
3813 if (val & BNX2_NVM_COMMAND_DONE)
3814 break;
3815 }
3816
3817 if (j >= NVRAM_TIMEOUT_COUNT)
3818 return -EBUSY;
3819 }
3820 return 0;
3821 }
3822
3823 static void
3824 bnx2_disable_nvram_write(struct bnx2 *bp)
3825 {
3826 u32 val;
3827
3828 val = REG_RD(bp, BNX2_MISC_CFG);
3829 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3830 }
3831
3832
3833 static void
3834 bnx2_enable_nvram_access(struct bnx2 *bp)
3835 {
3836 u32 val;
3837
3838 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3839 /* Enable both bits, even on read. */
3840 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3841 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3842 }
3843
3844 static void
3845 bnx2_disable_nvram_access(struct bnx2 *bp)
3846 {
3847 u32 val;
3848
3849 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3850 /* Disable both bits, even after read. */
3851 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3852 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3853 BNX2_NVM_ACCESS_ENABLE_WR_EN));
3854 }
3855
3856 static int
3857 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3858 {
3859 u32 cmd;
3860 int j;
3861
3862 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
3863 /* Buffered flash, no erase needed */
3864 return 0;
3865
3866 /* Build an erase command */
3867 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3868 BNX2_NVM_COMMAND_DOIT;
3869
3870 /* Need to clear DONE bit separately. */
3871 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3872
3873 /* Address of the NVRAM to read from. */
3874 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3875
3876 /* Issue an erase command. */
3877 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3878
3879 /* Wait for completion. */
3880 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3881 u32 val;
3882
3883 udelay(5);
3884
3885 val = REG_RD(bp, BNX2_NVM_COMMAND);
3886 if (val & BNX2_NVM_COMMAND_DONE)
3887 break;
3888 }
3889
3890 if (j >= NVRAM_TIMEOUT_COUNT)
3891 return -EBUSY;
3892
3893 return 0;
3894 }
3895
3896 static int
3897 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3898 {
3899 u32 cmd;
3900 int j;
3901
3902 /* Build the command word. */
3903 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3904
3905 /* Calculate an offset of a buffered flash, not needed for 5709. */
3906 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3907 offset = ((offset / bp->flash_info->page_size) <<
3908 bp->flash_info->page_bits) +
3909 (offset % bp->flash_info->page_size);
3910 }
3911
3912 /* Need to clear DONE bit separately. */
3913 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3914
3915 /* Address of the NVRAM to read from. */
3916 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3917
3918 /* Issue a read command. */
3919 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3920
3921 /* Wait for completion. */
3922 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3923 u32 val;
3924
3925 udelay(5);
3926
3927 val = REG_RD(bp, BNX2_NVM_COMMAND);
3928 if (val & BNX2_NVM_COMMAND_DONE) {
3929 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3930 memcpy(ret_val, &v, 4);
3931 break;
3932 }
3933 }
3934 if (j >= NVRAM_TIMEOUT_COUNT)
3935 return -EBUSY;
3936
3937 return 0;
3938 }
3939
3940
3941 static int
3942 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3943 {
3944 u32 cmd;
3945 __be32 val32;
3946 int j;
3947
3948 /* Build the command word. */
3949 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3950
3951 /* Calculate an offset of a buffered flash, not needed for 5709. */
3952 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3953 offset = ((offset / bp->flash_info->page_size) <<
3954 bp->flash_info->page_bits) +
3955 (offset % bp->flash_info->page_size);
3956 }
3957
3958 /* Need to clear DONE bit separately. */
3959 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3960
3961 memcpy(&val32, val, 4);
3962
3963 /* Write the data. */
3964 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
3965
3966 /* Address of the NVRAM to write to. */
3967 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3968
3969 /* Issue the write command. */
3970 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3971
3972 /* Wait for completion. */
3973 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3974 udelay(5);
3975
3976 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3977 break;
3978 }
3979 if (j >= NVRAM_TIMEOUT_COUNT)
3980 return -EBUSY;
3981
3982 return 0;
3983 }
3984
3985 static int
3986 bnx2_init_nvram(struct bnx2 *bp)
3987 {
3988 u32 val;
3989 int j, entry_count, rc = 0;
3990 struct flash_spec *flash;
3991
3992 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3993 bp->flash_info = &flash_5709;
3994 goto get_flash_size;
3995 }
3996
3997 /* Determine the selected interface. */
3998 val = REG_RD(bp, BNX2_NVM_CFG1);
3999
4000 entry_count = ARRAY_SIZE(flash_table);
4001
4002 if (val & 0x40000000) {
4003
4004 /* Flash interface has been reconfigured */
4005 for (j = 0, flash = &flash_table[0]; j < entry_count;
4006 j++, flash++) {
4007 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4008 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
4009 bp->flash_info = flash;
4010 break;
4011 }
4012 }
4013 }
4014 else {
4015 u32 mask;
4016 /* Not yet been reconfigured */
4017
4018 if (val & (1 << 23))
4019 mask = FLASH_BACKUP_STRAP_MASK;
4020 else
4021 mask = FLASH_STRAP_MASK;
4022
4023 for (j = 0, flash = &flash_table[0]; j < entry_count;
4024 j++, flash++) {
4025
4026 if ((val & mask) == (flash->strapping & mask)) {
4027 bp->flash_info = flash;
4028
4029 /* Request access to the flash interface. */
4030 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4031 return rc;
4032
4033 /* Enable access to flash interface */
4034 bnx2_enable_nvram_access(bp);
4035
4036 /* Reconfigure the flash interface */
4037 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4038 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4039 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4040 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4041
4042 /* Disable access to flash interface */
4043 bnx2_disable_nvram_access(bp);
4044 bnx2_release_nvram_lock(bp);
4045
4046 break;
4047 }
4048 }
4049 } /* if (val & 0x40000000) */
4050
4051 if (j == entry_count) {
4052 bp->flash_info = NULL;
4053 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
4054 return -ENODEV;
4055 }
4056
4057 get_flash_size:
4058 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4059 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4060 if (val)
4061 bp->flash_size = val;
4062 else
4063 bp->flash_size = bp->flash_info->total_size;
4064
4065 return rc;
4066 }
4067
4068 static int
4069 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4070 int buf_size)
4071 {
4072 int rc = 0;
4073 u32 cmd_flags, offset32, len32, extra;
4074
4075 if (buf_size == 0)
4076 return 0;
4077
4078 /* Request access to the flash interface. */
4079 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4080 return rc;
4081
4082 /* Enable access to flash interface */
4083 bnx2_enable_nvram_access(bp);
4084
4085 len32 = buf_size;
4086 offset32 = offset;
4087 extra = 0;
4088
4089 cmd_flags = 0;
4090
4091 if (offset32 & 3) {
4092 u8 buf[4];
4093 u32 pre_len;
4094
4095 offset32 &= ~3;
4096 pre_len = 4 - (offset & 3);
4097
4098 if (pre_len >= len32) {
4099 pre_len = len32;
4100 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4101 BNX2_NVM_COMMAND_LAST;
4102 }
4103 else {
4104 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4105 }
4106
4107 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4108
4109 if (rc)
4110 return rc;
4111
4112 memcpy(ret_buf, buf + (offset & 3), pre_len);
4113
4114 offset32 += 4;
4115 ret_buf += pre_len;
4116 len32 -= pre_len;
4117 }
4118 if (len32 & 3) {
4119 extra = 4 - (len32 & 3);
4120 len32 = (len32 + 4) & ~3;
4121 }
4122
4123 if (len32 == 4) {
4124 u8 buf[4];
4125
4126 if (cmd_flags)
4127 cmd_flags = BNX2_NVM_COMMAND_LAST;
4128 else
4129 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4130 BNX2_NVM_COMMAND_LAST;
4131
4132 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4133
4134 memcpy(ret_buf, buf, 4 - extra);
4135 }
4136 else if (len32 > 0) {
4137 u8 buf[4];
4138
4139 /* Read the first word. */
4140 if (cmd_flags)
4141 cmd_flags = 0;
4142 else
4143 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4144
4145 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4146
4147 /* Advance to the next dword. */
4148 offset32 += 4;
4149 ret_buf += 4;
4150 len32 -= 4;
4151
4152 while (len32 > 4 && rc == 0) {
4153 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4154
4155 /* Advance to the next dword. */
4156 offset32 += 4;
4157 ret_buf += 4;
4158 len32 -= 4;
4159 }
4160
4161 if (rc)
4162 return rc;
4163
4164 cmd_flags = BNX2_NVM_COMMAND_LAST;
4165 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4166
4167 memcpy(ret_buf, buf, 4 - extra);
4168 }
4169
4170 /* Disable access to flash interface */
4171 bnx2_disable_nvram_access(bp);
4172
4173 bnx2_release_nvram_lock(bp);
4174
4175 return rc;
4176 }
4177
4178 static int
4179 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4180 int buf_size)
4181 {
4182 u32 written, offset32, len32;
4183 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4184 int rc = 0;
4185 int align_start, align_end;
4186
4187 buf = data_buf;
4188 offset32 = offset;
4189 len32 = buf_size;
4190 align_start = align_end = 0;
4191
4192 if ((align_start = (offset32 & 3))) {
4193 offset32 &= ~3;
4194 len32 += align_start;
4195 if (len32 < 4)
4196 len32 = 4;
4197 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4198 return rc;
4199 }
4200
4201 if (len32 & 3) {
4202 align_end = 4 - (len32 & 3);
4203 len32 += align_end;
4204 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4205 return rc;
4206 }
4207
4208 if (align_start || align_end) {
4209 align_buf = kmalloc(len32, GFP_KERNEL);
4210 if (align_buf == NULL)
4211 return -ENOMEM;
4212 if (align_start) {
4213 memcpy(align_buf, start, 4);
4214 }
4215 if (align_end) {
4216 memcpy(align_buf + len32 - 4, end, 4);
4217 }
4218 memcpy(align_buf + align_start, data_buf, buf_size);
4219 buf = align_buf;
4220 }
4221
4222 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4223 flash_buffer = kmalloc(264, GFP_KERNEL);
4224 if (flash_buffer == NULL) {
4225 rc = -ENOMEM;
4226 goto nvram_write_end;
4227 }
4228 }
4229
4230 written = 0;
4231 while ((written < len32) && (rc == 0)) {
4232 u32 page_start, page_end, data_start, data_end;
4233 u32 addr, cmd_flags;
4234 int i;
4235
4236 /* Find the page_start addr */
4237 page_start = offset32 + written;
4238 page_start -= (page_start % bp->flash_info->page_size);
4239 /* Find the page_end addr */
4240 page_end = page_start + bp->flash_info->page_size;
4241 /* Find the data_start addr */
4242 data_start = (written == 0) ? offset32 : page_start;
4243 /* Find the data_end addr */
4244 data_end = (page_end > offset32 + len32) ?
4245 (offset32 + len32) : page_end;
4246
4247 /* Request access to the flash interface. */
4248 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4249 goto nvram_write_end;
4250
4251 /* Enable access to flash interface */
4252 bnx2_enable_nvram_access(bp);
4253
4254 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4255 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4256 int j;
4257
4258 /* Read the whole page into the buffer
4259 * (non-buffer flash only) */
4260 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4261 if (j == (bp->flash_info->page_size - 4)) {
4262 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4263 }
4264 rc = bnx2_nvram_read_dword(bp,
4265 page_start + j,
4266 &flash_buffer[j],
4267 cmd_flags);
4268
4269 if (rc)
4270 goto nvram_write_end;
4271
4272 cmd_flags = 0;
4273 }
4274 }
4275
4276 /* Enable writes to flash interface (unlock write-protect) */
4277 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4278 goto nvram_write_end;
4279
4280 /* Loop to write back the buffer data from page_start to
4281 * data_start */
4282 i = 0;
4283 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4284 /* Erase the page */
4285 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4286 goto nvram_write_end;
4287
4288 /* Re-enable the write again for the actual write */
4289 bnx2_enable_nvram_write(bp);
4290
4291 for (addr = page_start; addr < data_start;
4292 addr += 4, i += 4) {
4293
4294 rc = bnx2_nvram_write_dword(bp, addr,
4295 &flash_buffer[i], cmd_flags);
4296
4297 if (rc != 0)
4298 goto nvram_write_end;
4299
4300 cmd_flags = 0;
4301 }
4302 }
4303
4304 /* Loop to write the new data from data_start to data_end */
4305 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4306 if ((addr == page_end - 4) ||
4307 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4308 (addr == data_end - 4))) {
4309
4310 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4311 }
4312 rc = bnx2_nvram_write_dword(bp, addr, buf,
4313 cmd_flags);
4314
4315 if (rc != 0)
4316 goto nvram_write_end;
4317
4318 cmd_flags = 0;
4319 buf += 4;
4320 }
4321
4322 /* Loop to write back the buffer data from data_end
4323 * to page_end */
4324 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4325 for (addr = data_end; addr < page_end;
4326 addr += 4, i += 4) {
4327
4328 if (addr == page_end-4) {
4329 cmd_flags = BNX2_NVM_COMMAND_LAST;
4330 }
4331 rc = bnx2_nvram_write_dword(bp, addr,
4332 &flash_buffer[i], cmd_flags);
4333
4334 if (rc != 0)
4335 goto nvram_write_end;
4336
4337 cmd_flags = 0;
4338 }
4339 }
4340
4341 /* Disable writes to flash interface (lock write-protect) */
4342 bnx2_disable_nvram_write(bp);
4343
4344 /* Disable access to flash interface */
4345 bnx2_disable_nvram_access(bp);
4346 bnx2_release_nvram_lock(bp);
4347
4348 /* Increment written */
4349 written += data_end - data_start;
4350 }
4351
4352 nvram_write_end:
4353 kfree(flash_buffer);
4354 kfree(align_buf);
4355 return rc;
4356 }
4357
4358 static void
4359 bnx2_init_fw_cap(struct bnx2 *bp)
4360 {
4361 u32 val, sig = 0;
4362
4363 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4364 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4365
4366 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4367 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4368
4369 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4370 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4371 return;
4372
4373 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4374 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4375 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4376 }
4377
4378 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4379 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4380 u32 link;
4381
4382 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4383
4384 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4385 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4386 bp->phy_port = PORT_FIBRE;
4387 else
4388 bp->phy_port = PORT_TP;
4389
4390 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4391 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4392 }
4393
4394 if (netif_running(bp->dev) && sig)
4395 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4396 }
4397
4398 static void
4399 bnx2_setup_msix_tbl(struct bnx2 *bp)
4400 {
4401 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4402
4403 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4404 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4405 }
4406
4407 static int
4408 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4409 {
4410 u32 val;
4411 int i, rc = 0;
4412 u8 old_port;
4413
4414 /* Wait for the current PCI transaction to complete before
4415 * issuing a reset. */
4416 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4417 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4418 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4419 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4420 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4421 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4422 udelay(5);
4423
4424 /* Wait for the firmware to tell us it is ok to issue a reset. */
4425 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4426
4427 /* Deposit a driver reset signature so the firmware knows that
4428 * this is a soft reset. */
4429 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4430 BNX2_DRV_RESET_SIGNATURE_MAGIC);
4431
4432 /* Do a dummy read to force the chip to complete all current transaction
4433 * before we issue a reset. */
4434 val = REG_RD(bp, BNX2_MISC_ID);
4435
4436 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4437 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4438 REG_RD(bp, BNX2_MISC_COMMAND);
4439 udelay(5);
4440
4441 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4442 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4443
4444 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4445
4446 } else {
4447 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4448 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4449 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4450
4451 /* Chip reset. */
4452 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4453
4454 /* Reading back any register after chip reset will hang the
4455 * bus on 5706 A0 and A1. The msleep below provides plenty
4456 * of margin for write posting.
4457 */
4458 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4459 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4460 msleep(20);
4461
4462 /* Reset takes approximate 30 usec */
4463 for (i = 0; i < 10; i++) {
4464 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4465 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4466 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4467 break;
4468 udelay(10);
4469 }
4470
4471 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4472 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4473 printk(KERN_ERR PFX "Chip reset did not complete\n");
4474 return -EBUSY;
4475 }
4476 }
4477
4478 /* Make sure byte swapping is properly configured. */
4479 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4480 if (val != 0x01020304) {
4481 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4482 return -ENODEV;
4483 }
4484
4485 /* Wait for the firmware to finish its initialization. */
4486 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4487 if (rc)
4488 return rc;
4489
4490 spin_lock_bh(&bp->phy_lock);
4491 old_port = bp->phy_port;
4492 bnx2_init_fw_cap(bp);
4493 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4494 old_port != bp->phy_port)
4495 bnx2_set_default_remote_link(bp);
4496 spin_unlock_bh(&bp->phy_lock);
4497
4498 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4499 /* Adjust the voltage regular to two steps lower. The default
4500 * of this register is 0x0000000e. */
4501 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4502
4503 /* Remove bad rbuf memory from the free pool. */
4504 rc = bnx2_alloc_bad_rbuf(bp);
4505 }
4506
4507 if (bp->flags & BNX2_FLAG_USING_MSIX)
4508 bnx2_setup_msix_tbl(bp);
4509
4510 return rc;
4511 }
4512
4513 static int
4514 bnx2_init_chip(struct bnx2 *bp)
4515 {
4516 u32 val, mtu;
4517 int rc, i;
4518
4519 /* Make sure the interrupt is not active. */
4520 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4521
4522 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4523 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4524 #ifdef __BIG_ENDIAN
4525 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4526 #endif
4527 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4528 DMA_READ_CHANS << 12 |
4529 DMA_WRITE_CHANS << 16;
4530
4531 val |= (0x2 << 20) | (1 << 11);
4532
4533 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4534 val |= (1 << 23);
4535
4536 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4537 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4538 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4539
4540 REG_WR(bp, BNX2_DMA_CONFIG, val);
4541
4542 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4543 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4544 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4545 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4546 }
4547
4548 if (bp->flags & BNX2_FLAG_PCIX) {
4549 u16 val16;
4550
4551 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4552 &val16);
4553 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4554 val16 & ~PCI_X_CMD_ERO);
4555 }
4556
4557 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4558 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4559 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4560 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4561
4562 /* Initialize context mapping and zero out the quick contexts. The
4563 * context block must have already been enabled. */
4564 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4565 rc = bnx2_init_5709_context(bp);
4566 if (rc)
4567 return rc;
4568 } else
4569 bnx2_init_context(bp);
4570
4571 if ((rc = bnx2_init_cpus(bp)) != 0)
4572 return rc;
4573
4574 bnx2_init_nvram(bp);
4575
4576 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4577
4578 val = REG_RD(bp, BNX2_MQ_CONFIG);
4579 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4580 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4581 if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4582 val |= BNX2_MQ_CONFIG_HALT_DIS;
4583
4584 REG_WR(bp, BNX2_MQ_CONFIG, val);
4585
4586 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4587 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4588 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4589
4590 val = (BCM_PAGE_BITS - 8) << 24;
4591 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4592
4593 /* Configure page size. */
4594 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4595 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4596 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4597 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4598
4599 val = bp->mac_addr[0] +
4600 (bp->mac_addr[1] << 8) +
4601 (bp->mac_addr[2] << 16) +
4602 bp->mac_addr[3] +
4603 (bp->mac_addr[4] << 8) +
4604 (bp->mac_addr[5] << 16);
4605 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4606
4607 /* Program the MTU. Also include 4 bytes for CRC32. */
4608 mtu = bp->dev->mtu;
4609 val = mtu + ETH_HLEN + ETH_FCS_LEN;
4610 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4611 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4612 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4613
4614 if (mtu < 1500)
4615 mtu = 1500;
4616
4617 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4618 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4619 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4620
4621 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4622 bp->bnx2_napi[i].last_status_idx = 0;
4623
4624 bp->idle_chk_status_idx = 0xffff;
4625
4626 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4627
4628 /* Set up how to generate a link change interrupt. */
4629 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4630
4631 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4632 (u64) bp->status_blk_mapping & 0xffffffff);
4633 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4634
4635 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4636 (u64) bp->stats_blk_mapping & 0xffffffff);
4637 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4638 (u64) bp->stats_blk_mapping >> 32);
4639
4640 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4641 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4642
4643 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4644 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4645
4646 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4647 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4648
4649 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4650
4651 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4652
4653 REG_WR(bp, BNX2_HC_COM_TICKS,
4654 (bp->com_ticks_int << 16) | bp->com_ticks);
4655
4656 REG_WR(bp, BNX2_HC_CMD_TICKS,
4657 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4658
4659 if (CHIP_NUM(bp) == CHIP_NUM_5708)
4660 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4661 else
4662 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4663 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4664
4665 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4666 val = BNX2_HC_CONFIG_COLLECT_STATS;
4667 else {
4668 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4669 BNX2_HC_CONFIG_COLLECT_STATS;
4670 }
4671
4672 if (bp->irq_nvecs > 1) {
4673 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4674 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4675
4676 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4677 }
4678
4679 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4680 val |= BNX2_HC_CONFIG_ONE_SHOT;
4681
4682 REG_WR(bp, BNX2_HC_CONFIG, val);
4683
4684 for (i = 1; i < bp->irq_nvecs; i++) {
4685 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4686 BNX2_HC_SB_CONFIG_1;
4687
4688 REG_WR(bp, base,
4689 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4690 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4691 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4692
4693 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4694 (bp->tx_quick_cons_trip_int << 16) |
4695 bp->tx_quick_cons_trip);
4696
4697 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4698 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4699
4700 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4701 (bp->rx_quick_cons_trip_int << 16) |
4702 bp->rx_quick_cons_trip);
4703
4704 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4705 (bp->rx_ticks_int << 16) | bp->rx_ticks);
4706 }
4707
4708 /* Clear internal stats counters. */
4709 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4710
4711 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4712
4713 /* Initialize the receive filter. */
4714 bnx2_set_rx_mode(bp->dev);
4715
4716 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4717 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4718 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4719 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4720 }
4721 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4722 1, 0);
4723
4724 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4725 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4726
4727 udelay(20);
4728
4729 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4730
4731 return rc;
4732 }
4733
4734 static void
4735 bnx2_clear_ring_states(struct bnx2 *bp)
4736 {
4737 struct bnx2_napi *bnapi;
4738 struct bnx2_tx_ring_info *txr;
4739 struct bnx2_rx_ring_info *rxr;
4740 int i;
4741
4742 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4743 bnapi = &bp->bnx2_napi[i];
4744 txr = &bnapi->tx_ring;
4745 rxr = &bnapi->rx_ring;
4746
4747 txr->tx_cons = 0;
4748 txr->hw_tx_cons = 0;
4749 rxr->rx_prod_bseq = 0;
4750 rxr->rx_prod = 0;
4751 rxr->rx_cons = 0;
4752 rxr->rx_pg_prod = 0;
4753 rxr->rx_pg_cons = 0;
4754 }
4755 }
4756
4757 static void
4758 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
4759 {
4760 u32 val, offset0, offset1, offset2, offset3;
4761 u32 cid_addr = GET_CID_ADDR(cid);
4762
4763 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4764 offset0 = BNX2_L2CTX_TYPE_XI;
4765 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4766 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4767 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4768 } else {
4769 offset0 = BNX2_L2CTX_TYPE;
4770 offset1 = BNX2_L2CTX_CMD_TYPE;
4771 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4772 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4773 }
4774 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4775 bnx2_ctx_wr(bp, cid_addr, offset0, val);
4776
4777 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4778 bnx2_ctx_wr(bp, cid_addr, offset1, val);
4779
4780 val = (u64) txr->tx_desc_mapping >> 32;
4781 bnx2_ctx_wr(bp, cid_addr, offset2, val);
4782
4783 val = (u64) txr->tx_desc_mapping & 0xffffffff;
4784 bnx2_ctx_wr(bp, cid_addr, offset3, val);
4785 }
4786
4787 static void
4788 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
4789 {
4790 struct tx_bd *txbd;
4791 u32 cid = TX_CID;
4792 struct bnx2_napi *bnapi;
4793 struct bnx2_tx_ring_info *txr;
4794
4795 bnapi = &bp->bnx2_napi[ring_num];
4796 txr = &bnapi->tx_ring;
4797
4798 if (ring_num == 0)
4799 cid = TX_CID;
4800 else
4801 cid = TX_TSS_CID + ring_num - 1;
4802
4803 bp->tx_wake_thresh = bp->tx_ring_size / 2;
4804
4805 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
4806
4807 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
4808 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
4809
4810 txr->tx_prod = 0;
4811 txr->tx_prod_bseq = 0;
4812
4813 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4814 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
4815
4816 bnx2_init_tx_context(bp, cid, txr);
4817 }
4818
4819 static void
4820 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4821 int num_rings)
4822 {
4823 int i;
4824 struct rx_bd *rxbd;
4825
4826 for (i = 0; i < num_rings; i++) {
4827 int j;
4828
4829 rxbd = &rx_ring[i][0];
4830 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
4831 rxbd->rx_bd_len = buf_size;
4832 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4833 }
4834 if (i == (num_rings - 1))
4835 j = 0;
4836 else
4837 j = i + 1;
4838 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4839 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
4840 }
4841 }
4842
4843 static void
4844 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
4845 {
4846 int i;
4847 u16 prod, ring_prod;
4848 u32 cid, rx_cid_addr, val;
4849 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
4850 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
4851
4852 if (ring_num == 0)
4853 cid = RX_CID;
4854 else
4855 cid = RX_RSS_CID + ring_num - 1;
4856
4857 rx_cid_addr = GET_CID_ADDR(cid);
4858
4859 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
4860 bp->rx_buf_use_size, bp->rx_max_ring);
4861
4862 bnx2_init_rx_context(bp, cid);
4863
4864 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4865 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4866 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4867 }
4868
4869 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
4870 if (bp->rx_pg_ring_size) {
4871 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
4872 rxr->rx_pg_desc_mapping,
4873 PAGE_SIZE, bp->rx_max_pg_ring);
4874 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
4875 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4876 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
4877 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
4878
4879 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
4880 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
4881
4882 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
4883 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
4884
4885 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4886 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4887 }
4888
4889 val = (u64) rxr->rx_desc_mapping[0] >> 32;
4890 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4891
4892 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
4893 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4894
4895 ring_prod = prod = rxr->rx_pg_prod;
4896 for (i = 0; i < bp->rx_pg_ring_size; i++) {
4897 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
4898 break;
4899 prod = NEXT_RX_BD(prod);
4900 ring_prod = RX_PG_RING_IDX(prod);
4901 }
4902 rxr->rx_pg_prod = prod;
4903
4904 ring_prod = prod = rxr->rx_prod;
4905 for (i = 0; i < bp->rx_ring_size; i++) {
4906 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
4907 break;
4908 prod = NEXT_RX_BD(prod);
4909 ring_prod = RX_RING_IDX(prod);
4910 }
4911 rxr->rx_prod = prod;
4912
4913 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
4914 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
4915 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
4916
4917 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
4918 REG_WR16(bp, rxr->rx_bidx_addr, prod);
4919
4920 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
4921 }
4922
4923 static void
4924 bnx2_init_all_rings(struct bnx2 *bp)
4925 {
4926 int i;
4927 u32 val;
4928
4929 bnx2_clear_ring_states(bp);
4930
4931 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
4932 for (i = 0; i < bp->num_tx_rings; i++)
4933 bnx2_init_tx_ring(bp, i);
4934
4935 if (bp->num_tx_rings > 1)
4936 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
4937 (TX_TSS_CID << 7));
4938
4939 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
4940 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
4941
4942 for (i = 0; i < bp->num_rx_rings; i++)
4943 bnx2_init_rx_ring(bp, i);
4944
4945 if (bp->num_rx_rings > 1) {
4946 u32 tbl_32;
4947 u8 *tbl = (u8 *) &tbl_32;
4948
4949 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
4950 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
4951
4952 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
4953 tbl[i % 4] = i % (bp->num_rx_rings - 1);
4954 if ((i % 4) == 3)
4955 bnx2_reg_wr_ind(bp,
4956 BNX2_RXP_SCRATCH_RSS_TBL + i,
4957 cpu_to_be32(tbl_32));
4958 }
4959
4960 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
4961 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
4962
4963 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
4964
4965 }
4966 }
4967
4968 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
4969 {
4970 u32 max, num_rings = 1;
4971
4972 while (ring_size > MAX_RX_DESC_CNT) {
4973 ring_size -= MAX_RX_DESC_CNT;
4974 num_rings++;
4975 }
4976 /* round to next power of 2 */
4977 max = max_size;
4978 while ((max & num_rings) == 0)
4979 max >>= 1;
4980
4981 if (num_rings != max)
4982 max <<= 1;
4983
4984 return max;
4985 }
4986
4987 static void
4988 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4989 {
4990 u32 rx_size, rx_space, jumbo_size;
4991
4992 /* 8 for CRC and VLAN */
4993 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
4994
4995 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4996 sizeof(struct skb_shared_info);
4997
4998 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
4999 bp->rx_pg_ring_size = 0;
5000 bp->rx_max_pg_ring = 0;
5001 bp->rx_max_pg_ring_idx = 0;
5002 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
5003 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5004
5005 jumbo_size = size * pages;
5006 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5007 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5008
5009 bp->rx_pg_ring_size = jumbo_size;
5010 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5011 MAX_RX_PG_RINGS);
5012 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
5013 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
5014 bp->rx_copy_thresh = 0;
5015 }
5016
5017 bp->rx_buf_use_size = rx_size;
5018 /* hw alignment */
5019 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
5020 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5021 bp->rx_ring_size = size;
5022 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
5023 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5024 }
5025
5026 static void
5027 bnx2_free_tx_skbs(struct bnx2 *bp)
5028 {
5029 int i;
5030
5031 for (i = 0; i < bp->num_tx_rings; i++) {
5032 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5033 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5034 int j;
5035
5036 if (txr->tx_buf_ring == NULL)
5037 continue;
5038
5039 for (j = 0; j < TX_DESC_CNT; ) {
5040 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
5041 struct sk_buff *skb = tx_buf->skb;
5042
5043 if (skb == NULL) {
5044 j++;
5045 continue;
5046 }
5047
5048 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
5049
5050 tx_buf->skb = NULL;
5051
5052 j += skb_shinfo(skb)->nr_frags + 1;
5053 dev_kfree_skb(skb);
5054 }
5055 }
5056 }
5057
5058 static void
5059 bnx2_free_rx_skbs(struct bnx2 *bp)
5060 {
5061 int i;
5062
5063 for (i = 0; i < bp->num_rx_rings; i++) {
5064 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5065 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5066 int j;
5067
5068 if (rxr->rx_buf_ring == NULL)
5069 return;
5070
5071 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5072 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5073 struct sk_buff *skb = rx_buf->skb;
5074
5075 if (skb == NULL)
5076 continue;
5077
5078 pci_unmap_single(bp->pdev,
5079 pci_unmap_addr(rx_buf, mapping),
5080 bp->rx_buf_use_size,
5081 PCI_DMA_FROMDEVICE);
5082
5083 rx_buf->skb = NULL;
5084
5085 dev_kfree_skb(skb);
5086 }
5087 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5088 bnx2_free_rx_page(bp, rxr, j);
5089 }
5090 }
5091
5092 static void
5093 bnx2_free_skbs(struct bnx2 *bp)
5094 {
5095 bnx2_free_tx_skbs(bp);
5096 bnx2_free_rx_skbs(bp);
5097 }
5098
5099 static int
5100 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5101 {
5102 int rc;
5103
5104 rc = bnx2_reset_chip(bp, reset_code);
5105 bnx2_free_skbs(bp);
5106 if (rc)
5107 return rc;
5108
5109 if ((rc = bnx2_init_chip(bp)) != 0)
5110 return rc;
5111
5112 bnx2_init_all_rings(bp);
5113 return 0;
5114 }
5115
5116 static int
5117 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5118 {
5119 int rc;
5120
5121 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5122 return rc;
5123
5124 spin_lock_bh(&bp->phy_lock);
5125 bnx2_init_phy(bp, reset_phy);
5126 bnx2_set_link(bp);
5127 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5128 bnx2_remote_phy_event(bp);
5129 spin_unlock_bh(&bp->phy_lock);
5130 return 0;
5131 }
5132
5133 static int
5134 bnx2_shutdown_chip(struct bnx2 *bp)
5135 {
5136 u32 reset_code;
5137
5138 if (bp->flags & BNX2_FLAG_NO_WOL)
5139 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5140 else if (bp->wol)
5141 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5142 else
5143 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5144
5145 return bnx2_reset_chip(bp, reset_code);
5146 }
5147
5148 static int
5149 bnx2_test_registers(struct bnx2 *bp)
5150 {
5151 int ret;
5152 int i, is_5709;
5153 static const struct {
5154 u16 offset;
5155 u16 flags;
5156 #define BNX2_FL_NOT_5709 1
5157 u32 rw_mask;
5158 u32 ro_mask;
5159 } reg_tbl[] = {
5160 { 0x006c, 0, 0x00000000, 0x0000003f },
5161 { 0x0090, 0, 0xffffffff, 0x00000000 },
5162 { 0x0094, 0, 0x00000000, 0x00000000 },
5163
5164 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5165 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5166 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5167 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5168 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5169 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5170 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5171 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5172 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5173
5174 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5175 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5176 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5177 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5178 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5179 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5180
5181 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5182 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5183 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
5184
5185 { 0x1000, 0, 0x00000000, 0x00000001 },
5186 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5187
5188 { 0x1408, 0, 0x01c00800, 0x00000000 },
5189 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5190 { 0x14a8, 0, 0x00000000, 0x000001ff },
5191 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5192 { 0x14b0, 0, 0x00000002, 0x00000001 },
5193 { 0x14b8, 0, 0x00000000, 0x00000000 },
5194 { 0x14c0, 0, 0x00000000, 0x00000009 },
5195 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5196 { 0x14cc, 0, 0x00000000, 0x00000001 },
5197 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5198
5199 { 0x1800, 0, 0x00000000, 0x00000001 },
5200 { 0x1804, 0, 0x00000000, 0x00000003 },
5201
5202 { 0x2800, 0, 0x00000000, 0x00000001 },
5203 { 0x2804, 0, 0x00000000, 0x00003f01 },
5204 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5205 { 0x2810, 0, 0xffff0000, 0x00000000 },
5206 { 0x2814, 0, 0xffff0000, 0x00000000 },
5207 { 0x2818, 0, 0xffff0000, 0x00000000 },
5208 { 0x281c, 0, 0xffff0000, 0x00000000 },
5209 { 0x2834, 0, 0xffffffff, 0x00000000 },
5210 { 0x2840, 0, 0x00000000, 0xffffffff },
5211 { 0x2844, 0, 0x00000000, 0xffffffff },
5212 { 0x2848, 0, 0xffffffff, 0x00000000 },
5213 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5214
5215 { 0x2c00, 0, 0x00000000, 0x00000011 },
5216 { 0x2c04, 0, 0x00000000, 0x00030007 },
5217
5218 { 0x3c00, 0, 0x00000000, 0x00000001 },
5219 { 0x3c04, 0, 0x00000000, 0x00070000 },
5220 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5221 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5222 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5223 { 0x3c14, 0, 0x00000000, 0xffffffff },
5224 { 0x3c18, 0, 0x00000000, 0xffffffff },
5225 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5226 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5227
5228 { 0x5004, 0, 0x00000000, 0x0000007f },
5229 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5230
5231 { 0x5c00, 0, 0x00000000, 0x00000001 },
5232 { 0x5c04, 0, 0x00000000, 0x0003000f },
5233 { 0x5c08, 0, 0x00000003, 0x00000000 },
5234 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5235 { 0x5c10, 0, 0x00000000, 0xffffffff },
5236 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5237 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5238 { 0x5c88, 0, 0x00000000, 0x00077373 },
5239 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5240
5241 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5242 { 0x680c, 0, 0xffffffff, 0x00000000 },
5243 { 0x6810, 0, 0xffffffff, 0x00000000 },
5244 { 0x6814, 0, 0xffffffff, 0x00000000 },
5245 { 0x6818, 0, 0xffffffff, 0x00000000 },
5246 { 0x681c, 0, 0xffffffff, 0x00000000 },
5247 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5248 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5249 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5250 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5251 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5252 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5253 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5254 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5255 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5256 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5257 { 0x684c, 0, 0xffffffff, 0x00000000 },
5258 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5259 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5260 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5261 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5262 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5263 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5264
5265 { 0xffff, 0, 0x00000000, 0x00000000 },
5266 };
5267
5268 ret = 0;
5269 is_5709 = 0;
5270 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5271 is_5709 = 1;
5272
5273 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5274 u32 offset, rw_mask, ro_mask, save_val, val;
5275 u16 flags = reg_tbl[i].flags;
5276
5277 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5278 continue;
5279
5280 offset = (u32) reg_tbl[i].offset;
5281 rw_mask = reg_tbl[i].rw_mask;
5282 ro_mask = reg_tbl[i].ro_mask;
5283
5284 save_val = readl(bp->regview + offset);
5285
5286 writel(0, bp->regview + offset);
5287
5288 val = readl(bp->regview + offset);
5289 if ((val & rw_mask) != 0) {
5290 goto reg_test_err;
5291 }
5292
5293 if ((val & ro_mask) != (save_val & ro_mask)) {
5294 goto reg_test_err;
5295 }
5296
5297 writel(0xffffffff, bp->regview + offset);
5298
5299 val = readl(bp->regview + offset);
5300 if ((val & rw_mask) != rw_mask) {
5301 goto reg_test_err;
5302 }
5303
5304 if ((val & ro_mask) != (save_val & ro_mask)) {
5305 goto reg_test_err;
5306 }
5307
5308 writel(save_val, bp->regview + offset);
5309 continue;
5310
5311 reg_test_err:
5312 writel(save_val, bp->regview + offset);
5313 ret = -ENODEV;
5314 break;
5315 }
5316 return ret;
5317 }
5318
5319 static int
5320 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5321 {
5322 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5323 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5324 int i;
5325
5326 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5327 u32 offset;
5328
5329 for (offset = 0; offset < size; offset += 4) {
5330
5331 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5332
5333 if (bnx2_reg_rd_ind(bp, start + offset) !=
5334 test_pattern[i]) {
5335 return -ENODEV;
5336 }
5337 }
5338 }
5339 return 0;
5340 }
5341
5342 static int
5343 bnx2_test_memory(struct bnx2 *bp)
5344 {
5345 int ret = 0;
5346 int i;
5347 static struct mem_entry {
5348 u32 offset;
5349 u32 len;
5350 } mem_tbl_5706[] = {
5351 { 0x60000, 0x4000 },
5352 { 0xa0000, 0x3000 },
5353 { 0xe0000, 0x4000 },
5354 { 0x120000, 0x4000 },
5355 { 0x1a0000, 0x4000 },
5356 { 0x160000, 0x4000 },
5357 { 0xffffffff, 0 },
5358 },
5359 mem_tbl_5709[] = {
5360 { 0x60000, 0x4000 },
5361 { 0xa0000, 0x3000 },
5362 { 0xe0000, 0x4000 },
5363 { 0x120000, 0x4000 },
5364 { 0x1a0000, 0x4000 },
5365 { 0xffffffff, 0 },
5366 };
5367 struct mem_entry *mem_tbl;
5368
5369 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5370 mem_tbl = mem_tbl_5709;
5371 else
5372 mem_tbl = mem_tbl_5706;
5373
5374 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5375 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5376 mem_tbl[i].len)) != 0) {
5377 return ret;
5378 }
5379 }
5380
5381 return ret;
5382 }
5383
5384 #define BNX2_MAC_LOOPBACK 0
5385 #define BNX2_PHY_LOOPBACK 1
5386
5387 static int
5388 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5389 {
5390 unsigned int pkt_size, num_pkts, i;
5391 struct sk_buff *skb, *rx_skb;
5392 unsigned char *packet;
5393 u16 rx_start_idx, rx_idx;
5394 dma_addr_t map;
5395 struct tx_bd *txbd;
5396 struct sw_bd *rx_buf;
5397 struct l2_fhdr *rx_hdr;
5398 int ret = -ENODEV;
5399 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5400 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5401 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5402
5403 tx_napi = bnapi;
5404
5405 txr = &tx_napi->tx_ring;
5406 rxr = &bnapi->rx_ring;
5407 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5408 bp->loopback = MAC_LOOPBACK;
5409 bnx2_set_mac_loopback(bp);
5410 }
5411 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5412 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5413 return 0;
5414
5415 bp->loopback = PHY_LOOPBACK;
5416 bnx2_set_phy_loopback(bp);
5417 }
5418 else
5419 return -EINVAL;
5420
5421 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5422 skb = netdev_alloc_skb(bp->dev, pkt_size);
5423 if (!skb)
5424 return -ENOMEM;
5425 packet = skb_put(skb, pkt_size);
5426 memcpy(packet, bp->dev->dev_addr, 6);
5427 memset(packet + 6, 0x0, 8);
5428 for (i = 14; i < pkt_size; i++)
5429 packet[i] = (unsigned char) (i & 0xff);
5430
5431 if (skb_dma_map(&bp->pdev->dev, skb, DMA_TO_DEVICE)) {
5432 dev_kfree_skb(skb);
5433 return -EIO;
5434 }
5435 map = skb_shinfo(skb)->dma_maps[0];
5436
5437 REG_WR(bp, BNX2_HC_COMMAND,
5438 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5439
5440 REG_RD(bp, BNX2_HC_COMMAND);
5441
5442 udelay(5);
5443 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5444
5445 num_pkts = 0;
5446
5447 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5448
5449 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5450 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5451 txbd->tx_bd_mss_nbytes = pkt_size;
5452 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5453
5454 num_pkts++;
5455 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5456 txr->tx_prod_bseq += pkt_size;
5457
5458 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5459 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5460
5461 udelay(100);
5462
5463 REG_WR(bp, BNX2_HC_COMMAND,
5464 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5465
5466 REG_RD(bp, BNX2_HC_COMMAND);
5467
5468 udelay(5);
5469
5470 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
5471 dev_kfree_skb(skb);
5472
5473 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5474 goto loopback_test_done;
5475
5476 rx_idx = bnx2_get_hw_rx_cons(bnapi);
5477 if (rx_idx != rx_start_idx + num_pkts) {
5478 goto loopback_test_done;
5479 }
5480
5481 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5482 rx_skb = rx_buf->skb;
5483
5484 rx_hdr = (struct l2_fhdr *) rx_skb->data;
5485 skb_reserve(rx_skb, BNX2_RX_OFFSET);
5486
5487 pci_dma_sync_single_for_cpu(bp->pdev,
5488 pci_unmap_addr(rx_buf, mapping),
5489 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5490
5491 if (rx_hdr->l2_fhdr_status &
5492 (L2_FHDR_ERRORS_BAD_CRC |
5493 L2_FHDR_ERRORS_PHY_DECODE |
5494 L2_FHDR_ERRORS_ALIGNMENT |
5495 L2_FHDR_ERRORS_TOO_SHORT |
5496 L2_FHDR_ERRORS_GIANT_FRAME)) {
5497
5498 goto loopback_test_done;
5499 }
5500
5501 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5502 goto loopback_test_done;
5503 }
5504
5505 for (i = 14; i < pkt_size; i++) {
5506 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5507 goto loopback_test_done;
5508 }
5509 }
5510
5511 ret = 0;
5512
5513 loopback_test_done:
5514 bp->loopback = 0;
5515 return ret;
5516 }
5517
5518 #define BNX2_MAC_LOOPBACK_FAILED 1
5519 #define BNX2_PHY_LOOPBACK_FAILED 2
5520 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5521 BNX2_PHY_LOOPBACK_FAILED)
5522
5523 static int
5524 bnx2_test_loopback(struct bnx2 *bp)
5525 {
5526 int rc = 0;
5527
5528 if (!netif_running(bp->dev))
5529 return BNX2_LOOPBACK_FAILED;
5530
5531 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5532 spin_lock_bh(&bp->phy_lock);
5533 bnx2_init_phy(bp, 1);
5534 spin_unlock_bh(&bp->phy_lock);
5535 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5536 rc |= BNX2_MAC_LOOPBACK_FAILED;
5537 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5538 rc |= BNX2_PHY_LOOPBACK_FAILED;
5539 return rc;
5540 }
5541
5542 #define NVRAM_SIZE 0x200
5543 #define CRC32_RESIDUAL 0xdebb20e3
5544
5545 static int
5546 bnx2_test_nvram(struct bnx2 *bp)
5547 {
5548 __be32 buf[NVRAM_SIZE / 4];
5549 u8 *data = (u8 *) buf;
5550 int rc = 0;
5551 u32 magic, csum;
5552
5553 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5554 goto test_nvram_done;
5555
5556 magic = be32_to_cpu(buf[0]);
5557 if (magic != 0x669955aa) {
5558 rc = -ENODEV;
5559 goto test_nvram_done;
5560 }
5561
5562 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5563 goto test_nvram_done;
5564
5565 csum = ether_crc_le(0x100, data);
5566 if (csum != CRC32_RESIDUAL) {
5567 rc = -ENODEV;
5568 goto test_nvram_done;
5569 }
5570
5571 csum = ether_crc_le(0x100, data + 0x100);
5572 if (csum != CRC32_RESIDUAL) {
5573 rc = -ENODEV;
5574 }
5575
5576 test_nvram_done:
5577 return rc;
5578 }
5579
5580 static int
5581 bnx2_test_link(struct bnx2 *bp)
5582 {
5583 u32 bmsr;
5584
5585 if (!netif_running(bp->dev))
5586 return -ENODEV;
5587
5588 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5589 if (bp->link_up)
5590 return 0;
5591 return -ENODEV;
5592 }
5593 spin_lock_bh(&bp->phy_lock);
5594 bnx2_enable_bmsr1(bp);
5595 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5596 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5597 bnx2_disable_bmsr1(bp);
5598 spin_unlock_bh(&bp->phy_lock);
5599
5600 if (bmsr & BMSR_LSTATUS) {
5601 return 0;
5602 }
5603 return -ENODEV;
5604 }
5605
5606 static int
5607 bnx2_test_intr(struct bnx2 *bp)
5608 {
5609 int i;
5610 u16 status_idx;
5611
5612 if (!netif_running(bp->dev))
5613 return -ENODEV;
5614
5615 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5616
5617 /* This register is not touched during run-time. */
5618 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5619 REG_RD(bp, BNX2_HC_COMMAND);
5620
5621 for (i = 0; i < 10; i++) {
5622 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5623 status_idx) {
5624
5625 break;
5626 }
5627
5628 msleep_interruptible(10);
5629 }
5630 if (i < 10)
5631 return 0;
5632
5633 return -ENODEV;
5634 }
5635
5636 /* Determining link for parallel detection. */
5637 static int
5638 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5639 {
5640 u32 mode_ctl, an_dbg, exp;
5641
5642 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5643 return 0;
5644
5645 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5646 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5647
5648 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5649 return 0;
5650
5651 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5652 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5653 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5654
5655 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5656 return 0;
5657
5658 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5659 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5660 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5661
5662 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5663 return 0;
5664
5665 return 1;
5666 }
5667
5668 static void
5669 bnx2_5706_serdes_timer(struct bnx2 *bp)
5670 {
5671 int check_link = 1;
5672
5673 spin_lock(&bp->phy_lock);
5674 if (bp->serdes_an_pending) {
5675 bp->serdes_an_pending--;
5676 check_link = 0;
5677 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5678 u32 bmcr;
5679
5680 bp->current_interval = BNX2_TIMER_INTERVAL;
5681
5682 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5683
5684 if (bmcr & BMCR_ANENABLE) {
5685 if (bnx2_5706_serdes_has_link(bp)) {
5686 bmcr &= ~BMCR_ANENABLE;
5687 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5688 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5689 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5690 }
5691 }
5692 }
5693 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5694 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5695 u32 phy2;
5696
5697 bnx2_write_phy(bp, 0x17, 0x0f01);
5698 bnx2_read_phy(bp, 0x15, &phy2);
5699 if (phy2 & 0x20) {
5700 u32 bmcr;
5701
5702 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5703 bmcr |= BMCR_ANENABLE;
5704 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5705
5706 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5707 }
5708 } else
5709 bp->current_interval = BNX2_TIMER_INTERVAL;
5710
5711 if (check_link) {
5712 u32 val;
5713
5714 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5715 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5716 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5717
5718 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5719 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5720 bnx2_5706s_force_link_dn(bp, 1);
5721 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5722 } else
5723 bnx2_set_link(bp);
5724 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5725 bnx2_set_link(bp);
5726 }
5727 spin_unlock(&bp->phy_lock);
5728 }
5729
5730 static void
5731 bnx2_5708_serdes_timer(struct bnx2 *bp)
5732 {
5733 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5734 return;
5735
5736 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
5737 bp->serdes_an_pending = 0;
5738 return;
5739 }
5740
5741 spin_lock(&bp->phy_lock);
5742 if (bp->serdes_an_pending)
5743 bp->serdes_an_pending--;
5744 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5745 u32 bmcr;
5746
5747 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5748 if (bmcr & BMCR_ANENABLE) {
5749 bnx2_enable_forced_2g5(bp);
5750 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
5751 } else {
5752 bnx2_disable_forced_2g5(bp);
5753 bp->serdes_an_pending = 2;
5754 bp->current_interval = BNX2_TIMER_INTERVAL;
5755 }
5756
5757 } else
5758 bp->current_interval = BNX2_TIMER_INTERVAL;
5759
5760 spin_unlock(&bp->phy_lock);
5761 }
5762
5763 static void
5764 bnx2_timer(unsigned long data)
5765 {
5766 struct bnx2 *bp = (struct bnx2 *) data;
5767
5768 if (!netif_running(bp->dev))
5769 return;
5770
5771 if (atomic_read(&bp->intr_sem) != 0)
5772 goto bnx2_restart_timer;
5773
5774 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
5775 BNX2_FLAG_USING_MSI)
5776 bnx2_chk_missed_msi(bp);
5777
5778 bnx2_send_heart_beat(bp);
5779
5780 bp->stats_blk->stat_FwRxDrop =
5781 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
5782
5783 /* workaround occasional corrupted counters */
5784 if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5785 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5786 BNX2_HC_COMMAND_STATS_NOW);
5787
5788 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5789 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5790 bnx2_5706_serdes_timer(bp);
5791 else
5792 bnx2_5708_serdes_timer(bp);
5793 }
5794
5795 bnx2_restart_timer:
5796 mod_timer(&bp->timer, jiffies + bp->current_interval);
5797 }
5798
5799 static int
5800 bnx2_request_irq(struct bnx2 *bp)
5801 {
5802 unsigned long flags;
5803 struct bnx2_irq *irq;
5804 int rc = 0, i;
5805
5806 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
5807 flags = 0;
5808 else
5809 flags = IRQF_SHARED;
5810
5811 for (i = 0; i < bp->irq_nvecs; i++) {
5812 irq = &bp->irq_tbl[i];
5813 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5814 &bp->bnx2_napi[i]);
5815 if (rc)
5816 break;
5817 irq->requested = 1;
5818 }
5819 return rc;
5820 }
5821
5822 static void
5823 bnx2_free_irq(struct bnx2 *bp)
5824 {
5825 struct bnx2_irq *irq;
5826 int i;
5827
5828 for (i = 0; i < bp->irq_nvecs; i++) {
5829 irq = &bp->irq_tbl[i];
5830 if (irq->requested)
5831 free_irq(irq->vector, &bp->bnx2_napi[i]);
5832 irq->requested = 0;
5833 }
5834 if (bp->flags & BNX2_FLAG_USING_MSI)
5835 pci_disable_msi(bp->pdev);
5836 else if (bp->flags & BNX2_FLAG_USING_MSIX)
5837 pci_disable_msix(bp->pdev);
5838
5839 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
5840 }
5841
5842 static void
5843 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
5844 {
5845 int i, rc;
5846 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
5847 struct net_device *dev = bp->dev;
5848 const int len = sizeof(bp->irq_tbl[0].name);
5849
5850 bnx2_setup_msix_tbl(bp);
5851 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5852 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5853 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
5854
5855 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5856 msix_ent[i].entry = i;
5857 msix_ent[i].vector = 0;
5858 }
5859
5860 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5861 if (rc != 0)
5862 return;
5863
5864 bp->irq_nvecs = msix_vecs;
5865 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
5866 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5867 bp->irq_tbl[i].vector = msix_ent[i].vector;
5868 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
5869 bp->irq_tbl[i].handler = bnx2_msi_1shot;
5870 }
5871 }
5872
5873 static void
5874 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5875 {
5876 int cpus = num_online_cpus();
5877 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
5878
5879 bp->irq_tbl[0].handler = bnx2_interrupt;
5880 strcpy(bp->irq_tbl[0].name, bp->dev->name);
5881 bp->irq_nvecs = 1;
5882 bp->irq_tbl[0].vector = bp->pdev->irq;
5883
5884 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
5885 bnx2_enable_msix(bp, msix_vecs);
5886
5887 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5888 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
5889 if (pci_enable_msi(bp->pdev) == 0) {
5890 bp->flags |= BNX2_FLAG_USING_MSI;
5891 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5892 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
5893 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5894 } else
5895 bp->irq_tbl[0].handler = bnx2_msi;
5896
5897 bp->irq_tbl[0].vector = bp->pdev->irq;
5898 }
5899 }
5900
5901 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
5902 bp->dev->real_num_tx_queues = bp->num_tx_rings;
5903
5904 bp->num_rx_rings = bp->irq_nvecs;
5905 }
5906
5907 /* Called with rtnl_lock */
5908 static int
5909 bnx2_open(struct net_device *dev)
5910 {
5911 struct bnx2 *bp = netdev_priv(dev);
5912 int rc;
5913
5914 netif_carrier_off(dev);
5915
5916 bnx2_set_power_state(bp, PCI_D0);
5917 bnx2_disable_int(bp);
5918
5919 bnx2_setup_int_mode(bp, disable_msi);
5920 bnx2_napi_enable(bp);
5921 rc = bnx2_alloc_mem(bp);
5922 if (rc)
5923 goto open_err;
5924
5925 rc = bnx2_request_irq(bp);
5926 if (rc)
5927 goto open_err;
5928
5929 rc = bnx2_init_nic(bp, 1);
5930 if (rc)
5931 goto open_err;
5932
5933 mod_timer(&bp->timer, jiffies + bp->current_interval);
5934
5935 atomic_set(&bp->intr_sem, 0);
5936
5937 bnx2_enable_int(bp);
5938
5939 if (bp->flags & BNX2_FLAG_USING_MSI) {
5940 /* Test MSI to make sure it is working
5941 * If MSI test fails, go back to INTx mode
5942 */
5943 if (bnx2_test_intr(bp) != 0) {
5944 printk(KERN_WARNING PFX "%s: No interrupt was generated"
5945 " using MSI, switching to INTx mode. Please"
5946 " report this failure to the PCI maintainer"
5947 " and include system chipset information.\n",
5948 bp->dev->name);
5949
5950 bnx2_disable_int(bp);
5951 bnx2_free_irq(bp);
5952
5953 bnx2_setup_int_mode(bp, 1);
5954
5955 rc = bnx2_init_nic(bp, 0);
5956
5957 if (!rc)
5958 rc = bnx2_request_irq(bp);
5959
5960 if (rc) {
5961 del_timer_sync(&bp->timer);
5962 goto open_err;
5963 }
5964 bnx2_enable_int(bp);
5965 }
5966 }
5967 if (bp->flags & BNX2_FLAG_USING_MSI)
5968 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
5969 else if (bp->flags & BNX2_FLAG_USING_MSIX)
5970 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
5971
5972 netif_tx_start_all_queues(dev);
5973
5974 return 0;
5975
5976 open_err:
5977 bnx2_napi_disable(bp);
5978 bnx2_free_skbs(bp);
5979 bnx2_free_irq(bp);
5980 bnx2_free_mem(bp);
5981 return rc;
5982 }
5983
5984 static void
5985 bnx2_reset_task(struct work_struct *work)
5986 {
5987 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
5988
5989 if (!netif_running(bp->dev))
5990 return;
5991
5992 bnx2_netif_stop(bp);
5993
5994 bnx2_init_nic(bp, 1);
5995
5996 atomic_set(&bp->intr_sem, 1);
5997 bnx2_netif_start(bp);
5998 }
5999
6000 static void
6001 bnx2_tx_timeout(struct net_device *dev)
6002 {
6003 struct bnx2 *bp = netdev_priv(dev);
6004
6005 /* This allows the netif to be shutdown gracefully before resetting */
6006 schedule_work(&bp->reset_task);
6007 }
6008
6009 #ifdef BCM_VLAN
6010 /* Called with rtnl_lock */
6011 static void
6012 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
6013 {
6014 struct bnx2 *bp = netdev_priv(dev);
6015
6016 bnx2_netif_stop(bp);
6017
6018 bp->vlgrp = vlgrp;
6019 bnx2_set_rx_mode(dev);
6020 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
6021 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
6022
6023 bnx2_netif_start(bp);
6024 }
6025 #endif
6026
6027 /* Called with netif_tx_lock.
6028 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6029 * netif_wake_queue().
6030 */
6031 static int
6032 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6033 {
6034 struct bnx2 *bp = netdev_priv(dev);
6035 dma_addr_t mapping;
6036 struct tx_bd *txbd;
6037 struct sw_tx_bd *tx_buf;
6038 u32 len, vlan_tag_flags, last_frag, mss;
6039 u16 prod, ring_prod;
6040 int i;
6041 struct bnx2_napi *bnapi;
6042 struct bnx2_tx_ring_info *txr;
6043 struct netdev_queue *txq;
6044 struct skb_shared_info *sp;
6045
6046 /* Determine which tx ring we will be placed on */
6047 i = skb_get_queue_mapping(skb);
6048 bnapi = &bp->bnx2_napi[i];
6049 txr = &bnapi->tx_ring;
6050 txq = netdev_get_tx_queue(dev, i);
6051
6052 if (unlikely(bnx2_tx_avail(bp, txr) <
6053 (skb_shinfo(skb)->nr_frags + 1))) {
6054 netif_tx_stop_queue(txq);
6055 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
6056 dev->name);
6057
6058 return NETDEV_TX_BUSY;
6059 }
6060 len = skb_headlen(skb);
6061 prod = txr->tx_prod;
6062 ring_prod = TX_RING_IDX(prod);
6063
6064 vlan_tag_flags = 0;
6065 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6066 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6067 }
6068
6069 #ifdef BCM_VLAN
6070 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
6071 vlan_tag_flags |=
6072 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6073 }
6074 #endif
6075 if ((mss = skb_shinfo(skb)->gso_size)) {
6076 u32 tcp_opt_len;
6077 struct iphdr *iph;
6078
6079 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6080
6081 tcp_opt_len = tcp_optlen(skb);
6082
6083 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6084 u32 tcp_off = skb_transport_offset(skb) -
6085 sizeof(struct ipv6hdr) - ETH_HLEN;
6086
6087 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6088 TX_BD_FLAGS_SW_FLAGS;
6089 if (likely(tcp_off == 0))
6090 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6091 else {
6092 tcp_off >>= 3;
6093 vlan_tag_flags |= ((tcp_off & 0x3) <<
6094 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6095 ((tcp_off & 0x10) <<
6096 TX_BD_FLAGS_TCP6_OFF4_SHL);
6097 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6098 }
6099 } else {
6100 iph = ip_hdr(skb);
6101 if (tcp_opt_len || (iph->ihl > 5)) {
6102 vlan_tag_flags |= ((iph->ihl - 5) +
6103 (tcp_opt_len >> 2)) << 8;
6104 }
6105 }
6106 } else
6107 mss = 0;
6108
6109 if (skb_dma_map(&bp->pdev->dev, skb, DMA_TO_DEVICE)) {
6110 dev_kfree_skb(skb);
6111 return NETDEV_TX_OK;
6112 }
6113
6114 sp = skb_shinfo(skb);
6115 mapping = sp->dma_maps[0];
6116
6117 tx_buf = &txr->tx_buf_ring[ring_prod];
6118 tx_buf->skb = skb;
6119
6120 txbd = &txr->tx_desc_ring[ring_prod];
6121
6122 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6123 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6124 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6125 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6126
6127 last_frag = skb_shinfo(skb)->nr_frags;
6128
6129 for (i = 0; i < last_frag; i++) {
6130 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6131
6132 prod = NEXT_TX_BD(prod);
6133 ring_prod = TX_RING_IDX(prod);
6134 txbd = &txr->tx_desc_ring[ring_prod];
6135
6136 len = frag->size;
6137 mapping = sp->dma_maps[i + 1];
6138
6139 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6140 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6141 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6142 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6143
6144 }
6145 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6146
6147 prod = NEXT_TX_BD(prod);
6148 txr->tx_prod_bseq += skb->len;
6149
6150 REG_WR16(bp, txr->tx_bidx_addr, prod);
6151 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6152
6153 mmiowb();
6154
6155 txr->tx_prod = prod;
6156 dev->trans_start = jiffies;
6157
6158 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6159 netif_tx_stop_queue(txq);
6160 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6161 netif_tx_wake_queue(txq);
6162 }
6163
6164 return NETDEV_TX_OK;
6165 }
6166
6167 /* Called with rtnl_lock */
6168 static int
6169 bnx2_close(struct net_device *dev)
6170 {
6171 struct bnx2 *bp = netdev_priv(dev);
6172
6173 cancel_work_sync(&bp->reset_task);
6174
6175 bnx2_disable_int_sync(bp);
6176 bnx2_napi_disable(bp);
6177 del_timer_sync(&bp->timer);
6178 bnx2_shutdown_chip(bp);
6179 bnx2_free_irq(bp);
6180 bnx2_free_skbs(bp);
6181 bnx2_free_mem(bp);
6182 bp->link_up = 0;
6183 netif_carrier_off(bp->dev);
6184 bnx2_set_power_state(bp, PCI_D3hot);
6185 return 0;
6186 }
6187
6188 #define GET_NET_STATS64(ctr) \
6189 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
6190 (unsigned long) (ctr##_lo)
6191
6192 #define GET_NET_STATS32(ctr) \
6193 (ctr##_lo)
6194
6195 #if (BITS_PER_LONG == 64)
6196 #define GET_NET_STATS GET_NET_STATS64
6197 #else
6198 #define GET_NET_STATS GET_NET_STATS32
6199 #endif
6200
6201 static struct net_device_stats *
6202 bnx2_get_stats(struct net_device *dev)
6203 {
6204 struct bnx2 *bp = netdev_priv(dev);
6205 struct statistics_block *stats_blk = bp->stats_blk;
6206 struct net_device_stats *net_stats = &dev->stats;
6207
6208 if (bp->stats_blk == NULL) {
6209 return net_stats;
6210 }
6211 net_stats->rx_packets =
6212 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
6213 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
6214 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
6215
6216 net_stats->tx_packets =
6217 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
6218 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
6219 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
6220
6221 net_stats->rx_bytes =
6222 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
6223
6224 net_stats->tx_bytes =
6225 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
6226
6227 net_stats->multicast =
6228 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
6229
6230 net_stats->collisions =
6231 (unsigned long) stats_blk->stat_EtherStatsCollisions;
6232
6233 net_stats->rx_length_errors =
6234 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
6235 stats_blk->stat_EtherStatsOverrsizePkts);
6236
6237 net_stats->rx_over_errors =
6238 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
6239
6240 net_stats->rx_frame_errors =
6241 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
6242
6243 net_stats->rx_crc_errors =
6244 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
6245
6246 net_stats->rx_errors = net_stats->rx_length_errors +
6247 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6248 net_stats->rx_crc_errors;
6249
6250 net_stats->tx_aborted_errors =
6251 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
6252 stats_blk->stat_Dot3StatsLateCollisions);
6253
6254 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6255 (CHIP_ID(bp) == CHIP_ID_5708_A0))
6256 net_stats->tx_carrier_errors = 0;
6257 else {
6258 net_stats->tx_carrier_errors =
6259 (unsigned long)
6260 stats_blk->stat_Dot3StatsCarrierSenseErrors;
6261 }
6262
6263 net_stats->tx_errors =
6264 (unsigned long)
6265 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6266 +
6267 net_stats->tx_aborted_errors +
6268 net_stats->tx_carrier_errors;
6269
6270 net_stats->rx_missed_errors =
6271 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
6272 stats_blk->stat_FwRxDrop);
6273
6274 return net_stats;
6275 }
6276
6277 /* All ethtool functions called with rtnl_lock */
6278
6279 static int
6280 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6281 {
6282 struct bnx2 *bp = netdev_priv(dev);
6283 int support_serdes = 0, support_copper = 0;
6284
6285 cmd->supported = SUPPORTED_Autoneg;
6286 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6287 support_serdes = 1;
6288 support_copper = 1;
6289 } else if (bp->phy_port == PORT_FIBRE)
6290 support_serdes = 1;
6291 else
6292 support_copper = 1;
6293
6294 if (support_serdes) {
6295 cmd->supported |= SUPPORTED_1000baseT_Full |
6296 SUPPORTED_FIBRE;
6297 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6298 cmd->supported |= SUPPORTED_2500baseX_Full;
6299
6300 }
6301 if (support_copper) {
6302 cmd->supported |= SUPPORTED_10baseT_Half |
6303 SUPPORTED_10baseT_Full |
6304 SUPPORTED_100baseT_Half |
6305 SUPPORTED_100baseT_Full |
6306 SUPPORTED_1000baseT_Full |
6307 SUPPORTED_TP;
6308
6309 }
6310
6311 spin_lock_bh(&bp->phy_lock);
6312 cmd->port = bp->phy_port;
6313 cmd->advertising = bp->advertising;
6314
6315 if (bp->autoneg & AUTONEG_SPEED) {
6316 cmd->autoneg = AUTONEG_ENABLE;
6317 }
6318 else {
6319 cmd->autoneg = AUTONEG_DISABLE;
6320 }
6321
6322 if (netif_carrier_ok(dev)) {
6323 cmd->speed = bp->line_speed;
6324 cmd->duplex = bp->duplex;
6325 }
6326 else {
6327 cmd->speed = -1;
6328 cmd->duplex = -1;
6329 }
6330 spin_unlock_bh(&bp->phy_lock);
6331
6332 cmd->transceiver = XCVR_INTERNAL;
6333 cmd->phy_address = bp->phy_addr;
6334
6335 return 0;
6336 }
6337
6338 static int
6339 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6340 {
6341 struct bnx2 *bp = netdev_priv(dev);
6342 u8 autoneg = bp->autoneg;
6343 u8 req_duplex = bp->req_duplex;
6344 u16 req_line_speed = bp->req_line_speed;
6345 u32 advertising = bp->advertising;
6346 int err = -EINVAL;
6347
6348 spin_lock_bh(&bp->phy_lock);
6349
6350 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6351 goto err_out_unlock;
6352
6353 if (cmd->port != bp->phy_port &&
6354 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6355 goto err_out_unlock;
6356
6357 /* If device is down, we can store the settings only if the user
6358 * is setting the currently active port.
6359 */
6360 if (!netif_running(dev) && cmd->port != bp->phy_port)
6361 goto err_out_unlock;
6362
6363 if (cmd->autoneg == AUTONEG_ENABLE) {
6364 autoneg |= AUTONEG_SPEED;
6365
6366 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
6367
6368 /* allow advertising 1 speed */
6369 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6370 (cmd->advertising == ADVERTISED_10baseT_Full) ||
6371 (cmd->advertising == ADVERTISED_100baseT_Half) ||
6372 (cmd->advertising == ADVERTISED_100baseT_Full)) {
6373
6374 if (cmd->port == PORT_FIBRE)
6375 goto err_out_unlock;
6376
6377 advertising = cmd->advertising;
6378
6379 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
6380 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
6381 (cmd->port == PORT_TP))
6382 goto err_out_unlock;
6383 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
6384 advertising = cmd->advertising;
6385 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6386 goto err_out_unlock;
6387 else {
6388 if (cmd->port == PORT_FIBRE)
6389 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6390 else
6391 advertising = ETHTOOL_ALL_COPPER_SPEED;
6392 }
6393 advertising |= ADVERTISED_Autoneg;
6394 }
6395 else {
6396 if (cmd->port == PORT_FIBRE) {
6397 if ((cmd->speed != SPEED_1000 &&
6398 cmd->speed != SPEED_2500) ||
6399 (cmd->duplex != DUPLEX_FULL))
6400 goto err_out_unlock;
6401
6402 if (cmd->speed == SPEED_2500 &&
6403 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6404 goto err_out_unlock;
6405 }
6406 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6407 goto err_out_unlock;
6408
6409 autoneg &= ~AUTONEG_SPEED;
6410 req_line_speed = cmd->speed;
6411 req_duplex = cmd->duplex;
6412 advertising = 0;
6413 }
6414
6415 bp->autoneg = autoneg;
6416 bp->advertising = advertising;
6417 bp->req_line_speed = req_line_speed;
6418 bp->req_duplex = req_duplex;
6419
6420 err = 0;
6421 /* If device is down, the new settings will be picked up when it is
6422 * brought up.
6423 */
6424 if (netif_running(dev))
6425 err = bnx2_setup_phy(bp, cmd->port);
6426
6427 err_out_unlock:
6428 spin_unlock_bh(&bp->phy_lock);
6429
6430 return err;
6431 }
6432
6433 static void
6434 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6435 {
6436 struct bnx2 *bp = netdev_priv(dev);
6437
6438 strcpy(info->driver, DRV_MODULE_NAME);
6439 strcpy(info->version, DRV_MODULE_VERSION);
6440 strcpy(info->bus_info, pci_name(bp->pdev));
6441 strcpy(info->fw_version, bp->fw_version);
6442 }
6443
6444 #define BNX2_REGDUMP_LEN (32 * 1024)
6445
6446 static int
6447 bnx2_get_regs_len(struct net_device *dev)
6448 {
6449 return BNX2_REGDUMP_LEN;
6450 }
6451
6452 static void
6453 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6454 {
6455 u32 *p = _p, i, offset;
6456 u8 *orig_p = _p;
6457 struct bnx2 *bp = netdev_priv(dev);
6458 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6459 0x0800, 0x0880, 0x0c00, 0x0c10,
6460 0x0c30, 0x0d08, 0x1000, 0x101c,
6461 0x1040, 0x1048, 0x1080, 0x10a4,
6462 0x1400, 0x1490, 0x1498, 0x14f0,
6463 0x1500, 0x155c, 0x1580, 0x15dc,
6464 0x1600, 0x1658, 0x1680, 0x16d8,
6465 0x1800, 0x1820, 0x1840, 0x1854,
6466 0x1880, 0x1894, 0x1900, 0x1984,
6467 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6468 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6469 0x2000, 0x2030, 0x23c0, 0x2400,
6470 0x2800, 0x2820, 0x2830, 0x2850,
6471 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6472 0x3c00, 0x3c94, 0x4000, 0x4010,
6473 0x4080, 0x4090, 0x43c0, 0x4458,
6474 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6475 0x4fc0, 0x5010, 0x53c0, 0x5444,
6476 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6477 0x5fc0, 0x6000, 0x6400, 0x6428,
6478 0x6800, 0x6848, 0x684c, 0x6860,
6479 0x6888, 0x6910, 0x8000 };
6480
6481 regs->version = 0;
6482
6483 memset(p, 0, BNX2_REGDUMP_LEN);
6484
6485 if (!netif_running(bp->dev))
6486 return;
6487
6488 i = 0;
6489 offset = reg_boundaries[0];
6490 p += offset;
6491 while (offset < BNX2_REGDUMP_LEN) {
6492 *p++ = REG_RD(bp, offset);
6493 offset += 4;
6494 if (offset == reg_boundaries[i + 1]) {
6495 offset = reg_boundaries[i + 2];
6496 p = (u32 *) (orig_p + offset);
6497 i += 2;
6498 }
6499 }
6500 }
6501
6502 static void
6503 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6504 {
6505 struct bnx2 *bp = netdev_priv(dev);
6506
6507 if (bp->flags & BNX2_FLAG_NO_WOL) {
6508 wol->supported = 0;
6509 wol->wolopts = 0;
6510 }
6511 else {
6512 wol->supported = WAKE_MAGIC;
6513 if (bp->wol)
6514 wol->wolopts = WAKE_MAGIC;
6515 else
6516 wol->wolopts = 0;
6517 }
6518 memset(&wol->sopass, 0, sizeof(wol->sopass));
6519 }
6520
6521 static int
6522 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6523 {
6524 struct bnx2 *bp = netdev_priv(dev);
6525
6526 if (wol->wolopts & ~WAKE_MAGIC)
6527 return -EINVAL;
6528
6529 if (wol->wolopts & WAKE_MAGIC) {
6530 if (bp->flags & BNX2_FLAG_NO_WOL)
6531 return -EINVAL;
6532
6533 bp->wol = 1;
6534 }
6535 else {
6536 bp->wol = 0;
6537 }
6538 return 0;
6539 }
6540
6541 static int
6542 bnx2_nway_reset(struct net_device *dev)
6543 {
6544 struct bnx2 *bp = netdev_priv(dev);
6545 u32 bmcr;
6546
6547 if (!netif_running(dev))
6548 return -EAGAIN;
6549
6550 if (!(bp->autoneg & AUTONEG_SPEED)) {
6551 return -EINVAL;
6552 }
6553
6554 spin_lock_bh(&bp->phy_lock);
6555
6556 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6557 int rc;
6558
6559 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6560 spin_unlock_bh(&bp->phy_lock);
6561 return rc;
6562 }
6563
6564 /* Force a link down visible on the other side */
6565 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6566 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6567 spin_unlock_bh(&bp->phy_lock);
6568
6569 msleep(20);
6570
6571 spin_lock_bh(&bp->phy_lock);
6572
6573 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
6574 bp->serdes_an_pending = 1;
6575 mod_timer(&bp->timer, jiffies + bp->current_interval);
6576 }
6577
6578 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6579 bmcr &= ~BMCR_LOOPBACK;
6580 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6581
6582 spin_unlock_bh(&bp->phy_lock);
6583
6584 return 0;
6585 }
6586
6587 static int
6588 bnx2_get_eeprom_len(struct net_device *dev)
6589 {
6590 struct bnx2 *bp = netdev_priv(dev);
6591
6592 if (bp->flash_info == NULL)
6593 return 0;
6594
6595 return (int) bp->flash_size;
6596 }
6597
6598 static int
6599 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6600 u8 *eebuf)
6601 {
6602 struct bnx2 *bp = netdev_priv(dev);
6603 int rc;
6604
6605 if (!netif_running(dev))
6606 return -EAGAIN;
6607
6608 /* parameters already validated in ethtool_get_eeprom */
6609
6610 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6611
6612 return rc;
6613 }
6614
6615 static int
6616 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6617 u8 *eebuf)
6618 {
6619 struct bnx2 *bp = netdev_priv(dev);
6620 int rc;
6621
6622 if (!netif_running(dev))
6623 return -EAGAIN;
6624
6625 /* parameters already validated in ethtool_set_eeprom */
6626
6627 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6628
6629 return rc;
6630 }
6631
6632 static int
6633 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6634 {
6635 struct bnx2 *bp = netdev_priv(dev);
6636
6637 memset(coal, 0, sizeof(struct ethtool_coalesce));
6638
6639 coal->rx_coalesce_usecs = bp->rx_ticks;
6640 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6641 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6642 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6643
6644 coal->tx_coalesce_usecs = bp->tx_ticks;
6645 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6646 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6647 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6648
6649 coal->stats_block_coalesce_usecs = bp->stats_ticks;
6650
6651 return 0;
6652 }
6653
6654 static int
6655 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6656 {
6657 struct bnx2 *bp = netdev_priv(dev);
6658
6659 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6660 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6661
6662 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
6663 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6664
6665 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6666 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6667
6668 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6669 if (bp->rx_quick_cons_trip_int > 0xff)
6670 bp->rx_quick_cons_trip_int = 0xff;
6671
6672 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6673 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6674
6675 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6676 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6677
6678 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6679 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6680
6681 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6682 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6683 0xff;
6684
6685 bp->stats_ticks = coal->stats_block_coalesce_usecs;
6686 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6687 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6688 bp->stats_ticks = USEC_PER_SEC;
6689 }
6690 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6691 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6692 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6693
6694 if (netif_running(bp->dev)) {
6695 bnx2_netif_stop(bp);
6696 bnx2_init_nic(bp, 0);
6697 bnx2_netif_start(bp);
6698 }
6699
6700 return 0;
6701 }
6702
6703 static void
6704 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6705 {
6706 struct bnx2 *bp = netdev_priv(dev);
6707
6708 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
6709 ering->rx_mini_max_pending = 0;
6710 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
6711
6712 ering->rx_pending = bp->rx_ring_size;
6713 ering->rx_mini_pending = 0;
6714 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
6715
6716 ering->tx_max_pending = MAX_TX_DESC_CNT;
6717 ering->tx_pending = bp->tx_ring_size;
6718 }
6719
6720 static int
6721 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
6722 {
6723 if (netif_running(bp->dev)) {
6724 bnx2_netif_stop(bp);
6725 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6726 bnx2_free_skbs(bp);
6727 bnx2_free_mem(bp);
6728 }
6729
6730 bnx2_set_rx_ring_size(bp, rx);
6731 bp->tx_ring_size = tx;
6732
6733 if (netif_running(bp->dev)) {
6734 int rc;
6735
6736 rc = bnx2_alloc_mem(bp);
6737 if (rc)
6738 return rc;
6739 bnx2_init_nic(bp, 0);
6740 bnx2_netif_start(bp);
6741 }
6742 return 0;
6743 }
6744
6745 static int
6746 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6747 {
6748 struct bnx2 *bp = netdev_priv(dev);
6749 int rc;
6750
6751 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6752 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6753 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6754
6755 return -EINVAL;
6756 }
6757 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6758 return rc;
6759 }
6760
6761 static void
6762 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6763 {
6764 struct bnx2 *bp = netdev_priv(dev);
6765
6766 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6767 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6768 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6769 }
6770
6771 static int
6772 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6773 {
6774 struct bnx2 *bp = netdev_priv(dev);
6775
6776 bp->req_flow_ctrl = 0;
6777 if (epause->rx_pause)
6778 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6779 if (epause->tx_pause)
6780 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6781
6782 if (epause->autoneg) {
6783 bp->autoneg |= AUTONEG_FLOW_CTRL;
6784 }
6785 else {
6786 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6787 }
6788
6789 if (netif_running(dev)) {
6790 spin_lock_bh(&bp->phy_lock);
6791 bnx2_setup_phy(bp, bp->phy_port);
6792 spin_unlock_bh(&bp->phy_lock);
6793 }
6794
6795 return 0;
6796 }
6797
6798 static u32
6799 bnx2_get_rx_csum(struct net_device *dev)
6800 {
6801 struct bnx2 *bp = netdev_priv(dev);
6802
6803 return bp->rx_csum;
6804 }
6805
6806 static int
6807 bnx2_set_rx_csum(struct net_device *dev, u32 data)
6808 {
6809 struct bnx2 *bp = netdev_priv(dev);
6810
6811 bp->rx_csum = data;
6812 return 0;
6813 }
6814
6815 static int
6816 bnx2_set_tso(struct net_device *dev, u32 data)
6817 {
6818 struct bnx2 *bp = netdev_priv(dev);
6819
6820 if (data) {
6821 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
6822 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6823 dev->features |= NETIF_F_TSO6;
6824 } else
6825 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6826 NETIF_F_TSO_ECN);
6827 return 0;
6828 }
6829
6830 #define BNX2_NUM_STATS 46
6831
6832 static struct {
6833 char string[ETH_GSTRING_LEN];
6834 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6835 { "rx_bytes" },
6836 { "rx_error_bytes" },
6837 { "tx_bytes" },
6838 { "tx_error_bytes" },
6839 { "rx_ucast_packets" },
6840 { "rx_mcast_packets" },
6841 { "rx_bcast_packets" },
6842 { "tx_ucast_packets" },
6843 { "tx_mcast_packets" },
6844 { "tx_bcast_packets" },
6845 { "tx_mac_errors" },
6846 { "tx_carrier_errors" },
6847 { "rx_crc_errors" },
6848 { "rx_align_errors" },
6849 { "tx_single_collisions" },
6850 { "tx_multi_collisions" },
6851 { "tx_deferred" },
6852 { "tx_excess_collisions" },
6853 { "tx_late_collisions" },
6854 { "tx_total_collisions" },
6855 { "rx_fragments" },
6856 { "rx_jabbers" },
6857 { "rx_undersize_packets" },
6858 { "rx_oversize_packets" },
6859 { "rx_64_byte_packets" },
6860 { "rx_65_to_127_byte_packets" },
6861 { "rx_128_to_255_byte_packets" },
6862 { "rx_256_to_511_byte_packets" },
6863 { "rx_512_to_1023_byte_packets" },
6864 { "rx_1024_to_1522_byte_packets" },
6865 { "rx_1523_to_9022_byte_packets" },
6866 { "tx_64_byte_packets" },
6867 { "tx_65_to_127_byte_packets" },
6868 { "tx_128_to_255_byte_packets" },
6869 { "tx_256_to_511_byte_packets" },
6870 { "tx_512_to_1023_byte_packets" },
6871 { "tx_1024_to_1522_byte_packets" },
6872 { "tx_1523_to_9022_byte_packets" },
6873 { "rx_xon_frames" },
6874 { "rx_xoff_frames" },
6875 { "tx_xon_frames" },
6876 { "tx_xoff_frames" },
6877 { "rx_mac_ctrl_frames" },
6878 { "rx_filtered_packets" },
6879 { "rx_discards" },
6880 { "rx_fw_discards" },
6881 };
6882
6883 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6884
6885 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
6886 STATS_OFFSET32(stat_IfHCInOctets_hi),
6887 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6888 STATS_OFFSET32(stat_IfHCOutOctets_hi),
6889 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6890 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6891 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6892 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6893 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6894 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6895 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6896 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6897 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6898 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6899 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6900 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6901 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6902 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6903 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6904 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6905 STATS_OFFSET32(stat_EtherStatsCollisions),
6906 STATS_OFFSET32(stat_EtherStatsFragments),
6907 STATS_OFFSET32(stat_EtherStatsJabbers),
6908 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6909 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6910 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6911 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6912 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6913 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6914 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6915 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6916 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6917 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6918 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6919 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6920 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6921 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6922 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6923 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6924 STATS_OFFSET32(stat_XonPauseFramesReceived),
6925 STATS_OFFSET32(stat_XoffPauseFramesReceived),
6926 STATS_OFFSET32(stat_OutXonSent),
6927 STATS_OFFSET32(stat_OutXoffSent),
6928 STATS_OFFSET32(stat_MacControlFramesReceived),
6929 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6930 STATS_OFFSET32(stat_IfInMBUFDiscards),
6931 STATS_OFFSET32(stat_FwRxDrop),
6932 };
6933
6934 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6935 * skipped because of errata.
6936 */
6937 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
6938 8,0,8,8,8,8,8,8,8,8,
6939 4,0,4,4,4,4,4,4,4,4,
6940 4,4,4,4,4,4,4,4,4,4,
6941 4,4,4,4,4,4,4,4,4,4,
6942 4,4,4,4,4,4,
6943 };
6944
6945 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6946 8,0,8,8,8,8,8,8,8,8,
6947 4,4,4,4,4,4,4,4,4,4,
6948 4,4,4,4,4,4,4,4,4,4,
6949 4,4,4,4,4,4,4,4,4,4,
6950 4,4,4,4,4,4,
6951 };
6952
6953 #define BNX2_NUM_TESTS 6
6954
6955 static struct {
6956 char string[ETH_GSTRING_LEN];
6957 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6958 { "register_test (offline)" },
6959 { "memory_test (offline)" },
6960 { "loopback_test (offline)" },
6961 { "nvram_test (online)" },
6962 { "interrupt_test (online)" },
6963 { "link_test (online)" },
6964 };
6965
6966 static int
6967 bnx2_get_sset_count(struct net_device *dev, int sset)
6968 {
6969 switch (sset) {
6970 case ETH_SS_TEST:
6971 return BNX2_NUM_TESTS;
6972 case ETH_SS_STATS:
6973 return BNX2_NUM_STATS;
6974 default:
6975 return -EOPNOTSUPP;
6976 }
6977 }
6978
6979 static void
6980 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6981 {
6982 struct bnx2 *bp = netdev_priv(dev);
6983
6984 bnx2_set_power_state(bp, PCI_D0);
6985
6986 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6987 if (etest->flags & ETH_TEST_FL_OFFLINE) {
6988 int i;
6989
6990 bnx2_netif_stop(bp);
6991 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6992 bnx2_free_skbs(bp);
6993
6994 if (bnx2_test_registers(bp) != 0) {
6995 buf[0] = 1;
6996 etest->flags |= ETH_TEST_FL_FAILED;
6997 }
6998 if (bnx2_test_memory(bp) != 0) {
6999 buf[1] = 1;
7000 etest->flags |= ETH_TEST_FL_FAILED;
7001 }
7002 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
7003 etest->flags |= ETH_TEST_FL_FAILED;
7004
7005 if (!netif_running(bp->dev))
7006 bnx2_shutdown_chip(bp);
7007 else {
7008 bnx2_init_nic(bp, 1);
7009 bnx2_netif_start(bp);
7010 }
7011
7012 /* wait for link up */
7013 for (i = 0; i < 7; i++) {
7014 if (bp->link_up)
7015 break;
7016 msleep_interruptible(1000);
7017 }
7018 }
7019
7020 if (bnx2_test_nvram(bp) != 0) {
7021 buf[3] = 1;
7022 etest->flags |= ETH_TEST_FL_FAILED;
7023 }
7024 if (bnx2_test_intr(bp) != 0) {
7025 buf[4] = 1;
7026 etest->flags |= ETH_TEST_FL_FAILED;
7027 }
7028
7029 if (bnx2_test_link(bp) != 0) {
7030 buf[5] = 1;
7031 etest->flags |= ETH_TEST_FL_FAILED;
7032
7033 }
7034 if (!netif_running(bp->dev))
7035 bnx2_set_power_state(bp, PCI_D3hot);
7036 }
7037
7038 static void
7039 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7040 {
7041 switch (stringset) {
7042 case ETH_SS_STATS:
7043 memcpy(buf, bnx2_stats_str_arr,
7044 sizeof(bnx2_stats_str_arr));
7045 break;
7046 case ETH_SS_TEST:
7047 memcpy(buf, bnx2_tests_str_arr,
7048 sizeof(bnx2_tests_str_arr));
7049 break;
7050 }
7051 }
7052
7053 static void
7054 bnx2_get_ethtool_stats(struct net_device *dev,
7055 struct ethtool_stats *stats, u64 *buf)
7056 {
7057 struct bnx2 *bp = netdev_priv(dev);
7058 int i;
7059 u32 *hw_stats = (u32 *) bp->stats_blk;
7060 u8 *stats_len_arr = NULL;
7061
7062 if (hw_stats == NULL) {
7063 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7064 return;
7065 }
7066
7067 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7068 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7069 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7070 (CHIP_ID(bp) == CHIP_ID_5708_A0))
7071 stats_len_arr = bnx2_5706_stats_len_arr;
7072 else
7073 stats_len_arr = bnx2_5708_stats_len_arr;
7074
7075 for (i = 0; i < BNX2_NUM_STATS; i++) {
7076 if (stats_len_arr[i] == 0) {
7077 /* skip this counter */
7078 buf[i] = 0;
7079 continue;
7080 }
7081 if (stats_len_arr[i] == 4) {
7082 /* 4-byte counter */
7083 buf[i] = (u64)
7084 *(hw_stats + bnx2_stats_offset_arr[i]);
7085 continue;
7086 }
7087 /* 8-byte counter */
7088 buf[i] = (((u64) *(hw_stats +
7089 bnx2_stats_offset_arr[i])) << 32) +
7090 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
7091 }
7092 }
7093
7094 static int
7095 bnx2_phys_id(struct net_device *dev, u32 data)
7096 {
7097 struct bnx2 *bp = netdev_priv(dev);
7098 int i;
7099 u32 save;
7100
7101 bnx2_set_power_state(bp, PCI_D0);
7102
7103 if (data == 0)
7104 data = 2;
7105
7106 save = REG_RD(bp, BNX2_MISC_CFG);
7107 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7108
7109 for (i = 0; i < (data * 2); i++) {
7110 if ((i % 2) == 0) {
7111 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7112 }
7113 else {
7114 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7115 BNX2_EMAC_LED_1000MB_OVERRIDE |
7116 BNX2_EMAC_LED_100MB_OVERRIDE |
7117 BNX2_EMAC_LED_10MB_OVERRIDE |
7118 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7119 BNX2_EMAC_LED_TRAFFIC);
7120 }
7121 msleep_interruptible(500);
7122 if (signal_pending(current))
7123 break;
7124 }
7125 REG_WR(bp, BNX2_EMAC_LED, 0);
7126 REG_WR(bp, BNX2_MISC_CFG, save);
7127
7128 if (!netif_running(dev))
7129 bnx2_set_power_state(bp, PCI_D3hot);
7130
7131 return 0;
7132 }
7133
7134 static int
7135 bnx2_set_tx_csum(struct net_device *dev, u32 data)
7136 {
7137 struct bnx2 *bp = netdev_priv(dev);
7138
7139 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7140 return (ethtool_op_set_tx_ipv6_csum(dev, data));
7141 else
7142 return (ethtool_op_set_tx_csum(dev, data));
7143 }
7144
7145 static const struct ethtool_ops bnx2_ethtool_ops = {
7146 .get_settings = bnx2_get_settings,
7147 .set_settings = bnx2_set_settings,
7148 .get_drvinfo = bnx2_get_drvinfo,
7149 .get_regs_len = bnx2_get_regs_len,
7150 .get_regs = bnx2_get_regs,
7151 .get_wol = bnx2_get_wol,
7152 .set_wol = bnx2_set_wol,
7153 .nway_reset = bnx2_nway_reset,
7154 .get_link = ethtool_op_get_link,
7155 .get_eeprom_len = bnx2_get_eeprom_len,
7156 .get_eeprom = bnx2_get_eeprom,
7157 .set_eeprom = bnx2_set_eeprom,
7158 .get_coalesce = bnx2_get_coalesce,
7159 .set_coalesce = bnx2_set_coalesce,
7160 .get_ringparam = bnx2_get_ringparam,
7161 .set_ringparam = bnx2_set_ringparam,
7162 .get_pauseparam = bnx2_get_pauseparam,
7163 .set_pauseparam = bnx2_set_pauseparam,
7164 .get_rx_csum = bnx2_get_rx_csum,
7165 .set_rx_csum = bnx2_set_rx_csum,
7166 .set_tx_csum = bnx2_set_tx_csum,
7167 .set_sg = ethtool_op_set_sg,
7168 .set_tso = bnx2_set_tso,
7169 .self_test = bnx2_self_test,
7170 .get_strings = bnx2_get_strings,
7171 .phys_id = bnx2_phys_id,
7172 .get_ethtool_stats = bnx2_get_ethtool_stats,
7173 .get_sset_count = bnx2_get_sset_count,
7174 };
7175
7176 /* Called with rtnl_lock */
7177 static int
7178 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7179 {
7180 struct mii_ioctl_data *data = if_mii(ifr);
7181 struct bnx2 *bp = netdev_priv(dev);
7182 int err;
7183
7184 switch(cmd) {
7185 case SIOCGMIIPHY:
7186 data->phy_id = bp->phy_addr;
7187
7188 /* fallthru */
7189 case SIOCGMIIREG: {
7190 u32 mii_regval;
7191
7192 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7193 return -EOPNOTSUPP;
7194
7195 if (!netif_running(dev))
7196 return -EAGAIN;
7197
7198 spin_lock_bh(&bp->phy_lock);
7199 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7200 spin_unlock_bh(&bp->phy_lock);
7201
7202 data->val_out = mii_regval;
7203
7204 return err;
7205 }
7206
7207 case SIOCSMIIREG:
7208 if (!capable(CAP_NET_ADMIN))
7209 return -EPERM;
7210
7211 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7212 return -EOPNOTSUPP;
7213
7214 if (!netif_running(dev))
7215 return -EAGAIN;
7216
7217 spin_lock_bh(&bp->phy_lock);
7218 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7219 spin_unlock_bh(&bp->phy_lock);
7220
7221 return err;
7222
7223 default:
7224 /* do nothing */
7225 break;
7226 }
7227 return -EOPNOTSUPP;
7228 }
7229
7230 /* Called with rtnl_lock */
7231 static int
7232 bnx2_change_mac_addr(struct net_device *dev, void *p)
7233 {
7234 struct sockaddr *addr = p;
7235 struct bnx2 *bp = netdev_priv(dev);
7236
7237 if (!is_valid_ether_addr(addr->sa_data))
7238 return -EINVAL;
7239
7240 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7241 if (netif_running(dev))
7242 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7243
7244 return 0;
7245 }
7246
7247 /* Called with rtnl_lock */
7248 static int
7249 bnx2_change_mtu(struct net_device *dev, int new_mtu)
7250 {
7251 struct bnx2 *bp = netdev_priv(dev);
7252
7253 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7254 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7255 return -EINVAL;
7256
7257 dev->mtu = new_mtu;
7258 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
7259 }
7260
7261 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7262 static void
7263 poll_bnx2(struct net_device *dev)
7264 {
7265 struct bnx2 *bp = netdev_priv(dev);
7266 int i;
7267
7268 for (i = 0; i < bp->irq_nvecs; i++) {
7269 disable_irq(bp->irq_tbl[i].vector);
7270 bnx2_interrupt(bp->irq_tbl[i].vector, &bp->bnx2_napi[i]);
7271 enable_irq(bp->irq_tbl[i].vector);
7272 }
7273 }
7274 #endif
7275
7276 static void __devinit
7277 bnx2_get_5709_media(struct bnx2 *bp)
7278 {
7279 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7280 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7281 u32 strap;
7282
7283 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7284 return;
7285 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7286 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7287 return;
7288 }
7289
7290 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7291 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7292 else
7293 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7294
7295 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7296 switch (strap) {
7297 case 0x4:
7298 case 0x5:
7299 case 0x6:
7300 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7301 return;
7302 }
7303 } else {
7304 switch (strap) {
7305 case 0x1:
7306 case 0x2:
7307 case 0x4:
7308 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7309 return;
7310 }
7311 }
7312 }
7313
7314 static void __devinit
7315 bnx2_get_pci_speed(struct bnx2 *bp)
7316 {
7317 u32 reg;
7318
7319 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7320 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7321 u32 clkreg;
7322
7323 bp->flags |= BNX2_FLAG_PCIX;
7324
7325 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7326
7327 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7328 switch (clkreg) {
7329 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7330 bp->bus_speed_mhz = 133;
7331 break;
7332
7333 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7334 bp->bus_speed_mhz = 100;
7335 break;
7336
7337 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7338 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7339 bp->bus_speed_mhz = 66;
7340 break;
7341
7342 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7343 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7344 bp->bus_speed_mhz = 50;
7345 break;
7346
7347 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7348 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7349 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7350 bp->bus_speed_mhz = 33;
7351 break;
7352 }
7353 }
7354 else {
7355 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7356 bp->bus_speed_mhz = 66;
7357 else
7358 bp->bus_speed_mhz = 33;
7359 }
7360
7361 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7362 bp->flags |= BNX2_FLAG_PCI_32BIT;
7363
7364 }
7365
7366 static int __devinit
7367 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7368 {
7369 struct bnx2 *bp;
7370 unsigned long mem_len;
7371 int rc, i, j;
7372 u32 reg;
7373 u64 dma_mask, persist_dma_mask;
7374
7375 SET_NETDEV_DEV(dev, &pdev->dev);
7376 bp = netdev_priv(dev);
7377
7378 bp->flags = 0;
7379 bp->phy_flags = 0;
7380
7381 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7382 rc = pci_enable_device(pdev);
7383 if (rc) {
7384 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
7385 goto err_out;
7386 }
7387
7388 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7389 dev_err(&pdev->dev,
7390 "Cannot find PCI device base address, aborting.\n");
7391 rc = -ENODEV;
7392 goto err_out_disable;
7393 }
7394
7395 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7396 if (rc) {
7397 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
7398 goto err_out_disable;
7399 }
7400
7401 pci_set_master(pdev);
7402 pci_save_state(pdev);
7403
7404 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7405 if (bp->pm_cap == 0) {
7406 dev_err(&pdev->dev,
7407 "Cannot find power management capability, aborting.\n");
7408 rc = -EIO;
7409 goto err_out_release;
7410 }
7411
7412 bp->dev = dev;
7413 bp->pdev = pdev;
7414
7415 spin_lock_init(&bp->phy_lock);
7416 spin_lock_init(&bp->indirect_lock);
7417 INIT_WORK(&bp->reset_task, bnx2_reset_task);
7418
7419 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7420 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS);
7421 dev->mem_end = dev->mem_start + mem_len;
7422 dev->irq = pdev->irq;
7423
7424 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7425
7426 if (!bp->regview) {
7427 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
7428 rc = -ENOMEM;
7429 goto err_out_release;
7430 }
7431
7432 /* Configure byte swap and enable write to the reg_window registers.
7433 * Rely on CPU to do target byte swapping on big endian systems
7434 * The chip's target access swapping will not swap all accesses
7435 */
7436 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7437 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7438 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7439
7440 bnx2_set_power_state(bp, PCI_D0);
7441
7442 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7443
7444 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7445 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7446 dev_err(&pdev->dev,
7447 "Cannot find PCIE capability, aborting.\n");
7448 rc = -EIO;
7449 goto err_out_unmap;
7450 }
7451 bp->flags |= BNX2_FLAG_PCIE;
7452 if (CHIP_REV(bp) == CHIP_REV_Ax)
7453 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7454 } else {
7455 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7456 if (bp->pcix_cap == 0) {
7457 dev_err(&pdev->dev,
7458 "Cannot find PCIX capability, aborting.\n");
7459 rc = -EIO;
7460 goto err_out_unmap;
7461 }
7462 }
7463
7464 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7465 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7466 bp->flags |= BNX2_FLAG_MSIX_CAP;
7467 }
7468
7469 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7470 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7471 bp->flags |= BNX2_FLAG_MSI_CAP;
7472 }
7473
7474 /* 5708 cannot support DMA addresses > 40-bit. */
7475 if (CHIP_NUM(bp) == CHIP_NUM_5708)
7476 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
7477 else
7478 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
7479
7480 /* Configure DMA attributes. */
7481 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7482 dev->features |= NETIF_F_HIGHDMA;
7483 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7484 if (rc) {
7485 dev_err(&pdev->dev,
7486 "pci_set_consistent_dma_mask failed, aborting.\n");
7487 goto err_out_unmap;
7488 }
7489 } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
7490 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7491 goto err_out_unmap;
7492 }
7493
7494 if (!(bp->flags & BNX2_FLAG_PCIE))
7495 bnx2_get_pci_speed(bp);
7496
7497 /* 5706A0 may falsely detect SERR and PERR. */
7498 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7499 reg = REG_RD(bp, PCI_COMMAND);
7500 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7501 REG_WR(bp, PCI_COMMAND, reg);
7502 }
7503 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7504 !(bp->flags & BNX2_FLAG_PCIX)) {
7505
7506 dev_err(&pdev->dev,
7507 "5706 A1 can only be used in a PCIX bus, aborting.\n");
7508 goto err_out_unmap;
7509 }
7510
7511 bnx2_init_nvram(bp);
7512
7513 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7514
7515 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
7516 BNX2_SHM_HDR_SIGNATURE_SIG) {
7517 u32 off = PCI_FUNC(pdev->devfn) << 2;
7518
7519 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
7520 } else
7521 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7522
7523 /* Get the permanent MAC address. First we need to make sure the
7524 * firmware is actually running.
7525 */
7526 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
7527
7528 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7529 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
7530 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
7531 rc = -ENODEV;
7532 goto err_out_unmap;
7533 }
7534
7535 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
7536 for (i = 0, j = 0; i < 3; i++) {
7537 u8 num, k, skip0;
7538
7539 num = (u8) (reg >> (24 - (i * 8)));
7540 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7541 if (num >= k || !skip0 || k == 1) {
7542 bp->fw_version[j++] = (num / k) + '0';
7543 skip0 = 0;
7544 }
7545 }
7546 if (i != 2)
7547 bp->fw_version[j++] = '.';
7548 }
7549 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
7550 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7551 bp->wol = 1;
7552
7553 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
7554 bp->flags |= BNX2_FLAG_ASF_ENABLE;
7555
7556 for (i = 0; i < 30; i++) {
7557 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7558 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7559 break;
7560 msleep(10);
7561 }
7562 }
7563 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7564 reg &= BNX2_CONDITION_MFW_RUN_MASK;
7565 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7566 reg != BNX2_CONDITION_MFW_RUN_NONE) {
7567 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
7568
7569 bp->fw_version[j++] = ' ';
7570 for (i = 0; i < 3; i++) {
7571 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
7572 reg = swab32(reg);
7573 memcpy(&bp->fw_version[j], &reg, 4);
7574 j += 4;
7575 }
7576 }
7577
7578 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
7579 bp->mac_addr[0] = (u8) (reg >> 8);
7580 bp->mac_addr[1] = (u8) reg;
7581
7582 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
7583 bp->mac_addr[2] = (u8) (reg >> 24);
7584 bp->mac_addr[3] = (u8) (reg >> 16);
7585 bp->mac_addr[4] = (u8) (reg >> 8);
7586 bp->mac_addr[5] = (u8) reg;
7587
7588 bp->tx_ring_size = MAX_TX_DESC_CNT;
7589 bnx2_set_rx_ring_size(bp, 255);
7590
7591 bp->rx_csum = 1;
7592
7593 bp->tx_quick_cons_trip_int = 20;
7594 bp->tx_quick_cons_trip = 20;
7595 bp->tx_ticks_int = 80;
7596 bp->tx_ticks = 80;
7597
7598 bp->rx_quick_cons_trip_int = 6;
7599 bp->rx_quick_cons_trip = 6;
7600 bp->rx_ticks_int = 18;
7601 bp->rx_ticks = 18;
7602
7603 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7604
7605 bp->current_interval = BNX2_TIMER_INTERVAL;
7606
7607 bp->phy_addr = 1;
7608
7609 /* Disable WOL support if we are running on a SERDES chip. */
7610 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7611 bnx2_get_5709_media(bp);
7612 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
7613 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7614
7615 bp->phy_port = PORT_TP;
7616 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
7617 bp->phy_port = PORT_FIBRE;
7618 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
7619 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
7620 bp->flags |= BNX2_FLAG_NO_WOL;
7621 bp->wol = 0;
7622 }
7623 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7624 /* Don't do parallel detect on this board because of
7625 * some board problems. The link will not go down
7626 * if we do parallel detect.
7627 */
7628 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7629 pdev->subsystem_device == 0x310c)
7630 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7631 } else {
7632 bp->phy_addr = 2;
7633 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
7634 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
7635 }
7636 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7637 CHIP_NUM(bp) == CHIP_NUM_5708)
7638 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
7639 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7640 (CHIP_REV(bp) == CHIP_REV_Ax ||
7641 CHIP_REV(bp) == CHIP_REV_Bx))
7642 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
7643
7644 bnx2_init_fw_cap(bp);
7645
7646 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7647 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
7648 (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
7649 !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
7650 bp->flags |= BNX2_FLAG_NO_WOL;
7651 bp->wol = 0;
7652 }
7653
7654 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7655 bp->tx_quick_cons_trip_int =
7656 bp->tx_quick_cons_trip;
7657 bp->tx_ticks_int = bp->tx_ticks;
7658 bp->rx_quick_cons_trip_int =
7659 bp->rx_quick_cons_trip;
7660 bp->rx_ticks_int = bp->rx_ticks;
7661 bp->comp_prod_trip_int = bp->comp_prod_trip;
7662 bp->com_ticks_int = bp->com_ticks;
7663 bp->cmd_ticks_int = bp->cmd_ticks;
7664 }
7665
7666 /* Disable MSI on 5706 if AMD 8132 bridge is found.
7667 *
7668 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
7669 * with byte enables disabled on the unused 32-bit word. This is legal
7670 * but causes problems on the AMD 8132 which will eventually stop
7671 * responding after a while.
7672 *
7673 * AMD believes this incompatibility is unique to the 5706, and
7674 * prefers to locally disable MSI rather than globally disabling it.
7675 */
7676 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7677 struct pci_dev *amd_8132 = NULL;
7678
7679 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7680 PCI_DEVICE_ID_AMD_8132_BRIDGE,
7681 amd_8132))) {
7682
7683 if (amd_8132->revision >= 0x10 &&
7684 amd_8132->revision <= 0x13) {
7685 disable_msi = 1;
7686 pci_dev_put(amd_8132);
7687 break;
7688 }
7689 }
7690 }
7691
7692 bnx2_set_default_link(bp);
7693 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7694
7695 init_timer(&bp->timer);
7696 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
7697 bp->timer.data = (unsigned long) bp;
7698 bp->timer.function = bnx2_timer;
7699
7700 return 0;
7701
7702 err_out_unmap:
7703 if (bp->regview) {
7704 iounmap(bp->regview);
7705 bp->regview = NULL;
7706 }
7707
7708 err_out_release:
7709 pci_release_regions(pdev);
7710
7711 err_out_disable:
7712 pci_disable_device(pdev);
7713 pci_set_drvdata(pdev, NULL);
7714
7715 err_out:
7716 return rc;
7717 }
7718
7719 static char * __devinit
7720 bnx2_bus_string(struct bnx2 *bp, char *str)
7721 {
7722 char *s = str;
7723
7724 if (bp->flags & BNX2_FLAG_PCIE) {
7725 s += sprintf(s, "PCI Express");
7726 } else {
7727 s += sprintf(s, "PCI");
7728 if (bp->flags & BNX2_FLAG_PCIX)
7729 s += sprintf(s, "-X");
7730 if (bp->flags & BNX2_FLAG_PCI_32BIT)
7731 s += sprintf(s, " 32-bit");
7732 else
7733 s += sprintf(s, " 64-bit");
7734 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7735 }
7736 return str;
7737 }
7738
7739 static void __devinit
7740 bnx2_init_napi(struct bnx2 *bp)
7741 {
7742 int i;
7743
7744 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
7745 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
7746 int (*poll)(struct napi_struct *, int);
7747
7748 if (i == 0)
7749 poll = bnx2_poll;
7750 else
7751 poll = bnx2_poll_msix;
7752
7753 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
7754 bnapi->bp = bp;
7755 }
7756 }
7757
7758 static const struct net_device_ops bnx2_netdev_ops = {
7759 .ndo_open = bnx2_open,
7760 .ndo_start_xmit = bnx2_start_xmit,
7761 .ndo_stop = bnx2_close,
7762 .ndo_get_stats = bnx2_get_stats,
7763 .ndo_set_rx_mode = bnx2_set_rx_mode,
7764 .ndo_do_ioctl = bnx2_ioctl,
7765 .ndo_validate_addr = eth_validate_addr,
7766 .ndo_set_mac_address = bnx2_change_mac_addr,
7767 .ndo_change_mtu = bnx2_change_mtu,
7768 .ndo_tx_timeout = bnx2_tx_timeout,
7769 #ifdef BCM_VLAN
7770 .ndo_vlan_rx_register = bnx2_vlan_rx_register,
7771 #endif
7772 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7773 .ndo_poll_controller = poll_bnx2,
7774 #endif
7775 };
7776
7777 static int __devinit
7778 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7779 {
7780 static int version_printed = 0;
7781 struct net_device *dev = NULL;
7782 struct bnx2 *bp;
7783 int rc;
7784 char str[40];
7785
7786 if (version_printed++ == 0)
7787 printk(KERN_INFO "%s", version);
7788
7789 /* dev zeroed in init_etherdev */
7790 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
7791
7792 if (!dev)
7793 return -ENOMEM;
7794
7795 rc = bnx2_init_board(pdev, dev);
7796 if (rc < 0) {
7797 free_netdev(dev);
7798 return rc;
7799 }
7800
7801 dev->netdev_ops = &bnx2_netdev_ops;
7802 dev->watchdog_timeo = TX_TIMEOUT;
7803 dev->ethtool_ops = &bnx2_ethtool_ops;
7804
7805 bp = netdev_priv(dev);
7806 bnx2_init_napi(bp);
7807
7808 pci_set_drvdata(pdev, dev);
7809
7810 memcpy(dev->dev_addr, bp->mac_addr, 6);
7811 memcpy(dev->perm_addr, bp->mac_addr, 6);
7812
7813 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
7814 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7815 dev->features |= NETIF_F_IPV6_CSUM;
7816
7817 #ifdef BCM_VLAN
7818 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7819 #endif
7820 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7821 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7822 dev->features |= NETIF_F_TSO6;
7823
7824 if ((rc = register_netdev(dev))) {
7825 dev_err(&pdev->dev, "Cannot register net device\n");
7826 if (bp->regview)
7827 iounmap(bp->regview);
7828 pci_release_regions(pdev);
7829 pci_disable_device(pdev);
7830 pci_set_drvdata(pdev, NULL);
7831 free_netdev(dev);
7832 return rc;
7833 }
7834
7835 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
7836 "IRQ %d, node addr %pM\n",
7837 dev->name,
7838 board_info[ent->driver_data].name,
7839 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7840 ((CHIP_ID(bp) & 0x0ff0) >> 4),
7841 bnx2_bus_string(bp, str),
7842 dev->base_addr,
7843 bp->pdev->irq, dev->dev_addr);
7844
7845 return 0;
7846 }
7847
7848 static void __devexit
7849 bnx2_remove_one(struct pci_dev *pdev)
7850 {
7851 struct net_device *dev = pci_get_drvdata(pdev);
7852 struct bnx2 *bp = netdev_priv(dev);
7853
7854 flush_scheduled_work();
7855
7856 unregister_netdev(dev);
7857
7858 if (bp->regview)
7859 iounmap(bp->regview);
7860
7861 free_netdev(dev);
7862 pci_release_regions(pdev);
7863 pci_disable_device(pdev);
7864 pci_set_drvdata(pdev, NULL);
7865 }
7866
7867 static int
7868 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
7869 {
7870 struct net_device *dev = pci_get_drvdata(pdev);
7871 struct bnx2 *bp = netdev_priv(dev);
7872
7873 /* PCI register 4 needs to be saved whether netif_running() or not.
7874 * MSI address and data need to be saved if using MSI and
7875 * netif_running().
7876 */
7877 pci_save_state(pdev);
7878 if (!netif_running(dev))
7879 return 0;
7880
7881 flush_scheduled_work();
7882 bnx2_netif_stop(bp);
7883 netif_device_detach(dev);
7884 del_timer_sync(&bp->timer);
7885 bnx2_shutdown_chip(bp);
7886 bnx2_free_skbs(bp);
7887 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
7888 return 0;
7889 }
7890
7891 static int
7892 bnx2_resume(struct pci_dev *pdev)
7893 {
7894 struct net_device *dev = pci_get_drvdata(pdev);
7895 struct bnx2 *bp = netdev_priv(dev);
7896
7897 pci_restore_state(pdev);
7898 if (!netif_running(dev))
7899 return 0;
7900
7901 bnx2_set_power_state(bp, PCI_D0);
7902 netif_device_attach(dev);
7903 bnx2_init_nic(bp, 1);
7904 bnx2_netif_start(bp);
7905 return 0;
7906 }
7907
7908 /**
7909 * bnx2_io_error_detected - called when PCI error is detected
7910 * @pdev: Pointer to PCI device
7911 * @state: The current pci connection state
7912 *
7913 * This function is called after a PCI bus error affecting
7914 * this device has been detected.
7915 */
7916 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
7917 pci_channel_state_t state)
7918 {
7919 struct net_device *dev = pci_get_drvdata(pdev);
7920 struct bnx2 *bp = netdev_priv(dev);
7921
7922 rtnl_lock();
7923 netif_device_detach(dev);
7924
7925 if (netif_running(dev)) {
7926 bnx2_netif_stop(bp);
7927 del_timer_sync(&bp->timer);
7928 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
7929 }
7930
7931 pci_disable_device(pdev);
7932 rtnl_unlock();
7933
7934 /* Request a slot slot reset. */
7935 return PCI_ERS_RESULT_NEED_RESET;
7936 }
7937
7938 /**
7939 * bnx2_io_slot_reset - called after the pci bus has been reset.
7940 * @pdev: Pointer to PCI device
7941 *
7942 * Restart the card from scratch, as if from a cold-boot.
7943 */
7944 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
7945 {
7946 struct net_device *dev = pci_get_drvdata(pdev);
7947 struct bnx2 *bp = netdev_priv(dev);
7948
7949 rtnl_lock();
7950 if (pci_enable_device(pdev)) {
7951 dev_err(&pdev->dev,
7952 "Cannot re-enable PCI device after reset.\n");
7953 rtnl_unlock();
7954 return PCI_ERS_RESULT_DISCONNECT;
7955 }
7956 pci_set_master(pdev);
7957 pci_restore_state(pdev);
7958
7959 if (netif_running(dev)) {
7960 bnx2_set_power_state(bp, PCI_D0);
7961 bnx2_init_nic(bp, 1);
7962 }
7963
7964 rtnl_unlock();
7965 return PCI_ERS_RESULT_RECOVERED;
7966 }
7967
7968 /**
7969 * bnx2_io_resume - called when traffic can start flowing again.
7970 * @pdev: Pointer to PCI device
7971 *
7972 * This callback is called when the error recovery driver tells us that
7973 * its OK to resume normal operation.
7974 */
7975 static void bnx2_io_resume(struct pci_dev *pdev)
7976 {
7977 struct net_device *dev = pci_get_drvdata(pdev);
7978 struct bnx2 *bp = netdev_priv(dev);
7979
7980 rtnl_lock();
7981 if (netif_running(dev))
7982 bnx2_netif_start(bp);
7983
7984 netif_device_attach(dev);
7985 rtnl_unlock();
7986 }
7987
7988 static struct pci_error_handlers bnx2_err_handler = {
7989 .error_detected = bnx2_io_error_detected,
7990 .slot_reset = bnx2_io_slot_reset,
7991 .resume = bnx2_io_resume,
7992 };
7993
7994 static struct pci_driver bnx2_pci_driver = {
7995 .name = DRV_MODULE_NAME,
7996 .id_table = bnx2_pci_tbl,
7997 .probe = bnx2_init_one,
7998 .remove = __devexit_p(bnx2_remove_one),
7999 .suspend = bnx2_suspend,
8000 .resume = bnx2_resume,
8001 .err_handler = &bnx2_err_handler,
8002 };
8003
8004 static int __init bnx2_init(void)
8005 {
8006 return pci_register_driver(&bnx2_pci_driver);
8007 }
8008
8009 static void __exit bnx2_cleanup(void)
8010 {
8011 pci_unregister_driver(&bnx2_pci_driver);
8012 }
8013
8014 module_init(bnx2_init);
8015 module_exit(bnx2_cleanup);
8016
8017
8018
x86 "subsystem" repository