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[libata] PCI ID table cleanup in various drivers
[linux-2.6/x86.git] / drivers / ata / sata_nv.c
blobd09d20a177908642aa944255bbae25e047341eeb
1 /*
2 * sata_nv.c - NVIDIA nForce SATA
3 *
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 * No hardware documentation available outside of NVIDIA.
27 * This driver programs the NVIDIA SATA controller in a similar
28 * fashion as with other PCI IDE BMDMA controllers, with a few
29 * NV-specific details such as register offsets, SATA phy location,
30 * hotplug info, etc.
31 *
32 */
33
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <linux/libata.h>
44
45 #define DRV_NAME "sata_nv"
46 #define DRV_VERSION "2.0"
47
48 enum {
49 NV_PORTS = 2,
50 NV_PIO_MASK = 0x1f,
51 NV_MWDMA_MASK = 0x07,
52 NV_UDMA_MASK = 0x7f,
53 NV_PORT0_SCR_REG_OFFSET = 0x00,
54 NV_PORT1_SCR_REG_OFFSET = 0x40,
55
56 /* INT_STATUS/ENABLE */
57 NV_INT_STATUS = 0x10,
58 NV_INT_ENABLE = 0x11,
59 NV_INT_STATUS_CK804 = 0x440,
60 NV_INT_ENABLE_CK804 = 0x441,
61
62 /* INT_STATUS/ENABLE bits */
63 NV_INT_DEV = 0x01,
64 NV_INT_PM = 0x02,
65 NV_INT_ADDED = 0x04,
66 NV_INT_REMOVED = 0x08,
67
68 NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */
69
70 NV_INT_ALL = 0x0f,
71 NV_INT_MASK = NV_INT_DEV |
72 NV_INT_ADDED | NV_INT_REMOVED,
73
74 /* INT_CONFIG */
75 NV_INT_CONFIG = 0x12,
76 NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
77
78 // For PCI config register 20
79 NV_MCP_SATA_CFG_20 = 0x50,
80 NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
81 };
82
83 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
84 static void nv_ck804_host_stop(struct ata_host *host);
85 static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance,
86 struct pt_regs *regs);
87 static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance,
88 struct pt_regs *regs);
89 static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance,
90 struct pt_regs *regs);
91 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
92 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
93
94 static void nv_nf2_freeze(struct ata_port *ap);
95 static void nv_nf2_thaw(struct ata_port *ap);
96 static void nv_ck804_freeze(struct ata_port *ap);
97 static void nv_ck804_thaw(struct ata_port *ap);
98 static void nv_error_handler(struct ata_port *ap);
99
100 enum nv_host_type
101 {
102 GENERIC,
103 NFORCE2,
104 NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */
105 CK804
106 };
107
108 static const struct pci_device_id nv_pci_tbl[] = {
109 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), NFORCE2 },
110 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), NFORCE3 },
111 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), NFORCE3 },
112 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA), CK804 },
113 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 },
114 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 },
115 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 },
116 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), GENERIC },
117 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), GENERIC },
118 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), GENERIC },
119 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), GENERIC },
120 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC },
121 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC },
122 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC },
123 { PCI_VDEVICE(NVIDIA, 0x045c), GENERIC },
124 { PCI_VDEVICE(NVIDIA, 0x045d), GENERIC },
125 { PCI_VDEVICE(NVIDIA, 0x045e), GENERIC },
126 { PCI_VDEVICE(NVIDIA, 0x045f), GENERIC },
127 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
128 PCI_ANY_ID, PCI_ANY_ID,
129 PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
130 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
131 PCI_ANY_ID, PCI_ANY_ID,
132 PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
133
134 { } /* terminate list */
135 };
136
137 static struct pci_driver nv_pci_driver = {
138 .name = DRV_NAME,
139 .id_table = nv_pci_tbl,
140 .probe = nv_init_one,
141 .remove = ata_pci_remove_one,
142 };
143
144 static struct scsi_host_template nv_sht = {
145 .module = THIS_MODULE,
146 .name = DRV_NAME,
147 .ioctl = ata_scsi_ioctl,
148 .queuecommand = ata_scsi_queuecmd,
149 .can_queue = ATA_DEF_QUEUE,
150 .this_id = ATA_SHT_THIS_ID,
151 .sg_tablesize = LIBATA_MAX_PRD,
152 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
153 .emulated = ATA_SHT_EMULATED,
154 .use_clustering = ATA_SHT_USE_CLUSTERING,
155 .proc_name = DRV_NAME,
156 .dma_boundary = ATA_DMA_BOUNDARY,
157 .slave_configure = ata_scsi_slave_config,
158 .slave_destroy = ata_scsi_slave_destroy,
159 .bios_param = ata_std_bios_param,
160 };
161
162 static const struct ata_port_operations nv_generic_ops = {
163 .port_disable = ata_port_disable,
164 .tf_load = ata_tf_load,
165 .tf_read = ata_tf_read,
166 .exec_command = ata_exec_command,
167 .check_status = ata_check_status,
168 .dev_select = ata_std_dev_select,
169 .bmdma_setup = ata_bmdma_setup,
170 .bmdma_start = ata_bmdma_start,
171 .bmdma_stop = ata_bmdma_stop,
172 .bmdma_status = ata_bmdma_status,
173 .qc_prep = ata_qc_prep,
174 .qc_issue = ata_qc_issue_prot,
175 .freeze = ata_bmdma_freeze,
176 .thaw = ata_bmdma_thaw,
177 .error_handler = nv_error_handler,
178 .post_internal_cmd = ata_bmdma_post_internal_cmd,
179 .data_xfer = ata_pio_data_xfer,
180 .irq_handler = nv_generic_interrupt,
181 .irq_clear = ata_bmdma_irq_clear,
182 .scr_read = nv_scr_read,
183 .scr_write = nv_scr_write,
184 .port_start = ata_port_start,
185 .port_stop = ata_port_stop,
186 .host_stop = ata_pci_host_stop,
187 };
188
189 static const struct ata_port_operations nv_nf2_ops = {
190 .port_disable = ata_port_disable,
191 .tf_load = ata_tf_load,
192 .tf_read = ata_tf_read,
193 .exec_command = ata_exec_command,
194 .check_status = ata_check_status,
195 .dev_select = ata_std_dev_select,
196 .bmdma_setup = ata_bmdma_setup,
197 .bmdma_start = ata_bmdma_start,
198 .bmdma_stop = ata_bmdma_stop,
199 .bmdma_status = ata_bmdma_status,
200 .qc_prep = ata_qc_prep,
201 .qc_issue = ata_qc_issue_prot,
202 .freeze = nv_nf2_freeze,
203 .thaw = nv_nf2_thaw,
204 .error_handler = nv_error_handler,
205 .post_internal_cmd = ata_bmdma_post_internal_cmd,
206 .data_xfer = ata_pio_data_xfer,
207 .irq_handler = nv_nf2_interrupt,
208 .irq_clear = ata_bmdma_irq_clear,
209 .scr_read = nv_scr_read,
210 .scr_write = nv_scr_write,
211 .port_start = ata_port_start,
212 .port_stop = ata_port_stop,
213 .host_stop = ata_pci_host_stop,
214 };
215
216 static const struct ata_port_operations nv_ck804_ops = {
217 .port_disable = ata_port_disable,
218 .tf_load = ata_tf_load,
219 .tf_read = ata_tf_read,
220 .exec_command = ata_exec_command,
221 .check_status = ata_check_status,
222 .dev_select = ata_std_dev_select,
223 .bmdma_setup = ata_bmdma_setup,
224 .bmdma_start = ata_bmdma_start,
225 .bmdma_stop = ata_bmdma_stop,
226 .bmdma_status = ata_bmdma_status,
227 .qc_prep = ata_qc_prep,
228 .qc_issue = ata_qc_issue_prot,
229 .freeze = nv_ck804_freeze,
230 .thaw = nv_ck804_thaw,
231 .error_handler = nv_error_handler,
232 .post_internal_cmd = ata_bmdma_post_internal_cmd,
233 .data_xfer = ata_pio_data_xfer,
234 .irq_handler = nv_ck804_interrupt,
235 .irq_clear = ata_bmdma_irq_clear,
236 .scr_read = nv_scr_read,
237 .scr_write = nv_scr_write,
238 .port_start = ata_port_start,
239 .port_stop = ata_port_stop,
240 .host_stop = nv_ck804_host_stop,
241 };
242
243 static struct ata_port_info nv_port_info[] = {
244 /* generic */
245 {
246 .sht = &nv_sht,
247 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
248 .pio_mask = NV_PIO_MASK,
249 .mwdma_mask = NV_MWDMA_MASK,
250 .udma_mask = NV_UDMA_MASK,
251 .port_ops = &nv_generic_ops,
252 },
253 /* nforce2/3 */
254 {
255 .sht = &nv_sht,
256 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
257 .pio_mask = NV_PIO_MASK,
258 .mwdma_mask = NV_MWDMA_MASK,
259 .udma_mask = NV_UDMA_MASK,
260 .port_ops = &nv_nf2_ops,
261 },
262 /* ck804 */
263 {
264 .sht = &nv_sht,
265 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
266 .pio_mask = NV_PIO_MASK,
267 .mwdma_mask = NV_MWDMA_MASK,
268 .udma_mask = NV_UDMA_MASK,
269 .port_ops = &nv_ck804_ops,
270 },
271 };
272
273 MODULE_AUTHOR("NVIDIA");
274 MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
275 MODULE_LICENSE("GPL");
276 MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
277 MODULE_VERSION(DRV_VERSION);
278
279 static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance,
280 struct pt_regs *regs)
281 {
282 struct ata_host *host = dev_instance;
283 unsigned int i;
284 unsigned int handled = 0;
285 unsigned long flags;
286
287 spin_lock_irqsave(&host->lock, flags);
288
289 for (i = 0; i < host->n_ports; i++) {
290 struct ata_port *ap;
291
292 ap = host->ports[i];
293 if (ap &&
294 !(ap->flags & ATA_FLAG_DISABLED)) {
295 struct ata_queued_cmd *qc;
296
297 qc = ata_qc_from_tag(ap, ap->active_tag);
298 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
299 handled += ata_host_intr(ap, qc);
300 else
301 // No request pending? Clear interrupt status
302 // anyway, in case there's one pending.
303 ap->ops->check_status(ap);
304 }
305
306 }
307
308 spin_unlock_irqrestore(&host->lock, flags);
309
310 return IRQ_RETVAL(handled);
311 }
312
313 static int nv_host_intr(struct ata_port *ap, u8 irq_stat)
314 {
315 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
316 int handled;
317
318 /* freeze if hotplugged */
319 if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) {
320 ata_port_freeze(ap);
321 return 1;
322 }
323
324 /* bail out if not our interrupt */
325 if (!(irq_stat & NV_INT_DEV))
326 return 0;
327
328 /* DEV interrupt w/ no active qc? */
329 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
330 ata_check_status(ap);
331 return 1;
332 }
333
334 /* handle interrupt */
335 handled = ata_host_intr(ap, qc);
336 if (unlikely(!handled)) {
337 /* spurious, clear it */
338 ata_check_status(ap);
339 }
340
341 return 1;
342 }
343
344 static irqreturn_t nv_do_interrupt(struct ata_host *host, u8 irq_stat)
345 {
346 int i, handled = 0;
347
348 for (i = 0; i < host->n_ports; i++) {
349 struct ata_port *ap = host->ports[i];
350
351 if (ap && !(ap->flags & ATA_FLAG_DISABLED))
352 handled += nv_host_intr(ap, irq_stat);
353
354 irq_stat >>= NV_INT_PORT_SHIFT;
355 }
356
357 return IRQ_RETVAL(handled);
358 }
359
360 static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance,
361 struct pt_regs *regs)
362 {
363 struct ata_host *host = dev_instance;
364 u8 irq_stat;
365 irqreturn_t ret;
366
367 spin_lock(&host->lock);
368 irq_stat = inb(host->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
369 ret = nv_do_interrupt(host, irq_stat);
370 spin_unlock(&host->lock);
371
372 return ret;
373 }
374
375 static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance,
376 struct pt_regs *regs)
377 {
378 struct ata_host *host = dev_instance;
379 u8 irq_stat;
380 irqreturn_t ret;
381
382 spin_lock(&host->lock);
383 irq_stat = readb(host->mmio_base + NV_INT_STATUS_CK804);
384 ret = nv_do_interrupt(host, irq_stat);
385 spin_unlock(&host->lock);
386
387 return ret;
388 }
389
390 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
391 {
392 if (sc_reg > SCR_CONTROL)
393 return 0xffffffffU;
394
395 return ioread32((void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
396 }
397
398 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
399 {
400 if (sc_reg > SCR_CONTROL)
401 return;
402
403 iowrite32(val, (void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
404 }
405
406 static void nv_nf2_freeze(struct ata_port *ap)
407 {
408 unsigned long scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
409 int shift = ap->port_no * NV_INT_PORT_SHIFT;
410 u8 mask;
411
412 mask = inb(scr_addr + NV_INT_ENABLE);
413 mask &= ~(NV_INT_ALL << shift);
414 outb(mask, scr_addr + NV_INT_ENABLE);
415 }
416
417 static void nv_nf2_thaw(struct ata_port *ap)
418 {
419 unsigned long scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
420 int shift = ap->port_no * NV_INT_PORT_SHIFT;
421 u8 mask;
422
423 outb(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS);
424
425 mask = inb(scr_addr + NV_INT_ENABLE);
426 mask |= (NV_INT_MASK << shift);
427 outb(mask, scr_addr + NV_INT_ENABLE);
428 }
429
430 static void nv_ck804_freeze(struct ata_port *ap)
431 {
432 void __iomem *mmio_base = ap->host->mmio_base;
433 int shift = ap->port_no * NV_INT_PORT_SHIFT;
434 u8 mask;
435
436 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
437 mask &= ~(NV_INT_ALL << shift);
438 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
439 }
440
441 static void nv_ck804_thaw(struct ata_port *ap)
442 {
443 void __iomem *mmio_base = ap->host->mmio_base;
444 int shift = ap->port_no * NV_INT_PORT_SHIFT;
445 u8 mask;
446
447 writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804);
448
449 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
450 mask |= (NV_INT_MASK << shift);
451 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
452 }
453
454 static int nv_hardreset(struct ata_port *ap, unsigned int *class)
455 {
456 unsigned int dummy;
457
458 /* SATA hardreset fails to retrieve proper device signature on
459 * some controllers. Don't classify on hardreset. For more
460 * info, see http://bugme.osdl.org/show_bug.cgi?id=3352
461 */
462 return sata_std_hardreset(ap, &dummy);
463 }
464
465 static void nv_error_handler(struct ata_port *ap)
466 {
467 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
468 nv_hardreset, ata_std_postreset);
469 }
470
471 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
472 {
473 static int printed_version = 0;
474 struct ata_port_info *ppi[2];
475 struct ata_probe_ent *probe_ent;
476 int pci_dev_busy = 0;
477 int rc;
478 u32 bar;
479 unsigned long base;
480
481 // Make sure this is a SATA controller by counting the number of bars
482 // (NVIDIA SATA controllers will always have six bars). Otherwise,
483 // it's an IDE controller and we ignore it.
484 for (bar=0; bar<6; bar++)
485 if (pci_resource_start(pdev, bar) == 0)
486 return -ENODEV;
487
488 if (!printed_version++)
489 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
490
491 rc = pci_enable_device(pdev);
492 if (rc)
493 goto err_out;
494
495 rc = pci_request_regions(pdev, DRV_NAME);
496 if (rc) {
497 pci_dev_busy = 1;
498 goto err_out_disable;
499 }
500
501 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
502 if (rc)
503 goto err_out_regions;
504 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
505 if (rc)
506 goto err_out_regions;
507
508 rc = -ENOMEM;
509
510 ppi[0] = ppi[1] = &nv_port_info[ent->driver_data];
511 probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
512 if (!probe_ent)
513 goto err_out_regions;
514
515 probe_ent->mmio_base = pci_iomap(pdev, 5, 0);
516 if (!probe_ent->mmio_base) {
517 rc = -EIO;
518 goto err_out_free_ent;
519 }
520
521 base = (unsigned long)probe_ent->mmio_base;
522
523 probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
524 probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
525
526 /* enable SATA space for CK804 */
527 if (ent->driver_data == CK804) {
528 u8 regval;
529
530 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
531 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
532 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
533 }
534
535 pci_set_master(pdev);
536
537 rc = ata_device_add(probe_ent);
538 if (rc != NV_PORTS)
539 goto err_out_iounmap;
540
541 kfree(probe_ent);
542
543 return 0;
544
545 err_out_iounmap:
546 pci_iounmap(pdev, probe_ent->mmio_base);
547 err_out_free_ent:
548 kfree(probe_ent);
549 err_out_regions:
550 pci_release_regions(pdev);
551 err_out_disable:
552 if (!pci_dev_busy)
553 pci_disable_device(pdev);
554 err_out:
555 return rc;
556 }
557
558 static void nv_ck804_host_stop(struct ata_host *host)
559 {
560 struct pci_dev *pdev = to_pci_dev(host->dev);
561 u8 regval;
562
563 /* disable SATA space for CK804 */
564 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
565 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
566 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
567
568 ata_pci_host_stop(host);
569 }
570
571 static int __init nv_init(void)
572 {
573 return pci_register_driver(&nv_pci_driver);
574 }
575
576 static void __exit nv_exit(void)
577 {
578 pci_unregister_driver(&nv_pci_driver);
579 }
580
581 module_init(nv_init);
582 module_exit(nv_exit);
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