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drm: fix EDID parser problem with positive/negative hsync/vsync
[linux-2.6/x86.git] / drivers / scsi / qla2xxx / qla_sup.c
blob284827926effc096155dd3e755a2348fb03631d6
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/delay.h>
10 #include <linux/vmalloc.h>
11 #include <asm/uaccess.h>
12
13 /*
14 * NVRAM support routines
15 */
16
17 /**
18 * qla2x00_lock_nvram_access() -
19 * @ha: HA context
20 */
21 static void
22 qla2x00_lock_nvram_access(struct qla_hw_data *ha)
23 {
24 uint16_t data;
25 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
26
27 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
28 data = RD_REG_WORD(&reg->nvram);
29 while (data & NVR_BUSY) {
30 udelay(100);
31 data = RD_REG_WORD(&reg->nvram);
32 }
33
34 /* Lock resource */
35 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
36 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
37 udelay(5);
38 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
39 while ((data & BIT_0) == 0) {
40 /* Lock failed */
41 udelay(100);
42 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
43 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
44 udelay(5);
45 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
46 }
47 }
48 }
49
50 /**
51 * qla2x00_unlock_nvram_access() -
52 * @ha: HA context
53 */
54 static void
55 qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
56 {
57 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
58
59 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
60 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
61 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
62 }
63 }
64
65 /**
66 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
67 * @ha: HA context
68 * @data: Serial interface selector
69 */
70 static void
71 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
72 {
73 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
74
75 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
76 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
77 NVRAM_DELAY();
78 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_CLOCK |
79 NVR_WRT_ENABLE);
80 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
81 NVRAM_DELAY();
82 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
83 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
84 NVRAM_DELAY();
85 }
86
87 /**
88 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
89 * NVRAM.
90 * @ha: HA context
91 * @nv_cmd: NVRAM command
92 *
93 * Bit definitions for NVRAM command:
94 *
95 * Bit 26 = start bit
96 * Bit 25, 24 = opcode
97 * Bit 23-16 = address
98 * Bit 15-0 = write data
99 *
100 * Returns the word read from nvram @addr.
101 */
102 static uint16_t
103 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
104 {
105 uint8_t cnt;
106 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
107 uint16_t data = 0;
108 uint16_t reg_data;
109
110 /* Send command to NVRAM. */
111 nv_cmd <<= 5;
112 for (cnt = 0; cnt < 11; cnt++) {
113 if (nv_cmd & BIT_31)
114 qla2x00_nv_write(ha, NVR_DATA_OUT);
115 else
116 qla2x00_nv_write(ha, 0);
117 nv_cmd <<= 1;
118 }
119
120 /* Read data from NVRAM. */
121 for (cnt = 0; cnt < 16; cnt++) {
122 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
123 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
124 NVRAM_DELAY();
125 data <<= 1;
126 reg_data = RD_REG_WORD(&reg->nvram);
127 if (reg_data & NVR_DATA_IN)
128 data |= BIT_0;
129 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
130 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
131 NVRAM_DELAY();
132 }
133
134 /* Deselect chip. */
135 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
136 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
137 NVRAM_DELAY();
138
139 return data;
140 }
141
142
143 /**
144 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
145 * request routine to get the word from NVRAM.
146 * @ha: HA context
147 * @addr: Address in NVRAM to read
148 *
149 * Returns the word read from nvram @addr.
150 */
151 static uint16_t
152 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
153 {
154 uint16_t data;
155 uint32_t nv_cmd;
156
157 nv_cmd = addr << 16;
158 nv_cmd |= NV_READ_OP;
159 data = qla2x00_nvram_request(ha, nv_cmd);
160
161 return (data);
162 }
163
164 /**
165 * qla2x00_nv_deselect() - Deselect NVRAM operations.
166 * @ha: HA context
167 */
168 static void
169 qla2x00_nv_deselect(struct qla_hw_data *ha)
170 {
171 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
172
173 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
174 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
175 NVRAM_DELAY();
176 }
177
178 /**
179 * qla2x00_write_nvram_word() - Write NVRAM data.
180 * @ha: HA context
181 * @addr: Address in NVRAM to write
182 * @data: word to program
183 */
184 static void
185 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
186 {
187 int count;
188 uint16_t word;
189 uint32_t nv_cmd, wait_cnt;
190 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
191
192 qla2x00_nv_write(ha, NVR_DATA_OUT);
193 qla2x00_nv_write(ha, 0);
194 qla2x00_nv_write(ha, 0);
195
196 for (word = 0; word < 8; word++)
197 qla2x00_nv_write(ha, NVR_DATA_OUT);
198
199 qla2x00_nv_deselect(ha);
200
201 /* Write data */
202 nv_cmd = (addr << 16) | NV_WRITE_OP;
203 nv_cmd |= data;
204 nv_cmd <<= 5;
205 for (count = 0; count < 27; count++) {
206 if (nv_cmd & BIT_31)
207 qla2x00_nv_write(ha, NVR_DATA_OUT);
208 else
209 qla2x00_nv_write(ha, 0);
210
211 nv_cmd <<= 1;
212 }
213
214 qla2x00_nv_deselect(ha);
215
216 /* Wait for NVRAM to become ready */
217 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
218 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
219 wait_cnt = NVR_WAIT_CNT;
220 do {
221 if (!--wait_cnt) {
222 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
223 __func__, vha->host_no));
224 break;
225 }
226 NVRAM_DELAY();
227 word = RD_REG_WORD(&reg->nvram);
228 } while ((word & NVR_DATA_IN) == 0);
229
230 qla2x00_nv_deselect(ha);
231
232 /* Disable writes */
233 qla2x00_nv_write(ha, NVR_DATA_OUT);
234 for (count = 0; count < 10; count++)
235 qla2x00_nv_write(ha, 0);
236
237 qla2x00_nv_deselect(ha);
238 }
239
240 static int
241 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
242 uint16_t data, uint32_t tmo)
243 {
244 int ret, count;
245 uint16_t word;
246 uint32_t nv_cmd;
247 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
248
249 ret = QLA_SUCCESS;
250
251 qla2x00_nv_write(ha, NVR_DATA_OUT);
252 qla2x00_nv_write(ha, 0);
253 qla2x00_nv_write(ha, 0);
254
255 for (word = 0; word < 8; word++)
256 qla2x00_nv_write(ha, NVR_DATA_OUT);
257
258 qla2x00_nv_deselect(ha);
259
260 /* Write data */
261 nv_cmd = (addr << 16) | NV_WRITE_OP;
262 nv_cmd |= data;
263 nv_cmd <<= 5;
264 for (count = 0; count < 27; count++) {
265 if (nv_cmd & BIT_31)
266 qla2x00_nv_write(ha, NVR_DATA_OUT);
267 else
268 qla2x00_nv_write(ha, 0);
269
270 nv_cmd <<= 1;
271 }
272
273 qla2x00_nv_deselect(ha);
274
275 /* Wait for NVRAM to become ready */
276 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
277 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
278 do {
279 NVRAM_DELAY();
280 word = RD_REG_WORD(&reg->nvram);
281 if (!--tmo) {
282 ret = QLA_FUNCTION_FAILED;
283 break;
284 }
285 } while ((word & NVR_DATA_IN) == 0);
286
287 qla2x00_nv_deselect(ha);
288
289 /* Disable writes */
290 qla2x00_nv_write(ha, NVR_DATA_OUT);
291 for (count = 0; count < 10; count++)
292 qla2x00_nv_write(ha, 0);
293
294 qla2x00_nv_deselect(ha);
295
296 return ret;
297 }
298
299 /**
300 * qla2x00_clear_nvram_protection() -
301 * @ha: HA context
302 */
303 static int
304 qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
305 {
306 int ret, stat;
307 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
308 uint32_t word, wait_cnt;
309 uint16_t wprot, wprot_old;
310
311 /* Clear NVRAM write protection. */
312 ret = QLA_FUNCTION_FAILED;
313
314 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
315 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
316 __constant_cpu_to_le16(0x1234), 100000);
317 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
318 if (stat != QLA_SUCCESS || wprot != 0x1234) {
319 /* Write enable. */
320 qla2x00_nv_write(ha, NVR_DATA_OUT);
321 qla2x00_nv_write(ha, 0);
322 qla2x00_nv_write(ha, 0);
323 for (word = 0; word < 8; word++)
324 qla2x00_nv_write(ha, NVR_DATA_OUT);
325
326 qla2x00_nv_deselect(ha);
327
328 /* Enable protection register. */
329 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
330 qla2x00_nv_write(ha, NVR_PR_ENABLE);
331 qla2x00_nv_write(ha, NVR_PR_ENABLE);
332 for (word = 0; word < 8; word++)
333 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
334
335 qla2x00_nv_deselect(ha);
336
337 /* Clear protection register (ffff is cleared). */
338 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
339 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
340 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
341 for (word = 0; word < 8; word++)
342 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
343
344 qla2x00_nv_deselect(ha);
345
346 /* Wait for NVRAM to become ready. */
347 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
348 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
349 wait_cnt = NVR_WAIT_CNT;
350 do {
351 if (!--wait_cnt) {
352 DEBUG9_10(qla_printk(
353 "NVRAM didn't go ready...\n"));
354 break;
355 }
356 NVRAM_DELAY();
357 word = RD_REG_WORD(&reg->nvram);
358 } while ((word & NVR_DATA_IN) == 0);
359
360 if (wait_cnt)
361 ret = QLA_SUCCESS;
362 } else
363 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
364
365 return ret;
366 }
367
368 static void
369 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
370 {
371 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
372 uint32_t word, wait_cnt;
373
374 if (stat != QLA_SUCCESS)
375 return;
376
377 /* Set NVRAM write protection. */
378 /* Write enable. */
379 qla2x00_nv_write(ha, NVR_DATA_OUT);
380 qla2x00_nv_write(ha, 0);
381 qla2x00_nv_write(ha, 0);
382 for (word = 0; word < 8; word++)
383 qla2x00_nv_write(ha, NVR_DATA_OUT);
384
385 qla2x00_nv_deselect(ha);
386
387 /* Enable protection register. */
388 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
389 qla2x00_nv_write(ha, NVR_PR_ENABLE);
390 qla2x00_nv_write(ha, NVR_PR_ENABLE);
391 for (word = 0; word < 8; word++)
392 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
393
394 qla2x00_nv_deselect(ha);
395
396 /* Enable protection register. */
397 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
398 qla2x00_nv_write(ha, NVR_PR_ENABLE);
399 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
400 for (word = 0; word < 8; word++)
401 qla2x00_nv_write(ha, NVR_PR_ENABLE);
402
403 qla2x00_nv_deselect(ha);
404
405 /* Wait for NVRAM to become ready. */
406 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
407 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
408 wait_cnt = NVR_WAIT_CNT;
409 do {
410 if (!--wait_cnt) {
411 DEBUG9_10(qla_printk("NVRAM didn't go ready...\n"));
412 break;
413 }
414 NVRAM_DELAY();
415 word = RD_REG_WORD(&reg->nvram);
416 } while ((word & NVR_DATA_IN) == 0);
417 }
418
419
420 /*****************************************************************************/
421 /* Flash Manipulation Routines */
422 /*****************************************************************************/
423
424 #define OPTROM_BURST_SIZE 0x1000
425 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
426
427 static inline uint32_t
428 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
429 {
430 return ha->flash_conf_off | faddr;
431 }
432
433 static inline uint32_t
434 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
435 {
436 return ha->flash_data_off | faddr;
437 }
438
439 static inline uint32_t
440 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
441 {
442 return ha->nvram_conf_off | naddr;
443 }
444
445 static inline uint32_t
446 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
447 {
448 return ha->nvram_data_off | naddr;
449 }
450
451 static uint32_t
452 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
453 {
454 int rval;
455 uint32_t cnt, data;
456 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
457
458 WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
459 /* Wait for READ cycle to complete. */
460 rval = QLA_SUCCESS;
461 for (cnt = 3000;
462 (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
463 rval == QLA_SUCCESS; cnt--) {
464 if (cnt)
465 udelay(10);
466 else
467 rval = QLA_FUNCTION_TIMEOUT;
468 cond_resched();
469 }
470
471 /* TODO: What happens if we time out? */
472 data = 0xDEADDEAD;
473 if (rval == QLA_SUCCESS)
474 data = RD_REG_DWORD(&reg->flash_data);
475
476 return data;
477 }
478
479 uint32_t *
480 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
481 uint32_t dwords)
482 {
483 uint32_t i;
484 struct qla_hw_data *ha = vha->hw;
485
486 /* Dword reads to flash. */
487 for (i = 0; i < dwords; i++, faddr++)
488 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
489 flash_data_addr(ha, faddr)));
490
491 return dwptr;
492 }
493
494 static int
495 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
496 {
497 int rval;
498 uint32_t cnt;
499 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
500
501 WRT_REG_DWORD(&reg->flash_data, data);
502 RD_REG_DWORD(&reg->flash_data); /* PCI Posting. */
503 WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
504 /* Wait for Write cycle to complete. */
505 rval = QLA_SUCCESS;
506 for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
507 rval == QLA_SUCCESS; cnt--) {
508 if (cnt)
509 udelay(10);
510 else
511 rval = QLA_FUNCTION_TIMEOUT;
512 cond_resched();
513 }
514 return rval;
515 }
516
517 static void
518 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
519 uint8_t *flash_id)
520 {
521 uint32_t ids;
522
523 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
524 *man_id = LSB(ids);
525 *flash_id = MSB(ids);
526
527 /* Check if man_id and flash_id are valid. */
528 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
529 /* Read information using 0x9f opcode
530 * Device ID, Mfg ID would be read in the format:
531 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
532 * Example: ATMEL 0x00 01 45 1F
533 * Extract MFG and Dev ID from last two bytes.
534 */
535 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
536 *man_id = LSB(ids);
537 *flash_id = MSB(ids);
538 }
539 }
540
541 static int
542 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
543 {
544 const char *loc, *locations[] = { "DEF", "PCI" };
545 uint32_t pcihdr, pcids;
546 uint32_t *dcode;
547 uint8_t *buf, *bcode, last_image;
548 uint16_t cnt, chksum, *wptr;
549 struct qla_flt_location *fltl;
550 struct qla_hw_data *ha = vha->hw;
551 struct req_que *req = ha->req_q_map[0];
552
553 /*
554 * FLT-location structure resides after the last PCI region.
555 */
556
557 /* Begin with sane defaults. */
558 loc = locations[0];
559 *start = 0;
560 if (IS_QLA24XX_TYPE(ha))
561 *start = FA_FLASH_LAYOUT_ADDR_24;
562 else if (IS_QLA25XX(ha))
563 *start = FA_FLASH_LAYOUT_ADDR;
564 else if (IS_QLA81XX(ha))
565 *start = FA_FLASH_LAYOUT_ADDR_81;
566 /* Begin with first PCI expansion ROM header. */
567 buf = (uint8_t *)req->ring;
568 dcode = (uint32_t *)req->ring;
569 pcihdr = 0;
570 last_image = 1;
571 do {
572 /* Verify PCI expansion ROM header. */
573 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
574 bcode = buf + (pcihdr % 4);
575 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
576 goto end;
577
578 /* Locate PCI data structure. */
579 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
580 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
581 bcode = buf + (pcihdr % 4);
582
583 /* Validate signature of PCI data structure. */
584 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
585 bcode[0x2] != 'I' || bcode[0x3] != 'R')
586 goto end;
587
588 last_image = bcode[0x15] & BIT_7;
589
590 /* Locate next PCI expansion ROM. */
591 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
592 } while (!last_image);
593
594 /* Now verify FLT-location structure. */
595 fltl = (struct qla_flt_location *)req->ring;
596 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
597 sizeof(struct qla_flt_location) >> 2);
598 if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
599 fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
600 goto end;
601
602 wptr = (uint16_t *)req->ring;
603 cnt = sizeof(struct qla_flt_location) >> 1;
604 for (chksum = 0; cnt; cnt--)
605 chksum += le16_to_cpu(*wptr++);
606 if (chksum) {
607 qla_printk(KERN_ERR, ha,
608 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
609 qla2x00_dump_buffer(buf, sizeof(struct qla_flt_location));
610 return QLA_FUNCTION_FAILED;
611 }
612
613 /* Good data. Use specified location. */
614 loc = locations[1];
615 *start = le16_to_cpu(fltl->start_hi) << 16 |
616 le16_to_cpu(fltl->start_lo);
617 end:
618 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
619 return QLA_SUCCESS;
620 }
621
622 static void
623 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
624 {
625 const char *loc, *locations[] = { "DEF", "FLT" };
626 const uint32_t def_fw[] =
627 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
628 const uint32_t def_boot[] =
629 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
630 const uint32_t def_vpd_nvram[] =
631 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
632 const uint32_t def_fdt[] =
633 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
634 FA_FLASH_DESCR_ADDR_81 };
635 const uint32_t def_npiv_conf0[] =
636 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
637 FA_NPIV_CONF0_ADDR_81 };
638 const uint32_t def_npiv_conf1[] =
639 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
640 FA_NPIV_CONF1_ADDR_81 };
641 uint32_t def;
642 uint16_t *wptr;
643 uint16_t cnt, chksum;
644 uint32_t start;
645 struct qla_flt_header *flt;
646 struct qla_flt_region *region;
647 struct qla_hw_data *ha = vha->hw;
648 struct req_que *req = ha->req_q_map[0];
649
650 ha->flt_region_flt = flt_addr;
651 wptr = (uint16_t *)req->ring;
652 flt = (struct qla_flt_header *)req->ring;
653 region = (struct qla_flt_region *)&flt[1];
654 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
655 flt_addr << 2, OPTROM_BURST_SIZE);
656 if (*wptr == __constant_cpu_to_le16(0xffff))
657 goto no_flash_data;
658 if (flt->version != __constant_cpu_to_le16(1)) {
659 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported FLT detected: "
660 "version=0x%x length=0x%x checksum=0x%x.\n",
661 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
662 le16_to_cpu(flt->checksum)));
663 goto no_flash_data;
664 }
665
666 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
667 for (chksum = 0; cnt; cnt--)
668 chksum += le16_to_cpu(*wptr++);
669 if (chksum) {
670 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
671 "version=0x%x length=0x%x checksum=0x%x.\n",
672 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
673 chksum));
674 goto no_flash_data;
675 }
676
677 loc = locations[1];
678 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
679 for ( ; cnt; cnt--, region++) {
680 /* Store addresses as DWORD offsets. */
681 start = le32_to_cpu(region->start) >> 2;
682
683 DEBUG3(qla_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
684 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
685 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
686
687 switch (le32_to_cpu(region->code) & 0xff) {
688 case FLT_REG_FW:
689 ha->flt_region_fw = start;
690 break;
691 case FLT_REG_BOOT_CODE:
692 ha->flt_region_boot = start;
693 break;
694 case FLT_REG_VPD_0:
695 ha->flt_region_vpd_nvram = start;
696 break;
697 case FLT_REG_FDT:
698 ha->flt_region_fdt = start;
699 break;
700 case FLT_REG_NPIV_CONF_0:
701 if (!(PCI_FUNC(ha->pdev->devfn) & 1))
702 ha->flt_region_npiv_conf = start;
703 break;
704 case FLT_REG_NPIV_CONF_1:
705 if (PCI_FUNC(ha->pdev->devfn) & 1)
706 ha->flt_region_npiv_conf = start;
707 break;
708 }
709 }
710 goto done;
711
712 no_flash_data:
713 /* Use hardcoded defaults. */
714 loc = locations[0];
715 def = 0;
716 if (IS_QLA24XX_TYPE(ha))
717 def = 0;
718 else if (IS_QLA25XX(ha))
719 def = 1;
720 else if (IS_QLA81XX(ha))
721 def = 2;
722 ha->flt_region_fw = def_fw[def];
723 ha->flt_region_boot = def_boot[def];
724 ha->flt_region_vpd_nvram = def_vpd_nvram[def];
725 ha->flt_region_fdt = def_fdt[def];
726 ha->flt_region_npiv_conf = !(PCI_FUNC(ha->pdev->devfn) & 1) ?
727 def_npiv_conf0[def]: def_npiv_conf1[def];
728 done:
729 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x "
730 "vpd_nvram=0x%x fdt=0x%x flt=0x%x npiv=0x%x.\n", loc,
731 ha->flt_region_boot, ha->flt_region_fw, ha->flt_region_vpd_nvram,
732 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf));
733 }
734
735 static void
736 qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
737 {
738 #define FLASH_BLK_SIZE_4K 0x1000
739 #define FLASH_BLK_SIZE_32K 0x8000
740 #define FLASH_BLK_SIZE_64K 0x10000
741 const char *loc, *locations[] = { "MID", "FDT" };
742 uint16_t cnt, chksum;
743 uint16_t *wptr;
744 struct qla_fdt_layout *fdt;
745 uint8_t man_id, flash_id;
746 uint16_t mid, fid;
747 struct qla_hw_data *ha = vha->hw;
748 struct req_que *req = ha->req_q_map[0];
749
750 wptr = (uint16_t *)req->ring;
751 fdt = (struct qla_fdt_layout *)req->ring;
752 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
753 ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
754 if (*wptr == __constant_cpu_to_le16(0xffff))
755 goto no_flash_data;
756 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
757 fdt->sig[3] != 'D')
758 goto no_flash_data;
759
760 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
761 cnt++)
762 chksum += le16_to_cpu(*wptr++);
763 if (chksum) {
764 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
765 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
766 le16_to_cpu(fdt->version)));
767 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt)));
768 goto no_flash_data;
769 }
770
771 loc = locations[1];
772 mid = le16_to_cpu(fdt->man_id);
773 fid = le16_to_cpu(fdt->id);
774 ha->fdt_wrt_disable = fdt->wrt_disable_bits;
775 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
776 ha->fdt_block_size = le32_to_cpu(fdt->block_size);
777 if (fdt->unprotect_sec_cmd) {
778 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
779 fdt->unprotect_sec_cmd);
780 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
781 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
782 flash_conf_addr(ha, 0x0336);
783 }
784 goto done;
785 no_flash_data:
786 loc = locations[0];
787 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
788 mid = man_id;
789 fid = flash_id;
790 ha->fdt_wrt_disable = 0x9c;
791 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
792 switch (man_id) {
793 case 0xbf: /* STT flash. */
794 if (flash_id == 0x8e)
795 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
796 else
797 ha->fdt_block_size = FLASH_BLK_SIZE_32K;
798
799 if (flash_id == 0x80)
800 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
801 break;
802 case 0x13: /* ST M25P80. */
803 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
804 break;
805 case 0x1f: /* Atmel 26DF081A. */
806 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
807 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
808 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
809 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
810 break;
811 default:
812 /* Default to 64 kb sector size. */
813 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
814 break;
815 }
816 done:
817 DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
818 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
819 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
820 ha->fdt_unprotect_sec_cmd, ha->fdt_wrt_disable,
821 ha->fdt_block_size));
822 }
823
824 int
825 qla2xxx_get_flash_info(scsi_qla_host_t *vha)
826 {
827 int ret;
828 uint32_t flt_addr;
829 struct qla_hw_data *ha = vha->hw;
830
831 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
832 return QLA_SUCCESS;
833
834 ret = qla2xxx_find_flt_start(vha, &flt_addr);
835 if (ret != QLA_SUCCESS)
836 return ret;
837
838 qla2xxx_get_flt_info(vha, flt_addr);
839 qla2xxx_get_fdt_info(vha);
840
841 return QLA_SUCCESS;
842 }
843
844 void
845 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
846 {
847 #define NPIV_CONFIG_SIZE (16*1024)
848 void *data;
849 uint16_t *wptr;
850 uint16_t cnt, chksum;
851 int i;
852 struct qla_npiv_header hdr;
853 struct qla_npiv_entry *entry;
854 struct qla_hw_data *ha = vha->hw;
855
856 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
857 return;
858
859 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
860 ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
861 if (hdr.version == __constant_cpu_to_le16(0xffff))
862 return;
863 if (hdr.version != __constant_cpu_to_le16(1)) {
864 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported NPIV-Config "
865 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
866 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
867 le16_to_cpu(hdr.checksum)));
868 return;
869 }
870
871 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
872 if (!data) {
873 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV-Config: Unable to "
874 "allocate memory.\n"));
875 return;
876 }
877
878 ha->isp_ops->read_optrom(vha, (uint8_t *)data,
879 ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
880
881 cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
882 sizeof(struct qla_npiv_entry)) >> 1;
883 for (wptr = data, chksum = 0; cnt; cnt--)
884 chksum += le16_to_cpu(*wptr++);
885 if (chksum) {
886 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent NPIV-Config "
887 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
888 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
889 chksum));
890 goto done;
891 }
892
893 entry = data + sizeof(struct qla_npiv_header);
894 cnt = le16_to_cpu(hdr.entries);
895 for (i = 0; cnt; cnt--, entry++, i++) {
896 uint16_t flags;
897 struct fc_vport_identifiers vid;
898 struct fc_vport *vport;
899
900 flags = le16_to_cpu(entry->flags);
901 if (flags == 0xffff)
902 continue;
903 if ((flags & BIT_0) == 0)
904 continue;
905
906 memset(&vid, 0, sizeof(vid));
907 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
908 vid.vport_type = FC_PORTTYPE_NPIV;
909 vid.disable = false;
910 vid.port_name = wwn_to_u64(entry->port_name);
911 vid.node_name = wwn_to_u64(entry->node_name);
912
913 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
914
915 DEBUG2(qla_printk(KERN_DEBUG, ha, "NPIV[%02x]: wwpn=%llx "
916 "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
917 vid.port_name, vid.node_name, le16_to_cpu(entry->vf_id),
918 entry->q_qos, entry->f_qos));
919
920 if (i < QLA_PRECONFIG_VPORTS) {
921 vport = fc_vport_create(vha->host, 0, &vid);
922 if (!vport)
923 qla_printk(KERN_INFO, ha,
924 "NPIV-Config: Failed to create vport [%02x]: "
925 "wwpn=%llx wwnn=%llx.\n", cnt,
926 vid.port_name, vid.node_name);
927 }
928 }
929 done:
930 kfree(data);
931 ha->npiv_info = NULL;
932 }
933
934 static void
935 qla24xx_unprotect_flash(struct qla_hw_data *ha)
936 {
937 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
938
939 /* Enable flash write. */
940 WRT_REG_DWORD(&reg->ctrl_status,
941 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
942 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
943
944 if (!ha->fdt_wrt_disable)
945 return;
946
947 /* Disable flash write-protection, first clear SR protection bit */
948 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
949 /* Then write zero again to clear remaining SR bits.*/
950 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
951 }
952
953 static void
954 qla24xx_protect_flash(struct qla_hw_data *ha)
955 {
956 uint32_t cnt;
957 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
958
959 if (!ha->fdt_wrt_disable)
960 goto skip_wrt_protect;
961
962 /* Enable flash write-protection and wait for completion. */
963 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
964 ha->fdt_wrt_disable);
965 for (cnt = 300; cnt &&
966 qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
967 cnt--) {
968 udelay(10);
969 }
970
971 skip_wrt_protect:
972 /* Disable flash write. */
973 WRT_REG_DWORD(&reg->ctrl_status,
974 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
975 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
976 }
977
978 static int
979 qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
980 uint32_t dwords)
981 {
982 int ret;
983 uint32_t liter;
984 uint32_t sec_mask, rest_addr;
985 uint32_t fdata;
986 dma_addr_t optrom_dma;
987 void *optrom = NULL;
988 struct qla_hw_data *ha = vha->hw;
989
990 ret = QLA_SUCCESS;
991
992 /* Prepare burst-capable write on supported ISPs. */
993 if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && !(faddr & 0xfff) &&
994 dwords > OPTROM_BURST_DWORDS) {
995 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
996 &optrom_dma, GFP_KERNEL);
997 if (!optrom) {
998 qla_printk(KERN_DEBUG, ha,
999 "Unable to allocate memory for optrom burst write "
1000 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
1001 }
1002 }
1003
1004 rest_addr = (ha->fdt_block_size >> 2) - 1;
1005 sec_mask = ~rest_addr;
1006
1007 qla24xx_unprotect_flash(ha);
1008
1009 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
1010 fdata = (faddr & sec_mask) << 2;
1011
1012 /* Are we at the beginning of a sector? */
1013 if ((faddr & rest_addr) == 0) {
1014 /* Do sector unprotect. */
1015 if (ha->fdt_unprotect_sec_cmd)
1016 qla24xx_write_flash_dword(ha,
1017 ha->fdt_unprotect_sec_cmd,
1018 (fdata & 0xff00) | ((fdata << 16) &
1019 0xff0000) | ((fdata >> 16) & 0xff));
1020 ret = qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1021 (fdata & 0xff00) |((fdata << 16) &
1022 0xff0000) | ((fdata >> 16) & 0xff));
1023 if (ret != QLA_SUCCESS) {
1024 DEBUG9(qla_printk("Unable to erase sector: "
1025 "address=%x.\n", faddr));
1026 break;
1027 }
1028 }
1029
1030 /* Go with burst-write. */
1031 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
1032 /* Copy data to DMA'ble buffer. */
1033 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
1034
1035 ret = qla2x00_load_ram(vha, optrom_dma,
1036 flash_data_addr(ha, faddr),
1037 OPTROM_BURST_DWORDS);
1038 if (ret != QLA_SUCCESS) {
1039 qla_printk(KERN_WARNING, ha,
1040 "Unable to burst-write optrom segment "
1041 "(%x/%x/%llx).\n", ret,
1042 flash_data_addr(ha, faddr),
1043 (unsigned long long)optrom_dma);
1044 qla_printk(KERN_WARNING, ha,
1045 "Reverting to slow-write.\n");
1046
1047 dma_free_coherent(&ha->pdev->dev,
1048 OPTROM_BURST_SIZE, optrom, optrom_dma);
1049 optrom = NULL;
1050 } else {
1051 liter += OPTROM_BURST_DWORDS - 1;
1052 faddr += OPTROM_BURST_DWORDS - 1;
1053 dwptr += OPTROM_BURST_DWORDS - 1;
1054 continue;
1055 }
1056 }
1057
1058 ret = qla24xx_write_flash_dword(ha,
1059 flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
1060 if (ret != QLA_SUCCESS) {
1061 DEBUG9(printk("%s(%ld) Unable to program flash "
1062 "address=%x data=%x.\n", __func__,
1063 vha->host_no, faddr, *dwptr));
1064 break;
1065 }
1066
1067 /* Do sector protect. */
1068 if (ha->fdt_unprotect_sec_cmd &&
1069 ((faddr & rest_addr) == rest_addr))
1070 qla24xx_write_flash_dword(ha,
1071 ha->fdt_protect_sec_cmd,
1072 (fdata & 0xff00) | ((fdata << 16) &
1073 0xff0000) | ((fdata >> 16) & 0xff));
1074 }
1075
1076 qla24xx_protect_flash(ha);
1077
1078 if (optrom)
1079 dma_free_coherent(&ha->pdev->dev,
1080 OPTROM_BURST_SIZE, optrom, optrom_dma);
1081
1082 return ret;
1083 }
1084
1085 uint8_t *
1086 qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1087 uint32_t bytes)
1088 {
1089 uint32_t i;
1090 uint16_t *wptr;
1091 struct qla_hw_data *ha = vha->hw;
1092
1093 /* Word reads to NVRAM via registers. */
1094 wptr = (uint16_t *)buf;
1095 qla2x00_lock_nvram_access(ha);
1096 for (i = 0; i < bytes >> 1; i++, naddr++)
1097 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1098 naddr));
1099 qla2x00_unlock_nvram_access(ha);
1100
1101 return buf;
1102 }
1103
1104 uint8_t *
1105 qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1106 uint32_t bytes)
1107 {
1108 uint32_t i;
1109 uint32_t *dwptr;
1110 struct qla_hw_data *ha = vha->hw;
1111
1112 /* Dword reads to flash. */
1113 dwptr = (uint32_t *)buf;
1114 for (i = 0; i < bytes >> 2; i++, naddr++)
1115 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1116 nvram_data_addr(ha, naddr)));
1117
1118 return buf;
1119 }
1120
1121 int
1122 qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1123 uint32_t bytes)
1124 {
1125 int ret, stat;
1126 uint32_t i;
1127 uint16_t *wptr;
1128 unsigned long flags;
1129 struct qla_hw_data *ha = vha->hw;
1130
1131 ret = QLA_SUCCESS;
1132
1133 spin_lock_irqsave(&ha->hardware_lock, flags);
1134 qla2x00_lock_nvram_access(ha);
1135
1136 /* Disable NVRAM write-protection. */
1137 stat = qla2x00_clear_nvram_protection(ha);
1138
1139 wptr = (uint16_t *)buf;
1140 for (i = 0; i < bytes >> 1; i++, naddr++) {
1141 qla2x00_write_nvram_word(ha, naddr,
1142 cpu_to_le16(*wptr));
1143 wptr++;
1144 }
1145
1146 /* Enable NVRAM write-protection. */
1147 qla2x00_set_nvram_protection(ha, stat);
1148
1149 qla2x00_unlock_nvram_access(ha);
1150 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1151
1152 return ret;
1153 }
1154
1155 int
1156 qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1157 uint32_t bytes)
1158 {
1159 int ret;
1160 uint32_t i;
1161 uint32_t *dwptr;
1162 struct qla_hw_data *ha = vha->hw;
1163 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1164
1165 ret = QLA_SUCCESS;
1166
1167 /* Enable flash write. */
1168 WRT_REG_DWORD(&reg->ctrl_status,
1169 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1170 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1171
1172 /* Disable NVRAM write-protection. */
1173 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1174 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1175
1176 /* Dword writes to flash. */
1177 dwptr = (uint32_t *)buf;
1178 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1179 ret = qla24xx_write_flash_dword(ha,
1180 nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
1181 if (ret != QLA_SUCCESS) {
1182 DEBUG9(qla_printk("Unable to program nvram address=%x "
1183 "data=%x.\n", naddr, *dwptr));
1184 break;
1185 }
1186 }
1187
1188 /* Enable NVRAM write-protection. */
1189 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
1190
1191 /* Disable flash write. */
1192 WRT_REG_DWORD(&reg->ctrl_status,
1193 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1194 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1195
1196 return ret;
1197 }
1198
1199 uint8_t *
1200 qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1201 uint32_t bytes)
1202 {
1203 uint32_t i;
1204 uint32_t *dwptr;
1205 struct qla_hw_data *ha = vha->hw;
1206
1207 /* Dword reads to flash. */
1208 dwptr = (uint32_t *)buf;
1209 for (i = 0; i < bytes >> 2; i++, naddr++)
1210 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1211 flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
1212
1213 return buf;
1214 }
1215
1216 int
1217 qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1218 uint32_t bytes)
1219 {
1220 struct qla_hw_data *ha = vha->hw;
1221 #define RMW_BUFFER_SIZE (64 * 1024)
1222 uint8_t *dbuf;
1223
1224 dbuf = vmalloc(RMW_BUFFER_SIZE);
1225 if (!dbuf)
1226 return QLA_MEMORY_ALLOC_FAILED;
1227 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1228 RMW_BUFFER_SIZE);
1229 memcpy(dbuf + (naddr << 2), buf, bytes);
1230 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1231 RMW_BUFFER_SIZE);
1232 vfree(dbuf);
1233
1234 return QLA_SUCCESS;
1235 }
1236
1237 static inline void
1238 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1239 {
1240 if (IS_QLA2322(ha)) {
1241 /* Flip all colors. */
1242 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1243 /* Turn off. */
1244 ha->beacon_color_state = 0;
1245 *pflags = GPIO_LED_ALL_OFF;
1246 } else {
1247 /* Turn on. */
1248 ha->beacon_color_state = QLA_LED_ALL_ON;
1249 *pflags = GPIO_LED_RGA_ON;
1250 }
1251 } else {
1252 /* Flip green led only. */
1253 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1254 /* Turn off. */
1255 ha->beacon_color_state = 0;
1256 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1257 } else {
1258 /* Turn on. */
1259 ha->beacon_color_state = QLA_LED_GRN_ON;
1260 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1261 }
1262 }
1263 }
1264
1265 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1266
1267 void
1268 qla2x00_beacon_blink(struct scsi_qla_host *vha)
1269 {
1270 uint16_t gpio_enable;
1271 uint16_t gpio_data;
1272 uint16_t led_color = 0;
1273 unsigned long flags;
1274 struct qla_hw_data *ha = vha->hw;
1275 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1276
1277 spin_lock_irqsave(&ha->hardware_lock, flags);
1278
1279 /* Save the Original GPIOE. */
1280 if (ha->pio_address) {
1281 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1282 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1283 } else {
1284 gpio_enable = RD_REG_WORD(&reg->gpioe);
1285 gpio_data = RD_REG_WORD(&reg->gpiod);
1286 }
1287
1288 /* Set the modified gpio_enable values */
1289 gpio_enable |= GPIO_LED_MASK;
1290
1291 if (ha->pio_address) {
1292 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1293 } else {
1294 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1295 RD_REG_WORD(&reg->gpioe);
1296 }
1297
1298 qla2x00_flip_colors(ha, &led_color);
1299
1300 /* Clear out any previously set LED color. */
1301 gpio_data &= ~GPIO_LED_MASK;
1302
1303 /* Set the new input LED color to GPIOD. */
1304 gpio_data |= led_color;
1305
1306 /* Set the modified gpio_data values */
1307 if (ha->pio_address) {
1308 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1309 } else {
1310 WRT_REG_WORD(&reg->gpiod, gpio_data);
1311 RD_REG_WORD(&reg->gpiod);
1312 }
1313
1314 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1315 }
1316
1317 int
1318 qla2x00_beacon_on(struct scsi_qla_host *vha)
1319 {
1320 uint16_t gpio_enable;
1321 uint16_t gpio_data;
1322 unsigned long flags;
1323 struct qla_hw_data *ha = vha->hw;
1324 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1325
1326 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1327 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1328
1329 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1330 qla_printk(KERN_WARNING, ha,
1331 "Unable to update fw options (beacon on).\n");
1332 return QLA_FUNCTION_FAILED;
1333 }
1334
1335 /* Turn off LEDs. */
1336 spin_lock_irqsave(&ha->hardware_lock, flags);
1337 if (ha->pio_address) {
1338 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1339 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1340 } else {
1341 gpio_enable = RD_REG_WORD(&reg->gpioe);
1342 gpio_data = RD_REG_WORD(&reg->gpiod);
1343 }
1344 gpio_enable |= GPIO_LED_MASK;
1345
1346 /* Set the modified gpio_enable values. */
1347 if (ha->pio_address) {
1348 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1349 } else {
1350 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1351 RD_REG_WORD(&reg->gpioe);
1352 }
1353
1354 /* Clear out previously set LED colour. */
1355 gpio_data &= ~GPIO_LED_MASK;
1356 if (ha->pio_address) {
1357 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1358 } else {
1359 WRT_REG_WORD(&reg->gpiod, gpio_data);
1360 RD_REG_WORD(&reg->gpiod);
1361 }
1362 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1363
1364 /*
1365 * Let the per HBA timer kick off the blinking process based on
1366 * the following flags. No need to do anything else now.
1367 */
1368 ha->beacon_blink_led = 1;
1369 ha->beacon_color_state = 0;
1370
1371 return QLA_SUCCESS;
1372 }
1373
1374 int
1375 qla2x00_beacon_off(struct scsi_qla_host *vha)
1376 {
1377 int rval = QLA_SUCCESS;
1378 struct qla_hw_data *ha = vha->hw;
1379
1380 ha->beacon_blink_led = 0;
1381
1382 /* Set the on flag so when it gets flipped it will be off. */
1383 if (IS_QLA2322(ha))
1384 ha->beacon_color_state = QLA_LED_ALL_ON;
1385 else
1386 ha->beacon_color_state = QLA_LED_GRN_ON;
1387
1388 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
1389
1390 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1391 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1392
1393 rval = qla2x00_set_fw_options(vha, ha->fw_options);
1394 if (rval != QLA_SUCCESS)
1395 qla_printk(KERN_WARNING, ha,
1396 "Unable to update fw options (beacon off).\n");
1397 return rval;
1398 }
1399
1400
1401 static inline void
1402 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1403 {
1404 /* Flip all colors. */
1405 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1406 /* Turn off. */
1407 ha->beacon_color_state = 0;
1408 *pflags = 0;
1409 } else {
1410 /* Turn on. */
1411 ha->beacon_color_state = QLA_LED_ALL_ON;
1412 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1413 }
1414 }
1415
1416 void
1417 qla24xx_beacon_blink(struct scsi_qla_host *vha)
1418 {
1419 uint16_t led_color = 0;
1420 uint32_t gpio_data;
1421 unsigned long flags;
1422 struct qla_hw_data *ha = vha->hw;
1423 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1424
1425 /* Save the Original GPIOD. */
1426 spin_lock_irqsave(&ha->hardware_lock, flags);
1427 gpio_data = RD_REG_DWORD(&reg->gpiod);
1428
1429 /* Enable the gpio_data reg for update. */
1430 gpio_data |= GPDX_LED_UPDATE_MASK;
1431
1432 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1433 gpio_data = RD_REG_DWORD(&reg->gpiod);
1434
1435 /* Set the color bits. */
1436 qla24xx_flip_colors(ha, &led_color);
1437
1438 /* Clear out any previously set LED color. */
1439 gpio_data &= ~GPDX_LED_COLOR_MASK;
1440
1441 /* Set the new input LED color to GPIOD. */
1442 gpio_data |= led_color;
1443
1444 /* Set the modified gpio_data values. */
1445 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1446 gpio_data = RD_REG_DWORD(&reg->gpiod);
1447 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1448 }
1449
1450 int
1451 qla24xx_beacon_on(struct scsi_qla_host *vha)
1452 {
1453 uint32_t gpio_data;
1454 unsigned long flags;
1455 struct qla_hw_data *ha = vha->hw;
1456 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1457
1458 if (ha->beacon_blink_led == 0) {
1459 /* Enable firmware for update */
1460 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1461
1462 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
1463 return QLA_FUNCTION_FAILED;
1464
1465 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
1466 QLA_SUCCESS) {
1467 qla_printk(KERN_WARNING, ha,
1468 "Unable to update fw options (beacon on).\n");
1469 return QLA_FUNCTION_FAILED;
1470 }
1471
1472 spin_lock_irqsave(&ha->hardware_lock, flags);
1473 gpio_data = RD_REG_DWORD(&reg->gpiod);
1474
1475 /* Enable the gpio_data reg for update. */
1476 gpio_data |= GPDX_LED_UPDATE_MASK;
1477 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1478 RD_REG_DWORD(&reg->gpiod);
1479
1480 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1481 }
1482
1483 /* So all colors blink together. */
1484 ha->beacon_color_state = 0;
1485
1486 /* Let the per HBA timer kick off the blinking process. */
1487 ha->beacon_blink_led = 1;
1488
1489 return QLA_SUCCESS;
1490 }
1491
1492 int
1493 qla24xx_beacon_off(struct scsi_qla_host *vha)
1494 {
1495 uint32_t gpio_data;
1496 unsigned long flags;
1497 struct qla_hw_data *ha = vha->hw;
1498 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1499
1500 ha->beacon_blink_led = 0;
1501 ha->beacon_color_state = QLA_LED_ALL_ON;
1502
1503 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
1504
1505 /* Give control back to firmware. */
1506 spin_lock_irqsave(&ha->hardware_lock, flags);
1507 gpio_data = RD_REG_DWORD(&reg->gpiod);
1508
1509 /* Disable the gpio_data reg for update. */
1510 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1511 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1512 RD_REG_DWORD(&reg->gpiod);
1513 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1514
1515 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1516
1517 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1518 qla_printk(KERN_WARNING, ha,
1519 "Unable to update fw options (beacon off).\n");
1520 return QLA_FUNCTION_FAILED;
1521 }
1522
1523 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1524 qla_printk(KERN_WARNING, ha,
1525 "Unable to get fw options (beacon off).\n");
1526 return QLA_FUNCTION_FAILED;
1527 }
1528
1529 return QLA_SUCCESS;
1530 }
1531
1532
1533 /*
1534 * Flash support routines
1535 */
1536
1537 /**
1538 * qla2x00_flash_enable() - Setup flash for reading and writing.
1539 * @ha: HA context
1540 */
1541 static void
1542 qla2x00_flash_enable(struct qla_hw_data *ha)
1543 {
1544 uint16_t data;
1545 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1546
1547 data = RD_REG_WORD(&reg->ctrl_status);
1548 data |= CSR_FLASH_ENABLE;
1549 WRT_REG_WORD(&reg->ctrl_status, data);
1550 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1551 }
1552
1553 /**
1554 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1555 * @ha: HA context
1556 */
1557 static void
1558 qla2x00_flash_disable(struct qla_hw_data *ha)
1559 {
1560 uint16_t data;
1561 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1562
1563 data = RD_REG_WORD(&reg->ctrl_status);
1564 data &= ~(CSR_FLASH_ENABLE);
1565 WRT_REG_WORD(&reg->ctrl_status, data);
1566 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1567 }
1568
1569 /**
1570 * qla2x00_read_flash_byte() - Reads a byte from flash
1571 * @ha: HA context
1572 * @addr: Address in flash to read
1573 *
1574 * A word is read from the chip, but, only the lower byte is valid.
1575 *
1576 * Returns the byte read from flash @addr.
1577 */
1578 static uint8_t
1579 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
1580 {
1581 uint16_t data;
1582 uint16_t bank_select;
1583 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1584
1585 bank_select = RD_REG_WORD(&reg->ctrl_status);
1586
1587 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1588 /* Specify 64K address range: */
1589 /* clear out Module Select and Flash Address bits [19:16]. */
1590 bank_select &= ~0xf8;
1591 bank_select |= addr >> 12 & 0xf0;
1592 bank_select |= CSR_FLASH_64K_BANK;
1593 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1594 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1595
1596 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1597 data = RD_REG_WORD(&reg->flash_data);
1598
1599 return (uint8_t)data;
1600 }
1601
1602 /* Setup bit 16 of flash address. */
1603 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1604 bank_select |= CSR_FLASH_64K_BANK;
1605 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1606 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1607 } else if (((addr & BIT_16) == 0) &&
1608 (bank_select & CSR_FLASH_64K_BANK)) {
1609 bank_select &= ~(CSR_FLASH_64K_BANK);
1610 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1611 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1612 }
1613
1614 /* Always perform IO mapped accesses to the FLASH registers. */
1615 if (ha->pio_address) {
1616 uint16_t data2;
1617
1618 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1619 do {
1620 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1621 barrier();
1622 cpu_relax();
1623 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1624 } while (data != data2);
1625 } else {
1626 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1627 data = qla2x00_debounce_register(&reg->flash_data);
1628 }
1629
1630 return (uint8_t)data;
1631 }
1632
1633 /**
1634 * qla2x00_write_flash_byte() - Write a byte to flash
1635 * @ha: HA context
1636 * @addr: Address in flash to write
1637 * @data: Data to write
1638 */
1639 static void
1640 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
1641 {
1642 uint16_t bank_select;
1643 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1644
1645 bank_select = RD_REG_WORD(&reg->ctrl_status);
1646 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1647 /* Specify 64K address range: */
1648 /* clear out Module Select and Flash Address bits [19:16]. */
1649 bank_select &= ~0xf8;
1650 bank_select |= addr >> 12 & 0xf0;
1651 bank_select |= CSR_FLASH_64K_BANK;
1652 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1653 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1654
1655 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1656 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1657 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1658 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1659
1660 return;
1661 }
1662
1663 /* Setup bit 16 of flash address. */
1664 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1665 bank_select |= CSR_FLASH_64K_BANK;
1666 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1667 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1668 } else if (((addr & BIT_16) == 0) &&
1669 (bank_select & CSR_FLASH_64K_BANK)) {
1670 bank_select &= ~(CSR_FLASH_64K_BANK);
1671 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1672 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1673 }
1674
1675 /* Always perform IO mapped accesses to the FLASH registers. */
1676 if (ha->pio_address) {
1677 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1678 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
1679 } else {
1680 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1681 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1682 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1683 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1684 }
1685 }
1686
1687 /**
1688 * qla2x00_poll_flash() - Polls flash for completion.
1689 * @ha: HA context
1690 * @addr: Address in flash to poll
1691 * @poll_data: Data to be polled
1692 * @man_id: Flash manufacturer ID
1693 * @flash_id: Flash ID
1694 *
1695 * This function polls the device until bit 7 of what is read matches data
1696 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
1697 * out (a fatal error). The flash book recommeds reading bit 7 again after
1698 * reading bit 5 as a 1.
1699 *
1700 * Returns 0 on success, else non-zero.
1701 */
1702 static int
1703 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
1704 uint8_t man_id, uint8_t flash_id)
1705 {
1706 int status;
1707 uint8_t flash_data;
1708 uint32_t cnt;
1709
1710 status = 1;
1711
1712 /* Wait for 30 seconds for command to finish. */
1713 poll_data &= BIT_7;
1714 for (cnt = 3000000; cnt; cnt--) {
1715 flash_data = qla2x00_read_flash_byte(ha, addr);
1716 if ((flash_data & BIT_7) == poll_data) {
1717 status = 0;
1718 break;
1719 }
1720
1721 if (man_id != 0x40 && man_id != 0xda) {
1722 if ((flash_data & BIT_5) && cnt > 2)
1723 cnt = 2;
1724 }
1725 udelay(10);
1726 barrier();
1727 cond_resched();
1728 }
1729 return status;
1730 }
1731
1732 /**
1733 * qla2x00_program_flash_address() - Programs a flash address
1734 * @ha: HA context
1735 * @addr: Address in flash to program
1736 * @data: Data to be written in flash
1737 * @man_id: Flash manufacturer ID
1738 * @flash_id: Flash ID
1739 *
1740 * Returns 0 on success, else non-zero.
1741 */
1742 static int
1743 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
1744 uint8_t data, uint8_t man_id, uint8_t flash_id)
1745 {
1746 /* Write Program Command Sequence. */
1747 if (IS_OEM_001(ha)) {
1748 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1749 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1750 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1751 qla2x00_write_flash_byte(ha, addr, data);
1752 } else {
1753 if (man_id == 0xda && flash_id == 0xc1) {
1754 qla2x00_write_flash_byte(ha, addr, data);
1755 if (addr & 0x7e)
1756 return 0;
1757 } else {
1758 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1759 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1760 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1761 qla2x00_write_flash_byte(ha, addr, data);
1762 }
1763 }
1764
1765 udelay(150);
1766
1767 /* Wait for write to complete. */
1768 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1769 }
1770
1771 /**
1772 * qla2x00_erase_flash() - Erase the flash.
1773 * @ha: HA context
1774 * @man_id: Flash manufacturer ID
1775 * @flash_id: Flash ID
1776 *
1777 * Returns 0 on success, else non-zero.
1778 */
1779 static int
1780 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
1781 {
1782 /* Individual Sector Erase Command Sequence */
1783 if (IS_OEM_001(ha)) {
1784 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1785 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1786 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1787 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1788 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1789 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1790 } else {
1791 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1792 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1793 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1794 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1795 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1796 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1797 }
1798
1799 udelay(150);
1800
1801 /* Wait for erase to complete. */
1802 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1803 }
1804
1805 /**
1806 * qla2x00_erase_flash_sector() - Erase a flash sector.
1807 * @ha: HA context
1808 * @addr: Flash sector to erase
1809 * @sec_mask: Sector address mask
1810 * @man_id: Flash manufacturer ID
1811 * @flash_id: Flash ID
1812 *
1813 * Returns 0 on success, else non-zero.
1814 */
1815 static int
1816 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
1817 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1818 {
1819 /* Individual Sector Erase Command Sequence */
1820 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1821 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1822 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1823 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1824 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1825 if (man_id == 0x1f && flash_id == 0x13)
1826 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1827 else
1828 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1829
1830 udelay(150);
1831
1832 /* Wait for erase to complete. */
1833 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1834 }
1835
1836 /**
1837 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1838 * @man_id: Flash manufacturer ID
1839 * @flash_id: Flash ID
1840 */
1841 static void
1842 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
1843 uint8_t *flash_id)
1844 {
1845 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1846 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1847 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1848 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1849 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1850 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1851 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1852 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1853 }
1854
1855 static void
1856 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
1857 uint32_t saddr, uint32_t length)
1858 {
1859 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1860 uint32_t midpoint, ilength;
1861 uint8_t data;
1862
1863 midpoint = length / 2;
1864
1865 WRT_REG_WORD(&reg->nvram, 0);
1866 RD_REG_WORD(&reg->nvram);
1867 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1868 if (ilength == midpoint) {
1869 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1870 RD_REG_WORD(&reg->nvram);
1871 }
1872 data = qla2x00_read_flash_byte(ha, saddr);
1873 if (saddr % 100)
1874 udelay(10);
1875 *tmp_buf = data;
1876 cond_resched();
1877 }
1878 }
1879
1880 static inline void
1881 qla2x00_suspend_hba(struct scsi_qla_host *vha)
1882 {
1883 int cnt;
1884 unsigned long flags;
1885 struct qla_hw_data *ha = vha->hw;
1886 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1887
1888 /* Suspend HBA. */
1889 scsi_block_requests(vha->host);
1890 ha->isp_ops->disable_intrs(ha);
1891 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1892
1893 /* Pause RISC. */
1894 spin_lock_irqsave(&ha->hardware_lock, flags);
1895 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1896 RD_REG_WORD(&reg->hccr);
1897 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1898 for (cnt = 0; cnt < 30000; cnt++) {
1899 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1900 break;
1901 udelay(100);
1902 }
1903 } else {
1904 udelay(10);
1905 }
1906 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1907 }
1908
1909 static inline void
1910 qla2x00_resume_hba(struct scsi_qla_host *vha)
1911 {
1912 struct qla_hw_data *ha = vha->hw;
1913
1914 /* Resume HBA. */
1915 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1916 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1917 qla2xxx_wake_dpc(vha);
1918 qla2x00_wait_for_hba_online(vha);
1919 scsi_unblock_requests(vha->host);
1920 }
1921
1922 uint8_t *
1923 qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
1924 uint32_t offset, uint32_t length)
1925 {
1926 uint32_t addr, midpoint;
1927 uint8_t *data;
1928 struct qla_hw_data *ha = vha->hw;
1929 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1930
1931 /* Suspend HBA. */
1932 qla2x00_suspend_hba(vha);
1933
1934 /* Go with read. */
1935 midpoint = ha->optrom_size / 2;
1936
1937 qla2x00_flash_enable(ha);
1938 WRT_REG_WORD(&reg->nvram, 0);
1939 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
1940 for (addr = offset, data = buf; addr < length; addr++, data++) {
1941 if (addr == midpoint) {
1942 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1943 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
1944 }
1945
1946 *data = qla2x00_read_flash_byte(ha, addr);
1947 }
1948 qla2x00_flash_disable(ha);
1949
1950 /* Resume HBA. */
1951 qla2x00_resume_hba(vha);
1952
1953 return buf;
1954 }
1955
1956 int
1957 qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
1958 uint32_t offset, uint32_t length)
1959 {
1960
1961 int rval;
1962 uint8_t man_id, flash_id, sec_number, data;
1963 uint16_t wd;
1964 uint32_t addr, liter, sec_mask, rest_addr;
1965 struct qla_hw_data *ha = vha->hw;
1966 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1967
1968 /* Suspend HBA. */
1969 qla2x00_suspend_hba(vha);
1970
1971 rval = QLA_SUCCESS;
1972 sec_number = 0;
1973
1974 /* Reset ISP chip. */
1975 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1976 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1977
1978 /* Go with write. */
1979 qla2x00_flash_enable(ha);
1980 do { /* Loop once to provide quick error exit */
1981 /* Structure of flash memory based on manufacturer */
1982 if (IS_OEM_001(ha)) {
1983 /* OEM variant with special flash part. */
1984 man_id = flash_id = 0;
1985 rest_addr = 0xffff;
1986 sec_mask = 0x10000;
1987 goto update_flash;
1988 }
1989 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
1990 switch (man_id) {
1991 case 0x20: /* ST flash. */
1992 if (flash_id == 0xd2 || flash_id == 0xe3) {
1993 /*
1994 * ST m29w008at part - 64kb sector size with
1995 * 32kb,8kb,8kb,16kb sectors at memory address
1996 * 0xf0000.
1997 */
1998 rest_addr = 0xffff;
1999 sec_mask = 0x10000;
2000 break;
2001 }
2002 /*
2003 * ST m29w010b part - 16kb sector size
2004 * Default to 16kb sectors
2005 */
2006 rest_addr = 0x3fff;
2007 sec_mask = 0x1c000;
2008 break;
2009 case 0x40: /* Mostel flash. */
2010 /* Mostel v29c51001 part - 512 byte sector size. */
2011 rest_addr = 0x1ff;
2012 sec_mask = 0x1fe00;
2013 break;
2014 case 0xbf: /* SST flash. */
2015 /* SST39sf10 part - 4kb sector size. */
2016 rest_addr = 0xfff;
2017 sec_mask = 0x1f000;
2018 break;
2019 case 0xda: /* Winbond flash. */
2020 /* Winbond W29EE011 part - 256 byte sector size. */
2021 rest_addr = 0x7f;
2022 sec_mask = 0x1ff80;
2023 break;
2024 case 0xc2: /* Macronix flash. */
2025 /* 64k sector size. */
2026 if (flash_id == 0x38 || flash_id == 0x4f) {
2027 rest_addr = 0xffff;
2028 sec_mask = 0x10000;
2029 break;
2030 }
2031 /* Fall through... */
2032
2033 case 0x1f: /* Atmel flash. */
2034 /* 512k sector size. */
2035 if (flash_id == 0x13) {
2036 rest_addr = 0x7fffffff;
2037 sec_mask = 0x80000000;
2038 break;
2039 }
2040 /* Fall through... */
2041
2042 case 0x01: /* AMD flash. */
2043 if (flash_id == 0x38 || flash_id == 0x40 ||
2044 flash_id == 0x4f) {
2045 /* Am29LV081 part - 64kb sector size. */
2046 /* Am29LV002BT part - 64kb sector size. */
2047 rest_addr = 0xffff;
2048 sec_mask = 0x10000;
2049 break;
2050 } else if (flash_id == 0x3e) {
2051 /*
2052 * Am29LV008b part - 64kb sector size with
2053 * 32kb,8kb,8kb,16kb sector at memory address
2054 * h0xf0000.
2055 */
2056 rest_addr = 0xffff;
2057 sec_mask = 0x10000;
2058 break;
2059 } else if (flash_id == 0x20 || flash_id == 0x6e) {
2060 /*
2061 * Am29LV010 part or AM29f010 - 16kb sector
2062 * size.
2063 */
2064 rest_addr = 0x3fff;
2065 sec_mask = 0x1c000;
2066 break;
2067 } else if (flash_id == 0x6d) {
2068 /* Am29LV001 part - 8kb sector size. */
2069 rest_addr = 0x1fff;
2070 sec_mask = 0x1e000;
2071 break;
2072 }
2073 default:
2074 /* Default to 16 kb sector size. */
2075 rest_addr = 0x3fff;
2076 sec_mask = 0x1c000;
2077 break;
2078 }
2079
2080 update_flash:
2081 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2082 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2083 rval = QLA_FUNCTION_FAILED;
2084 break;
2085 }
2086 }
2087
2088 for (addr = offset, liter = 0; liter < length; liter++,
2089 addr++) {
2090 data = buf[liter];
2091 /* Are we at the beginning of a sector? */
2092 if ((addr & rest_addr) == 0) {
2093 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2094 if (addr >= 0x10000UL) {
2095 if (((addr >> 12) & 0xf0) &&
2096 ((man_id == 0x01 &&
2097 flash_id == 0x3e) ||
2098 (man_id == 0x20 &&
2099 flash_id == 0xd2))) {
2100 sec_number++;
2101 if (sec_number == 1) {
2102 rest_addr =
2103 0x7fff;
2104 sec_mask =
2105 0x18000;
2106 } else if (
2107 sec_number == 2 ||
2108 sec_number == 3) {
2109 rest_addr =
2110 0x1fff;
2111 sec_mask =
2112 0x1e000;
2113 } else if (
2114 sec_number == 4) {
2115 rest_addr =
2116 0x3fff;
2117 sec_mask =
2118 0x1c000;
2119 }
2120 }
2121 }
2122 } else if (addr == ha->optrom_size / 2) {
2123 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2124 RD_REG_WORD(&reg->nvram);
2125 }
2126
2127 if (flash_id == 0xda && man_id == 0xc1) {
2128 qla2x00_write_flash_byte(ha, 0x5555,
2129 0xaa);
2130 qla2x00_write_flash_byte(ha, 0x2aaa,
2131 0x55);
2132 qla2x00_write_flash_byte(ha, 0x5555,
2133 0xa0);
2134 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2135 /* Then erase it */
2136 if (qla2x00_erase_flash_sector(ha,
2137 addr, sec_mask, man_id,
2138 flash_id)) {
2139 rval = QLA_FUNCTION_FAILED;
2140 break;
2141 }
2142 if (man_id == 0x01 && flash_id == 0x6d)
2143 sec_number++;
2144 }
2145 }
2146
2147 if (man_id == 0x01 && flash_id == 0x6d) {
2148 if (sec_number == 1 &&
2149 addr == (rest_addr - 1)) {
2150 rest_addr = 0x0fff;
2151 sec_mask = 0x1f000;
2152 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2153 rest_addr = 0x3fff;
2154 sec_mask = 0x1c000;
2155 }
2156 }
2157
2158 if (qla2x00_program_flash_address(ha, addr, data,
2159 man_id, flash_id)) {
2160 rval = QLA_FUNCTION_FAILED;
2161 break;
2162 }
2163 cond_resched();
2164 }
2165 } while (0);
2166 qla2x00_flash_disable(ha);
2167
2168 /* Resume HBA. */
2169 qla2x00_resume_hba(vha);
2170
2171 return rval;
2172 }
2173
2174 uint8_t *
2175 qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2176 uint32_t offset, uint32_t length)
2177 {
2178 struct qla_hw_data *ha = vha->hw;
2179
2180 /* Suspend HBA. */
2181 scsi_block_requests(vha->host);
2182 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2183
2184 /* Go with read. */
2185 qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
2186
2187 /* Resume HBA. */
2188 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2189 scsi_unblock_requests(vha->host);
2190
2191 return buf;
2192 }
2193
2194 int
2195 qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2196 uint32_t offset, uint32_t length)
2197 {
2198 int rval;
2199 struct qla_hw_data *ha = vha->hw;
2200
2201 /* Suspend HBA. */
2202 scsi_block_requests(vha->host);
2203 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2204
2205 /* Go with write. */
2206 rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
2207 length >> 2);
2208
2209 /* Resume HBA -- RISC reset needed. */
2210 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2211 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2212 qla2xxx_wake_dpc(vha);
2213 qla2x00_wait_for_hba_online(vha);
2214 scsi_unblock_requests(vha->host);
2215
2216 return rval;
2217 }
2218
2219 uint8_t *
2220 qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2221 uint32_t offset, uint32_t length)
2222 {
2223 int rval;
2224 dma_addr_t optrom_dma;
2225 void *optrom;
2226 uint8_t *pbuf;
2227 uint32_t faddr, left, burst;
2228 struct qla_hw_data *ha = vha->hw;
2229
2230 if (offset & 0xfff)
2231 goto slow_read;
2232 if (length < OPTROM_BURST_SIZE)
2233 goto slow_read;
2234
2235 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2236 &optrom_dma, GFP_KERNEL);
2237 if (!optrom) {
2238 qla_printk(KERN_DEBUG, ha,
2239 "Unable to allocate memory for optrom burst read "
2240 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
2241
2242 goto slow_read;
2243 }
2244
2245 pbuf = buf;
2246 faddr = offset >> 2;
2247 left = length >> 2;
2248 burst = OPTROM_BURST_DWORDS;
2249 while (left != 0) {
2250 if (burst > left)
2251 burst = left;
2252
2253 rval = qla2x00_dump_ram(vha, optrom_dma,
2254 flash_data_addr(ha, faddr), burst);
2255 if (rval) {
2256 qla_printk(KERN_WARNING, ha,
2257 "Unable to burst-read optrom segment "
2258 "(%x/%x/%llx).\n", rval,
2259 flash_data_addr(ha, faddr),
2260 (unsigned long long)optrom_dma);
2261 qla_printk(KERN_WARNING, ha,
2262 "Reverting to slow-read.\n");
2263
2264 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2265 optrom, optrom_dma);
2266 goto slow_read;
2267 }
2268
2269 memcpy(pbuf, optrom, burst * 4);
2270
2271 left -= burst;
2272 faddr += burst;
2273 pbuf += burst * 4;
2274 }
2275
2276 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2277 optrom_dma);
2278
2279 return buf;
2280
2281 slow_read:
2282 return qla24xx_read_optrom_data(vha, buf, offset, length);
2283 }
2284
2285 /**
2286 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2287 * @ha: HA context
2288 * @pcids: Pointer to the FCODE PCI data structure
2289 *
2290 * The process of retrieving the FCODE version information is at best
2291 * described as interesting.
2292 *
2293 * Within the first 100h bytes of the image an ASCII string is present
2294 * which contains several pieces of information including the FCODE
2295 * version. Unfortunately it seems the only reliable way to retrieve
2296 * the version is by scanning for another sentinel within the string,
2297 * the FCODE build date:
2298 *
2299 * ... 2.00.02 10/17/02 ...
2300 *
2301 * Returns QLA_SUCCESS on successful retrieval of version.
2302 */
2303 static void
2304 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
2305 {
2306 int ret = QLA_FUNCTION_FAILED;
2307 uint32_t istart, iend, iter, vend;
2308 uint8_t do_next, rbyte, *vbyte;
2309
2310 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2311
2312 /* Skip the PCI data structure. */
2313 istart = pcids +
2314 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2315 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2316 iend = istart + 0x100;
2317 do {
2318 /* Scan for the sentinel date string...eeewww. */
2319 do_next = 0;
2320 iter = istart;
2321 while ((iter < iend) && !do_next) {
2322 iter++;
2323 if (qla2x00_read_flash_byte(ha, iter) == '/') {
2324 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2325 '/')
2326 do_next++;
2327 else if (qla2x00_read_flash_byte(ha,
2328 iter + 3) == '/')
2329 do_next++;
2330 }
2331 }
2332 if (!do_next)
2333 break;
2334
2335 /* Backtrack to previous ' ' (space). */
2336 do_next = 0;
2337 while ((iter > istart) && !do_next) {
2338 iter--;
2339 if (qla2x00_read_flash_byte(ha, iter) == ' ')
2340 do_next++;
2341 }
2342 if (!do_next)
2343 break;
2344
2345 /*
2346 * Mark end of version tag, and find previous ' ' (space) or
2347 * string length (recent FCODE images -- major hack ahead!!!).
2348 */
2349 vend = iter - 1;
2350 do_next = 0;
2351 while ((iter > istart) && !do_next) {
2352 iter--;
2353 rbyte = qla2x00_read_flash_byte(ha, iter);
2354 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2355 do_next++;
2356 }
2357 if (!do_next)
2358 break;
2359
2360 /* Mark beginning of version tag, and copy data. */
2361 iter++;
2362 if ((vend - iter) &&
2363 ((vend - iter) < sizeof(ha->fcode_revision))) {
2364 vbyte = ha->fcode_revision;
2365 while (iter <= vend) {
2366 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2367 iter++;
2368 }
2369 ret = QLA_SUCCESS;
2370 }
2371 } while (0);
2372
2373 if (ret != QLA_SUCCESS)
2374 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2375 }
2376
2377 int
2378 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2379 {
2380 int ret = QLA_SUCCESS;
2381 uint8_t code_type, last_image;
2382 uint32_t pcihdr, pcids;
2383 uint8_t *dbyte;
2384 uint16_t *dcode;
2385 struct qla_hw_data *ha = vha->hw;
2386
2387 if (!ha->pio_address || !mbuf)
2388 return QLA_FUNCTION_FAILED;
2389
2390 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2391 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2392 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2393 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2394
2395 qla2x00_flash_enable(ha);
2396
2397 /* Begin with first PCI expansion ROM header. */
2398 pcihdr = 0;
2399 last_image = 1;
2400 do {
2401 /* Verify PCI expansion ROM header. */
2402 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2403 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2404 /* No signature */
2405 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2406 "signature.\n"));
2407 ret = QLA_FUNCTION_FAILED;
2408 break;
2409 }
2410
2411 /* Locate PCI data structure. */
2412 pcids = pcihdr +
2413 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2414 qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2415
2416 /* Validate signature of PCI data structure. */
2417 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2418 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2419 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2420 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2421 /* Incorrect header. */
2422 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2423 "found pcir_adr=%x.\n", pcids));
2424 ret = QLA_FUNCTION_FAILED;
2425 break;
2426 }
2427
2428 /* Read version */
2429 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2430 switch (code_type) {
2431 case ROM_CODE_TYPE_BIOS:
2432 /* Intel x86, PC-AT compatible. */
2433 ha->bios_revision[0] =
2434 qla2x00_read_flash_byte(ha, pcids + 0x12);
2435 ha->bios_revision[1] =
2436 qla2x00_read_flash_byte(ha, pcids + 0x13);
2437 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2438 ha->bios_revision[1], ha->bios_revision[0]));
2439 break;
2440 case ROM_CODE_TYPE_FCODE:
2441 /* Open Firmware standard for PCI (FCode). */
2442 /* Eeeewww... */
2443 qla2x00_get_fcode_version(ha, pcids);
2444 break;
2445 case ROM_CODE_TYPE_EFI:
2446 /* Extensible Firmware Interface (EFI). */
2447 ha->efi_revision[0] =
2448 qla2x00_read_flash_byte(ha, pcids + 0x12);
2449 ha->efi_revision[1] =
2450 qla2x00_read_flash_byte(ha, pcids + 0x13);
2451 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2452 ha->efi_revision[1], ha->efi_revision[0]));
2453 break;
2454 default:
2455 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2456 "type %x at pcids %x.\n", code_type, pcids));
2457 break;
2458 }
2459
2460 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2461
2462 /* Locate next PCI expansion ROM. */
2463 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2464 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2465 } while (!last_image);
2466
2467 if (IS_QLA2322(ha)) {
2468 /* Read firmware image information. */
2469 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2470 dbyte = mbuf;
2471 memset(dbyte, 0, 8);
2472 dcode = (uint16_t *)dbyte;
2473
2474 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
2475 8);
2476 DEBUG3(qla_printk(KERN_DEBUG, ha, "dumping fw ver from "
2477 "flash:\n"));
2478 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2479
2480 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2481 dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2482 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2483 dcode[3] == 0)) {
2484 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2485 "revision at %x.\n", ha->flt_region_fw * 4));
2486 } else {
2487 /* values are in big endian */
2488 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2489 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2490 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2491 }
2492 }
2493
2494 qla2x00_flash_disable(ha);
2495
2496 return ret;
2497 }
2498
2499 int
2500 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2501 {
2502 int ret = QLA_SUCCESS;
2503 uint32_t pcihdr, pcids;
2504 uint32_t *dcode;
2505 uint8_t *bcode;
2506 uint8_t code_type, last_image;
2507 int i;
2508 struct qla_hw_data *ha = vha->hw;
2509
2510 if (!mbuf)
2511 return QLA_FUNCTION_FAILED;
2512
2513 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2514 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2515 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2516 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2517
2518 dcode = mbuf;
2519
2520 /* Begin with first PCI expansion ROM header. */
2521 pcihdr = ha->flt_region_boot;
2522 last_image = 1;
2523 do {
2524 /* Verify PCI expansion ROM header. */
2525 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
2526 bcode = mbuf + (pcihdr % 4);
2527 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2528 /* No signature */
2529 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2530 "signature.\n"));
2531 ret = QLA_FUNCTION_FAILED;
2532 break;
2533 }
2534
2535 /* Locate PCI data structure. */
2536 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2537
2538 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
2539 bcode = mbuf + (pcihdr % 4);
2540
2541 /* Validate signature of PCI data structure. */
2542 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2543 bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2544 /* Incorrect header. */
2545 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2546 "found pcir_adr=%x.\n", pcids));
2547 ret = QLA_FUNCTION_FAILED;
2548 break;
2549 }
2550
2551 /* Read version */
2552 code_type = bcode[0x14];
2553 switch (code_type) {
2554 case ROM_CODE_TYPE_BIOS:
2555 /* Intel x86, PC-AT compatible. */
2556 ha->bios_revision[0] = bcode[0x12];
2557 ha->bios_revision[1] = bcode[0x13];
2558 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2559 ha->bios_revision[1], ha->bios_revision[0]));
2560 break;
2561 case ROM_CODE_TYPE_FCODE:
2562 /* Open Firmware standard for PCI (FCode). */
2563 ha->fcode_revision[0] = bcode[0x12];
2564 ha->fcode_revision[1] = bcode[0x13];
2565 DEBUG3(qla_printk(KERN_DEBUG, ha, "read FCODE %d.%d.\n",
2566 ha->fcode_revision[1], ha->fcode_revision[0]));
2567 break;
2568 case ROM_CODE_TYPE_EFI:
2569 /* Extensible Firmware Interface (EFI). */
2570 ha->efi_revision[0] = bcode[0x12];
2571 ha->efi_revision[1] = bcode[0x13];
2572 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2573 ha->efi_revision[1], ha->efi_revision[0]));
2574 break;
2575 default:
2576 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2577 "type %x at pcids %x.\n", code_type, pcids));
2578 break;
2579 }
2580
2581 last_image = bcode[0x15] & BIT_7;
2582
2583 /* Locate next PCI expansion ROM. */
2584 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2585 } while (!last_image);
2586
2587 /* Read firmware image information. */
2588 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2589 dcode = mbuf;
2590
2591 qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
2592 for (i = 0; i < 4; i++)
2593 dcode[i] = be32_to_cpu(dcode[i]);
2594
2595 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2596 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2597 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2598 dcode[3] == 0)) {
2599 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2600 "revision at %x.\n", ha->flt_region_fw * 4));
2601 } else {
2602 ha->fw_revision[0] = dcode[0];
2603 ha->fw_revision[1] = dcode[1];
2604 ha->fw_revision[2] = dcode[2];
2605 ha->fw_revision[3] = dcode[3];
2606 }
2607
2608 return ret;
2609 }
2610
2611 static int
2612 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2613 {
2614 if (pos >= end || *pos != 0x82)
2615 return 0;
2616
2617 pos += 3 + pos[1];
2618 if (pos >= end || *pos != 0x90)
2619 return 0;
2620
2621 pos += 3 + pos[1];
2622 if (pos >= end || *pos != 0x78)
2623 return 0;
2624
2625 return 1;
2626 }
2627
2628 int
2629 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
2630 {
2631 struct qla_hw_data *ha = vha->hw;
2632 uint8_t *pos = ha->vpd;
2633 uint8_t *end = pos + ha->vpd_size;
2634 int len = 0;
2635
2636 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2637 return 0;
2638
2639 while (pos < end && *pos != 0x78) {
2640 len = (*pos == 0x82) ? pos[1] : pos[2];
2641
2642 if (!strncmp(pos, key, strlen(key)))
2643 break;
2644
2645 if (*pos != 0x90 && *pos != 0x91)
2646 pos += len;
2647
2648 pos += 3;
2649 }
2650
2651 if (pos < end - len && *pos != 0x78)
2652 return snprintf(str, size, "%.*s", len, pos + 3);
2653
2654 return 0;
2655 }
x86 "subsystem" repository