2 * Copyright (c) 2000-2004 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/config.h>
21 #ifdef CONFIG_USB_DEBUG
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/dmapool.h>
30 #include <linux/kernel.h>
31 #include <linux/delay.h>
32 #include <linux/ioport.h>
33 #include <linux/sched.h>
34 #include <linux/slab.h>
35 #include <linux/smp_lock.h>
36 #include <linux/errno.h>
37 #include <linux/init.h>
38 #include <linux/timer.h>
39 #include <linux/list.h>
40 #include <linux/interrupt.h>
41 #include <linux/reboot.h>
42 #include <linux/usb.h>
43 #include <linux/moduleparam.h>
44 #include <linux/dma-mapping.h>
46 #include "../core/hcd.h"
48 #include <asm/byteorder.h>
51 #include <asm/system.h>
52 #include <asm/unaligned.h>
55 /*-------------------------------------------------------------------------*/
58 * EHCI hc_driver implementation ... experimental, incomplete.
59 * Based on the final 1.0 register interface specification.
61 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
62 * First was PCMCIA, like ISA; then CardBus, which is PCI.
63 * Next comes "CardBay", using USB 2.0 signals.
65 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
66 * Special thanks to Intel and VIA for providing host controllers to
67 * test this driver on, and Cypress (including In-System Design) for
68 * providing early devices for those host controllers to talk to!
72 * 2004-05-10 Root hub and PCI suspend/resume support; remote wakeup. (db)
73 * 2004-02-24 Replace pci_* with generic dma_* API calls (dsaxena@plexity.net)
74 * 2003-12-29 Rewritten high speed iso transfer support (by Michal Sojka,
75 * <sojkam@centrum.cz>, updates by DB).
77 * 2002-11-29 Correct handling for hw async_next register.
78 * 2002-08-06 Handling for bulk and interrupt transfers is mostly shared;
79 * only scheduling is different, no arbitrary limitations.
80 * 2002-07-25 Sanity check PCI reads, mostly for better cardbus support,
81 * clean up HC run state handshaking.
82 * 2002-05-24 Preliminary FS/LS interrupts, using scheduling shortcuts
83 * 2002-05-11 Clear TT errors for FS/LS ctrl/bulk. Fill in some other
84 * missing pieces: enabling 64bit dma, handoff from BIOS/SMM.
85 * 2002-05-07 Some error path cleanups to report better errors; wmb();
86 * use non-CVS version id; better iso bandwidth claim.
87 * 2002-04-19 Control/bulk/interrupt submit no longer uses giveback() on
88 * errors in submit path. Bugfixes to interrupt scheduling/processing.
89 * 2002-03-05 Initial high-speed ISO support; reduce ITD memory; shift
90 * more checking to generic hcd framework (db). Make it work with
91 * Philips EHCI; reduce PCI traffic; shorten IRQ path (Rory Bolt).
92 * 2002-01-14 Minor cleanup; version synch.
93 * 2002-01-08 Fix roothub handoff of FS/LS to companion controllers.
94 * 2002-01-04 Control/Bulk queuing behaves.
96 * 2001-12-12 Initial patch version for Linux 2.5.1 kernel.
97 * 2001-June Works with usb-storage and NEC EHCI on 2.4
100 #define DRIVER_VERSION "10 Dec 2004"
101 #define DRIVER_AUTHOR "David Brownell"
102 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
104 static const char hcd_name
[] = "ehci_hcd";
107 #undef EHCI_VERBOSE_DEBUG
108 #undef EHCI_URB_TRACE
114 /* magic numbers that can affect system performance */
115 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
116 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
117 #define EHCI_TUNE_RL_TT 0
118 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
119 #define EHCI_TUNE_MULT_TT 1
120 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
122 #define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */
123 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
124 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
125 #define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */
127 /* Initial IRQ latency: faster than hw default */
128 static int log2_irq_thresh
= 0; // 0 to 6
129 module_param (log2_irq_thresh
, int, S_IRUGO
);
130 MODULE_PARM_DESC (log2_irq_thresh
, "log2 IRQ latency, 1-64 microframes");
132 /* initial park setting: slower than hw default */
133 static unsigned park
= 0;
134 module_param (park
, uint
, S_IRUGO
);
135 MODULE_PARM_DESC (park
, "park setting; 1-3 back-to-back async packets");
137 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
139 /*-------------------------------------------------------------------------*/
142 #include "ehci-dbg.c"
144 /*-------------------------------------------------------------------------*/
147 * handshake - spin reading hc until handshake completes or fails
148 * @ptr: address of hc register to be read
149 * @mask: bits to look at in result of read
150 * @done: value of those bits when handshake succeeds
151 * @usec: timeout in microseconds
153 * Returns negative errno, or zero on success
155 * Success happens when the "mask" bits have the specified value (hardware
156 * handshake done). There are two failure modes: "usec" have passed (major
157 * hardware flakeout), or the register reads as all-ones (hardware removed).
159 * That last failure should_only happen in cases like physical cardbus eject
160 * before driver shutdown. But it also seems to be caused by bugs in cardbus
161 * bridge shutdown: shutting down the bridge before the devices using it.
163 static int handshake (void __iomem
*ptr
, u32 mask
, u32 done
, int usec
)
168 result
= readl (ptr
);
169 if (result
== ~(u32
)0) /* card removed */
180 /* force HC to halt state from unknown (EHCI spec section 2.3) */
181 static int ehci_halt (struct ehci_hcd
*ehci
)
183 u32 temp
= readl (&ehci
->regs
->status
);
185 if ((temp
& STS_HALT
) != 0)
188 temp
= readl (&ehci
->regs
->command
);
190 writel (temp
, &ehci
->regs
->command
);
191 return handshake (&ehci
->regs
->status
, STS_HALT
, STS_HALT
, 16 * 125);
194 /* put TDI/ARC silicon into EHCI mode */
195 static void tdi_reset (struct ehci_hcd
*ehci
)
197 u32 __iomem
*reg_ptr
;
200 reg_ptr
= (u32 __iomem
*)(((u8 __iomem
*)ehci
->regs
) + 0x68);
201 tmp
= readl (reg_ptr
);
203 writel (tmp
, reg_ptr
);
206 /* reset a non-running (STS_HALT == 1) controller */
207 static int ehci_reset (struct ehci_hcd
*ehci
)
210 u32 command
= readl (&ehci
->regs
->command
);
212 command
|= CMD_RESET
;
213 dbg_cmd (ehci
, "reset", command
);
214 writel (command
, &ehci
->regs
->command
);
215 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
216 ehci
->next_statechange
= jiffies
;
217 retval
= handshake (&ehci
->regs
->command
, CMD_RESET
, 0, 250 * 1000);
222 if (ehci_is_TDI(ehci
))
228 /* idle the controller (from running) */
229 static void ehci_quiesce (struct ehci_hcd
*ehci
)
234 if (!HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
))
238 /* wait for any schedule enables/disables to take effect */
239 temp
= readl (&ehci
->regs
->command
) << 10;
240 temp
&= STS_ASS
| STS_PSS
;
241 if (handshake (&ehci
->regs
->status
, STS_ASS
| STS_PSS
,
242 temp
, 16 * 125) != 0) {
243 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
247 /* then disable anything that's still active */
248 temp
= readl (&ehci
->regs
->command
);
249 temp
&= ~(CMD_ASE
| CMD_IAAD
| CMD_PSE
);
250 writel (temp
, &ehci
->regs
->command
);
252 /* hardware can take 16 microframes to turn off ... */
253 if (handshake (&ehci
->regs
->status
, STS_ASS
| STS_PSS
,
255 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
260 /*-------------------------------------------------------------------------*/
262 static void ehci_work(struct ehci_hcd
*ehci
, struct pt_regs
*regs
);
264 #include "ehci-hub.c"
265 #include "ehci-mem.c"
267 #include "ehci-sched.c"
269 /*-------------------------------------------------------------------------*/
271 static void ehci_watchdog (unsigned long param
)
273 struct ehci_hcd
*ehci
= (struct ehci_hcd
*) param
;
276 spin_lock_irqsave (&ehci
->lock
, flags
);
278 /* lost IAA irqs wedge things badly; seen with a vt8235 */
280 u32 status
= readl (&ehci
->regs
->status
);
282 if (status
& STS_IAA
) {
283 ehci_vdbg (ehci
, "lost IAA\n");
284 COUNT (ehci
->stats
.lost_iaa
);
285 writel (STS_IAA
, &ehci
->regs
->status
);
286 ehci
->reclaim_ready
= 1;
290 /* stop async processing after it's idled a bit */
291 if (test_bit (TIMER_ASYNC_OFF
, &ehci
->actions
))
292 start_unlink_async (ehci
, ehci
->async
);
294 /* ehci could run by timer, without IRQs ... */
295 ehci_work (ehci
, NULL
);
297 spin_unlock_irqrestore (&ehci
->lock
, flags
);
302 /* EHCI 0.96 (and later) section 5.1 says how to kick BIOS/SMM/...
303 * off the controller (maybe it can boot from highspeed USB disks).
305 static int bios_handoff (struct ehci_hcd
*ehci
, int where
, u32 cap
)
307 if (cap
& (1 << 16)) {
309 struct pci_dev
*pdev
=
310 to_pci_dev(ehci_to_hcd(ehci
)->self
.controller
);
312 /* request handoff to OS */
314 pci_write_config_dword(pdev
, where
, cap
);
316 /* and wait a while for it to happen */
320 pci_read_config_dword(pdev
, where
, &cap
);
321 } while ((cap
& (1 << 16)) && msec
);
322 if (cap
& (1 << 16)) {
323 ehci_err (ehci
, "BIOS handoff failed (%d, %04x)\n",
325 // some BIOS versions seem buggy...
327 ehci_warn (ehci
, "continuing after BIOS bug...\n");
330 ehci_dbg (ehci
, "BIOS handoff succeeded\n");
338 ehci_reboot (struct notifier_block
*self
, unsigned long code
, void *null
)
340 struct ehci_hcd
*ehci
;
342 ehci
= container_of (self
, struct ehci_hcd
, reboot_notifier
);
344 /* make BIOS/etc use companion controller during reboot */
345 writel (0, &ehci
->regs
->configured_flag
);
349 static void ehci_port_power (struct ehci_hcd
*ehci
, int is_on
)
353 if (!HCS_PPC (ehci
->hcs_params
))
356 ehci_dbg (ehci
, "...power%s ports...\n", is_on
? "up" : "down");
357 for (port
= HCS_N_PORTS (ehci
->hcs_params
); port
> 0; )
358 (void) ehci_hub_control(ehci_to_hcd(ehci
),
359 is_on
? SetPortFeature
: ClearPortFeature
,
366 /* called by khubd or root hub init threads */
368 static int ehci_hc_reset (struct usb_hcd
*hcd
)
370 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
372 unsigned count
= 256/4;
374 spin_lock_init (&ehci
->lock
);
376 ehci
->caps
= hcd
->regs
;
377 ehci
->regs
= hcd
->regs
+ HC_LENGTH (readl (&ehci
->caps
->hc_capbase
));
378 dbg_hcs_params (ehci
, "reset");
379 dbg_hcc_params (ehci
, "reset");
381 /* cache this readonly data; minimize chip reads */
382 ehci
->hcs_params
= readl (&ehci
->caps
->hcs_params
);
385 if (hcd
->self
.controller
->bus
== &pci_bus_type
) {
386 struct pci_dev
*pdev
= to_pci_dev(hcd
->self
.controller
);
388 switch (pdev
->vendor
) {
389 case PCI_VENDOR_ID_TDI
:
390 if (pdev
->device
== PCI_DEVICE_ID_TDI_EHCI
) {
391 ehci
->is_tdi_rh_tt
= 1;
395 case PCI_VENDOR_ID_AMD
:
396 /* AMD8111 EHCI doesn't work, according to AMD errata */
397 if (pdev
->device
== 0x7463) {
398 ehci_info (ehci
, "ignoring AMD8111 (errata)\n");
404 /* optional debug port, normally in the first BAR */
405 temp
= pci_find_capability (pdev
, 0x0a);
407 pci_read_config_dword(pdev
, temp
, &temp
);
409 if ((temp
& (3 << 13)) == (1 << 13)) {
411 ehci
->debug
= hcd
->regs
+ temp
;
412 temp
= readl (&ehci
->debug
->control
);
413 ehci_info (ehci
, "debug port %d%s\n",
414 HCS_DEBUG_PORT(ehci
->hcs_params
),
415 (temp
& DBGP_ENABLED
)
418 if (!(temp
& DBGP_ENABLED
))
423 temp
= HCC_EXT_CAPS (readl (&ehci
->caps
->hcc_params
));
427 /* EHCI 0.96 and later may have "extended capabilities" */
428 while (temp
&& count
--) {
431 pci_read_config_dword (to_pci_dev(hcd
->self
.controller
),
433 ehci_dbg (ehci
, "capability %04x at %02x\n", cap
, temp
);
434 switch (cap
& 0xff) {
435 case 1: /* BIOS/SMM/... handoff */
436 if (bios_handoff (ehci
, temp
, cap
) != 0)
439 case 0: /* illegal reserved capability */
440 ehci_warn (ehci
, "illegal capability!\n");
443 default: /* unknown */
446 temp
= (cap
>> 8) & 0xff;
449 ehci_err (ehci
, "bogus capabilities ... PCI problems!\n");
452 if (ehci_is_TDI(ehci
))
456 ehci_port_power (ehci
, 0);
458 /* at least the Genesys GL880S needs fixup here */
459 temp
= HCS_N_CC(ehci
->hcs_params
) * HCS_N_PCC(ehci
->hcs_params
);
461 if (temp
&& HCS_N_PORTS(ehci
->hcs_params
) > temp
) {
462 ehci_dbg (ehci
, "bogus port configuration: "
463 "cc=%d x pcc=%d < ports=%d\n",
464 HCS_N_CC(ehci
->hcs_params
),
465 HCS_N_PCC(ehci
->hcs_params
),
466 HCS_N_PORTS(ehci
->hcs_params
));
469 if (hcd
->self
.controller
->bus
== &pci_bus_type
) {
470 struct pci_dev
*pdev
;
472 pdev
= to_pci_dev(hcd
->self
.controller
);
473 switch (pdev
->vendor
) {
474 case 0x17a0: /* GENESYS */
475 /* GL880S: should be PORTS=2 */
476 temp
|= (ehci
->hcs_params
& ~0xf);
477 ehci
->hcs_params
= temp
;
479 case PCI_VENDOR_ID_NVIDIA
:
480 /* NF4: should be PCC=10 */
487 /* force HC to halt state */
488 return ehci_halt (ehci
);
491 static int ehci_start (struct usb_hcd
*hcd
)
493 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
500 /* skip some things on restart paths */
501 first
= (ehci
->watchdog
.data
== 0);
503 init_timer (&ehci
->watchdog
);
504 ehci
->watchdog
.function
= ehci_watchdog
;
505 ehci
->watchdog
.data
= (unsigned long) ehci
;
509 * hw default: 1K periodic list heads, one per frame.
510 * periodic_size can shrink by USBCMD update if hcc_params allows.
512 ehci
->periodic_size
= DEFAULT_I_TDPS
;
513 if (first
&& (retval
= ehci_mem_init (ehci
, GFP_KERNEL
)) < 0)
516 /* controllers may cache some of the periodic schedule ... */
517 hcc_params
= readl (&ehci
->caps
->hcc_params
);
518 if (HCC_ISOC_CACHE (hcc_params
)) // full frame cache
520 else // N microframes cached
521 ehci
->i_thresh
= 2 + HCC_ISOC_THRES (hcc_params
);
523 ehci
->reclaim
= NULL
;
524 ehci
->reclaim_ready
= 0;
525 ehci
->next_uframe
= -1;
527 /* controller state: unknown --> reset */
529 /* EHCI spec section 4.1 */
530 if ((retval
= ehci_reset (ehci
)) != 0) {
531 ehci_mem_cleanup (ehci
);
534 writel (ehci
->periodic_dma
, &ehci
->regs
->frame_list
);
537 if (hcd
->self
.controller
->bus
== &pci_bus_type
) {
538 struct pci_dev
*pdev
;
541 pdev
= to_pci_dev(hcd
->self
.controller
);
543 /* Serial Bus Release Number is at PCI 0x60 offset */
544 pci_read_config_byte(pdev
, 0x60, &sbrn
);
546 /* port wake capability, reported by boot firmware */
547 pci_read_config_word(pdev
, 0x62, &port_wake
);
548 hcd
->can_wakeup
= (port_wake
& 1) != 0;
550 /* help hc dma work well with cachelines */
556 * dedicate a qh for the async ring head, since we couldn't unlink
557 * a 'real' qh without stopping the async schedule [4.8]. use it
558 * as the 'reclamation list head' too.
559 * its dummy is used in hw_alt_next of many tds, to prevent the qh
560 * from automatically advancing to the next td after short reads.
563 ehci
->async
->qh_next
.qh
= NULL
;
564 ehci
->async
->hw_next
= QH_NEXT (ehci
->async
->qh_dma
);
565 ehci
->async
->hw_info1
= cpu_to_le32 (QH_HEAD
);
566 ehci
->async
->hw_token
= cpu_to_le32 (QTD_STS_HALT
);
567 ehci
->async
->hw_qtd_next
= EHCI_LIST_END
;
568 ehci
->async
->qh_state
= QH_STATE_LINKED
;
569 ehci
->async
->hw_alt_next
= QTD_NEXT (ehci
->async
->dummy
->qtd_dma
);
571 writel ((u32
)ehci
->async
->qh_dma
, &ehci
->regs
->async_next
);
574 * hcc_params controls whether ehci->regs->segment must (!!!)
575 * be used; it constrains QH/ITD/SITD and QTD locations.
576 * pci_pool consistent memory always uses segment zero.
577 * streaming mappings for I/O buffers, like pci_map_single(),
578 * can return segments above 4GB, if the device allows.
580 * NOTE: the dma mask is visible through dma_supported(), so
581 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
582 * Scsi_Host.highmem_io, and so forth. It's readonly to all
583 * host side drivers though.
585 if (HCC_64BIT_ADDR (hcc_params
)) {
586 writel (0, &ehci
->regs
->segment
);
588 // this is deeply broken on almost all architectures
589 if (!pci_set_dma_mask (to_pci_dev(hcd
->self
.controller
), 0xffffffffffffffffULL
))
590 ehci_info (ehci
, "enabled 64bit PCI DMA\n");
594 /* clear interrupt enables, set irq latency */
595 if (log2_irq_thresh
< 0 || log2_irq_thresh
> 6)
597 temp
= 1 << (16 + log2_irq_thresh
);
598 if (HCC_CANPARK(hcc_params
)) {
599 /* HW default park == 3, on hardware that supports it (like
600 * NVidia and ALI silicon), maximizes throughput on the async
601 * schedule by avoiding QH fetches between transfers.
603 * With fast usb storage devices and NForce2, "park" seems to
604 * make problems: throughput reduction (!), data errors...
607 park
= min (park
, (unsigned) 3);
611 ehci_info (ehci
, "park %d\n", park
);
613 if (HCC_PGM_FRAMELISTLEN (hcc_params
)) {
614 /* periodic schedule size can be smaller than default */
616 temp
|= (EHCI_TUNE_FLS
<< 2);
617 switch (EHCI_TUNE_FLS
) {
618 case 0: ehci
->periodic_size
= 1024; break;
619 case 1: ehci
->periodic_size
= 512; break;
620 case 2: ehci
->periodic_size
= 256; break;
624 // Philips, Intel, and maybe others need CMD_RUN before the
625 // root hub will detect new devices (why?); NEC doesn't
627 writel (temp
, &ehci
->regs
->command
);
628 dbg_cmd (ehci
, "init", temp
);
630 /* set async sleep time = 10 us ... ? */
633 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
634 * are explicitly handed to companion controller(s), so no TT is
635 * involved with the root hub. (Except where one is integrated,
636 * and there's no companion controller unless maybe for USB OTG.)
639 ehci
->reboot_notifier
.notifier_call
= ehci_reboot
;
640 register_reboot_notifier (&ehci
->reboot_notifier
);
643 hcd
->state
= HC_STATE_RUNNING
;
644 writel (FLAG_CF
, &ehci
->regs
->configured_flag
);
645 readl (&ehci
->regs
->command
); /* unblock posted write */
647 temp
= HC_VERSION(readl (&ehci
->caps
->hc_capbase
));
649 "USB %x.%x %s, EHCI %x.%02x, driver %s\n",
650 ((sbrn
& 0xf0)>>4), (sbrn
& 0x0f),
651 first
? "initialized" : "restarted",
652 temp
>> 8, temp
& 0xff, DRIVER_VERSION
);
654 writel (INTR_MASK
, &ehci
->regs
->intr_enable
); /* Turn On Interrupts */
657 create_debug_files (ehci
);
662 /* always called by thread; normally rmmod */
664 static void ehci_stop (struct usb_hcd
*hcd
)
666 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
668 ehci_dbg (ehci
, "stop\n");
670 /* Turn off port power on all root hub ports. */
671 ehci_port_power (ehci
, 0);
673 /* no more interrupts ... */
674 del_timer_sync (&ehci
->watchdog
);
676 spin_lock_irq(&ehci
->lock
);
677 if (HC_IS_RUNNING (hcd
->state
))
681 writel (0, &ehci
->regs
->intr_enable
);
682 spin_unlock_irq(&ehci
->lock
);
684 /* let companion controllers work when we aren't */
685 writel (0, &ehci
->regs
->configured_flag
);
686 unregister_reboot_notifier (&ehci
->reboot_notifier
);
688 remove_debug_files (ehci
);
690 /* root hub is shut down separately (first, when possible) */
691 spin_lock_irq (&ehci
->lock
);
693 ehci_work (ehci
, NULL
);
694 spin_unlock_irq (&ehci
->lock
);
695 ehci_mem_cleanup (ehci
);
698 ehci_dbg (ehci
, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
699 ehci
->stats
.normal
, ehci
->stats
.error
, ehci
->stats
.reclaim
,
700 ehci
->stats
.lost_iaa
);
701 ehci_dbg (ehci
, "complete %ld unlink %ld\n",
702 ehci
->stats
.complete
, ehci
->stats
.unlink
);
705 dbg_status (ehci
, "ehci_stop completed", readl (&ehci
->regs
->status
));
708 static int ehci_get_frame (struct usb_hcd
*hcd
)
710 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
711 return (readl (&ehci
->regs
->frame_index
) >> 3) % ehci
->periodic_size
;
714 /*-------------------------------------------------------------------------*/
718 /* suspend/resume, section 4.3 */
720 /* These routines rely on the bus (pci, platform, etc)
721 * to handle powerdown and wakeup, and currently also on
722 * transceivers that don't need any software attention to set up
723 * the right sort of wakeup.
726 static int ehci_suspend (struct usb_hcd
*hcd
, pm_message_t message
)
728 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
730 if (time_before (jiffies
, ehci
->next_statechange
))
733 #ifdef CONFIG_USB_SUSPEND
734 (void) usb_suspend_device (hcd
->self
.root_hub
, message
);
736 usb_lock_device (hcd
->self
.root_hub
);
737 (void) ehci_hub_suspend (hcd
);
738 usb_unlock_device (hcd
->self
.root_hub
);
741 // save (PCI) FLADJ in case of Vaux power loss
742 // ... we'd only use it to handle clock skew
747 static int ehci_resume (struct usb_hcd
*hcd
)
749 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
751 struct usb_device
*root
= hcd
->self
.root_hub
;
752 int retval
= -EINVAL
;
754 // maybe restore (PCI) FLADJ
756 if (time_before (jiffies
, ehci
->next_statechange
))
759 /* If any port is suspended, we know we can/must resume the HC. */
760 for (port
= HCS_N_PORTS (ehci
->hcs_params
); port
> 0; ) {
763 status
= readl (&ehci
->regs
->port_status
[port
]);
764 if (status
& PORT_SUSPEND
) {
765 down (&hcd
->self
.root_hub
->serialize
);
766 retval
= ehci_hub_resume (hcd
);
767 up (&hcd
->self
.root_hub
->serialize
);
770 if (!root
->children
[port
])
772 dbg_port (ehci
, __FUNCTION__
, port
+ 1, status
);
773 usb_set_device_state (root
->children
[port
],
774 USB_STATE_NOTATTACHED
);
777 /* Else reset, to cope with power loss or flush-to-storage
778 * style "resume" having activated BIOS during reboot.
781 (void) ehci_halt (ehci
);
782 (void) ehci_reset (ehci
);
783 (void) ehci_hc_reset (hcd
);
785 /* emptying the schedule aborts any urbs */
786 spin_lock_irq (&ehci
->lock
);
788 ehci
->reclaim_ready
= 1;
789 ehci_work (ehci
, NULL
);
790 spin_unlock_irq (&ehci
->lock
);
792 /* restart; khubd will disconnect devices */
793 retval
= ehci_start (hcd
);
795 /* here we "know" root ports should always stay powered;
796 * but some controllers may lose all power.
798 ehci_port_power (ehci
, 1);
806 /*-------------------------------------------------------------------------*/
809 * ehci_work is called from some interrupts, timers, and so on.
810 * it calls driver completion functions, after dropping ehci->lock.
812 static void ehci_work (struct ehci_hcd
*ehci
, struct pt_regs
*regs
)
814 timer_action_done (ehci
, TIMER_IO_WATCHDOG
);
815 if (ehci
->reclaim_ready
)
816 end_unlink_async (ehci
, regs
);
818 /* another CPU may drop ehci->lock during a schedule scan while
819 * it reports urb completions. this flag guards against bogus
820 * attempts at re-entrant schedule scanning.
825 scan_async (ehci
, regs
);
826 if (ehci
->next_uframe
!= -1)
827 scan_periodic (ehci
, regs
);
830 /* the IO watchdog guards against hardware or driver bugs that
831 * misplace IRQs, and should let us run completely without IRQs.
832 * such lossage has been observed on both VT6202 and VT8235.
834 if (HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
) &&
835 (ehci
->async
->qh_next
.ptr
!= NULL
||
836 ehci
->periodic_sched
!= 0))
837 timer_action (ehci
, TIMER_IO_WATCHDOG
);
840 /*-------------------------------------------------------------------------*/
842 static irqreturn_t
ehci_irq (struct usb_hcd
*hcd
, struct pt_regs
*regs
)
844 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
848 spin_lock (&ehci
->lock
);
850 status
= readl (&ehci
->regs
->status
);
852 /* e.g. cardbus physical eject */
853 if (status
== ~(u32
) 0) {
854 ehci_dbg (ehci
, "device removed\n");
859 if (!status
) { /* irq sharing? */
860 spin_unlock(&ehci
->lock
);
864 /* clear (just) interrupts */
865 writel (status
, &ehci
->regs
->status
);
866 readl (&ehci
->regs
->command
); /* unblock posted write */
869 #ifdef EHCI_VERBOSE_DEBUG
870 /* unrequested/ignored: Frame List Rollover */
871 dbg_status (ehci
, "irq", status
);
874 /* INT, ERR, and IAA interrupt rates can be throttled */
876 /* normal [4.15.1.2] or error [4.15.1.1] completion */
877 if (likely ((status
& (STS_INT
|STS_ERR
)) != 0)) {
878 if (likely ((status
& STS_ERR
) == 0))
879 COUNT (ehci
->stats
.normal
);
881 COUNT (ehci
->stats
.error
);
885 /* complete the unlinking of some qh [4.15.2.3] */
886 if (status
& STS_IAA
) {
887 COUNT (ehci
->stats
.reclaim
);
888 ehci
->reclaim_ready
= 1;
892 /* remote wakeup [4.3.1] */
893 if ((status
& STS_PCD
) && hcd
->remote_wakeup
) {
894 unsigned i
= HCS_N_PORTS (ehci
->hcs_params
);
896 /* resume root hub? */
897 status
= readl (&ehci
->regs
->command
);
898 if (!(status
& CMD_RUN
))
899 writel (status
| CMD_RUN
, &ehci
->regs
->command
);
902 status
= readl (&ehci
->regs
->port_status
[i
]);
903 if (status
& PORT_OWNER
)
905 if (!(status
& PORT_RESUME
)
906 || ehci
->reset_done
[i
] != 0)
909 /* start 20 msec resume signaling from this port,
910 * and make khubd collect PORT_STAT_C_SUSPEND to
911 * stop that signaling.
913 ehci
->reset_done
[i
] = jiffies
+ msecs_to_jiffies (20);
914 mod_timer (&hcd
->rh_timer
,
915 ehci
->reset_done
[i
] + 1);
916 ehci_dbg (ehci
, "port %d remote wakeup\n", i
+ 1);
920 /* PCI errors [4.15.2.4] */
921 if (unlikely ((status
& STS_FATAL
) != 0)) {
922 /* bogus "fatal" IRQs appear on some chips... why? */
923 status
= readl (&ehci
->regs
->status
);
924 dbg_cmd (ehci
, "fatal", readl (&ehci
->regs
->command
));
925 dbg_status (ehci
, "fatal", status
);
926 if (status
& STS_HALT
) {
927 ehci_err (ehci
, "fatal error\n");
930 writel (0, &ehci
->regs
->configured_flag
);
931 /* generic layer kills/unlinks all urbs, then
932 * uses ehci_stop to clean up the rest
939 ehci_work (ehci
, regs
);
940 spin_unlock (&ehci
->lock
);
944 /*-------------------------------------------------------------------------*/
947 * non-error returns are a promise to giveback() the urb later
948 * we drop ownership so next owner (or urb unlink) can get it
950 * urb + dev is in hcd.self.controller.urb_list
951 * we're queueing TDs onto software and hardware lists
953 * hcd-specific init for hcpriv hasn't been done yet
955 * NOTE: control, bulk, and interrupt share the same code to append TDs
956 * to a (possibly active) QH, and the same QH scanning code.
958 static int ehci_urb_enqueue (
960 struct usb_host_endpoint
*ep
,
964 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
965 struct list_head qtd_list
;
967 INIT_LIST_HEAD (&qtd_list
);
969 switch (usb_pipetype (urb
->pipe
)) {
970 // case PIPE_CONTROL:
973 if (!qh_urb_transaction (ehci
, urb
, &qtd_list
, mem_flags
))
975 return submit_async (ehci
, ep
, urb
, &qtd_list
, mem_flags
);
978 if (!qh_urb_transaction (ehci
, urb
, &qtd_list
, mem_flags
))
980 return intr_submit (ehci
, ep
, urb
, &qtd_list
, mem_flags
);
982 case PIPE_ISOCHRONOUS
:
983 if (urb
->dev
->speed
== USB_SPEED_HIGH
)
984 return itd_submit (ehci
, urb
, mem_flags
);
986 return sitd_submit (ehci
, urb
, mem_flags
);
990 static void unlink_async (struct ehci_hcd
*ehci
, struct ehci_qh
*qh
)
992 /* if we need to use IAA and it's busy, defer */
993 if (qh
->qh_state
== QH_STATE_LINKED
995 && HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
)) {
996 struct ehci_qh
*last
;
998 for (last
= ehci
->reclaim
;
1000 last
= last
->reclaim
)
1002 qh
->qh_state
= QH_STATE_UNLINK_WAIT
;
1005 /* bypass IAA if the hc can't care */
1006 } else if (!HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
) && ehci
->reclaim
)
1007 end_unlink_async (ehci
, NULL
);
1009 /* something else might have unlinked the qh by now */
1010 if (qh
->qh_state
== QH_STATE_LINKED
)
1011 start_unlink_async (ehci
, qh
);
1014 /* remove from hardware lists
1015 * completions normally happen asynchronously
1018 static int ehci_urb_dequeue (struct usb_hcd
*hcd
, struct urb
*urb
)
1020 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
1022 unsigned long flags
;
1024 spin_lock_irqsave (&ehci
->lock
, flags
);
1025 switch (usb_pipetype (urb
->pipe
)) {
1026 // case PIPE_CONTROL:
1029 qh
= (struct ehci_qh
*) urb
->hcpriv
;
1032 unlink_async (ehci
, qh
);
1035 case PIPE_INTERRUPT
:
1036 qh
= (struct ehci_qh
*) urb
->hcpriv
;
1039 switch (qh
->qh_state
) {
1040 case QH_STATE_LINKED
:
1041 intr_deschedule (ehci
, qh
);
1044 qh_completions (ehci
, qh
, NULL
);
1047 ehci_dbg (ehci
, "bogus qh %p state %d\n",
1052 /* reschedule QH iff another request is queued */
1053 if (!list_empty (&qh
->qtd_list
)
1054 && HC_IS_RUNNING (hcd
->state
)) {
1057 status
= qh_schedule (ehci
, qh
);
1058 spin_unlock_irqrestore (&ehci
->lock
, flags
);
1061 // shouldn't happen often, but ...
1062 // FIXME kill those tds' urbs
1063 err ("can't reschedule qh %p, err %d",
1070 case PIPE_ISOCHRONOUS
:
1073 // wait till next completion, do it then.
1074 // completion irqs can wait up to 1024 msec,
1078 spin_unlock_irqrestore (&ehci
->lock
, flags
);
1082 /*-------------------------------------------------------------------------*/
1084 // bulk qh holds the data toggle
1087 ehci_endpoint_disable (struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
)
1089 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
1090 unsigned long flags
;
1091 struct ehci_qh
*qh
, *tmp
;
1093 /* ASSERT: any requests/urbs are being unlinked */
1094 /* ASSERT: nobody can be submitting urbs for this any more */
1097 spin_lock_irqsave (&ehci
->lock
, flags
);
1102 /* endpoints can be iso streams. for now, we don't
1103 * accelerate iso completions ... so spin a while.
1105 if (qh
->hw_info1
== 0) {
1106 ehci_vdbg (ehci
, "iso delay\n");
1110 if (!HC_IS_RUNNING (hcd
->state
))
1111 qh
->qh_state
= QH_STATE_IDLE
;
1112 switch (qh
->qh_state
) {
1113 case QH_STATE_LINKED
:
1114 for (tmp
= ehci
->async
->qh_next
.qh
;
1116 tmp
= tmp
->qh_next
.qh
)
1118 /* periodic qh self-unlinks on empty */
1121 unlink_async (ehci
, qh
);
1123 case QH_STATE_UNLINK
: /* wait for hw to finish? */
1125 spin_unlock_irqrestore (&ehci
->lock
, flags
);
1126 set_current_state (TASK_UNINTERRUPTIBLE
);
1127 schedule_timeout (1);
1129 case QH_STATE_IDLE
: /* fully unlinked */
1130 if (list_empty (&qh
->qtd_list
)) {
1134 /* else FALL THROUGH */
1137 /* caller was supposed to have unlinked any requests;
1138 * that's not our job. just leak this memory.
1140 ehci_err (ehci
, "qh %p (#%02x) state %d%s\n",
1141 qh
, ep
->desc
.bEndpointAddress
, qh
->qh_state
,
1142 list_empty (&qh
->qtd_list
) ? "" : "(has tds)");
1147 spin_unlock_irqrestore (&ehci
->lock
, flags
);
1151 /*-------------------------------------------------------------------------*/
1153 static const struct hc_driver ehci_driver
= {
1154 .description
= hcd_name
,
1155 .product_desc
= "EHCI Host Controller",
1156 .hcd_priv_size
= sizeof(struct ehci_hcd
),
1159 * generic hardware linkage
1162 .flags
= HCD_MEMORY
| HCD_USB2
,
1165 * basic lifecycle operations
1167 .reset
= ehci_hc_reset
,
1168 .start
= ehci_start
,
1170 .suspend
= ehci_suspend
,
1171 .resume
= ehci_resume
,
1176 * managing i/o requests and associated device resources
1178 .urb_enqueue
= ehci_urb_enqueue
,
1179 .urb_dequeue
= ehci_urb_dequeue
,
1180 .endpoint_disable
= ehci_endpoint_disable
,
1183 * scheduling support
1185 .get_frame_number
= ehci_get_frame
,
1190 .hub_status_data
= ehci_hub_status_data
,
1191 .hub_control
= ehci_hub_control
,
1192 .hub_suspend
= ehci_hub_suspend
,
1193 .hub_resume
= ehci_hub_resume
,
1196 /*-------------------------------------------------------------------------*/
1198 /* EHCI 1.0 doesn't require PCI */
1202 /* PCI driver selection metadata; PCI hotplugging uses this */
1203 static const struct pci_device_id pci_ids
[] = { {
1204 /* handle any USB 2.0 EHCI controller */
1205 PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB
<< 8) | 0x20), ~0),
1206 .driver_data
= (unsigned long) &ehci_driver
,
1208 { /* end: all zeroes */ }
1210 MODULE_DEVICE_TABLE (pci
, pci_ids
);
1212 /* pci driver glue; this is a "new style" PCI driver module */
1213 static struct pci_driver ehci_pci_driver
= {
1214 .name
= (char *) hcd_name
,
1215 .id_table
= pci_ids
,
1217 .probe
= usb_hcd_pci_probe
,
1218 .remove
= usb_hcd_pci_remove
,
1221 .suspend
= usb_hcd_pci_suspend
,
1222 .resume
= usb_hcd_pci_resume
,
1229 #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
1231 MODULE_DESCRIPTION (DRIVER_INFO
);
1232 MODULE_AUTHOR (DRIVER_AUTHOR
);
1233 MODULE_LICENSE ("GPL");
1235 static int __init
init (void)
1240 pr_debug ("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1242 sizeof (struct ehci_qh
), sizeof (struct ehci_qtd
),
1243 sizeof (struct ehci_itd
), sizeof (struct ehci_sitd
));
1245 return pci_register_driver (&ehci_pci_driver
);
1249 static void __exit
cleanup (void)
1251 pci_unregister_driver (&ehci_pci_driver
);
1253 module_exit (cleanup
);