arch/ppc/kernel/traps.c

   1 /*
   2  *  arch/ppc/kernel/traps.c
   3  *
   4  *  Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
   5  *
   6  *  This program is free software; you can redistribute it and/or
   7  *  modify it under the terms of the GNU General Public License
   8  *  as published by the Free Software Foundation; either version
   9  *  2 of the License, or (at your option) any later version.
  10  *
  11  *  Modified by Cort Dougan (cort@cs.nmt.edu)
  12  *  and Paul Mackerras (paulus@cs.anu.edu.au)
  13  */
  14
  15 /*
  16  * This file handles the architecture-dependent parts of hardware exceptions
  17  */
  18
  19 #include <linux/errno.h>
  20 #include <linux/sched.h>
  21 #include <linux/kernel.h>
  22 #include <linux/mm.h>
  23 #include <linux/stddef.h>
  24 #include <linux/unistd.h>
  25 #include <linux/ptrace.h>
  26 #include <linux/slab.h>
  27 #include <linux/user.h>
  28 #include <linux/a.out.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/config.h>
  31 #include <linux/init.h>
  32 #include <linux/module.h>
  33 #include <linux/prctl.h>
  34
  35 #include <asm/pgtable.h>
  36 #include <asm/uaccess.h>
  37 #include <asm/system.h>
  38 #include <asm/io.h>
  39 #include <asm/reg.h>
  40 #include <asm/xmon.h>
  41 #ifdef CONFIG_PMAC_BACKLIGHT
  42 #include <asm/backlight.h>
  43 #endif
  44 #include <asm/perfmon.h>
  45
  46 #ifdef CONFIG_XMON
  47 void (*debugger)(struct pt_regs *regs) = xmon;
  48 int (*debugger_bpt)(struct pt_regs *regs) = xmon_bpt;
  49 int (*debugger_sstep)(struct pt_regs *regs) = xmon_sstep;
  50 int (*debugger_iabr_match)(struct pt_regs *regs) = xmon_iabr_match;
  51 int (*debugger_dabr_match)(struct pt_regs *regs) = xmon_dabr_match;
  52 void (*debugger_fault_handler)(struct pt_regs *regs);
  53 #else
  54 #ifdef CONFIG_KGDB
  55 void (*debugger)(struct pt_regs *regs);
  56 int (*debugger_bpt)(struct pt_regs *regs);
  57 int (*debugger_sstep)(struct pt_regs *regs);
  58 int (*debugger_iabr_match)(struct pt_regs *regs);
  59 int (*debugger_dabr_match)(struct pt_regs *regs);
  60 void (*debugger_fault_handler)(struct pt_regs *regs);
  61 #else
  62 #define debugger(regs)                  do { } while (0)
  63 #define debugger_bpt(regs)              0
  64 #define debugger_sstep(regs)            0
  65 #define debugger_iabr_match(regs)       0
  66 #define debugger_dabr_match(regs)       0
  67 #define debugger_fault_handler          ((void (*)(struct pt_regs *))0)
  68 #endif
  69 #endif
  70
  71 /*
  72  * Trap & Exception support
  73  */
  74
  75 DEFINE_SPINLOCK(die_lock);
  76
  77 void die(const char * str, struct pt_regs * fp, long err)
  78 {
  79         static int die_counter;
  80         int nl = 0;
  81         console_verbose();
  82         spin_lock_irq(&die_lock);
  83 #ifdef CONFIG_PMAC_BACKLIGHT
  84         if (_machine == _MACH_Pmac) {
  85                 set_backlight_enable(1);
  86                 set_backlight_level(BACKLIGHT_MAX);
  87         }
  88 #endif
  89         printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
  90 #ifdef CONFIG_PREEMPT
  91         printk("PREEMPT ");
  92         nl = 1;
  93 #endif
  94 #ifdef CONFIG_SMP
  95         printk("SMP NR_CPUS=%d ", NR_CPUS);
  96         nl = 1;
  97 #endif
  98         if (nl)
  99                 printk("\n");
 100         show_regs(fp);
 101         spin_unlock_irq(&die_lock);
 102         /* do_exit() should take care of panic'ing from an interrupt
 103          * context so we don't handle it here
 104          */
 105         do_exit(err);
 106 }
 107
 108 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
 109 {
 110         siginfo_t info;
 111
 112         if (!user_mode(regs)) {
 113                 debugger(regs);
 114                 die("Exception in kernel mode", regs, signr);
 115         }
 116         info.si_signo = signr;
 117         info.si_errno = 0;
 118         info.si_code = code;
 119         info.si_addr = (void __user *) addr;
 120         force_sig_info(signr, &info, current);
 121 }
 122
 123 /*
 124  * I/O accesses can cause machine checks on powermacs.
 125  * Check if the NIP corresponds to the address of a sync
 126  * instruction for which there is an entry in the exception
 127  * table.
 128  * Note that the 601 only takes a machine check on TEA
 129  * (transfer error ack) signal assertion, and does not
 130  * set any of the top 16 bits of SRR1.
 131  *  -- paulus.
 132  */
 133 static inline int check_io_access(struct pt_regs *regs)
 134 {
 135 #ifdef CONFIG_PPC_PMAC
 136         unsigned long msr = regs->msr;
 137         const struct exception_table_entry *entry;
 138         unsigned int *nip = (unsigned int *)regs->nip;
 139
 140         if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
 141             && (entry = search_exception_tables(regs->nip)) != NULL) {
 142                 /*
 143                  * Check that it's a sync instruction, or somewhere
 144                  * in the twi; isync; nop sequence that inb/inw/inl uses.
 145                  * As the address is in the exception table
 146                  * we should be able to read the instr there.
 147                  * For the debug message, we look at the preceding
 148                  * load or store.
 149                  */
 150                 if (*nip == 0x60000000)         /* nop */
 151                         nip -= 2;
 152                 else if (*nip == 0x4c00012c)    /* isync */
 153                         --nip;
 154                 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
 155                         /* sync or twi */
 156                         unsigned int rb;
 157
 158                         --nip;
 159                         rb = (*nip >> 11) & 0x1f;
 160                         printk(KERN_DEBUG "%s bad port %lx at %p\n",
 161                                (*nip & 0x100)? "OUT to": "IN from",
 162                                regs->gpr[rb] - _IO_BASE, nip);
 163                         regs->msr |= MSR_RI;
 164                         regs->nip = entry->fixup;
 165                         return 1;
 166                 }
 167         }
 168 #endif /* CONFIG_PPC_PMAC */
 169         return 0;
 170 }
 171
 172 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
 173 /* On 4xx, the reason for the machine check or program exception
 174    is in the ESR. */
 175 #define get_reason(regs)        ((regs)->dsisr)
 176 #ifndef CONFIG_E500
 177 #define get_mc_reason(regs)     ((regs)->dsisr)
 178 #else
 179 #define get_mc_reason(regs)     (mfspr(SPRN_MCSR))
 180 #endif
 181 #define REASON_FP               ESR_FP
 182 #define REASON_ILLEGAL          ESR_PIL
 183 #define REASON_PRIVILEGED       ESR_PPR
 184 #define REASON_TRAP             ESR_PTR
 185
 186 /* single-step stuff */
 187 #define single_stepping(regs)   (current->thread.dbcr0 & DBCR0_IC)
 188 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
 189
 190 #else
 191 /* On non-4xx, the reason for the machine check or program
 192    exception is in the MSR. */
 193 #define get_reason(regs)        ((regs)->msr)
 194 #define get_mc_reason(regs)     ((regs)->msr)
 195 #define REASON_FP               0x100000
 196 #define REASON_ILLEGAL          0x80000
 197 #define REASON_PRIVILEGED       0x40000
 198 #define REASON_TRAP             0x20000
 199
 200 #define single_stepping(regs)   ((regs)->msr & MSR_SE)
 201 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
 202 #endif
 203
 204 /*
 205  * This is "fall-back" implementation for configurations
 206  * which don't provide platform-specific machine check info
 207  */
 208 void __attribute__ ((weak))
 209 platform_machine_check(struct pt_regs *regs)
 210 {
 211 }
 212
 213 void MachineCheckException(struct pt_regs *regs)
 214 {
 215         unsigned long reason = get_mc_reason(regs);
 216
 217         if (user_mode(regs)) {
 218                 regs->msr |= MSR_RI;
 219                 _exception(SIGBUS, regs, BUS_ADRERR, regs->nip);
 220                 return;
 221         }
 222
 223 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
 224         /* the qspan pci read routines can cause machine checks -- Cort */
 225         bad_page_fault(regs, regs->dar, SIGBUS);
 226         return;
 227 #endif
 228
 229         if (debugger_fault_handler) {
 230                 debugger_fault_handler(regs);
 231                 regs->msr |= MSR_RI;
 232                 return;
 233         }
 234
 235         if (check_io_access(regs))
 236                 return;
 237
 238 #if defined(CONFIG_4xx) && !defined(CONFIG_440A)
 239         if (reason & ESR_IMCP) {
 240                 printk("Instruction");
 241                 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
 242         } else
 243                 printk("Data");
 244         printk(" machine check in kernel mode.\n");
 245 #elif defined(CONFIG_440A)
 246         printk("Machine check in kernel mode.\n");
 247         if (reason & ESR_IMCP){
 248                 printk("Instruction Synchronous Machine Check exception\n");
 249                 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
 250         }
 251         else {
 252                 u32 mcsr = mfspr(SPRN_MCSR);
 253                 if (mcsr & MCSR_IB)
 254                         printk("Instruction Read PLB Error\n");
 255                 if (mcsr & MCSR_DRB)
 256                         printk("Data Read PLB Error\n");
 257                 if (mcsr & MCSR_DWB)
 258                         printk("Data Write PLB Error\n");
 259                 if (mcsr & MCSR_TLBP)
 260                         printk("TLB Parity Error\n");
 261                 if (mcsr & MCSR_ICP){
 262                         flush_instruction_cache();
 263                         printk("I-Cache Parity Error\n");
 264                 }
 265                 if (mcsr & MCSR_DCSP)
 266                         printk("D-Cache Search Parity Error\n");
 267                 if (mcsr & MCSR_DCFP)
 268                         printk("D-Cache Flush Parity Error\n");
 269                 if (mcsr & MCSR_IMPE)
 270                         printk("Machine Check exception is imprecise\n");
 271
 272                 /* Clear MCSR */
 273                 mtspr(SPRN_MCSR, mcsr);
 274         }
 275 #elif defined (CONFIG_E500)
 276         printk("Machine check in kernel mode.\n");
 277         printk("Caused by (from MCSR=%lx): ", reason);
 278
 279         if (reason & MCSR_MCP)
 280                 printk("Machine Check Signal\n");
 281         if (reason & MCSR_ICPERR)
 282                 printk("Instruction Cache Parity Error\n");
 283         if (reason & MCSR_DCP_PERR)
 284                 printk("Data Cache Push Parity Error\n");
 285         if (reason & MCSR_DCPERR)
 286                 printk("Data Cache Parity Error\n");
 287         if (reason & MCSR_GL_CI)
 288                 printk("Guarded Load or Cache-Inhibited stwcx.\n");
 289         if (reason & MCSR_BUS_IAERR)
 290                 printk("Bus - Instruction Address Error\n");
 291         if (reason & MCSR_BUS_RAERR)
 292                 printk("Bus - Read Address Error\n");
 293         if (reason & MCSR_BUS_WAERR)
 294                 printk("Bus - Write Address Error\n");
 295         if (reason & MCSR_BUS_IBERR)
 296                 printk("Bus - Instruction Data Error\n");
 297         if (reason & MCSR_BUS_RBERR)
 298                 printk("Bus - Read Data Bus Error\n");
 299         if (reason & MCSR_BUS_WBERR)
 300                 printk("Bus - Read Data Bus Error\n");
 301         if (reason & MCSR_BUS_IPERR)
 302                 printk("Bus - Instruction Parity Error\n");
 303         if (reason & MCSR_BUS_RPERR)
 304                 printk("Bus - Read Parity Error\n");
 305 #else /* !CONFIG_4xx && !CONFIG_E500 */
 306         printk("Machine check in kernel mode.\n");
 307         printk("Caused by (from SRR1=%lx): ", reason);
 308         switch (reason & 0x601F0000) {
 309         case 0x80000:
 310                 printk("Machine check signal\n");
 311                 break;
 312         case 0:         /* for 601 */
 313         case 0x40000:
 314         case 0x140000:  /* 7450 MSS error and TEA */
 315                 printk("Transfer error ack signal\n");
 316                 break;
 317         case 0x20000:
 318                 printk("Data parity error signal\n");
 319                 break;
 320         case 0x10000:
 321                 printk("Address parity error signal\n");
 322                 break;
 323         case 0x20000000:
 324                 printk("L1 Data Cache error\n");
 325                 break;
 326         case 0x40000000:
 327                 printk("L1 Instruction Cache error\n");
 328                 break;
 329         case 0x00100000:
 330                 printk("L2 data cache parity error\n");
 331                 break;
 332         default:
 333                 printk("Unknown values in msr\n");
 334         }
 335 #endif /* CONFIG_4xx */
 336
 337         /*
 338          * Optional platform-provided routine to print out
 339          * additional info, e.g. bus error registers.
 340          */
 341         platform_machine_check(regs);
 342
 343         debugger(regs);
 344         die("machine check", regs, SIGBUS);
 345 }
 346
 347 void SMIException(struct pt_regs *regs)
 348 {
 349         debugger(regs);
 350 #if !(defined(CONFIG_XMON) || defined(CONFIG_KGDB))
 351         show_regs(regs);
 352         panic("System Management Interrupt");
 353 #endif
 354 }
 355
 356 void UnknownException(struct pt_regs *regs)
 357 {
 358         printk("Bad trap at PC: %lx, MSR: %lx, vector=%lx    %s\n",
 359                regs->nip, regs->msr, regs->trap, print_tainted());
 360         _exception(SIGTRAP, regs, 0, 0);
 361 }
 362
 363 void InstructionBreakpoint(struct pt_regs *regs)
 364 {
 365         if (debugger_iabr_match(regs))
 366                 return;
 367         _exception(SIGTRAP, regs, TRAP_BRKPT, 0);
 368 }
 369
 370 void RunModeException(struct pt_regs *regs)
 371 {
 372         _exception(SIGTRAP, regs, 0, 0);
 373 }
 374
 375 /* Illegal instruction emulation support.  Originally written to
 376  * provide the PVR to user applications using the mfspr rd, PVR.
 377  * Return non-zero if we can't emulate, or -EFAULT if the associated
 378  * memory access caused an access fault.  Return zero on success.
 379  *
 380  * There are a couple of ways to do this, either "decode" the instruction
 381  * or directly match lots of bits.  In this case, matching lots of
 382  * bits is faster and easier.
 383  *
 384  */
 385 #define INST_MFSPR_PVR          0x7c1f42a6
 386 #define INST_MFSPR_PVR_MASK     0xfc1fffff
 387
 388 #define INST_DCBA               0x7c0005ec
 389 #define INST_DCBA_MASK          0x7c0007fe
 390
 391 #define INST_MCRXR              0x7c000400
 392 #define INST_MCRXR_MASK         0x7c0007fe
 393
 394 #define INST_STRING             0x7c00042a
 395 #define INST_STRING_MASK        0x7c0007fe
 396 #define INST_STRING_GEN_MASK    0x7c00067e
 397 #define INST_LSWI               0x7c0004aa
 398 #define INST_LSWX               0x7c00042a
 399 #define INST_STSWI              0x7c0005aa
 400 #define INST_STSWX              0x7c00052a
 401
 402 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
 403 {
 404         u8 rT = (instword >> 21) & 0x1f;
 405         u8 rA = (instword >> 16) & 0x1f;
 406         u8 NB_RB = (instword >> 11) & 0x1f;
 407         u32 num_bytes;
 408         unsigned long EA;
 409         int pos = 0;
 410
 411         /* Early out if we are an invalid form of lswx */
 412         if ((instword & INST_STRING_MASK) == INST_LSWX)
 413                 if ((rT == rA) || (rT == NB_RB))
 414                         return -EINVAL;
 415
 416         EA = (rA == 0) ? 0 : regs->gpr[rA];
 417
 418         switch (instword & INST_STRING_MASK) {
 419                 case INST_LSWX:
 420                 case INST_STSWX:
 421                         EA += NB_RB;
 422                         num_bytes = regs->xer & 0x7f;
 423                         break;
 424                 case INST_LSWI:
 425                 case INST_STSWI:
 426                         num_bytes = (NB_RB == 0) ? 32 : NB_RB;
 427                         break;
 428                 default:
 429                         return -EINVAL;
 430         }
 431
 432         while (num_bytes != 0)
 433         {
 434                 u8 val;
 435                 u32 shift = 8 * (3 - (pos & 0x3));
 436
 437                 switch ((instword & INST_STRING_MASK)) {
 438                         case INST_LSWX:
 439                         case INST_LSWI:
 440                                 if (get_user(val, (u8 __user *)EA))
 441                                         return -EFAULT;
 442                                 /* first time updating this reg,
 443                                  * zero it out */
 444                                 if (pos == 0)
 445                                         regs->gpr[rT] = 0;
 446                                 regs->gpr[rT] |= val << shift;
 447                                 break;
 448                         case INST_STSWI:
 449                         case INST_STSWX:
 450                                 val = regs->gpr[rT] >> shift;
 451                                 if (put_user(val, (u8 __user *)EA))
 452                                         return -EFAULT;
 453                                 break;
 454                 }
 455                 /* move EA to next address */
 456                 EA += 1;
 457                 num_bytes--;
 458
 459                 /* manage our position within the register */
 460                 if (++pos == 4) {
 461                         pos = 0;
 462                         if (++rT == 32)
 463                                 rT = 0;
 464                 }
 465         }
 466
 467         return 0;
 468 }
 469
 470 static int emulate_instruction(struct pt_regs *regs)
 471 {
 472         u32 instword;
 473         u32 rd;
 474
 475         if (!user_mode(regs))
 476                 return -EINVAL;
 477         CHECK_FULL_REGS(regs);
 478
 479         if (get_user(instword, (u32 __user *)(regs->nip)))
 480                 return -EFAULT;
 481
 482         /* Emulate the mfspr rD, PVR.
 483          */
 484         if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) {
 485                 rd = (instword >> 21) & 0x1f;
 486                 regs->gpr[rd] = mfspr(SPRN_PVR);
 487                 return 0;
 488         }
 489
 490         /* Emulating the dcba insn is just a no-op.  */
 491         if ((instword & INST_DCBA_MASK) == INST_DCBA)
 492                 return 0;
 493
 494         /* Emulate the mcrxr insn.  */
 495         if ((instword & INST_MCRXR_MASK) == INST_MCRXR) {
 496                 int shift = (instword >> 21) & 0x1c;
 497                 unsigned long msk = 0xf0000000UL >> shift;
 498
 499                 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
 500                 regs->xer &= ~0xf0000000UL;
 501                 return 0;
 502         }
 503
 504         /* Emulate load/store string insn. */
 505         if ((instword & INST_STRING_GEN_MASK) == INST_STRING)
 506                 return emulate_string_inst(regs, instword);
 507
 508         return -EINVAL;
 509 }
 510
 511 /*
 512  * After we have successfully emulated an instruction, we have to
 513  * check if the instruction was being single-stepped, and if so,
 514  * pretend we got a single-step exception.  This was pointed out
 515  * by Kumar Gala.  -- paulus
 516  */
 517 static void emulate_single_step(struct pt_regs *regs)
 518 {
 519         if (single_stepping(regs)) {
 520                 clear_single_step(regs);
 521                 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
 522         }
 523 }
 524
 525 /*
 526  * Look through the list of trap instructions that are used for BUG(),
 527  * BUG_ON() and WARN_ON() and see if we hit one.  At this point we know
 528  * that the exception was caused by a trap instruction of some kind.
 529  * Returns 1 if we should continue (i.e. it was a WARN_ON) or 0
 530  * otherwise.
 531  */
 532 extern struct bug_entry __start___bug_table[], __stop___bug_table[];
 533
 534 #ifndef CONFIG_MODULES
 535 #define module_find_bug(x)      NULL
 536 #endif
 537
 538 static struct bug_entry *find_bug(unsigned long bugaddr)
 539 {
 540         struct bug_entry *bug;
 541
 542         for (bug = __start___bug_table; bug < __stop___bug_table; ++bug)
 543                 if (bugaddr == bug->bug_addr)
 544                         return bug;
 545         return module_find_bug(bugaddr);
 546 }
 547
 548 int check_bug_trap(struct pt_regs *regs)
 549 {
 550         struct bug_entry *bug;
 551         unsigned long addr;
 552
 553         if (regs->msr & MSR_PR)
 554                 return 0;       /* not in kernel */
 555         addr = regs->nip;       /* address of trap instruction */
 556         if (addr < PAGE_OFFSET)
 557                 return 0;
 558         bug = find_bug(regs->nip);
 559         if (bug == NULL)
 560                 return 0;
 561         if (bug->line & BUG_WARNING_TRAP) {
 562                 /* this is a WARN_ON rather than BUG/BUG_ON */
 563 #ifdef CONFIG_XMON
 564                 xmon_printf(KERN_ERR "Badness in %s at %s:%d\n",
 565                        bug->function, bug->file,
 566                        bug->line & ~BUG_WARNING_TRAP);
 567 #endif /* CONFIG_XMON */
 568                 printk(KERN_ERR "Badness in %s at %s:%d\n",
 569                        bug->function, bug->file,
 570                        bug->line & ~BUG_WARNING_TRAP);
 571                 dump_stack();
 572                 return 1;
 573         }
 574 #ifdef CONFIG_XMON
 575         xmon_printf(KERN_CRIT "kernel BUG in %s at %s:%d!\n",
 576                bug->function, bug->file, bug->line);
 577         xmon(regs);
 578 #endif /* CONFIG_XMON */
 579         printk(KERN_CRIT "kernel BUG in %s at %s:%d!\n",
 580                bug->function, bug->file, bug->line);
 581
 582         return 0;
 583 }
 584
 585 void ProgramCheckException(struct pt_regs *regs)
 586 {
 587         unsigned int reason = get_reason(regs);
 588         extern int do_mathemu(struct pt_regs *regs);
 589
 590 #ifdef CONFIG_MATH_EMULATION
 591         /* (reason & REASON_ILLEGAL) would be the obvious thing here,
 592          * but there seems to be a hardware bug on the 405GP (RevD)
 593          * that means ESR is sometimes set incorrectly - either to
 594          * ESR_DST (!?) or 0.  In the process of chasing this with the
 595          * hardware people - not sure if it can happen on any illegal
 596          * instruction or only on FP instructions, whether there is a
 597          * pattern to occurences etc. -dgibson 31/Mar/2003 */
 598         if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) {
 599                 emulate_single_step(regs);
 600                 return;
 601         }
 602 #endif /* CONFIG_MATH_EMULATION */
 603
 604         if (reason & REASON_FP) {
 605                 /* IEEE FP exception */
 606                 int code = 0;
 607                 u32 fpscr;
 608
 609                 /* We must make sure the FP state is consistent with
 610                  * our MSR_FP in regs
 611                  */
 612                 preempt_disable();
 613                 if (regs->msr & MSR_FP)
 614                         giveup_fpu(current);
 615                 preempt_enable();
 616
 617                 fpscr = current->thread.fpscr;
 618                 fpscr &= fpscr << 22;   /* mask summary bits with enables */
 619                 if (fpscr & FPSCR_VX)
 620                         code = FPE_FLTINV;
 621                 else if (fpscr & FPSCR_OX)
 622                         code = FPE_FLTOVF;
 623                 else if (fpscr & FPSCR_UX)
 624                         code = FPE_FLTUND;
 625                 else if (fpscr & FPSCR_ZX)
 626                         code = FPE_FLTDIV;
 627                 else if (fpscr & FPSCR_XX)
 628                         code = FPE_FLTRES;
 629                 _exception(SIGFPE, regs, code, regs->nip);
 630                 return;
 631         }
 632
 633         if (reason & REASON_TRAP) {
 634                 /* trap exception */
 635                 if (debugger_bpt(regs))
 636                         return;
 637                 if (check_bug_trap(regs)) {
 638                         regs->nip += 4;
 639                         return;
 640                 }
 641                 _exception(SIGTRAP, regs, TRAP_BRKPT, 0);
 642                 return;
 643         }
 644
 645         /* Try to emulate it if we should. */
 646         if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
 647                 switch (emulate_instruction(regs)) {
 648                 case 0:
 649                         regs->nip += 4;
 650                         emulate_single_step(regs);
 651                         return;
 652                 case -EFAULT:
 653                         _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
 654                         return;
 655                 }
 656         }
 657
 658         if (reason & REASON_PRIVILEGED)
 659                 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
 660         else
 661                 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
 662 }
 663
 664 void SingleStepException(struct pt_regs *regs)
 665 {
 666         regs->msr &= ~(MSR_SE | MSR_BE);  /* Turn off 'trace' bits */
 667         if (debugger_sstep(regs))
 668                 return;
 669         _exception(SIGTRAP, regs, TRAP_TRACE, 0);
 670 }
 671
 672 void AlignmentException(struct pt_regs *regs)
 673 {
 674         int fixed;
 675
 676         fixed = fix_alignment(regs);
 677         if (fixed == 1) {
 678                 regs->nip += 4; /* skip over emulated instruction */
 679                 emulate_single_step(regs);
 680                 return;
 681         }
 682         if (fixed == -EFAULT) {
 683                 /* fixed == -EFAULT means the operand address was bad */
 684                 if (user_mode(regs))
 685                         _exception(SIGSEGV, regs, SEGV_ACCERR, regs->dar);
 686                 else
 687                         bad_page_fault(regs, regs->dar, SIGSEGV);
 688                 return;
 689         }
 690         _exception(SIGBUS, regs, BUS_ADRALN, regs->dar);
 691 }
 692
 693 void StackOverflow(struct pt_regs *regs)
 694 {
 695         printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
 696                current, regs->gpr[1]);
 697         debugger(regs);
 698         show_regs(regs);
 699         panic("kernel stack overflow");
 700 }
 701
 702 void nonrecoverable_exception(struct pt_regs *regs)
 703 {
 704         printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
 705                regs->nip, regs->msr);
 706         debugger(regs);
 707         die("nonrecoverable exception", regs, SIGKILL);
 708 }
 709
 710 void trace_syscall(struct pt_regs *regs)
 711 {
 712         printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld    %s\n",
 713                current, current->pid, regs->nip, regs->link, regs->gpr[0],
 714                regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
 715 }
 716
 717 #ifdef CONFIG_8xx
 718 void SoftwareEmulation(struct pt_regs *regs)
 719 {
 720         extern int do_mathemu(struct pt_regs *);
 721         extern int Soft_emulate_8xx(struct pt_regs *);
 722         int errcode;
 723
 724         CHECK_FULL_REGS(regs);
 725
 726         if (!user_mode(regs)) {
 727                 debugger(regs);
 728                 die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
 729         }
 730
 731 #ifdef CONFIG_MATH_EMULATION
 732         errcode = do_mathemu(regs);
 733 #else
 734         errcode = Soft_emulate_8xx(regs);
 735 #endif
 736         if (errcode) {
 737                 if (errcode > 0)
 738                         _exception(SIGFPE, regs, 0, 0);
 739                 else if (errcode == -EFAULT)
 740                         _exception(SIGSEGV, regs, 0, 0);
 741                 else
 742                         _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
 743         } else
 744                 emulate_single_step(regs);
 745 }
 746 #endif /* CONFIG_8xx */
 747
 748 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
 749
 750 void DebugException(struct pt_regs *regs, unsigned long debug_status)
 751 {
 752         if (debug_status & DBSR_IC) {   /* instruction completion */
 753                 regs->msr &= ~MSR_DE;
 754                 if (user_mode(regs)) {
 755                         current->thread.dbcr0 &= ~DBCR0_IC;
 756                 } else {
 757                         /* Disable instruction completion */
 758                         mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
 759                         /* Clear the instruction completion event */
 760                         mtspr(SPRN_DBSR, DBSR_IC);
 761                         if (debugger_sstep(regs))
 762                                 return;
 763                 }
 764                 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
 765         }
 766 }
 767 #endif /* CONFIG_4xx || CONFIG_BOOKE */
 768
 769 #if !defined(CONFIG_TAU_INT)
 770 void TAUException(struct pt_regs *regs)
 771 {
 772         printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx    %s\n",
 773                regs->nip, regs->msr, regs->trap, print_tainted());
 774 }
 775 #endif /* CONFIG_INT_TAU */
 776
 777 void AltivecUnavailException(struct pt_regs *regs)
 778 {
 779         static int kernel_altivec_count;
 780
 781 #ifndef CONFIG_ALTIVEC
 782         if (user_mode(regs)) {
 783                 /* A user program has executed an altivec instruction,
 784                    but this kernel doesn't support altivec. */
 785                 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
 786                 return;
 787         }
 788 #endif
 789         /* The kernel has executed an altivec instruction without
 790            first enabling altivec.  Whinge but let it do it. */
 791         if (++kernel_altivec_count < 10)
 792                 printk(KERN_ERR "AltiVec used in kernel (task=%p, pc=%lx)\n",
 793                        current, regs->nip);
 794         regs->msr |= MSR_VEC;
 795 }
 796
 797 #ifdef CONFIG_ALTIVEC
 798 void AltivecAssistException(struct pt_regs *regs)
 799 {
 800         int err;
 801
 802         preempt_disable();
 803         if (regs->msr & MSR_VEC)
 804                 giveup_altivec(current);
 805         preempt_enable();
 806         if (!user_mode(regs)) {
 807                 printk(KERN_ERR "altivec assist exception in kernel mode"
 808                        " at %lx\n", regs->nip);
 809                 debugger(regs);
 810                 die("altivec assist exception", regs, SIGFPE);
 811                 return;
 812         }
 813
 814         err = emulate_altivec(regs);
 815         if (err == 0) {
 816                 regs->nip += 4;         /* skip emulated instruction */
 817                 emulate_single_step(regs);
 818                 return;
 819         }
 820
 821         if (err == -EFAULT) {
 822                 /* got an error reading the instruction */
 823                 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
 824         } else {
 825                 /* didn't recognize the instruction */
 826                 /* XXX quick hack for now: set the non-Java bit in the VSCR */
 827                 printk(KERN_ERR "unrecognized altivec instruction "
 828                        "in %s at %lx\n", current->comm, regs->nip);
 829                 current->thread.vscr.u[3] |= 0x10000;
 830         }
 831 }
 832 #endif /* CONFIG_ALTIVEC */
 833
 834 void PerformanceMonitorException(struct pt_regs *regs)
 835 {
 836         perf_irq(regs);
 837 }
 838
 839 #ifdef CONFIG_FSL_BOOKE
 840 void CacheLockingException(struct pt_regs *regs, unsigned long address,
 841                            unsigned long error_code)
 842 {
 843         /* We treat cache locking instructions from the user
 844          * as priv ops, in the future we could try to do
 845          * something smarter
 846          */
 847         if (error_code & (ESR_DLK|ESR_ILK))
 848                 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
 849         return;
 850 }
 851 #endif /* CONFIG_FSL_BOOKE */
 852
 853 #ifdef CONFIG_SPE
 854 void SPEFloatingPointException(struct pt_regs *regs)
 855 {
 856         unsigned long spefscr;
 857         int fpexc_mode;
 858         int code = 0;
 859
 860         spefscr = current->thread.spefscr;
 861         fpexc_mode = current->thread.fpexc_mode;
 862
 863         /* Hardware does not neccessarily set sticky
 864          * underflow/overflow/invalid flags */
 865         if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
 866                 code = FPE_FLTOVF;
 867                 spefscr |= SPEFSCR_FOVFS;
 868         }
 869         else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
 870                 code = FPE_FLTUND;
 871                 spefscr |= SPEFSCR_FUNFS;
 872         }
 873         else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
 874                 code = FPE_FLTDIV;
 875         else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
 876                 code = FPE_FLTINV;
 877                 spefscr |= SPEFSCR_FINVS;
 878         }
 879         else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
 880                 code = FPE_FLTRES;
 881
 882         current->thread.spefscr = spefscr;
 883
 884         _exception(SIGFPE, regs, code, regs->nip);
 885         return;
 886 }
 887 #endif
 888
 889 void __init trap_init(void)
 890 {
 891 }