arch/mips/mips-boards/sim/sim_time.c

   1 #include <linux/types.h>
   2 #include <linux/init.h>
   3 #include <linux/kernel_stat.h>
   4 #include <linux/sched.h>
   5 #include <linux/spinlock.h>
   6
   7 #include <asm/mipsregs.h>
   8 #include <asm/ptrace.h>
   9 #include <asm/hardirq.h>
  10 #include <asm/div64.h>
  11 #include <asm/cpu.h>
  12 #include <asm/time.h>
  13
  14 #include <linux/interrupt.h>
  15 #include <linux/mc146818rtc.h>
  16 #include <linux/timex.h>
  17 #include <asm/mipsregs.h>
  18 #include <asm/hardirq.h>
  19 #include <asm/irq.h>
  20 #include <asm/div64.h>
  21 #include <asm/cpu.h>
  22 #include <asm/time.h>
  23 #include <asm/mc146818-time.h>
  24 #include <asm/msc01_ic.h>
  25
  26 #include <asm/mips-boards/generic.h>
  27 #include <asm/mips-boards/prom.h>
  28 #include <asm/mips-boards/simint.h>
  29 #include <asm/mc146818-time.h>
  30 #include <asm/smp.h>
  31
  32
  33 unsigned long cpu_khz;
  34
  35 irqreturn_t sim_timer_interrupt(int irq, void *dev_id)
  36 {
  37 #ifdef CONFIG_SMP
  38         int cpu = smp_processor_id();
  39
  40         /*
  41          * CPU 0 handles the global timer interrupt job
  42          * resets count/compare registers to trigger next timer int.
  43          */
  44 #ifndef CONFIG_MIPS_MT_SMTC
  45         if (cpu == 0) {
  46                 timer_interrupt(irq, dev_id);
  47         }
  48         else {
  49                 /* Everyone else needs to reset the timer int here as
  50                    ll_local_timer_interrupt doesn't */
  51                 /*
  52                  * FIXME: need to cope with counter underflow.
  53                  * More support needs to be added to kernel/time for
  54                  * counter/timer interrupts on multiple CPU's
  55                  */
  56                 write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
  57         }
  58 #else /* SMTC */
  59         /*
  60          *  In SMTC system, one Count/Compare set exists per VPE.
  61          *  Which TC within a VPE gets the interrupt is essentially
  62          *  random - we only know that it shouldn't be one with
  63          *  IXMT set. Whichever TC gets the interrupt needs to
  64          *  send special interprocessor interrupts to the other
  65          *  TCs to make sure that they schedule, etc.
  66          *
  67          *  That code is specific to the SMTC kernel, not to
  68          *  the simulation platform, so it's invoked from
  69          *  the general MIPS timer_interrupt routine.
  70          *
  71          * We have a problem in that the interrupt vector code
  72          * had to turn off the timer IM bit to avoid redundant
  73          * entries, but we may never get to mips_cpu_irq_end
  74          * to turn it back on again if the scheduler gets
  75          * involved.  So we clear the pending timer here,
  76          * and re-enable the mask...
  77          */
  78
  79         int vpflags = dvpe();
  80         write_c0_compare (read_c0_count() - 1);
  81         clear_c0_cause(0x100 << MIPSCPU_INT_CPUCTR);
  82         set_c0_status(0x100 << MIPSCPU_INT_CPUCTR);
  83         irq_enable_hazard();
  84         evpe(vpflags);
  85
  86         if(cpu_data[cpu].vpe_id == 0) timer_interrupt(irq, dev_id);
  87         else write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
  88         smtc_timer_broadcast(cpu_data[cpu].vpe_id);
  89
  90 #endif /* CONFIG_MIPS_MT_SMTC */
  91
  92         /*
  93          * every CPU should do profiling and process accounting
  94          */
  95         local_timer_interrupt (irq, dev_id);
  96         return IRQ_HANDLED;
  97 #else
  98         return timer_interrupt (irq, dev_id);
  99 #endif
 100 }
 101
 102
 103
 104 /*
 105  * Estimate CPU frequency.  Sets mips_hpt_frequency as a side-effect
 106  */
 107 static unsigned int __init estimate_cpu_frequency(void)
 108 {
 109         unsigned int prid = read_c0_prid() & 0xffff00;
 110         unsigned int count;
 111
 112 #if 1
 113         /*
 114          * hardwire the board frequency to 12MHz.
 115          */
 116
 117         if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
 118             (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
 119                 count = 12000000;
 120         else
 121                 count =  6000000;
 122 #else
 123         unsigned int flags;
 124
 125         local_irq_save(flags);
 126
 127         /* Start counter exactly on falling edge of update flag */
 128         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 129         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 130
 131         /* Start r4k counter. */
 132         write_c0_count(0);
 133
 134         /* Read counter exactly on falling edge of update flag */
 135         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 136         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 137
 138         count = read_c0_count();
 139
 140         /* restore interrupts */
 141         local_irq_restore(flags);
 142 #endif
 143
 144         mips_hpt_frequency = count;
 145
 146         if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
 147             (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
 148                 count *= 2;
 149
 150         count += 5000;    /* round */
 151         count -= count%10000;
 152
 153         return count;
 154 }
 155
 156 void __init sim_time_init(void)
 157 {
 158         unsigned int est_freq, flags;
 159
 160         local_irq_save(flags);
 161
 162
 163         /* Set Data mode - binary. */
 164         CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
 165
 166
 167         est_freq = estimate_cpu_frequency ();
 168
 169         printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
 170                (est_freq%1000000)*100/1000000);
 171
 172         cpu_khz = est_freq / 1000;
 173
 174         local_irq_restore(flags);
 175 }
 176
 177 static int mips_cpu_timer_irq;
 178
 179 static void mips_timer_dispatch(void)
 180 {
 181         do_IRQ(mips_cpu_timer_irq);
 182 }
 183
 184
 185 void __init plat_timer_setup(struct irqaction *irq)
 186 {
 187         if (cpu_has_veic) {
 188                 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
 189                 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
 190         }
 191         else {
 192                 if (cpu_has_vint)
 193                         set_vi_handler(MIPSCPU_INT_CPUCTR, mips_timer_dispatch);
 194                 mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR;
 195         }
 196
 197         /* we are using the cpu counter for timer interrupts */
 198         irq->handler = sim_timer_interrupt;
 199         setup_irq(mips_cpu_timer_irq, irq);
 200
 201 #ifdef CONFIG_SMP
 202         /* irq_desc(riptor) is a global resource, when the interrupt overlaps
 203            on seperate cpu's the first one tries to handle the second interrupt.
 204            The effect is that the int remains disabled on the second cpu.
 205            Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
 206         irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
 207 #endif
 208
 209         /* to generate the first timer interrupt */
 210         write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ));
 211 }