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drivers/net/*/: Use static const
[linux-2.6/x86.git] / drivers / net / bnx2x / bnx2x_main.c
blobcf54427a8d80e799731c62e188e79785fe8130bc
1 /* bnx2x_main.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h> /* for dev_info() */
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/skbuff.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/bitops.h>
34 #include <linux/irq.h>
35 #include <linux/delay.h>
36 #include <asm/byteorder.h>
37 #include <linux/time.h>
38 #include <linux/ethtool.h>
39 #include <linux/mii.h>
40 #include <linux/if_vlan.h>
41 #include <net/ip.h>
42 #include <net/tcp.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/crc32c.h>
48 #include <linux/prefetch.h>
49 #include <linux/zlib.h>
50 #include <linux/io.h>
51 #include <linux/stringify.h>
52
53 #define BNX2X_MAIN
54 #include "bnx2x.h"
55 #include "bnx2x_init.h"
56 #include "bnx2x_init_ops.h"
57 #include "bnx2x_cmn.h"
58 #include "bnx2x_dcb.h"
59
60 #include <linux/firmware.h>
61 #include "bnx2x_fw_file_hdr.h"
62 /* FW files */
63 #define FW_FILE_VERSION \
64 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
65 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
66 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
67 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
68 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
69 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
70 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
71
72 /* Time in jiffies before concluding the transmitter is hung */
73 #define TX_TIMEOUT (5*HZ)
74
75 static char version[] __devinitdata =
76 "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
77 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
78
79 MODULE_AUTHOR("Eliezer Tamir");
80 MODULE_DESCRIPTION("Broadcom NetXtreme II "
81 "BCM57710/57711/57711E/57712/57712E Driver");
82 MODULE_LICENSE("GPL");
83 MODULE_VERSION(DRV_MODULE_VERSION);
84 MODULE_FIRMWARE(FW_FILE_NAME_E1);
85 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
86 MODULE_FIRMWARE(FW_FILE_NAME_E2);
87
88 static int multi_mode = 1;
89 module_param(multi_mode, int, 0);
90 MODULE_PARM_DESC(multi_mode, " Multi queue mode "
91 "(0 Disable; 1 Enable (default))");
92
93 int num_queues;
94 module_param(num_queues, int, 0);
95 MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
96 " (default is as a number of CPUs)");
97
98 static int disable_tpa;
99 module_param(disable_tpa, int, 0);
100 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
101
102 static int int_mode;
103 module_param(int_mode, int, 0);
104 MODULE_PARM_DESC(int_mode, " Force interrupt mode other then MSI-X "
105 "(1 INT#x; 2 MSI)");
106
107 static int dropless_fc;
108 module_param(dropless_fc, int, 0);
109 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
110
111 static int poll;
112 module_param(poll, int, 0);
113 MODULE_PARM_DESC(poll, " Use polling (for debug)");
114
115 static int mrrs = -1;
116 module_param(mrrs, int, 0);
117 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
118
119 static int debug;
120 module_param(debug, int, 0);
121 MODULE_PARM_DESC(debug, " Default debug msglevel");
122
123 static struct workqueue_struct *bnx2x_wq;
124
125 #ifdef BCM_CNIC
126 static u8 ALL_ENODE_MACS[] = {0x01, 0x10, 0x18, 0x01, 0x00, 0x01};
127 #endif
128
129 enum bnx2x_board_type {
130 BCM57710 = 0,
131 BCM57711 = 1,
132 BCM57711E = 2,
133 BCM57712 = 3,
134 BCM57712E = 4
135 };
136
137 /* indexed by board_type, above */
138 static struct {
139 char *name;
140 } board_info[] __devinitdata = {
141 { "Broadcom NetXtreme II BCM57710 XGb" },
142 { "Broadcom NetXtreme II BCM57711 XGb" },
143 { "Broadcom NetXtreme II BCM57711E XGb" },
144 { "Broadcom NetXtreme II BCM57712 XGb" },
145 { "Broadcom NetXtreme II BCM57712E XGb" }
146 };
147
148 #ifndef PCI_DEVICE_ID_NX2_57712
149 #define PCI_DEVICE_ID_NX2_57712 0x1662
150 #endif
151 #ifndef PCI_DEVICE_ID_NX2_57712E
152 #define PCI_DEVICE_ID_NX2_57712E 0x1663
153 #endif
154
155 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
156 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
157 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
158 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
159 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
160 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712E), BCM57712E },
161 { 0 }
162 };
163
164 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
165
166 /****************************************************************************
167 * General service functions
168 ****************************************************************************/
169
170 static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
171 u32 addr, dma_addr_t mapping)
172 {
173 REG_WR(bp, addr, U64_LO(mapping));
174 REG_WR(bp, addr + 4, U64_HI(mapping));
175 }
176
177 static inline void __storm_memset_fill(struct bnx2x *bp,
178 u32 addr, size_t size, u32 val)
179 {
180 int i;
181 for (i = 0; i < size/4; i++)
182 REG_WR(bp, addr + (i * 4), val);
183 }
184
185 static inline void storm_memset_ustats_zero(struct bnx2x *bp,
186 u8 port, u16 stat_id)
187 {
188 size_t size = sizeof(struct ustorm_per_client_stats);
189
190 u32 addr = BAR_USTRORM_INTMEM +
191 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
192
193 __storm_memset_fill(bp, addr, size, 0);
194 }
195
196 static inline void storm_memset_tstats_zero(struct bnx2x *bp,
197 u8 port, u16 stat_id)
198 {
199 size_t size = sizeof(struct tstorm_per_client_stats);
200
201 u32 addr = BAR_TSTRORM_INTMEM +
202 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
203
204 __storm_memset_fill(bp, addr, size, 0);
205 }
206
207 static inline void storm_memset_xstats_zero(struct bnx2x *bp,
208 u8 port, u16 stat_id)
209 {
210 size_t size = sizeof(struct xstorm_per_client_stats);
211
212 u32 addr = BAR_XSTRORM_INTMEM +
213 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
214
215 __storm_memset_fill(bp, addr, size, 0);
216 }
217
218
219 static inline void storm_memset_spq_addr(struct bnx2x *bp,
220 dma_addr_t mapping, u16 abs_fid)
221 {
222 u32 addr = XSEM_REG_FAST_MEMORY +
223 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
224
225 __storm_memset_dma_mapping(bp, addr, mapping);
226 }
227
228 static inline void storm_memset_ov(struct bnx2x *bp, u16 ov, u16 abs_fid)
229 {
230 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(abs_fid), ov);
231 }
232
233 static inline void storm_memset_func_cfg(struct bnx2x *bp,
234 struct tstorm_eth_function_common_config *tcfg,
235 u16 abs_fid)
236 {
237 size_t size = sizeof(struct tstorm_eth_function_common_config);
238
239 u32 addr = BAR_TSTRORM_INTMEM +
240 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
241
242 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
243 }
244
245 static inline void storm_memset_xstats_flags(struct bnx2x *bp,
246 struct stats_indication_flags *flags,
247 u16 abs_fid)
248 {
249 size_t size = sizeof(struct stats_indication_flags);
250
251 u32 addr = BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(abs_fid);
252
253 __storm_memset_struct(bp, addr, size, (u32 *)flags);
254 }
255
256 static inline void storm_memset_tstats_flags(struct bnx2x *bp,
257 struct stats_indication_flags *flags,
258 u16 abs_fid)
259 {
260 size_t size = sizeof(struct stats_indication_flags);
261
262 u32 addr = BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(abs_fid);
263
264 __storm_memset_struct(bp, addr, size, (u32 *)flags);
265 }
266
267 static inline void storm_memset_ustats_flags(struct bnx2x *bp,
268 struct stats_indication_flags *flags,
269 u16 abs_fid)
270 {
271 size_t size = sizeof(struct stats_indication_flags);
272
273 u32 addr = BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(abs_fid);
274
275 __storm_memset_struct(bp, addr, size, (u32 *)flags);
276 }
277
278 static inline void storm_memset_cstats_flags(struct bnx2x *bp,
279 struct stats_indication_flags *flags,
280 u16 abs_fid)
281 {
282 size_t size = sizeof(struct stats_indication_flags);
283
284 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(abs_fid);
285
286 __storm_memset_struct(bp, addr, size, (u32 *)flags);
287 }
288
289 static inline void storm_memset_xstats_addr(struct bnx2x *bp,
290 dma_addr_t mapping, u16 abs_fid)
291 {
292 u32 addr = BAR_XSTRORM_INTMEM +
293 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
294
295 __storm_memset_dma_mapping(bp, addr, mapping);
296 }
297
298 static inline void storm_memset_tstats_addr(struct bnx2x *bp,
299 dma_addr_t mapping, u16 abs_fid)
300 {
301 u32 addr = BAR_TSTRORM_INTMEM +
302 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
303
304 __storm_memset_dma_mapping(bp, addr, mapping);
305 }
306
307 static inline void storm_memset_ustats_addr(struct bnx2x *bp,
308 dma_addr_t mapping, u16 abs_fid)
309 {
310 u32 addr = BAR_USTRORM_INTMEM +
311 USTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
312
313 __storm_memset_dma_mapping(bp, addr, mapping);
314 }
315
316 static inline void storm_memset_cstats_addr(struct bnx2x *bp,
317 dma_addr_t mapping, u16 abs_fid)
318 {
319 u32 addr = BAR_CSTRORM_INTMEM +
320 CSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
321
322 __storm_memset_dma_mapping(bp, addr, mapping);
323 }
324
325 static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
326 u16 pf_id)
327 {
328 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
329 pf_id);
330 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
331 pf_id);
332 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
333 pf_id);
334 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
335 pf_id);
336 }
337
338 static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
339 u8 enable)
340 {
341 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
342 enable);
343 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
344 enable);
345 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
346 enable);
347 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
348 enable);
349 }
350
351 static inline void storm_memset_eq_data(struct bnx2x *bp,
352 struct event_ring_data *eq_data,
353 u16 pfid)
354 {
355 size_t size = sizeof(struct event_ring_data);
356
357 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
358
359 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
360 }
361
362 static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
363 u16 pfid)
364 {
365 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
366 REG_WR16(bp, addr, eq_prod);
367 }
368
369 static inline void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
370 u16 fw_sb_id, u8 sb_index,
371 u8 ticks)
372 {
373
374 int index_offset = CHIP_IS_E2(bp) ?
375 offsetof(struct hc_status_block_data_e2, index_data) :
376 offsetof(struct hc_status_block_data_e1x, index_data);
377 u32 addr = BAR_CSTRORM_INTMEM +
378 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
379 index_offset +
380 sizeof(struct hc_index_data)*sb_index +
381 offsetof(struct hc_index_data, timeout);
382 REG_WR8(bp, addr, ticks);
383 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d ticks %d\n",
384 port, fw_sb_id, sb_index, ticks);
385 }
386 static inline void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
387 u16 fw_sb_id, u8 sb_index,
388 u8 disable)
389 {
390 u32 enable_flag = disable ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
391 int index_offset = CHIP_IS_E2(bp) ?
392 offsetof(struct hc_status_block_data_e2, index_data) :
393 offsetof(struct hc_status_block_data_e1x, index_data);
394 u32 addr = BAR_CSTRORM_INTMEM +
395 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
396 index_offset +
397 sizeof(struct hc_index_data)*sb_index +
398 offsetof(struct hc_index_data, flags);
399 u16 flags = REG_RD16(bp, addr);
400 /* clear and set */
401 flags &= ~HC_INDEX_DATA_HC_ENABLED;
402 flags |= enable_flag;
403 REG_WR16(bp, addr, flags);
404 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d disable %d\n",
405 port, fw_sb_id, sb_index, disable);
406 }
407
408 /* used only at init
409 * locking is done by mcp
410 */
411 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
412 {
413 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
414 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
415 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
416 PCICFG_VENDOR_ID_OFFSET);
417 }
418
419 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
420 {
421 u32 val;
422
423 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
424 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
425 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
426 PCICFG_VENDOR_ID_OFFSET);
427
428 return val;
429 }
430
431 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
432 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
433 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
434 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
435 #define DMAE_DP_DST_NONE "dst_addr [none]"
436
437 static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
438 int msglvl)
439 {
440 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
441
442 switch (dmae->opcode & DMAE_COMMAND_DST) {
443 case DMAE_CMD_DST_PCI:
444 if (src_type == DMAE_CMD_SRC_PCI)
445 DP(msglvl, "DMAE: opcode 0x%08x\n"
446 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
447 "comp_addr [%x:%08x], comp_val 0x%08x\n",
448 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
449 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
450 dmae->comp_addr_hi, dmae->comp_addr_lo,
451 dmae->comp_val);
452 else
453 DP(msglvl, "DMAE: opcode 0x%08x\n"
454 "src [%08x], len [%d*4], dst [%x:%08x]\n"
455 "comp_addr [%x:%08x], comp_val 0x%08x\n",
456 dmae->opcode, dmae->src_addr_lo >> 2,
457 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
458 dmae->comp_addr_hi, dmae->comp_addr_lo,
459 dmae->comp_val);
460 break;
461 case DMAE_CMD_DST_GRC:
462 if (src_type == DMAE_CMD_SRC_PCI)
463 DP(msglvl, "DMAE: opcode 0x%08x\n"
464 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
465 "comp_addr [%x:%08x], comp_val 0x%08x\n",
466 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
467 dmae->len, dmae->dst_addr_lo >> 2,
468 dmae->comp_addr_hi, dmae->comp_addr_lo,
469 dmae->comp_val);
470 else
471 DP(msglvl, "DMAE: opcode 0x%08x\n"
472 "src [%08x], len [%d*4], dst [%08x]\n"
473 "comp_addr [%x:%08x], comp_val 0x%08x\n",
474 dmae->opcode, dmae->src_addr_lo >> 2,
475 dmae->len, dmae->dst_addr_lo >> 2,
476 dmae->comp_addr_hi, dmae->comp_addr_lo,
477 dmae->comp_val);
478 break;
479 default:
480 if (src_type == DMAE_CMD_SRC_PCI)
481 DP(msglvl, "DMAE: opcode 0x%08x\n"
482 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
483 "dst_addr [none]\n"
484 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
485 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
486 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
487 dmae->comp_val);
488 else
489 DP(msglvl, "DMAE: opcode 0x%08x\n"
490 DP_LEVEL "src_addr [%08x] len [%d * 4] "
491 "dst_addr [none]\n"
492 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
493 dmae->opcode, dmae->src_addr_lo >> 2,
494 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
495 dmae->comp_val);
496 break;
497 }
498
499 }
500
501 const u32 dmae_reg_go_c[] = {
502 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
503 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
504 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
505 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
506 };
507
508 /* copy command into DMAE command memory and set DMAE command go */
509 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
510 {
511 u32 cmd_offset;
512 int i;
513
514 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
515 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
516 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
517
518 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
519 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
520 }
521 REG_WR(bp, dmae_reg_go_c[idx], 1);
522 }
523
524 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
525 {
526 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
527 DMAE_CMD_C_ENABLE);
528 }
529
530 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
531 {
532 return opcode & ~DMAE_CMD_SRC_RESET;
533 }
534
535 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
536 bool with_comp, u8 comp_type)
537 {
538 u32 opcode = 0;
539
540 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
541 (dst_type << DMAE_COMMAND_DST_SHIFT));
542
543 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
544
545 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
546 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
547 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
548 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
549
550 #ifdef __BIG_ENDIAN
551 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
552 #else
553 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
554 #endif
555 if (with_comp)
556 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
557 return opcode;
558 }
559
560 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
561 struct dmae_command *dmae,
562 u8 src_type, u8 dst_type)
563 {
564 memset(dmae, 0, sizeof(struct dmae_command));
565
566 /* set the opcode */
567 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
568 true, DMAE_COMP_PCI);
569
570 /* fill in the completion parameters */
571 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
572 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
573 dmae->comp_val = DMAE_COMP_VAL;
574 }
575
576 /* issue a dmae command over the init-channel and wailt for completion */
577 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
578 struct dmae_command *dmae)
579 {
580 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
581 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 40;
582 int rc = 0;
583
584 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
585 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
586 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
587
588 /* lock the dmae channel */
589 mutex_lock(&bp->dmae_mutex);
590
591 /* reset completion */
592 *wb_comp = 0;
593
594 /* post the command on the channel used for initializations */
595 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
596
597 /* wait for completion */
598 udelay(5);
599 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
600 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
601
602 if (!cnt) {
603 BNX2X_ERR("DMAE timeout!\n");
604 rc = DMAE_TIMEOUT;
605 goto unlock;
606 }
607 cnt--;
608 udelay(50);
609 }
610 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
611 BNX2X_ERR("DMAE PCI error!\n");
612 rc = DMAE_PCI_ERROR;
613 }
614
615 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
616 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
617 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
618
619 unlock:
620 mutex_unlock(&bp->dmae_mutex);
621 return rc;
622 }
623
624 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
625 u32 len32)
626 {
627 struct dmae_command dmae;
628
629 if (!bp->dmae_ready) {
630 u32 *data = bnx2x_sp(bp, wb_data[0]);
631
632 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
633 " using indirect\n", dst_addr, len32);
634 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
635 return;
636 }
637
638 /* set opcode and fixed command fields */
639 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
640
641 /* fill in addresses and len */
642 dmae.src_addr_lo = U64_LO(dma_addr);
643 dmae.src_addr_hi = U64_HI(dma_addr);
644 dmae.dst_addr_lo = dst_addr >> 2;
645 dmae.dst_addr_hi = 0;
646 dmae.len = len32;
647
648 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
649
650 /* issue the command and wait for completion */
651 bnx2x_issue_dmae_with_comp(bp, &dmae);
652 }
653
654 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
655 {
656 struct dmae_command dmae;
657
658 if (!bp->dmae_ready) {
659 u32 *data = bnx2x_sp(bp, wb_data[0]);
660 int i;
661
662 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
663 " using indirect\n", src_addr, len32);
664 for (i = 0; i < len32; i++)
665 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
666 return;
667 }
668
669 /* set opcode and fixed command fields */
670 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
671
672 /* fill in addresses and len */
673 dmae.src_addr_lo = src_addr >> 2;
674 dmae.src_addr_hi = 0;
675 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
676 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
677 dmae.len = len32;
678
679 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
680
681 /* issue the command and wait for completion */
682 bnx2x_issue_dmae_with_comp(bp, &dmae);
683 }
684
685 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
686 u32 addr, u32 len)
687 {
688 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
689 int offset = 0;
690
691 while (len > dmae_wr_max) {
692 bnx2x_write_dmae(bp, phys_addr + offset,
693 addr + offset, dmae_wr_max);
694 offset += dmae_wr_max * 4;
695 len -= dmae_wr_max;
696 }
697
698 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
699 }
700
701 /* used only for slowpath so not inlined */
702 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
703 {
704 u32 wb_write[2];
705
706 wb_write[0] = val_hi;
707 wb_write[1] = val_lo;
708 REG_WR_DMAE(bp, reg, wb_write, 2);
709 }
710
711 #ifdef USE_WB_RD
712 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
713 {
714 u32 wb_data[2];
715
716 REG_RD_DMAE(bp, reg, wb_data, 2);
717
718 return HILO_U64(wb_data[0], wb_data[1]);
719 }
720 #endif
721
722 static int bnx2x_mc_assert(struct bnx2x *bp)
723 {
724 char last_idx;
725 int i, rc = 0;
726 u32 row0, row1, row2, row3;
727
728 /* XSTORM */
729 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
730 XSTORM_ASSERT_LIST_INDEX_OFFSET);
731 if (last_idx)
732 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
733
734 /* print the asserts */
735 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
736
737 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
738 XSTORM_ASSERT_LIST_OFFSET(i));
739 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
740 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
741 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
742 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
743 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
744 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
745
746 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
747 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
748 " 0x%08x 0x%08x 0x%08x\n",
749 i, row3, row2, row1, row0);
750 rc++;
751 } else {
752 break;
753 }
754 }
755
756 /* TSTORM */
757 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
758 TSTORM_ASSERT_LIST_INDEX_OFFSET);
759 if (last_idx)
760 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
761
762 /* print the asserts */
763 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
764
765 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
766 TSTORM_ASSERT_LIST_OFFSET(i));
767 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
768 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
769 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
770 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
771 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
772 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
773
774 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
775 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
776 " 0x%08x 0x%08x 0x%08x\n",
777 i, row3, row2, row1, row0);
778 rc++;
779 } else {
780 break;
781 }
782 }
783
784 /* CSTORM */
785 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
786 CSTORM_ASSERT_LIST_INDEX_OFFSET);
787 if (last_idx)
788 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
789
790 /* print the asserts */
791 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
792
793 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
794 CSTORM_ASSERT_LIST_OFFSET(i));
795 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
796 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
797 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
798 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
799 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
800 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
801
802 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
803 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
804 " 0x%08x 0x%08x 0x%08x\n",
805 i, row3, row2, row1, row0);
806 rc++;
807 } else {
808 break;
809 }
810 }
811
812 /* USTORM */
813 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
814 USTORM_ASSERT_LIST_INDEX_OFFSET);
815 if (last_idx)
816 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
817
818 /* print the asserts */
819 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
820
821 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
822 USTORM_ASSERT_LIST_OFFSET(i));
823 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
824 USTORM_ASSERT_LIST_OFFSET(i) + 4);
825 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
826 USTORM_ASSERT_LIST_OFFSET(i) + 8);
827 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
828 USTORM_ASSERT_LIST_OFFSET(i) + 12);
829
830 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
831 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
832 " 0x%08x 0x%08x 0x%08x\n",
833 i, row3, row2, row1, row0);
834 rc++;
835 } else {
836 break;
837 }
838 }
839
840 return rc;
841 }
842
843 static void bnx2x_fw_dump(struct bnx2x *bp)
844 {
845 u32 addr;
846 u32 mark, offset;
847 __be32 data[9];
848 int word;
849 u32 trace_shmem_base;
850 if (BP_NOMCP(bp)) {
851 BNX2X_ERR("NO MCP - can not dump\n");
852 return;
853 }
854
855 if (BP_PATH(bp) == 0)
856 trace_shmem_base = bp->common.shmem_base;
857 else
858 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
859 addr = trace_shmem_base - 0x0800 + 4;
860 mark = REG_RD(bp, addr);
861 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
862 + ((mark + 0x3) & ~0x3) - 0x08000000;
863 pr_err("begin fw dump (mark 0x%x)\n", mark);
864
865 pr_err("");
866 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
867 for (word = 0; word < 8; word++)
868 data[word] = htonl(REG_RD(bp, offset + 4*word));
869 data[8] = 0x0;
870 pr_cont("%s", (char *)data);
871 }
872 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
873 for (word = 0; word < 8; word++)
874 data[word] = htonl(REG_RD(bp, offset + 4*word));
875 data[8] = 0x0;
876 pr_cont("%s", (char *)data);
877 }
878 pr_err("end of fw dump\n");
879 }
880
881 void bnx2x_panic_dump(struct bnx2x *bp)
882 {
883 int i;
884 u16 j;
885 struct hc_sp_status_block_data sp_sb_data;
886 int func = BP_FUNC(bp);
887 #ifdef BNX2X_STOP_ON_ERROR
888 u16 start = 0, end = 0;
889 #endif
890
891 bp->stats_state = STATS_STATE_DISABLED;
892 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
893
894 BNX2X_ERR("begin crash dump -----------------\n");
895
896 /* Indices */
897 /* Common */
898 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
899 " spq_prod_idx(0x%x)\n",
900 bp->def_idx, bp->def_att_idx,
901 bp->attn_state, bp->spq_prod_idx);
902 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
903 bp->def_status_blk->atten_status_block.attn_bits,
904 bp->def_status_blk->atten_status_block.attn_bits_ack,
905 bp->def_status_blk->atten_status_block.status_block_id,
906 bp->def_status_blk->atten_status_block.attn_bits_index);
907 BNX2X_ERR(" def (");
908 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
909 pr_cont("0x%x%s",
910 bp->def_status_blk->sp_sb.index_values[i],
911 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
912
913 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
914 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
915 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
916 i*sizeof(u32));
917
918 pr_cont("igu_sb_id(0x%x) igu_seg_id (0x%x) "
919 "pf_id(0x%x) vnic_id(0x%x) "
920 "vf_id(0x%x) vf_valid (0x%x)\n",
921 sp_sb_data.igu_sb_id,
922 sp_sb_data.igu_seg_id,
923 sp_sb_data.p_func.pf_id,
924 sp_sb_data.p_func.vnic_id,
925 sp_sb_data.p_func.vf_id,
926 sp_sb_data.p_func.vf_valid);
927
928
929 for_each_eth_queue(bp, i) {
930 struct bnx2x_fastpath *fp = &bp->fp[i];
931 int loop;
932 struct hc_status_block_data_e2 sb_data_e2;
933 struct hc_status_block_data_e1x sb_data_e1x;
934 struct hc_status_block_sm *hc_sm_p =
935 CHIP_IS_E2(bp) ?
936 sb_data_e2.common.state_machine :
937 sb_data_e1x.common.state_machine;
938 struct hc_index_data *hc_index_p =
939 CHIP_IS_E2(bp) ?
940 sb_data_e2.index_data :
941 sb_data_e1x.index_data;
942 int data_size;
943 u32 *sb_data_p;
944
945 /* Rx */
946 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
947 " rx_comp_prod(0x%x)"
948 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
949 i, fp->rx_bd_prod, fp->rx_bd_cons,
950 fp->rx_comp_prod,
951 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
952 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
953 " fp_hc_idx(0x%x)\n",
954 fp->rx_sge_prod, fp->last_max_sge,
955 le16_to_cpu(fp->fp_hc_idx));
956
957 /* Tx */
958 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
959 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
960 " *tx_cons_sb(0x%x)\n",
961 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
962 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
963
964 loop = CHIP_IS_E2(bp) ?
965 HC_SB_MAX_INDICES_E2 : HC_SB_MAX_INDICES_E1X;
966
967 /* host sb data */
968
969 #ifdef BCM_CNIC
970 if (IS_FCOE_FP(fp))
971 continue;
972 #endif
973 BNX2X_ERR(" run indexes (");
974 for (j = 0; j < HC_SB_MAX_SM; j++)
975 pr_cont("0x%x%s",
976 fp->sb_running_index[j],
977 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
978
979 BNX2X_ERR(" indexes (");
980 for (j = 0; j < loop; j++)
981 pr_cont("0x%x%s",
982 fp->sb_index_values[j],
983 (j == loop - 1) ? ")" : " ");
984 /* fw sb data */
985 data_size = CHIP_IS_E2(bp) ?
986 sizeof(struct hc_status_block_data_e2) :
987 sizeof(struct hc_status_block_data_e1x);
988 data_size /= sizeof(u32);
989 sb_data_p = CHIP_IS_E2(bp) ?
990 (u32 *)&sb_data_e2 :
991 (u32 *)&sb_data_e1x;
992 /* copy sb data in here */
993 for (j = 0; j < data_size; j++)
994 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
995 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
996 j * sizeof(u32));
997
998 if (CHIP_IS_E2(bp)) {
999 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
1000 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
1001 sb_data_e2.common.p_func.pf_id,
1002 sb_data_e2.common.p_func.vf_id,
1003 sb_data_e2.common.p_func.vf_valid,
1004 sb_data_e2.common.p_func.vnic_id,
1005 sb_data_e2.common.same_igu_sb_1b);
1006 } else {
1007 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
1008 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
1009 sb_data_e1x.common.p_func.pf_id,
1010 sb_data_e1x.common.p_func.vf_id,
1011 sb_data_e1x.common.p_func.vf_valid,
1012 sb_data_e1x.common.p_func.vnic_id,
1013 sb_data_e1x.common.same_igu_sb_1b);
1014 }
1015
1016 /* SB_SMs data */
1017 for (j = 0; j < HC_SB_MAX_SM; j++) {
1018 pr_cont("SM[%d] __flags (0x%x) "
1019 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
1020 "time_to_expire (0x%x) "
1021 "timer_value(0x%x)\n", j,
1022 hc_sm_p[j].__flags,
1023 hc_sm_p[j].igu_sb_id,
1024 hc_sm_p[j].igu_seg_id,
1025 hc_sm_p[j].time_to_expire,
1026 hc_sm_p[j].timer_value);
1027 }
1028
1029 /* Indecies data */
1030 for (j = 0; j < loop; j++) {
1031 pr_cont("INDEX[%d] flags (0x%x) "
1032 "timeout (0x%x)\n", j,
1033 hc_index_p[j].flags,
1034 hc_index_p[j].timeout);
1035 }
1036 }
1037
1038 #ifdef BNX2X_STOP_ON_ERROR
1039 /* Rings */
1040 /* Rx */
1041 for_each_rx_queue(bp, i) {
1042 struct bnx2x_fastpath *fp = &bp->fp[i];
1043
1044 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1045 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1046 for (j = start; j != end; j = RX_BD(j + 1)) {
1047 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1048 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1049
1050 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1051 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
1052 }
1053
1054 start = RX_SGE(fp->rx_sge_prod);
1055 end = RX_SGE(fp->last_max_sge);
1056 for (j = start; j != end; j = RX_SGE(j + 1)) {
1057 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1058 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1059
1060 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1061 i, j, rx_sge[1], rx_sge[0], sw_page->page);
1062 }
1063
1064 start = RCQ_BD(fp->rx_comp_cons - 10);
1065 end = RCQ_BD(fp->rx_comp_cons + 503);
1066 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1067 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1068
1069 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1070 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1071 }
1072 }
1073
1074 /* Tx */
1075 for_each_tx_queue(bp, i) {
1076 struct bnx2x_fastpath *fp = &bp->fp[i];
1077
1078 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
1079 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
1080 for (j = start; j != end; j = TX_BD(j + 1)) {
1081 struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
1082
1083 BNX2X_ERR("fp%d: packet[%x]=[%p,%x]\n",
1084 i, j, sw_bd->skb, sw_bd->first_bd);
1085 }
1086
1087 start = TX_BD(fp->tx_bd_cons - 10);
1088 end = TX_BD(fp->tx_bd_cons + 254);
1089 for (j = start; j != end; j = TX_BD(j + 1)) {
1090 u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
1091
1092 BNX2X_ERR("fp%d: tx_bd[%x]=[%x:%x:%x:%x]\n",
1093 i, j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
1094 }
1095 }
1096 #endif
1097 bnx2x_fw_dump(bp);
1098 bnx2x_mc_assert(bp);
1099 BNX2X_ERR("end crash dump -----------------\n");
1100 }
1101
1102 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1103 {
1104 int port = BP_PORT(bp);
1105 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1106 u32 val = REG_RD(bp, addr);
1107 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1108 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1109
1110 if (msix) {
1111 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1112 HC_CONFIG_0_REG_INT_LINE_EN_0);
1113 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1114 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1115 } else if (msi) {
1116 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1117 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1118 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1119 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1120 } else {
1121 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1122 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1123 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1124 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1125
1126 if (!CHIP_IS_E1(bp)) {
1127 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1128 val, port, addr);
1129
1130 REG_WR(bp, addr, val);
1131
1132 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1133 }
1134 }
1135
1136 if (CHIP_IS_E1(bp))
1137 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1138
1139 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1140 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1141
1142 REG_WR(bp, addr, val);
1143 /*
1144 * Ensure that HC_CONFIG is written before leading/trailing edge config
1145 */
1146 mmiowb();
1147 barrier();
1148
1149 if (!CHIP_IS_E1(bp)) {
1150 /* init leading/trailing edge */
1151 if (IS_MF(bp)) {
1152 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1153 if (bp->port.pmf)
1154 /* enable nig and gpio3 attention */
1155 val |= 0x1100;
1156 } else
1157 val = 0xffff;
1158
1159 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1160 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1161 }
1162
1163 /* Make sure that interrupts are indeed enabled from here on */
1164 mmiowb();
1165 }
1166
1167 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1168 {
1169 u32 val;
1170 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1171 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1172
1173 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1174
1175 if (msix) {
1176 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1177 IGU_PF_CONF_SINGLE_ISR_EN);
1178 val |= (IGU_PF_CONF_FUNC_EN |
1179 IGU_PF_CONF_MSI_MSIX_EN |
1180 IGU_PF_CONF_ATTN_BIT_EN);
1181 } else if (msi) {
1182 val &= ~IGU_PF_CONF_INT_LINE_EN;
1183 val |= (IGU_PF_CONF_FUNC_EN |
1184 IGU_PF_CONF_MSI_MSIX_EN |
1185 IGU_PF_CONF_ATTN_BIT_EN |
1186 IGU_PF_CONF_SINGLE_ISR_EN);
1187 } else {
1188 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1189 val |= (IGU_PF_CONF_FUNC_EN |
1190 IGU_PF_CONF_INT_LINE_EN |
1191 IGU_PF_CONF_ATTN_BIT_EN |
1192 IGU_PF_CONF_SINGLE_ISR_EN);
1193 }
1194
1195 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1196 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1197
1198 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1199
1200 barrier();
1201
1202 /* init leading/trailing edge */
1203 if (IS_MF(bp)) {
1204 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1205 if (bp->port.pmf)
1206 /* enable nig and gpio3 attention */
1207 val |= 0x1100;
1208 } else
1209 val = 0xffff;
1210
1211 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1212 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1213
1214 /* Make sure that interrupts are indeed enabled from here on */
1215 mmiowb();
1216 }
1217
1218 void bnx2x_int_enable(struct bnx2x *bp)
1219 {
1220 if (bp->common.int_block == INT_BLOCK_HC)
1221 bnx2x_hc_int_enable(bp);
1222 else
1223 bnx2x_igu_int_enable(bp);
1224 }
1225
1226 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1227 {
1228 int port = BP_PORT(bp);
1229 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1230 u32 val = REG_RD(bp, addr);
1231
1232 /*
1233 * in E1 we must use only PCI configuration space to disable
1234 * MSI/MSIX capablility
1235 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1236 */
1237 if (CHIP_IS_E1(bp)) {
1238 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1239 * Use mask register to prevent from HC sending interrupts
1240 * after we exit the function
1241 */
1242 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1243
1244 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1245 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1246 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1247 } else
1248 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1249 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1250 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1251 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1252
1253 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1254 val, port, addr);
1255
1256 /* flush all outstanding writes */
1257 mmiowb();
1258
1259 REG_WR(bp, addr, val);
1260 if (REG_RD(bp, addr) != val)
1261 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1262 }
1263
1264 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1265 {
1266 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1267
1268 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1269 IGU_PF_CONF_INT_LINE_EN |
1270 IGU_PF_CONF_ATTN_BIT_EN);
1271
1272 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1273
1274 /* flush all outstanding writes */
1275 mmiowb();
1276
1277 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1278 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1279 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1280 }
1281
1282 static void bnx2x_int_disable(struct bnx2x *bp)
1283 {
1284 if (bp->common.int_block == INT_BLOCK_HC)
1285 bnx2x_hc_int_disable(bp);
1286 else
1287 bnx2x_igu_int_disable(bp);
1288 }
1289
1290 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1291 {
1292 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1293 int i, offset;
1294
1295 /* disable interrupt handling */
1296 atomic_inc(&bp->intr_sem);
1297 smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
1298
1299 if (disable_hw)
1300 /* prevent the HW from sending interrupts */
1301 bnx2x_int_disable(bp);
1302
1303 /* make sure all ISRs are done */
1304 if (msix) {
1305 synchronize_irq(bp->msix_table[0].vector);
1306 offset = 1;
1307 #ifdef BCM_CNIC
1308 offset++;
1309 #endif
1310 for_each_eth_queue(bp, i)
1311 synchronize_irq(bp->msix_table[i + offset].vector);
1312 } else
1313 synchronize_irq(bp->pdev->irq);
1314
1315 /* make sure sp_task is not running */
1316 cancel_delayed_work(&bp->sp_task);
1317 flush_workqueue(bnx2x_wq);
1318 }
1319
1320 /* fast path */
1321
1322 /*
1323 * General service functions
1324 */
1325
1326 /* Return true if succeeded to acquire the lock */
1327 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1328 {
1329 u32 lock_status;
1330 u32 resource_bit = (1 << resource);
1331 int func = BP_FUNC(bp);
1332 u32 hw_lock_control_reg;
1333
1334 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1335
1336 /* Validating that the resource is within range */
1337 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1338 DP(NETIF_MSG_HW,
1339 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1340 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1341 return false;
1342 }
1343
1344 if (func <= 5)
1345 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1346 else
1347 hw_lock_control_reg =
1348 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1349
1350 /* Try to acquire the lock */
1351 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1352 lock_status = REG_RD(bp, hw_lock_control_reg);
1353 if (lock_status & resource_bit)
1354 return true;
1355
1356 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1357 return false;
1358 }
1359
1360 #ifdef BCM_CNIC
1361 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid);
1362 #endif
1363
1364 void bnx2x_sp_event(struct bnx2x_fastpath *fp,
1365 union eth_rx_cqe *rr_cqe)
1366 {
1367 struct bnx2x *bp = fp->bp;
1368 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1369 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1370
1371 DP(BNX2X_MSG_SP,
1372 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1373 fp->index, cid, command, bp->state,
1374 rr_cqe->ramrod_cqe.ramrod_type);
1375
1376 switch (command | fp->state) {
1377 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP | BNX2X_FP_STATE_OPENING):
1378 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n", cid);
1379 fp->state = BNX2X_FP_STATE_OPEN;
1380 break;
1381
1382 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
1383 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n", cid);
1384 fp->state = BNX2X_FP_STATE_HALTED;
1385 break;
1386
1387 case (RAMROD_CMD_ID_ETH_TERMINATE | BNX2X_FP_STATE_TERMINATING):
1388 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] teminate ramrod\n", cid);
1389 fp->state = BNX2X_FP_STATE_TERMINATED;
1390 break;
1391
1392 default:
1393 BNX2X_ERR("unexpected MC reply (%d) "
1394 "fp[%d] state is %x\n",
1395 command, fp->index, fp->state);
1396 break;
1397 }
1398
1399 smp_mb__before_atomic_inc();
1400 atomic_inc(&bp->spq_left);
1401 /* push the change in fp->state and towards the memory */
1402 smp_wmb();
1403
1404 return;
1405 }
1406
1407 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1408 {
1409 struct bnx2x *bp = netdev_priv(dev_instance);
1410 u16 status = bnx2x_ack_int(bp);
1411 u16 mask;
1412 int i;
1413
1414 /* Return here if interrupt is shared and it's not for us */
1415 if (unlikely(status == 0)) {
1416 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1417 return IRQ_NONE;
1418 }
1419 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1420
1421 /* Return here if interrupt is disabled */
1422 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1423 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1424 return IRQ_HANDLED;
1425 }
1426
1427 #ifdef BNX2X_STOP_ON_ERROR
1428 if (unlikely(bp->panic))
1429 return IRQ_HANDLED;
1430 #endif
1431
1432 for_each_eth_queue(bp, i) {
1433 struct bnx2x_fastpath *fp = &bp->fp[i];
1434
1435 mask = 0x2 << (fp->index + CNIC_CONTEXT_USE);
1436 if (status & mask) {
1437 /* Handle Rx and Tx according to SB id */
1438 prefetch(fp->rx_cons_sb);
1439 prefetch(fp->tx_cons_sb);
1440 prefetch(&fp->sb_running_index[SM_RX_ID]);
1441 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1442 status &= ~mask;
1443 }
1444 }
1445
1446 #ifdef BCM_CNIC
1447 mask = 0x2;
1448 if (status & (mask | 0x1)) {
1449 struct cnic_ops *c_ops = NULL;
1450
1451 rcu_read_lock();
1452 c_ops = rcu_dereference(bp->cnic_ops);
1453 if (c_ops)
1454 c_ops->cnic_handler(bp->cnic_data, NULL);
1455 rcu_read_unlock();
1456
1457 status &= ~mask;
1458 }
1459 #endif
1460
1461 if (unlikely(status & 0x1)) {
1462 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1463
1464 status &= ~0x1;
1465 if (!status)
1466 return IRQ_HANDLED;
1467 }
1468
1469 if (unlikely(status))
1470 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1471 status);
1472
1473 return IRQ_HANDLED;
1474 }
1475
1476 /* end of fast path */
1477
1478
1479 /* Link */
1480
1481 /*
1482 * General service functions
1483 */
1484
1485 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1486 {
1487 u32 lock_status;
1488 u32 resource_bit = (1 << resource);
1489 int func = BP_FUNC(bp);
1490 u32 hw_lock_control_reg;
1491 int cnt;
1492
1493 /* Validating that the resource is within range */
1494 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1495 DP(NETIF_MSG_HW,
1496 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1497 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1498 return -EINVAL;
1499 }
1500
1501 if (func <= 5) {
1502 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1503 } else {
1504 hw_lock_control_reg =
1505 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1506 }
1507
1508 /* Validating that the resource is not already taken */
1509 lock_status = REG_RD(bp, hw_lock_control_reg);
1510 if (lock_status & resource_bit) {
1511 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1512 lock_status, resource_bit);
1513 return -EEXIST;
1514 }
1515
1516 /* Try for 5 second every 5ms */
1517 for (cnt = 0; cnt < 1000; cnt++) {
1518 /* Try to acquire the lock */
1519 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1520 lock_status = REG_RD(bp, hw_lock_control_reg);
1521 if (lock_status & resource_bit)
1522 return 0;
1523
1524 msleep(5);
1525 }
1526 DP(NETIF_MSG_HW, "Timeout\n");
1527 return -EAGAIN;
1528 }
1529
1530 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1531 {
1532 u32 lock_status;
1533 u32 resource_bit = (1 << resource);
1534 int func = BP_FUNC(bp);
1535 u32 hw_lock_control_reg;
1536
1537 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1538
1539 /* Validating that the resource is within range */
1540 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1541 DP(NETIF_MSG_HW,
1542 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1543 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1544 return -EINVAL;
1545 }
1546
1547 if (func <= 5) {
1548 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1549 } else {
1550 hw_lock_control_reg =
1551 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1552 }
1553
1554 /* Validating that the resource is currently taken */
1555 lock_status = REG_RD(bp, hw_lock_control_reg);
1556 if (!(lock_status & resource_bit)) {
1557 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1558 lock_status, resource_bit);
1559 return -EFAULT;
1560 }
1561
1562 REG_WR(bp, hw_lock_control_reg, resource_bit);
1563 return 0;
1564 }
1565
1566
1567 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1568 {
1569 /* The GPIO should be swapped if swap register is set and active */
1570 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1571 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1572 int gpio_shift = gpio_num +
1573 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1574 u32 gpio_mask = (1 << gpio_shift);
1575 u32 gpio_reg;
1576 int value;
1577
1578 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1579 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1580 return -EINVAL;
1581 }
1582
1583 /* read GPIO value */
1584 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1585
1586 /* get the requested pin value */
1587 if ((gpio_reg & gpio_mask) == gpio_mask)
1588 value = 1;
1589 else
1590 value = 0;
1591
1592 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1593
1594 return value;
1595 }
1596
1597 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1598 {
1599 /* The GPIO should be swapped if swap register is set and active */
1600 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1601 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1602 int gpio_shift = gpio_num +
1603 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1604 u32 gpio_mask = (1 << gpio_shift);
1605 u32 gpio_reg;
1606
1607 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1608 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1609 return -EINVAL;
1610 }
1611
1612 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1613 /* read GPIO and mask except the float bits */
1614 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1615
1616 switch (mode) {
1617 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1618 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1619 gpio_num, gpio_shift);
1620 /* clear FLOAT and set CLR */
1621 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1622 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1623 break;
1624
1625 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1626 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1627 gpio_num, gpio_shift);
1628 /* clear FLOAT and set SET */
1629 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1630 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1631 break;
1632
1633 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1634 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1635 gpio_num, gpio_shift);
1636 /* set FLOAT */
1637 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1638 break;
1639
1640 default:
1641 break;
1642 }
1643
1644 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1645 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1646
1647 return 0;
1648 }
1649
1650 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1651 {
1652 /* The GPIO should be swapped if swap register is set and active */
1653 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1654 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1655 int gpio_shift = gpio_num +
1656 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1657 u32 gpio_mask = (1 << gpio_shift);
1658 u32 gpio_reg;
1659
1660 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1661 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1662 return -EINVAL;
1663 }
1664
1665 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1666 /* read GPIO int */
1667 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
1668
1669 switch (mode) {
1670 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
1671 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
1672 "output low\n", gpio_num, gpio_shift);
1673 /* clear SET and set CLR */
1674 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1675 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1676 break;
1677
1678 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
1679 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
1680 "output high\n", gpio_num, gpio_shift);
1681 /* clear CLR and set SET */
1682 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1683 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1684 break;
1685
1686 default:
1687 break;
1688 }
1689
1690 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
1691 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1692
1693 return 0;
1694 }
1695
1696 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1697 {
1698 u32 spio_mask = (1 << spio_num);
1699 u32 spio_reg;
1700
1701 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1702 (spio_num > MISC_REGISTERS_SPIO_7)) {
1703 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
1704 return -EINVAL;
1705 }
1706
1707 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1708 /* read SPIO and mask except the float bits */
1709 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
1710
1711 switch (mode) {
1712 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
1713 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1714 /* clear FLOAT and set CLR */
1715 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1716 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1717 break;
1718
1719 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
1720 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1721 /* clear FLOAT and set SET */
1722 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1723 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
1724 break;
1725
1726 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
1727 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
1728 /* set FLOAT */
1729 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1730 break;
1731
1732 default:
1733 break;
1734 }
1735
1736 REG_WR(bp, MISC_REG_SPIO, spio_reg);
1737 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1738
1739 return 0;
1740 }
1741
1742 int bnx2x_get_link_cfg_idx(struct bnx2x *bp)
1743 {
1744 u32 sel_phy_idx = 0;
1745 if (bp->link_vars.link_up) {
1746 sel_phy_idx = EXT_PHY1;
1747 /* In case link is SERDES, check if the EXT_PHY2 is the one */
1748 if ((bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
1749 (bp->link_params.phy[EXT_PHY2].supported & SUPPORTED_FIBRE))
1750 sel_phy_idx = EXT_PHY2;
1751 } else {
1752
1753 switch (bnx2x_phy_selection(&bp->link_params)) {
1754 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
1755 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
1756 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
1757 sel_phy_idx = EXT_PHY1;
1758 break;
1759 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
1760 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
1761 sel_phy_idx = EXT_PHY2;
1762 break;
1763 }
1764 }
1765 /*
1766 * The selected actived PHY is always after swapping (in case PHY
1767 * swapping is enabled). So when swapping is enabled, we need to reverse
1768 * the configuration
1769 */
1770
1771 if (bp->link_params.multi_phy_config &
1772 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
1773 if (sel_phy_idx == EXT_PHY1)
1774 sel_phy_idx = EXT_PHY2;
1775 else if (sel_phy_idx == EXT_PHY2)
1776 sel_phy_idx = EXT_PHY1;
1777 }
1778 return LINK_CONFIG_IDX(sel_phy_idx);
1779 }
1780
1781 void bnx2x_calc_fc_adv(struct bnx2x *bp)
1782 {
1783 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1784 switch (bp->link_vars.ieee_fc &
1785 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
1786 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
1787 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
1788 ADVERTISED_Pause);
1789 break;
1790
1791 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
1792 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
1793 ADVERTISED_Pause);
1794 break;
1795
1796 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
1797 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
1798 break;
1799
1800 default:
1801 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
1802 ADVERTISED_Pause);
1803 break;
1804 }
1805 }
1806
1807 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
1808 {
1809 if (!BP_NOMCP(bp)) {
1810 u8 rc;
1811 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
1812 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
1813 /* Initialize link parameters structure variables */
1814 /* It is recommended to turn off RX FC for jumbo frames
1815 for better performance */
1816 if ((CHIP_IS_E1x(bp)) && (bp->dev->mtu > 5000))
1817 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
1818 else
1819 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
1820
1821 bnx2x_acquire_phy_lock(bp);
1822
1823 if (load_mode == LOAD_DIAG) {
1824 bp->link_params.loopback_mode = LOOPBACK_XGXS;
1825 bp->link_params.req_line_speed[cfx_idx] = SPEED_10000;
1826 }
1827
1828 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1829
1830 bnx2x_release_phy_lock(bp);
1831
1832 bnx2x_calc_fc_adv(bp);
1833
1834 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
1835 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
1836 bnx2x_link_report(bp);
1837 }
1838 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
1839 return rc;
1840 }
1841 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
1842 return -EINVAL;
1843 }
1844
1845 void bnx2x_link_set(struct bnx2x *bp)
1846 {
1847 if (!BP_NOMCP(bp)) {
1848 bnx2x_acquire_phy_lock(bp);
1849 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
1850 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1851 bnx2x_release_phy_lock(bp);
1852
1853 bnx2x_calc_fc_adv(bp);
1854 } else
1855 BNX2X_ERR("Bootcode is missing - can not set link\n");
1856 }
1857
1858 static void bnx2x__link_reset(struct bnx2x *bp)
1859 {
1860 if (!BP_NOMCP(bp)) {
1861 bnx2x_acquire_phy_lock(bp);
1862 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
1863 bnx2x_release_phy_lock(bp);
1864 } else
1865 BNX2X_ERR("Bootcode is missing - can not reset link\n");
1866 }
1867
1868 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
1869 {
1870 u8 rc = 0;
1871
1872 if (!BP_NOMCP(bp)) {
1873 bnx2x_acquire_phy_lock(bp);
1874 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
1875 is_serdes);
1876 bnx2x_release_phy_lock(bp);
1877 } else
1878 BNX2X_ERR("Bootcode is missing - can not test link\n");
1879
1880 return rc;
1881 }
1882
1883 static void bnx2x_init_port_minmax(struct bnx2x *bp)
1884 {
1885 u32 r_param = bp->link_vars.line_speed / 8;
1886 u32 fair_periodic_timeout_usec;
1887 u32 t_fair;
1888
1889 memset(&(bp->cmng.rs_vars), 0,
1890 sizeof(struct rate_shaping_vars_per_port));
1891 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
1892
1893 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
1894 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
1895
1896 /* this is the threshold below which no timer arming will occur
1897 1.25 coefficient is for the threshold to be a little bigger
1898 than the real time, to compensate for timer in-accuracy */
1899 bp->cmng.rs_vars.rs_threshold =
1900 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
1901
1902 /* resolution of fairness timer */
1903 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
1904 /* for 10G it is 1000usec. for 1G it is 10000usec. */
1905 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
1906
1907 /* this is the threshold below which we won't arm the timer anymore */
1908 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
1909
1910 /* we multiply by 1e3/8 to get bytes/msec.
1911 We don't want the credits to pass a credit
1912 of the t_fair*FAIR_MEM (algorithm resolution) */
1913 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
1914 /* since each tick is 4 usec */
1915 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
1916 }
1917
1918 /* Calculates the sum of vn_min_rates.
1919 It's needed for further normalizing of the min_rates.
1920 Returns:
1921 sum of vn_min_rates.
1922 or
1923 0 - if all the min_rates are 0.
1924 In the later case fainess algorithm should be deactivated.
1925 If not all min_rates are zero then those that are zeroes will be set to 1.
1926 */
1927 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
1928 {
1929 int all_zero = 1;
1930 int vn;
1931
1932 bp->vn_weight_sum = 0;
1933 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
1934 u32 vn_cfg = bp->mf_config[vn];
1935 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1936 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
1937
1938 /* Skip hidden vns */
1939 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
1940 continue;
1941
1942 /* If min rate is zero - set it to 1 */
1943 if (!vn_min_rate)
1944 vn_min_rate = DEF_MIN_RATE;
1945 else
1946 all_zero = 0;
1947
1948 bp->vn_weight_sum += vn_min_rate;
1949 }
1950
1951 /* ... only if all min rates are zeros - disable fairness */
1952 if (all_zero) {
1953 bp->cmng.flags.cmng_enables &=
1954 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
1955 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
1956 " fairness will be disabled\n");
1957 } else
1958 bp->cmng.flags.cmng_enables |=
1959 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
1960 }
1961
1962 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
1963 {
1964 struct rate_shaping_vars_per_vn m_rs_vn;
1965 struct fairness_vars_per_vn m_fair_vn;
1966 u32 vn_cfg = bp->mf_config[vn];
1967 int func = 2*vn + BP_PORT(bp);
1968 u16 vn_min_rate, vn_max_rate;
1969 int i;
1970
1971 /* If function is hidden - set min and max to zeroes */
1972 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
1973 vn_min_rate = 0;
1974 vn_max_rate = 0;
1975
1976 } else {
1977 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1978 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
1979 /* If min rate is zero - set it to 1 */
1980 if (bp->vn_weight_sum && (vn_min_rate == 0))
1981 vn_min_rate = DEF_MIN_RATE;
1982 vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
1983 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
1984 }
1985
1986 DP(NETIF_MSG_IFUP,
1987 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
1988 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
1989
1990 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
1991 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
1992
1993 /* global vn counter - maximal Mbps for this vn */
1994 m_rs_vn.vn_counter.rate = vn_max_rate;
1995
1996 /* quota - number of bytes transmitted in this period */
1997 m_rs_vn.vn_counter.quota =
1998 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
1999
2000 if (bp->vn_weight_sum) {
2001 /* credit for each period of the fairness algorithm:
2002 number of bytes in T_FAIR (the vn share the port rate).
2003 vn_weight_sum should not be larger than 10000, thus
2004 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2005 than zero */
2006 m_fair_vn.vn_credit_delta =
2007 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2008 (8 * bp->vn_weight_sum))),
2009 (bp->cmng.fair_vars.fair_threshold * 2));
2010 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
2011 m_fair_vn.vn_credit_delta);
2012 }
2013
2014 /* Store it to internal memory */
2015 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2016 REG_WR(bp, BAR_XSTRORM_INTMEM +
2017 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2018 ((u32 *)(&m_rs_vn))[i]);
2019
2020 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2021 REG_WR(bp, BAR_XSTRORM_INTMEM +
2022 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2023 ((u32 *)(&m_fair_vn))[i]);
2024 }
2025
2026 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2027 {
2028 if (CHIP_REV_IS_SLOW(bp))
2029 return CMNG_FNS_NONE;
2030 if (IS_MF(bp))
2031 return CMNG_FNS_MINMAX;
2032
2033 return CMNG_FNS_NONE;
2034 }
2035
2036 static void bnx2x_read_mf_cfg(struct bnx2x *bp)
2037 {
2038 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2039
2040 if (BP_NOMCP(bp))
2041 return; /* what should be the default bvalue in this case */
2042
2043 /* For 2 port configuration the absolute function number formula
2044 * is:
2045 * abs_func = 2 * vn + BP_PORT + BP_PATH
2046 *
2047 * and there are 4 functions per port
2048 *
2049 * For 4 port configuration it is
2050 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2051 *
2052 * and there are 2 functions per port
2053 */
2054 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2055 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2056
2057 if (func >= E1H_FUNC_MAX)
2058 break;
2059
2060 bp->mf_config[vn] =
2061 MF_CFG_RD(bp, func_mf_config[func].config);
2062 }
2063 }
2064
2065 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2066 {
2067
2068 if (cmng_type == CMNG_FNS_MINMAX) {
2069 int vn;
2070
2071 /* clear cmng_enables */
2072 bp->cmng.flags.cmng_enables = 0;
2073
2074 /* read mf conf from shmem */
2075 if (read_cfg)
2076 bnx2x_read_mf_cfg(bp);
2077
2078 /* Init rate shaping and fairness contexts */
2079 bnx2x_init_port_minmax(bp);
2080
2081 /* vn_weight_sum and enable fairness if not 0 */
2082 bnx2x_calc_vn_weight_sum(bp);
2083
2084 /* calculate and set min-max rate for each vn */
2085 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2086 bnx2x_init_vn_minmax(bp, vn);
2087
2088 /* always enable rate shaping and fairness */
2089 bp->cmng.flags.cmng_enables |=
2090 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2091 if (!bp->vn_weight_sum)
2092 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2093 " fairness will be disabled\n");
2094 return;
2095 }
2096
2097 /* rate shaping and fairness are disabled */
2098 DP(NETIF_MSG_IFUP,
2099 "rate shaping and fairness are disabled\n");
2100 }
2101
2102 static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2103 {
2104 int port = BP_PORT(bp);
2105 int func;
2106 int vn;
2107
2108 /* Set the attention towards other drivers on the same port */
2109 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2110 if (vn == BP_E1HVN(bp))
2111 continue;
2112
2113 func = ((vn << 1) | port);
2114 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2115 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2116 }
2117 }
2118
2119 /* This function is called upon link interrupt */
2120 static void bnx2x_link_attn(struct bnx2x *bp)
2121 {
2122 u32 prev_link_status = bp->link_vars.link_status;
2123 /* Make sure that we are synced with the current statistics */
2124 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2125
2126 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2127
2128 if (bp->link_vars.link_up) {
2129
2130 /* dropless flow control */
2131 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2132 int port = BP_PORT(bp);
2133 u32 pause_enabled = 0;
2134
2135 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2136 pause_enabled = 1;
2137
2138 REG_WR(bp, BAR_USTRORM_INTMEM +
2139 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2140 pause_enabled);
2141 }
2142
2143 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
2144 struct host_port_stats *pstats;
2145
2146 pstats = bnx2x_sp(bp, port_stats);
2147 /* reset old bmac stats */
2148 memset(&(pstats->mac_stx[0]), 0,
2149 sizeof(struct mac_stx));
2150 }
2151 if (bp->state == BNX2X_STATE_OPEN)
2152 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2153 }
2154
2155 /* indicate link status only if link status actually changed */
2156 if (prev_link_status != bp->link_vars.link_status)
2157 bnx2x_link_report(bp);
2158
2159 if (IS_MF(bp))
2160 bnx2x_link_sync_notify(bp);
2161
2162 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2163 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2164
2165 if (cmng_fns != CMNG_FNS_NONE) {
2166 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2167 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2168 } else
2169 /* rate shaping and fairness are disabled */
2170 DP(NETIF_MSG_IFUP,
2171 "single function mode without fairness\n");
2172 }
2173 }
2174
2175 void bnx2x__link_status_update(struct bnx2x *bp)
2176 {
2177 if ((bp->state != BNX2X_STATE_OPEN) || (bp->flags & MF_FUNC_DIS))
2178 return;
2179
2180 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2181
2182 if (bp->link_vars.link_up)
2183 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2184 else
2185 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2186
2187 /* the link status update could be the result of a DCC event
2188 hence re-read the shmem mf configuration */
2189 bnx2x_read_mf_cfg(bp);
2190
2191 /* indicate link status */
2192 bnx2x_link_report(bp);
2193 }
2194
2195 static void bnx2x_pmf_update(struct bnx2x *bp)
2196 {
2197 int port = BP_PORT(bp);
2198 u32 val;
2199
2200 bp->port.pmf = 1;
2201 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2202
2203 /* enable nig attention */
2204 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
2205 if (bp->common.int_block == INT_BLOCK_HC) {
2206 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2207 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2208 } else if (CHIP_IS_E2(bp)) {
2209 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2210 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2211 }
2212
2213 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2214 }
2215
2216 /* end of Link */
2217
2218 /* slow path */
2219
2220 /*
2221 * General service functions
2222 */
2223
2224 /* send the MCP a request, block until there is a reply */
2225 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2226 {
2227 int mb_idx = BP_FW_MB_IDX(bp);
2228 u32 seq = ++bp->fw_seq;
2229 u32 rc = 0;
2230 u32 cnt = 1;
2231 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2232
2233 mutex_lock(&bp->fw_mb_mutex);
2234 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2235 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2236
2237 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
2238
2239 do {
2240 /* let the FW do it's magic ... */
2241 msleep(delay);
2242
2243 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2244
2245 /* Give the FW up to 5 second (500*10ms) */
2246 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2247
2248 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2249 cnt*delay, rc, seq);
2250
2251 /* is this a reply to our command? */
2252 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2253 rc &= FW_MSG_CODE_MASK;
2254 else {
2255 /* FW BUG! */
2256 BNX2X_ERR("FW failed to respond!\n");
2257 bnx2x_fw_dump(bp);
2258 rc = 0;
2259 }
2260 mutex_unlock(&bp->fw_mb_mutex);
2261
2262 return rc;
2263 }
2264
2265 static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2266 {
2267 #ifdef BCM_CNIC
2268 if (IS_FCOE_FP(fp) && IS_MF(bp))
2269 return false;
2270 #endif
2271 return true;
2272 }
2273
2274 /* must be called under rtnl_lock */
2275 static void bnx2x_rxq_set_mac_filters(struct bnx2x *bp, u16 cl_id, u32 filters)
2276 {
2277 u32 mask = (1 << cl_id);
2278
2279 /* initial seeting is BNX2X_ACCEPT_NONE */
2280 u8 drop_all_ucast = 1, drop_all_bcast = 1, drop_all_mcast = 1;
2281 u8 accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0;
2282 u8 unmatched_unicast = 0;
2283
2284 if (filters & BNX2X_ACCEPT_UNMATCHED_UCAST)
2285 unmatched_unicast = 1;
2286
2287 if (filters & BNX2X_PROMISCUOUS_MODE) {
2288 /* promiscious - accept all, drop none */
2289 drop_all_ucast = drop_all_bcast = drop_all_mcast = 0;
2290 accp_all_ucast = accp_all_bcast = accp_all_mcast = 1;
2291 if (IS_MF_SI(bp)) {
2292 /*
2293 * SI mode defines to accept in promiscuos mode
2294 * only unmatched packets
2295 */
2296 unmatched_unicast = 1;
2297 accp_all_ucast = 0;
2298 }
2299 }
2300 if (filters & BNX2X_ACCEPT_UNICAST) {
2301 /* accept matched ucast */
2302 drop_all_ucast = 0;
2303 }
2304 if (filters & BNX2X_ACCEPT_MULTICAST) {
2305 /* accept matched mcast */
2306 drop_all_mcast = 0;
2307 if (IS_MF_SI(bp))
2308 /* since mcast addresses won't arrive with ovlan,
2309 * fw needs to accept all of them in
2310 * switch-independent mode */
2311 accp_all_mcast = 1;
2312 }
2313 if (filters & BNX2X_ACCEPT_ALL_UNICAST) {
2314 /* accept all mcast */
2315 drop_all_ucast = 0;
2316 accp_all_ucast = 1;
2317 }
2318 if (filters & BNX2X_ACCEPT_ALL_MULTICAST) {
2319 /* accept all mcast */
2320 drop_all_mcast = 0;
2321 accp_all_mcast = 1;
2322 }
2323 if (filters & BNX2X_ACCEPT_BROADCAST) {
2324 /* accept (all) bcast */
2325 drop_all_bcast = 0;
2326 accp_all_bcast = 1;
2327 }
2328
2329 bp->mac_filters.ucast_drop_all = drop_all_ucast ?
2330 bp->mac_filters.ucast_drop_all | mask :
2331 bp->mac_filters.ucast_drop_all & ~mask;
2332
2333 bp->mac_filters.mcast_drop_all = drop_all_mcast ?
2334 bp->mac_filters.mcast_drop_all | mask :
2335 bp->mac_filters.mcast_drop_all & ~mask;
2336
2337 bp->mac_filters.bcast_drop_all = drop_all_bcast ?
2338 bp->mac_filters.bcast_drop_all | mask :
2339 bp->mac_filters.bcast_drop_all & ~mask;
2340
2341 bp->mac_filters.ucast_accept_all = accp_all_ucast ?
2342 bp->mac_filters.ucast_accept_all | mask :
2343 bp->mac_filters.ucast_accept_all & ~mask;
2344
2345 bp->mac_filters.mcast_accept_all = accp_all_mcast ?
2346 bp->mac_filters.mcast_accept_all | mask :
2347 bp->mac_filters.mcast_accept_all & ~mask;
2348
2349 bp->mac_filters.bcast_accept_all = accp_all_bcast ?
2350 bp->mac_filters.bcast_accept_all | mask :
2351 bp->mac_filters.bcast_accept_all & ~mask;
2352
2353 bp->mac_filters.unmatched_unicast = unmatched_unicast ?
2354 bp->mac_filters.unmatched_unicast | mask :
2355 bp->mac_filters.unmatched_unicast & ~mask;
2356 }
2357
2358 static void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2359 {
2360 struct tstorm_eth_function_common_config tcfg = {0};
2361 u16 rss_flgs;
2362
2363 /* tpa */
2364 if (p->func_flgs & FUNC_FLG_TPA)
2365 tcfg.config_flags |=
2366 TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA;
2367
2368 /* set rss flags */
2369 rss_flgs = (p->rss->mode <<
2370 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT);
2371
2372 if (p->rss->cap & RSS_IPV4_CAP)
2373 rss_flgs |= RSS_IPV4_CAP_MASK;
2374 if (p->rss->cap & RSS_IPV4_TCP_CAP)
2375 rss_flgs |= RSS_IPV4_TCP_CAP_MASK;
2376 if (p->rss->cap & RSS_IPV6_CAP)
2377 rss_flgs |= RSS_IPV6_CAP_MASK;
2378 if (p->rss->cap & RSS_IPV6_TCP_CAP)
2379 rss_flgs |= RSS_IPV6_TCP_CAP_MASK;
2380
2381 tcfg.config_flags |= rss_flgs;
2382 tcfg.rss_result_mask = p->rss->result_mask;
2383
2384 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2385
2386 /* Enable the function in the FW */
2387 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2388 storm_memset_func_en(bp, p->func_id, 1);
2389
2390 /* statistics */
2391 if (p->func_flgs & FUNC_FLG_STATS) {
2392 struct stats_indication_flags stats_flags = {0};
2393 stats_flags.collect_eth = 1;
2394
2395 storm_memset_xstats_flags(bp, &stats_flags, p->func_id);
2396 storm_memset_xstats_addr(bp, p->fw_stat_map, p->func_id);
2397
2398 storm_memset_tstats_flags(bp, &stats_flags, p->func_id);
2399 storm_memset_tstats_addr(bp, p->fw_stat_map, p->func_id);
2400
2401 storm_memset_ustats_flags(bp, &stats_flags, p->func_id);
2402 storm_memset_ustats_addr(bp, p->fw_stat_map, p->func_id);
2403
2404 storm_memset_cstats_flags(bp, &stats_flags, p->func_id);
2405 storm_memset_cstats_addr(bp, p->fw_stat_map, p->func_id);
2406 }
2407
2408 /* spq */
2409 if (p->func_flgs & FUNC_FLG_SPQ) {
2410 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2411 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2412 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2413 }
2414 }
2415
2416 static inline u16 bnx2x_get_cl_flags(struct bnx2x *bp,
2417 struct bnx2x_fastpath *fp)
2418 {
2419 u16 flags = 0;
2420
2421 /* calculate queue flags */
2422 flags |= QUEUE_FLG_CACHE_ALIGN;
2423 flags |= QUEUE_FLG_HC;
2424 flags |= IS_MF_SD(bp) ? QUEUE_FLG_OV : 0;
2425
2426 flags |= QUEUE_FLG_VLAN;
2427 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
2428
2429 if (!fp->disable_tpa)
2430 flags |= QUEUE_FLG_TPA;
2431
2432 flags = stat_counter_valid(bp, fp) ?
2433 (flags | QUEUE_FLG_STATS) : (flags & ~QUEUE_FLG_STATS);
2434
2435 return flags;
2436 }
2437
2438 static void bnx2x_pf_rx_cl_prep(struct bnx2x *bp,
2439 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2440 struct bnx2x_rxq_init_params *rxq_init)
2441 {
2442 u16 max_sge = 0;
2443 u16 sge_sz = 0;
2444 u16 tpa_agg_size = 0;
2445
2446 /* calculate queue flags */
2447 u16 flags = bnx2x_get_cl_flags(bp, fp);
2448
2449 if (!fp->disable_tpa) {
2450 pause->sge_th_hi = 250;
2451 pause->sge_th_lo = 150;
2452 tpa_agg_size = min_t(u32,
2453 (min_t(u32, 8, MAX_SKB_FRAGS) *
2454 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2455 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2456 SGE_PAGE_SHIFT;
2457 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2458 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2459 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2460 0xffff);
2461 }
2462
2463 /* pause - not for e1 */
2464 if (!CHIP_IS_E1(bp)) {
2465 pause->bd_th_hi = 350;
2466 pause->bd_th_lo = 250;
2467 pause->rcq_th_hi = 350;
2468 pause->rcq_th_lo = 250;
2469 pause->sge_th_hi = 0;
2470 pause->sge_th_lo = 0;
2471 pause->pri_map = 1;
2472 }
2473
2474 /* rxq setup */
2475 rxq_init->flags = flags;
2476 rxq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2477 rxq_init->dscr_map = fp->rx_desc_mapping;
2478 rxq_init->sge_map = fp->rx_sge_mapping;
2479 rxq_init->rcq_map = fp->rx_comp_mapping;
2480 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2481 rxq_init->mtu = bp->dev->mtu;
2482 rxq_init->buf_sz = bp->rx_buf_size;
2483 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2484 rxq_init->cl_id = fp->cl_id;
2485 rxq_init->spcl_id = fp->cl_id;
2486 rxq_init->stat_id = fp->cl_id;
2487 rxq_init->tpa_agg_sz = tpa_agg_size;
2488 rxq_init->sge_buf_sz = sge_sz;
2489 rxq_init->max_sges_pkt = max_sge;
2490 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2491 rxq_init->fw_sb_id = fp->fw_sb_id;
2492
2493 if (IS_FCOE_FP(fp))
2494 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2495 else
2496 rxq_init->sb_cq_index = U_SB_ETH_RX_CQ_INDEX;
2497
2498 rxq_init->cid = HW_CID(bp, fp->cid);
2499
2500 rxq_init->hc_rate = bp->rx_ticks ? (1000000 / bp->rx_ticks) : 0;
2501 }
2502
2503 static void bnx2x_pf_tx_cl_prep(struct bnx2x *bp,
2504 struct bnx2x_fastpath *fp, struct bnx2x_txq_init_params *txq_init)
2505 {
2506 u16 flags = bnx2x_get_cl_flags(bp, fp);
2507
2508 txq_init->flags = flags;
2509 txq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2510 txq_init->dscr_map = fp->tx_desc_mapping;
2511 txq_init->stat_id = fp->cl_id;
2512 txq_init->cid = HW_CID(bp, fp->cid);
2513 txq_init->sb_cq_index = C_SB_ETH_TX_CQ_INDEX;
2514 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2515 txq_init->fw_sb_id = fp->fw_sb_id;
2516
2517 if (IS_FCOE_FP(fp)) {
2518 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2519 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2520 }
2521
2522 txq_init->hc_rate = bp->tx_ticks ? (1000000 / bp->tx_ticks) : 0;
2523 }
2524
2525 static void bnx2x_pf_init(struct bnx2x *bp)
2526 {
2527 struct bnx2x_func_init_params func_init = {0};
2528 struct bnx2x_rss_params rss = {0};
2529 struct event_ring_data eq_data = { {0} };
2530 u16 flags;
2531
2532 /* pf specific setups */
2533 if (!CHIP_IS_E1(bp))
2534 storm_memset_ov(bp, bp->mf_ov, BP_FUNC(bp));
2535
2536 if (CHIP_IS_E2(bp)) {
2537 /* reset IGU PF statistics: MSIX + ATTN */
2538 /* PF */
2539 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2540 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2541 (CHIP_MODE_IS_4_PORT(bp) ?
2542 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2543 /* ATTN */
2544 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2545 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2546 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2547 (CHIP_MODE_IS_4_PORT(bp) ?
2548 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2549 }
2550
2551 /* function setup flags */
2552 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2553
2554 if (CHIP_IS_E1x(bp))
2555 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2556 else
2557 flags |= FUNC_FLG_TPA;
2558
2559 /* function setup */
2560
2561 /**
2562 * Although RSS is meaningless when there is a single HW queue we
2563 * still need it enabled in order to have HW Rx hash generated.
2564 */
2565 rss.cap = (RSS_IPV4_CAP | RSS_IPV4_TCP_CAP |
2566 RSS_IPV6_CAP | RSS_IPV6_TCP_CAP);
2567 rss.mode = bp->multi_mode;
2568 rss.result_mask = MULTI_MASK;
2569 func_init.rss = &rss;
2570
2571 func_init.func_flgs = flags;
2572 func_init.pf_id = BP_FUNC(bp);
2573 func_init.func_id = BP_FUNC(bp);
2574 func_init.fw_stat_map = bnx2x_sp_mapping(bp, fw_stats);
2575 func_init.spq_map = bp->spq_mapping;
2576 func_init.spq_prod = bp->spq_prod_idx;
2577
2578 bnx2x_func_init(bp, &func_init);
2579
2580 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2581
2582 /*
2583 Congestion management values depend on the link rate
2584 There is no active link so initial link rate is set to 10 Gbps.
2585 When the link comes up The congestion management values are
2586 re-calculated according to the actual link rate.
2587 */
2588 bp->link_vars.line_speed = SPEED_10000;
2589 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2590
2591 /* Only the PMF sets the HW */
2592 if (bp->port.pmf)
2593 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2594
2595 /* no rx until link is up */
2596 bp->rx_mode = BNX2X_RX_MODE_NONE;
2597 bnx2x_set_storm_rx_mode(bp);
2598
2599 /* init Event Queue */
2600 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2601 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2602 eq_data.producer = bp->eq_prod;
2603 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2604 eq_data.sb_id = DEF_SB_ID;
2605 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2606 }
2607
2608
2609 static void bnx2x_e1h_disable(struct bnx2x *bp)
2610 {
2611 int port = BP_PORT(bp);
2612
2613 netif_tx_disable(bp->dev);
2614
2615 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2616
2617 netif_carrier_off(bp->dev);
2618 }
2619
2620 static void bnx2x_e1h_enable(struct bnx2x *bp)
2621 {
2622 int port = BP_PORT(bp);
2623
2624 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2625
2626 /* Tx queue should be only reenabled */
2627 netif_tx_wake_all_queues(bp->dev);
2628
2629 /*
2630 * Should not call netif_carrier_on since it will be called if the link
2631 * is up when checking for link state
2632 */
2633 }
2634
2635 /* called due to MCP event (on pmf):
2636 * reread new bandwidth configuration
2637 * configure FW
2638 * notify others function about the change
2639 */
2640 static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2641 {
2642 if (bp->link_vars.link_up) {
2643 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2644 bnx2x_link_sync_notify(bp);
2645 }
2646 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2647 }
2648
2649 static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2650 {
2651 bnx2x_config_mf_bw(bp);
2652 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2653 }
2654
2655 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2656 {
2657 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2658
2659 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2660
2661 /*
2662 * This is the only place besides the function initialization
2663 * where the bp->flags can change so it is done without any
2664 * locks
2665 */
2666 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2667 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2668 bp->flags |= MF_FUNC_DIS;
2669
2670 bnx2x_e1h_disable(bp);
2671 } else {
2672 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2673 bp->flags &= ~MF_FUNC_DIS;
2674
2675 bnx2x_e1h_enable(bp);
2676 }
2677 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2678 }
2679 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
2680 bnx2x_config_mf_bw(bp);
2681 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2682 }
2683
2684 /* Report results to MCP */
2685 if (dcc_event)
2686 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2687 else
2688 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2689 }
2690
2691 /* must be called under the spq lock */
2692 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2693 {
2694 struct eth_spe *next_spe = bp->spq_prod_bd;
2695
2696 if (bp->spq_prod_bd == bp->spq_last_bd) {
2697 bp->spq_prod_bd = bp->spq;
2698 bp->spq_prod_idx = 0;
2699 DP(NETIF_MSG_TIMER, "end of spq\n");
2700 } else {
2701 bp->spq_prod_bd++;
2702 bp->spq_prod_idx++;
2703 }
2704 return next_spe;
2705 }
2706
2707 /* must be called under the spq lock */
2708 static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2709 {
2710 int func = BP_FUNC(bp);
2711
2712 /* Make sure that BD data is updated before writing the producer */
2713 wmb();
2714
2715 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
2716 bp->spq_prod_idx);
2717 mmiowb();
2718 }
2719
2720 /* the slow path queue is odd since completions arrive on the fastpath ring */
2721 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2722 u32 data_hi, u32 data_lo, int common)
2723 {
2724 struct eth_spe *spe;
2725 u16 type;
2726
2727 #ifdef BNX2X_STOP_ON_ERROR
2728 if (unlikely(bp->panic))
2729 return -EIO;
2730 #endif
2731
2732 spin_lock_bh(&bp->spq_lock);
2733
2734 if (!atomic_read(&bp->spq_left)) {
2735 BNX2X_ERR("BUG! SPQ ring full!\n");
2736 spin_unlock_bh(&bp->spq_lock);
2737 bnx2x_panic();
2738 return -EBUSY;
2739 }
2740
2741 spe = bnx2x_sp_get_next(bp);
2742
2743 /* CID needs port number to be encoded int it */
2744 spe->hdr.conn_and_cmd_data =
2745 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
2746 HW_CID(bp, cid));
2747
2748 if (common)
2749 /* Common ramrods:
2750 * FUNC_START, FUNC_STOP, CFC_DEL, STATS, SET_MAC
2751 * TRAFFIC_STOP, TRAFFIC_START
2752 */
2753 type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2754 & SPE_HDR_CONN_TYPE;
2755 else
2756 /* ETH ramrods: SETUP, HALT */
2757 type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2758 & SPE_HDR_CONN_TYPE;
2759
2760 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
2761 SPE_HDR_FUNCTION_ID);
2762
2763 spe->hdr.type = cpu_to_le16(type);
2764
2765 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
2766 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
2767
2768 /* stats ramrod has it's own slot on the spq */
2769 if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY)
2770 /* It's ok if the actual decrement is issued towards the memory
2771 * somewhere between the spin_lock and spin_unlock. Thus no
2772 * more explict memory barrier is needed.
2773 */
2774 atomic_dec(&bp->spq_left);
2775
2776 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
2777 "SPQE[%x] (%x:%x) command %d hw_cid %x data (%x:%x) "
2778 "type(0x%x) left %x\n",
2779 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
2780 (u32)(U64_LO(bp->spq_mapping) +
2781 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
2782 HW_CID(bp, cid), data_hi, data_lo, type, atomic_read(&bp->spq_left));
2783
2784 bnx2x_sp_prod_update(bp);
2785 spin_unlock_bh(&bp->spq_lock);
2786 return 0;
2787 }
2788
2789 /* acquire split MCP access lock register */
2790 static int bnx2x_acquire_alr(struct bnx2x *bp)
2791 {
2792 u32 j, val;
2793 int rc = 0;
2794
2795 might_sleep();
2796 for (j = 0; j < 1000; j++) {
2797 val = (1UL << 31);
2798 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2799 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
2800 if (val & (1L << 31))
2801 break;
2802
2803 msleep(5);
2804 }
2805 if (!(val & (1L << 31))) {
2806 BNX2X_ERR("Cannot acquire MCP access lock register\n");
2807 rc = -EBUSY;
2808 }
2809
2810 return rc;
2811 }
2812
2813 /* release split MCP access lock register */
2814 static void bnx2x_release_alr(struct bnx2x *bp)
2815 {
2816 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
2817 }
2818
2819 #define BNX2X_DEF_SB_ATT_IDX 0x0001
2820 #define BNX2X_DEF_SB_IDX 0x0002
2821
2822 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2823 {
2824 struct host_sp_status_block *def_sb = bp->def_status_blk;
2825 u16 rc = 0;
2826
2827 barrier(); /* status block is written to by the chip */
2828 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2829 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
2830 rc |= BNX2X_DEF_SB_ATT_IDX;
2831 }
2832
2833 if (bp->def_idx != def_sb->sp_sb.running_index) {
2834 bp->def_idx = def_sb->sp_sb.running_index;
2835 rc |= BNX2X_DEF_SB_IDX;
2836 }
2837
2838 /* Do not reorder: indecies reading should complete before handling */
2839 barrier();
2840 return rc;
2841 }
2842
2843 /*
2844 * slow path service functions
2845 */
2846
2847 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2848 {
2849 int port = BP_PORT(bp);
2850 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2851 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2852 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2853 NIG_REG_MASK_INTERRUPT_PORT0;
2854 u32 aeu_mask;
2855 u32 nig_mask = 0;
2856 u32 reg_addr;
2857
2858 if (bp->attn_state & asserted)
2859 BNX2X_ERR("IGU ERROR\n");
2860
2861 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2862 aeu_mask = REG_RD(bp, aeu_addr);
2863
2864 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
2865 aeu_mask, asserted);
2866 aeu_mask &= ~(asserted & 0x3ff);
2867 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2868
2869 REG_WR(bp, aeu_addr, aeu_mask);
2870 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2871
2872 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2873 bp->attn_state |= asserted;
2874 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2875
2876 if (asserted & ATTN_HARD_WIRED_MASK) {
2877 if (asserted & ATTN_NIG_FOR_FUNC) {
2878
2879 bnx2x_acquire_phy_lock(bp);
2880
2881 /* save nig interrupt mask */
2882 nig_mask = REG_RD(bp, nig_int_mask_addr);
2883 REG_WR(bp, nig_int_mask_addr, 0);
2884
2885 bnx2x_link_attn(bp);
2886
2887 /* handle unicore attn? */
2888 }
2889 if (asserted & ATTN_SW_TIMER_4_FUNC)
2890 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
2891
2892 if (asserted & GPIO_2_FUNC)
2893 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
2894
2895 if (asserted & GPIO_3_FUNC)
2896 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
2897
2898 if (asserted & GPIO_4_FUNC)
2899 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
2900
2901 if (port == 0) {
2902 if (asserted & ATTN_GENERAL_ATTN_1) {
2903 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
2904 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2905 }
2906 if (asserted & ATTN_GENERAL_ATTN_2) {
2907 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
2908 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2909 }
2910 if (asserted & ATTN_GENERAL_ATTN_3) {
2911 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
2912 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2913 }
2914 } else {
2915 if (asserted & ATTN_GENERAL_ATTN_4) {
2916 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
2917 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2918 }
2919 if (asserted & ATTN_GENERAL_ATTN_5) {
2920 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
2921 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2922 }
2923 if (asserted & ATTN_GENERAL_ATTN_6) {
2924 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
2925 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2926 }
2927 }
2928
2929 } /* if hardwired */
2930
2931 if (bp->common.int_block == INT_BLOCK_HC)
2932 reg_addr = (HC_REG_COMMAND_REG + port*32 +
2933 COMMAND_REG_ATTN_BITS_SET);
2934 else
2935 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
2936
2937 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
2938 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
2939 REG_WR(bp, reg_addr, asserted);
2940
2941 /* now set back the mask */
2942 if (asserted & ATTN_NIG_FOR_FUNC) {
2943 REG_WR(bp, nig_int_mask_addr, nig_mask);
2944 bnx2x_release_phy_lock(bp);
2945 }
2946 }
2947
2948 static inline void bnx2x_fan_failure(struct bnx2x *bp)
2949 {
2950 int port = BP_PORT(bp);
2951 u32 ext_phy_config;
2952 /* mark the failure */
2953 ext_phy_config =
2954 SHMEM_RD(bp,
2955 dev_info.port_hw_config[port].external_phy_config);
2956
2957 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2958 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2959 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
2960 ext_phy_config);
2961
2962 /* log the failure */
2963 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
2964 " the driver to shutdown the card to prevent permanent"
2965 " damage. Please contact OEM Support for assistance\n");
2966 }
2967
2968 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
2969 {
2970 int port = BP_PORT(bp);
2971 int reg_offset;
2972 u32 val;
2973
2974 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
2975 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
2976
2977 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
2978
2979 val = REG_RD(bp, reg_offset);
2980 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
2981 REG_WR(bp, reg_offset, val);
2982
2983 BNX2X_ERR("SPIO5 hw attention\n");
2984
2985 /* Fan failure attention */
2986 bnx2x_hw_reset_phy(&bp->link_params);
2987 bnx2x_fan_failure(bp);
2988 }
2989
2990 if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
2991 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
2992 bnx2x_acquire_phy_lock(bp);
2993 bnx2x_handle_module_detect_int(&bp->link_params);
2994 bnx2x_release_phy_lock(bp);
2995 }
2996
2997 if (attn & HW_INTERRUT_ASSERT_SET_0) {
2998
2999 val = REG_RD(bp, reg_offset);
3000 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3001 REG_WR(bp, reg_offset, val);
3002
3003 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3004 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3005 bnx2x_panic();
3006 }
3007 }
3008
3009 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3010 {
3011 u32 val;
3012
3013 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3014
3015 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3016 BNX2X_ERR("DB hw attention 0x%x\n", val);
3017 /* DORQ discard attention */
3018 if (val & 0x2)
3019 BNX2X_ERR("FATAL error from DORQ\n");
3020 }
3021
3022 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3023
3024 int port = BP_PORT(bp);
3025 int reg_offset;
3026
3027 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3028 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3029
3030 val = REG_RD(bp, reg_offset);
3031 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3032 REG_WR(bp, reg_offset, val);
3033
3034 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3035 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3036 bnx2x_panic();
3037 }
3038 }
3039
3040 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3041 {
3042 u32 val;
3043
3044 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3045
3046 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3047 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3048 /* CFC error attention */
3049 if (val & 0x2)
3050 BNX2X_ERR("FATAL error from CFC\n");
3051 }
3052
3053 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3054
3055 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3056 BNX2X_ERR("PXP hw attention 0x%x\n", val);
3057 /* RQ_USDMDP_FIFO_OVERFLOW */
3058 if (val & 0x18000)
3059 BNX2X_ERR("FATAL error from PXP\n");
3060 if (CHIP_IS_E2(bp)) {
3061 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3062 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3063 }
3064 }
3065
3066 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3067
3068 int port = BP_PORT(bp);
3069 int reg_offset;
3070
3071 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3072 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3073
3074 val = REG_RD(bp, reg_offset);
3075 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3076 REG_WR(bp, reg_offset, val);
3077
3078 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3079 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3080 bnx2x_panic();
3081 }
3082 }
3083
3084 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3085 {
3086 u32 val;
3087
3088 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3089
3090 if (attn & BNX2X_PMF_LINK_ASSERT) {
3091 int func = BP_FUNC(bp);
3092
3093 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3094 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3095 func_mf_config[BP_ABS_FUNC(bp)].config);
3096 val = SHMEM_RD(bp,
3097 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3098 if (val & DRV_STATUS_DCC_EVENT_MASK)
3099 bnx2x_dcc_event(bp,
3100 (val & DRV_STATUS_DCC_EVENT_MASK));
3101
3102 if (val & DRV_STATUS_SET_MF_BW)
3103 bnx2x_set_mf_bw(bp);
3104
3105 bnx2x__link_status_update(bp);
3106 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3107 bnx2x_pmf_update(bp);
3108
3109 if (bp->port.pmf &&
3110 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS))
3111 /* start dcbx state machine */
3112 bnx2x_dcbx_set_params(bp,
3113 BNX2X_DCBX_STATE_NEG_RECEIVED);
3114 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3115
3116 BNX2X_ERR("MC assert!\n");
3117 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3118 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3119 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3120 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3121 bnx2x_panic();
3122
3123 } else if (attn & BNX2X_MCP_ASSERT) {
3124
3125 BNX2X_ERR("MCP assert!\n");
3126 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3127 bnx2x_fw_dump(bp);
3128
3129 } else
3130 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3131 }
3132
3133 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3134 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3135 if (attn & BNX2X_GRC_TIMEOUT) {
3136 val = CHIP_IS_E1(bp) ? 0 :
3137 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3138 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3139 }
3140 if (attn & BNX2X_GRC_RSV) {
3141 val = CHIP_IS_E1(bp) ? 0 :
3142 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3143 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3144 }
3145 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3146 }
3147 }
3148
3149 #define BNX2X_MISC_GEN_REG MISC_REG_GENERIC_POR_1
3150 #define LOAD_COUNTER_BITS 16 /* Number of bits for load counter */
3151 #define LOAD_COUNTER_MASK (((u32)0x1 << LOAD_COUNTER_BITS) - 1)
3152 #define RESET_DONE_FLAG_MASK (~LOAD_COUNTER_MASK)
3153 #define RESET_DONE_FLAG_SHIFT LOAD_COUNTER_BITS
3154 #define CHIP_PARITY_SUPPORTED(bp) (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp))
3155
3156 /*
3157 * should be run under rtnl lock
3158 */
3159 static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3160 {
3161 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3162 val &= ~(1 << RESET_DONE_FLAG_SHIFT);
3163 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3164 barrier();
3165 mmiowb();
3166 }
3167
3168 /*
3169 * should be run under rtnl lock
3170 */
3171 static inline void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3172 {
3173 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3174 val |= (1 << 16);
3175 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3176 barrier();
3177 mmiowb();
3178 }
3179
3180 /*
3181 * should be run under rtnl lock
3182 */
3183 bool bnx2x_reset_is_done(struct bnx2x *bp)
3184 {
3185 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3186 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3187 return (val & RESET_DONE_FLAG_MASK) ? false : true;
3188 }
3189
3190 /*
3191 * should be run under rtnl lock
3192 */
3193 inline void bnx2x_inc_load_cnt(struct bnx2x *bp)
3194 {
3195 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3196
3197 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3198
3199 val1 = ((val & LOAD_COUNTER_MASK) + 1) & LOAD_COUNTER_MASK;
3200 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3201 barrier();
3202 mmiowb();
3203 }
3204
3205 /*
3206 * should be run under rtnl lock
3207 */
3208 u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
3209 {
3210 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3211
3212 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3213
3214 val1 = ((val & LOAD_COUNTER_MASK) - 1) & LOAD_COUNTER_MASK;
3215 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3216 barrier();
3217 mmiowb();
3218
3219 return val1;
3220 }
3221
3222 /*
3223 * should be run under rtnl lock
3224 */
3225 static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp)
3226 {
3227 return REG_RD(bp, BNX2X_MISC_GEN_REG) & LOAD_COUNTER_MASK;
3228 }
3229
3230 static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3231 {
3232 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3233 REG_WR(bp, BNX2X_MISC_GEN_REG, val & (~LOAD_COUNTER_MASK));
3234 }
3235
3236 static inline void _print_next_block(int idx, const char *blk)
3237 {
3238 if (idx)
3239 pr_cont(", ");
3240 pr_cont("%s", blk);
3241 }
3242
3243 static inline int bnx2x_print_blocks_with_parity0(u32 sig, int par_num)
3244 {
3245 int i = 0;
3246 u32 cur_bit = 0;
3247 for (i = 0; sig; i++) {
3248 cur_bit = ((u32)0x1 << i);
3249 if (sig & cur_bit) {
3250 switch (cur_bit) {
3251 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3252 _print_next_block(par_num++, "BRB");
3253 break;
3254 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3255 _print_next_block(par_num++, "PARSER");
3256 break;
3257 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3258 _print_next_block(par_num++, "TSDM");
3259 break;
3260 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3261 _print_next_block(par_num++, "SEARCHER");
3262 break;
3263 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3264 _print_next_block(par_num++, "TSEMI");
3265 break;
3266 }
3267
3268 /* Clear the bit */
3269 sig &= ~cur_bit;
3270 }
3271 }
3272
3273 return par_num;
3274 }
3275
3276 static inline int bnx2x_print_blocks_with_parity1(u32 sig, int par_num)
3277 {
3278 int i = 0;
3279 u32 cur_bit = 0;
3280 for (i = 0; sig; i++) {
3281 cur_bit = ((u32)0x1 << i);
3282 if (sig & cur_bit) {
3283 switch (cur_bit) {
3284 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3285 _print_next_block(par_num++, "PBCLIENT");
3286 break;
3287 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3288 _print_next_block(par_num++, "QM");
3289 break;
3290 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3291 _print_next_block(par_num++, "XSDM");
3292 break;
3293 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3294 _print_next_block(par_num++, "XSEMI");
3295 break;
3296 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3297 _print_next_block(par_num++, "DOORBELLQ");
3298 break;
3299 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3300 _print_next_block(par_num++, "VAUX PCI CORE");
3301 break;
3302 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3303 _print_next_block(par_num++, "DEBUG");
3304 break;
3305 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3306 _print_next_block(par_num++, "USDM");
3307 break;
3308 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3309 _print_next_block(par_num++, "USEMI");
3310 break;
3311 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3312 _print_next_block(par_num++, "UPB");
3313 break;
3314 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3315 _print_next_block(par_num++, "CSDM");
3316 break;
3317 }
3318
3319 /* Clear the bit */
3320 sig &= ~cur_bit;
3321 }
3322 }
3323
3324 return par_num;
3325 }
3326
3327 static inline int bnx2x_print_blocks_with_parity2(u32 sig, int par_num)
3328 {
3329 int i = 0;
3330 u32 cur_bit = 0;
3331 for (i = 0; sig; i++) {
3332 cur_bit = ((u32)0x1 << i);
3333 if (sig & cur_bit) {
3334 switch (cur_bit) {
3335 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3336 _print_next_block(par_num++, "CSEMI");
3337 break;
3338 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3339 _print_next_block(par_num++, "PXP");
3340 break;
3341 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3342 _print_next_block(par_num++,
3343 "PXPPCICLOCKCLIENT");
3344 break;
3345 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3346 _print_next_block(par_num++, "CFC");
3347 break;
3348 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3349 _print_next_block(par_num++, "CDU");
3350 break;
3351 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3352 _print_next_block(par_num++, "IGU");
3353 break;
3354 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3355 _print_next_block(par_num++, "MISC");
3356 break;
3357 }
3358
3359 /* Clear the bit */
3360 sig &= ~cur_bit;
3361 }
3362 }
3363
3364 return par_num;
3365 }
3366
3367 static inline int bnx2x_print_blocks_with_parity3(u32 sig, int par_num)
3368 {
3369 int i = 0;
3370 u32 cur_bit = 0;
3371 for (i = 0; sig; i++) {
3372 cur_bit = ((u32)0x1 << i);
3373 if (sig & cur_bit) {
3374 switch (cur_bit) {
3375 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3376 _print_next_block(par_num++, "MCP ROM");
3377 break;
3378 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3379 _print_next_block(par_num++, "MCP UMP RX");
3380 break;
3381 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3382 _print_next_block(par_num++, "MCP UMP TX");
3383 break;
3384 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3385 _print_next_block(par_num++, "MCP SCPAD");
3386 break;
3387 }
3388
3389 /* Clear the bit */
3390 sig &= ~cur_bit;
3391 }
3392 }
3393
3394 return par_num;
3395 }
3396
3397 static inline bool bnx2x_parity_attn(struct bnx2x *bp, u32 sig0, u32 sig1,
3398 u32 sig2, u32 sig3)
3399 {
3400 if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) ||
3401 (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) {
3402 int par_num = 0;
3403 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
3404 "[0]:0x%08x [1]:0x%08x "
3405 "[2]:0x%08x [3]:0x%08x\n",
3406 sig0 & HW_PRTY_ASSERT_SET_0,
3407 sig1 & HW_PRTY_ASSERT_SET_1,
3408 sig2 & HW_PRTY_ASSERT_SET_2,
3409 sig3 & HW_PRTY_ASSERT_SET_3);
3410 printk(KERN_ERR"%s: Parity errors detected in blocks: ",
3411 bp->dev->name);
3412 par_num = bnx2x_print_blocks_with_parity0(
3413 sig0 & HW_PRTY_ASSERT_SET_0, par_num);
3414 par_num = bnx2x_print_blocks_with_parity1(
3415 sig1 & HW_PRTY_ASSERT_SET_1, par_num);
3416 par_num = bnx2x_print_blocks_with_parity2(
3417 sig2 & HW_PRTY_ASSERT_SET_2, par_num);
3418 par_num = bnx2x_print_blocks_with_parity3(
3419 sig3 & HW_PRTY_ASSERT_SET_3, par_num);
3420 printk("\n");
3421 return true;
3422 } else
3423 return false;
3424 }
3425
3426 bool bnx2x_chk_parity_attn(struct bnx2x *bp)
3427 {
3428 struct attn_route attn;
3429 int port = BP_PORT(bp);
3430
3431 attn.sig[0] = REG_RD(bp,
3432 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
3433 port*4);
3434 attn.sig[1] = REG_RD(bp,
3435 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
3436 port*4);
3437 attn.sig[2] = REG_RD(bp,
3438 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
3439 port*4);
3440 attn.sig[3] = REG_RD(bp,
3441 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
3442 port*4);
3443
3444 return bnx2x_parity_attn(bp, attn.sig[0], attn.sig[1], attn.sig[2],
3445 attn.sig[3]);
3446 }
3447
3448
3449 static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
3450 {
3451 u32 val;
3452 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3453
3454 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3455 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
3456 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3457 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3458 "ADDRESS_ERROR\n");
3459 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3460 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3461 "INCORRECT_RCV_BEHAVIOR\n");
3462 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3463 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3464 "WAS_ERROR_ATTN\n");
3465 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3466 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3467 "VF_LENGTH_VIOLATION_ATTN\n");
3468 if (val &
3469 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3470 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3471 "VF_GRC_SPACE_VIOLATION_ATTN\n");
3472 if (val &
3473 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3474 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3475 "VF_MSIX_BAR_VIOLATION_ATTN\n");
3476 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3477 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3478 "TCPL_ERROR_ATTN\n");
3479 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3480 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3481 "TCPL_IN_TWO_RCBS_ATTN\n");
3482 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3483 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3484 "CSSNOOP_FIFO_OVERFLOW\n");
3485 }
3486 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3487 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
3488 BNX2X_ERR("ATC hw attention 0x%x\n", val);
3489 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3490 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
3491 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3492 BNX2X_ERR("ATC_ATC_INT_STS_REG"
3493 "_ATC_TCPL_TO_NOT_PEND\n");
3494 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3495 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3496 "ATC_GPA_MULTIPLE_HITS\n");
3497 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3498 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3499 "ATC_RCPL_TO_EMPTY_CNT\n");
3500 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3501 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
3502 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3503 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3504 "ATC_IREQ_LESS_THAN_STU\n");
3505 }
3506
3507 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3508 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3509 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
3510 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3511 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3512 }
3513
3514 }
3515
3516 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
3517 {
3518 struct attn_route attn, *group_mask;
3519 int port = BP_PORT(bp);
3520 int index;
3521 u32 reg_addr;
3522 u32 val;
3523 u32 aeu_mask;
3524
3525 /* need to take HW lock because MCP or other port might also
3526 try to handle this event */
3527 bnx2x_acquire_alr(bp);
3528
3529 if (bnx2x_chk_parity_attn(bp)) {
3530 bp->recovery_state = BNX2X_RECOVERY_INIT;
3531 bnx2x_set_reset_in_progress(bp);
3532 schedule_delayed_work(&bp->reset_task, 0);
3533 /* Disable HW interrupts */
3534 bnx2x_int_disable(bp);
3535 bnx2x_release_alr(bp);
3536 /* In case of parity errors don't handle attentions so that
3537 * other function would "see" parity errors.
3538 */
3539 return;
3540 }
3541
3542 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
3543 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
3544 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
3545 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
3546 if (CHIP_IS_E2(bp))
3547 attn.sig[4] =
3548 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
3549 else
3550 attn.sig[4] = 0;
3551
3552 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
3553 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
3554
3555 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
3556 if (deasserted & (1 << index)) {
3557 group_mask = &bp->attn_group[index];
3558
3559 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
3560 "%08x %08x %08x\n",
3561 index,
3562 group_mask->sig[0], group_mask->sig[1],
3563 group_mask->sig[2], group_mask->sig[3],
3564 group_mask->sig[4]);
3565
3566 bnx2x_attn_int_deasserted4(bp,
3567 attn.sig[4] & group_mask->sig[4]);
3568 bnx2x_attn_int_deasserted3(bp,
3569 attn.sig[3] & group_mask->sig[3]);
3570 bnx2x_attn_int_deasserted1(bp,
3571 attn.sig[1] & group_mask->sig[1]);
3572 bnx2x_attn_int_deasserted2(bp,
3573 attn.sig[2] & group_mask->sig[2]);
3574 bnx2x_attn_int_deasserted0(bp,
3575 attn.sig[0] & group_mask->sig[0]);
3576 }
3577 }
3578
3579 bnx2x_release_alr(bp);
3580
3581 if (bp->common.int_block == INT_BLOCK_HC)
3582 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3583 COMMAND_REG_ATTN_BITS_CLR);
3584 else
3585 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
3586
3587 val = ~deasserted;
3588 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
3589 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3590 REG_WR(bp, reg_addr, val);
3591
3592 if (~bp->attn_state & deasserted)
3593 BNX2X_ERR("IGU ERROR\n");
3594
3595 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3596 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3597
3598 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3599 aeu_mask = REG_RD(bp, reg_addr);
3600
3601 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
3602 aeu_mask, deasserted);
3603 aeu_mask |= (deasserted & 0x3ff);
3604 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3605
3606 REG_WR(bp, reg_addr, aeu_mask);
3607 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3608
3609 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3610 bp->attn_state &= ~deasserted;
3611 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3612 }
3613
3614 static void bnx2x_attn_int(struct bnx2x *bp)
3615 {
3616 /* read local copy of bits */
3617 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
3618 attn_bits);
3619 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
3620 attn_bits_ack);
3621 u32 attn_state = bp->attn_state;
3622
3623 /* look for changed bits */
3624 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
3625 u32 deasserted = ~attn_bits & attn_ack & attn_state;
3626
3627 DP(NETIF_MSG_HW,
3628 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
3629 attn_bits, attn_ack, asserted, deasserted);
3630
3631 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
3632 BNX2X_ERR("BAD attention state\n");
3633
3634 /* handle bits that were raised */
3635 if (asserted)
3636 bnx2x_attn_int_asserted(bp, asserted);
3637
3638 if (deasserted)
3639 bnx2x_attn_int_deasserted(bp, deasserted);
3640 }
3641
3642 static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
3643 {
3644 /* No memory barriers */
3645 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
3646 mmiowb(); /* keep prod updates ordered */
3647 }
3648
3649 #ifdef BCM_CNIC
3650 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
3651 union event_ring_elem *elem)
3652 {
3653 if (!bp->cnic_eth_dev.starting_cid ||
3654 cid < bp->cnic_eth_dev.starting_cid)
3655 return 1;
3656
3657 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
3658
3659 if (unlikely(elem->message.data.cfc_del_event.error)) {
3660 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
3661 cid);
3662 bnx2x_panic_dump(bp);
3663 }
3664 bnx2x_cnic_cfc_comp(bp, cid);
3665 return 0;
3666 }
3667 #endif
3668
3669 static void bnx2x_eq_int(struct bnx2x *bp)
3670 {
3671 u16 hw_cons, sw_cons, sw_prod;
3672 union event_ring_elem *elem;
3673 u32 cid;
3674 u8 opcode;
3675 int spqe_cnt = 0;
3676
3677 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
3678
3679 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
3680 * when we get the the next-page we nned to adjust so the loop
3681 * condition below will be met. The next element is the size of a
3682 * regular element and hence incrementing by 1
3683 */
3684 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
3685 hw_cons++;
3686
3687 /* This function may never run in parralel with itself for a
3688 * specific bp, thus there is no need in "paired" read memory
3689 * barrier here.
3690 */
3691 sw_cons = bp->eq_cons;
3692 sw_prod = bp->eq_prod;
3693
3694 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->spq_left %u\n",
3695 hw_cons, sw_cons, atomic_read(&bp->spq_left));
3696
3697 for (; sw_cons != hw_cons;
3698 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
3699
3700
3701 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
3702
3703 cid = SW_CID(elem->message.data.cfc_del_event.cid);
3704 opcode = elem->message.opcode;
3705
3706
3707 /* handle eq element */
3708 switch (opcode) {
3709 case EVENT_RING_OPCODE_STAT_QUERY:
3710 DP(NETIF_MSG_TIMER, "got statistics comp event\n");
3711 /* nothing to do with stats comp */
3712 continue;
3713
3714 case EVENT_RING_OPCODE_CFC_DEL:
3715 /* handle according to cid range */
3716 /*
3717 * we may want to verify here that the bp state is
3718 * HALTING
3719 */
3720 DP(NETIF_MSG_IFDOWN,
3721 "got delete ramrod for MULTI[%d]\n", cid);
3722 #ifdef BCM_CNIC
3723 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
3724 goto next_spqe;
3725 if (cid == BNX2X_FCOE_ETH_CID)
3726 bnx2x_fcoe(bp, state) = BNX2X_FP_STATE_CLOSED;
3727 else
3728 #endif
3729 bnx2x_fp(bp, cid, state) =
3730 BNX2X_FP_STATE_CLOSED;
3731
3732 goto next_spqe;
3733
3734 case EVENT_RING_OPCODE_STOP_TRAFFIC:
3735 DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
3736 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
3737 goto next_spqe;
3738 case EVENT_RING_OPCODE_START_TRAFFIC:
3739 DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
3740 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
3741 goto next_spqe;
3742 }
3743
3744 switch (opcode | bp->state) {
3745 case (EVENT_RING_OPCODE_FUNCTION_START |
3746 BNX2X_STATE_OPENING_WAIT4_PORT):
3747 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
3748 bp->state = BNX2X_STATE_FUNC_STARTED;
3749 break;
3750
3751 case (EVENT_RING_OPCODE_FUNCTION_STOP |
3752 BNX2X_STATE_CLOSING_WAIT4_HALT):
3753 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
3754 bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
3755 break;
3756
3757 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
3758 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
3759 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
3760 bp->set_mac_pending = 0;
3761 break;
3762
3763 case (EVENT_RING_OPCODE_SET_MAC |
3764 BNX2X_STATE_CLOSING_WAIT4_HALT):
3765 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
3766 bp->set_mac_pending = 0;
3767 break;
3768 default:
3769 /* unknown event log error and continue */
3770 BNX2X_ERR("Unknown EQ event %d\n",
3771 elem->message.opcode);
3772 }
3773 next_spqe:
3774 spqe_cnt++;
3775 } /* for */
3776
3777 smp_mb__before_atomic_inc();
3778 atomic_add(spqe_cnt, &bp->spq_left);
3779
3780 bp->eq_cons = sw_cons;
3781 bp->eq_prod = sw_prod;
3782 /* Make sure that above mem writes were issued towards the memory */
3783 smp_wmb();
3784
3785 /* update producer */
3786 bnx2x_update_eq_prod(bp, bp->eq_prod);
3787 }
3788
3789 static void bnx2x_sp_task(struct work_struct *work)
3790 {
3791 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
3792 u16 status;
3793
3794 /* Return here if interrupt is disabled */
3795 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3796 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
3797 return;
3798 }
3799
3800 status = bnx2x_update_dsb_idx(bp);
3801 /* if (status == 0) */
3802 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
3803
3804 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
3805
3806 /* HW attentions */
3807 if (status & BNX2X_DEF_SB_ATT_IDX) {
3808 bnx2x_attn_int(bp);
3809 status &= ~BNX2X_DEF_SB_ATT_IDX;
3810 }
3811
3812 /* SP events: STAT_QUERY and others */
3813 if (status & BNX2X_DEF_SB_IDX) {
3814 #ifdef BCM_CNIC
3815 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
3816
3817 if ((!NO_FCOE(bp)) &&
3818 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp)))
3819 napi_schedule(&bnx2x_fcoe(bp, napi));
3820 #endif
3821 /* Handle EQ completions */
3822 bnx2x_eq_int(bp);
3823
3824 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
3825 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
3826
3827 status &= ~BNX2X_DEF_SB_IDX;
3828 }
3829
3830 if (unlikely(status))
3831 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
3832 status);
3833
3834 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
3835 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
3836 }
3837
3838 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
3839 {
3840 struct net_device *dev = dev_instance;
3841 struct bnx2x *bp = netdev_priv(dev);
3842
3843 /* Return here if interrupt is disabled */
3844 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3845 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
3846 return IRQ_HANDLED;
3847 }
3848
3849 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
3850 IGU_INT_DISABLE, 0);
3851
3852 #ifdef BNX2X_STOP_ON_ERROR
3853 if (unlikely(bp->panic))
3854 return IRQ_HANDLED;
3855 #endif
3856
3857 #ifdef BCM_CNIC
3858 {
3859 struct cnic_ops *c_ops;
3860
3861 rcu_read_lock();
3862 c_ops = rcu_dereference(bp->cnic_ops);
3863 if (c_ops)
3864 c_ops->cnic_handler(bp->cnic_data, NULL);
3865 rcu_read_unlock();
3866 }
3867 #endif
3868 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
3869
3870 return IRQ_HANDLED;
3871 }
3872
3873 /* end of slow path */
3874
3875 static void bnx2x_timer(unsigned long data)
3876 {
3877 struct bnx2x *bp = (struct bnx2x *) data;
3878
3879 if (!netif_running(bp->dev))
3880 return;
3881
3882 if (atomic_read(&bp->intr_sem) != 0)
3883 goto timer_restart;
3884
3885 if (poll) {
3886 struct bnx2x_fastpath *fp = &bp->fp[0];
3887 int rc;
3888
3889 bnx2x_tx_int(fp);
3890 rc = bnx2x_rx_int(fp, 1000);
3891 }
3892
3893 if (!BP_NOMCP(bp)) {
3894 int mb_idx = BP_FW_MB_IDX(bp);
3895 u32 drv_pulse;
3896 u32 mcp_pulse;
3897
3898 ++bp->fw_drv_pulse_wr_seq;
3899 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
3900 /* TBD - add SYSTEM_TIME */
3901 drv_pulse = bp->fw_drv_pulse_wr_seq;
3902 SHMEM_WR(bp, func_mb[mb_idx].drv_pulse_mb, drv_pulse);
3903
3904 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
3905 MCP_PULSE_SEQ_MASK);
3906 /* The delta between driver pulse and mcp response
3907 * should be 1 (before mcp response) or 0 (after mcp response)
3908 */
3909 if ((drv_pulse != mcp_pulse) &&
3910 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
3911 /* someone lost a heartbeat... */
3912 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
3913 drv_pulse, mcp_pulse);
3914 }
3915 }
3916
3917 if (bp->state == BNX2X_STATE_OPEN)
3918 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
3919
3920 timer_restart:
3921 mod_timer(&bp->timer, jiffies + bp->current_interval);
3922 }
3923
3924 /* end of Statistics */
3925
3926 /* nic init */
3927
3928 /*
3929 * nic init service functions
3930 */
3931
3932 static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
3933 {
3934 u32 i;
3935 if (!(len%4) && !(addr%4))
3936 for (i = 0; i < len; i += 4)
3937 REG_WR(bp, addr + i, fill);
3938 else
3939 for (i = 0; i < len; i++)
3940 REG_WR8(bp, addr + i, fill);
3941
3942 }
3943
3944 /* helper: writes FP SP data to FW - data_size in dwords */
3945 static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
3946 int fw_sb_id,
3947 u32 *sb_data_p,
3948 u32 data_size)
3949 {
3950 int index;
3951 for (index = 0; index < data_size; index++)
3952 REG_WR(bp, BAR_CSTRORM_INTMEM +
3953 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
3954 sizeof(u32)*index,
3955 *(sb_data_p + index));
3956 }
3957
3958 static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
3959 {
3960 u32 *sb_data_p;
3961 u32 data_size = 0;
3962 struct hc_status_block_data_e2 sb_data_e2;
3963 struct hc_status_block_data_e1x sb_data_e1x;
3964
3965 /* disable the function first */
3966 if (CHIP_IS_E2(bp)) {
3967 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
3968 sb_data_e2.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3969 sb_data_e2.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3970 sb_data_e2.common.p_func.vf_valid = false;
3971 sb_data_p = (u32 *)&sb_data_e2;
3972 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
3973 } else {
3974 memset(&sb_data_e1x, 0,
3975 sizeof(struct hc_status_block_data_e1x));
3976 sb_data_e1x.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3977 sb_data_e1x.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3978 sb_data_e1x.common.p_func.vf_valid = false;
3979 sb_data_p = (u32 *)&sb_data_e1x;
3980 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
3981 }
3982 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
3983
3984 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
3985 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
3986 CSTORM_STATUS_BLOCK_SIZE);
3987 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
3988 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
3989 CSTORM_SYNC_BLOCK_SIZE);
3990 }
3991
3992 /* helper: writes SP SB data to FW */
3993 static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
3994 struct hc_sp_status_block_data *sp_sb_data)
3995 {
3996 int func = BP_FUNC(bp);
3997 int i;
3998 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
3999 REG_WR(bp, BAR_CSTRORM_INTMEM +
4000 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4001 i*sizeof(u32),
4002 *((u32 *)sp_sb_data + i));
4003 }
4004
4005 static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
4006 {
4007 int func = BP_FUNC(bp);
4008 struct hc_sp_status_block_data sp_sb_data;
4009 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4010
4011 sp_sb_data.p_func.pf_id = HC_FUNCTION_DISABLED;
4012 sp_sb_data.p_func.vf_id = HC_FUNCTION_DISABLED;
4013 sp_sb_data.p_func.vf_valid = false;
4014
4015 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4016
4017 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4018 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4019 CSTORM_SP_STATUS_BLOCK_SIZE);
4020 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4021 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4022 CSTORM_SP_SYNC_BLOCK_SIZE);
4023
4024 }
4025
4026
4027 static inline
4028 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4029 int igu_sb_id, int igu_seg_id)
4030 {
4031 hc_sm->igu_sb_id = igu_sb_id;
4032 hc_sm->igu_seg_id = igu_seg_id;
4033 hc_sm->timer_value = 0xFF;
4034 hc_sm->time_to_expire = 0xFFFFFFFF;
4035 }
4036
4037 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
4038 u8 vf_valid, int fw_sb_id, int igu_sb_id)
4039 {
4040 int igu_seg_id;
4041
4042 struct hc_status_block_data_e2 sb_data_e2;
4043 struct hc_status_block_data_e1x sb_data_e1x;
4044 struct hc_status_block_sm *hc_sm_p;
4045 struct hc_index_data *hc_index_p;
4046 int data_size;
4047 u32 *sb_data_p;
4048
4049 if (CHIP_INT_MODE_IS_BC(bp))
4050 igu_seg_id = HC_SEG_ACCESS_NORM;
4051 else
4052 igu_seg_id = IGU_SEG_ACCESS_NORM;
4053
4054 bnx2x_zero_fp_sb(bp, fw_sb_id);
4055
4056 if (CHIP_IS_E2(bp)) {
4057 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4058 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4059 sb_data_e2.common.p_func.vf_id = vfid;
4060 sb_data_e2.common.p_func.vf_valid = vf_valid;
4061 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4062 sb_data_e2.common.same_igu_sb_1b = true;
4063 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4064 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4065 hc_sm_p = sb_data_e2.common.state_machine;
4066 hc_index_p = sb_data_e2.index_data;
4067 sb_data_p = (u32 *)&sb_data_e2;
4068 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4069 } else {
4070 memset(&sb_data_e1x, 0,
4071 sizeof(struct hc_status_block_data_e1x));
4072 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4073 sb_data_e1x.common.p_func.vf_id = 0xff;
4074 sb_data_e1x.common.p_func.vf_valid = false;
4075 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4076 sb_data_e1x.common.same_igu_sb_1b = true;
4077 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4078 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4079 hc_sm_p = sb_data_e1x.common.state_machine;
4080 hc_index_p = sb_data_e1x.index_data;
4081 sb_data_p = (u32 *)&sb_data_e1x;
4082 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4083 }
4084
4085 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4086 igu_sb_id, igu_seg_id);
4087 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4088 igu_sb_id, igu_seg_id);
4089
4090 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4091
4092 /* write indecies to HW */
4093 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4094 }
4095
4096 static void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u16 fw_sb_id,
4097 u8 sb_index, u8 disable, u16 usec)
4098 {
4099 int port = BP_PORT(bp);
4100 u8 ticks = usec / BNX2X_BTR;
4101
4102 storm_memset_hc_timeout(bp, port, fw_sb_id, sb_index, ticks);
4103
4104 disable = disable ? 1 : (usec ? 0 : 1);
4105 storm_memset_hc_disable(bp, port, fw_sb_id, sb_index, disable);
4106 }
4107
4108 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u16 fw_sb_id,
4109 u16 tx_usec, u16 rx_usec)
4110 {
4111 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, U_SB_ETH_RX_CQ_INDEX,
4112 false, rx_usec);
4113 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, C_SB_ETH_TX_CQ_INDEX,
4114 false, tx_usec);
4115 }
4116
4117 static void bnx2x_init_def_sb(struct bnx2x *bp)
4118 {
4119 struct host_sp_status_block *def_sb = bp->def_status_blk;
4120 dma_addr_t mapping = bp->def_status_blk_mapping;
4121 int igu_sp_sb_index;
4122 int igu_seg_id;
4123 int port = BP_PORT(bp);
4124 int func = BP_FUNC(bp);
4125 int reg_offset;
4126 u64 section;
4127 int index;
4128 struct hc_sp_status_block_data sp_sb_data;
4129 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4130
4131 if (CHIP_INT_MODE_IS_BC(bp)) {
4132 igu_sp_sb_index = DEF_SB_IGU_ID;
4133 igu_seg_id = HC_SEG_ACCESS_DEF;
4134 } else {
4135 igu_sp_sb_index = bp->igu_dsb_id;
4136 igu_seg_id = IGU_SEG_ACCESS_DEF;
4137 }
4138
4139 /* ATTN */
4140 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4141 atten_status_block);
4142 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
4143
4144 bp->attn_state = 0;
4145
4146 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4147 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4148 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4149 int sindex;
4150 /* take care of sig[0]..sig[4] */
4151 for (sindex = 0; sindex < 4; sindex++)
4152 bp->attn_group[index].sig[sindex] =
4153 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
4154
4155 if (CHIP_IS_E2(bp))
4156 /*
4157 * enable5 is separate from the rest of the registers,
4158 * and therefore the address skip is 4
4159 * and not 16 between the different groups
4160 */
4161 bp->attn_group[index].sig[4] = REG_RD(bp,
4162 reg_offset + 0x10 + 0x4*index);
4163 else
4164 bp->attn_group[index].sig[4] = 0;
4165 }
4166
4167 if (bp->common.int_block == INT_BLOCK_HC) {
4168 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4169 HC_REG_ATTN_MSG0_ADDR_L);
4170
4171 REG_WR(bp, reg_offset, U64_LO(section));
4172 REG_WR(bp, reg_offset + 4, U64_HI(section));
4173 } else if (CHIP_IS_E2(bp)) {
4174 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4175 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4176 }
4177
4178 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4179 sp_sb);
4180
4181 bnx2x_zero_sp_sb(bp);
4182
4183 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4184 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4185 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4186 sp_sb_data.igu_seg_id = igu_seg_id;
4187 sp_sb_data.p_func.pf_id = func;
4188 sp_sb_data.p_func.vnic_id = BP_VN(bp);
4189 sp_sb_data.p_func.vf_id = 0xff;
4190
4191 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4192
4193 bp->stats_pending = 0;
4194 bp->set_mac_pending = 0;
4195
4196 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
4197 }
4198
4199 void bnx2x_update_coalesce(struct bnx2x *bp)
4200 {
4201 int i;
4202
4203 for_each_eth_queue(bp, i)
4204 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
4205 bp->rx_ticks, bp->tx_ticks);
4206 }
4207
4208 static void bnx2x_init_sp_ring(struct bnx2x *bp)
4209 {
4210 spin_lock_init(&bp->spq_lock);
4211 atomic_set(&bp->spq_left, MAX_SPQ_PENDING);
4212
4213 bp->spq_prod_idx = 0;
4214 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4215 bp->spq_prod_bd = bp->spq;
4216 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
4217 }
4218
4219 static void bnx2x_init_eq_ring(struct bnx2x *bp)
4220 {
4221 int i;
4222 for (i = 1; i <= NUM_EQ_PAGES; i++) {
4223 union event_ring_elem *elem =
4224 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
4225
4226 elem->next_page.addr.hi =
4227 cpu_to_le32(U64_HI(bp->eq_mapping +
4228 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
4229 elem->next_page.addr.lo =
4230 cpu_to_le32(U64_LO(bp->eq_mapping +
4231 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
4232 }
4233 bp->eq_cons = 0;
4234 bp->eq_prod = NUM_EQ_DESC;
4235 bp->eq_cons_sb = BNX2X_EQ_INDEX;
4236 }
4237
4238 static void bnx2x_init_ind_table(struct bnx2x *bp)
4239 {
4240 int func = BP_FUNC(bp);
4241 int i;
4242
4243 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
4244 return;
4245
4246 DP(NETIF_MSG_IFUP,
4247 "Initializing indirection table multi_mode %d\n", bp->multi_mode);
4248 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
4249 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4250 TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
4251 bp->fp->cl_id + (i % (bp->num_queues -
4252 NONE_ETH_CONTEXT_USE)));
4253 }
4254
4255 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4256 {
4257 int mode = bp->rx_mode;
4258 int port = BP_PORT(bp);
4259 u16 cl_id;
4260 u32 def_q_filters = 0;
4261
4262 /* All but management unicast packets should pass to the host as well */
4263 u32 llh_mask =
4264 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST |
4265 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST |
4266 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN |
4267 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN;
4268
4269 switch (mode) {
4270 case BNX2X_RX_MODE_NONE: /* no Rx */
4271 def_q_filters = BNX2X_ACCEPT_NONE;
4272 #ifdef BCM_CNIC
4273 if (!NO_FCOE(bp)) {
4274 cl_id = bnx2x_fcoe(bp, cl_id);
4275 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_NONE);
4276 }
4277 #endif
4278 break;
4279
4280 case BNX2X_RX_MODE_NORMAL:
4281 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4282 BNX2X_ACCEPT_MULTICAST;
4283 #ifdef BCM_CNIC
4284 cl_id = bnx2x_fcoe(bp, cl_id);
4285 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_UNICAST |
4286 BNX2X_ACCEPT_MULTICAST);
4287 #endif
4288 break;
4289
4290 case BNX2X_RX_MODE_ALLMULTI:
4291 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4292 BNX2X_ACCEPT_ALL_MULTICAST;
4293 #ifdef BCM_CNIC
4294 cl_id = bnx2x_fcoe(bp, cl_id);
4295 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_UNICAST |
4296 BNX2X_ACCEPT_MULTICAST);
4297 #endif
4298 break;
4299
4300 case BNX2X_RX_MODE_PROMISC:
4301 def_q_filters |= BNX2X_PROMISCUOUS_MODE;
4302 #ifdef BCM_CNIC
4303 cl_id = bnx2x_fcoe(bp, cl_id);
4304 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_UNICAST |
4305 BNX2X_ACCEPT_MULTICAST);
4306 #endif
4307 /* pass management unicast packets as well */
4308 llh_mask |= NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST;
4309 break;
4310
4311 default:
4312 BNX2X_ERR("BAD rx mode (%d)\n", mode);
4313 break;
4314 }
4315
4316 cl_id = BP_L_ID(bp);
4317 bnx2x_rxq_set_mac_filters(bp, cl_id, def_q_filters);
4318
4319 REG_WR(bp,
4320 (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
4321 NIG_REG_LLH0_BRB1_DRV_MASK), llh_mask);
4322
4323 DP(NETIF_MSG_IFUP, "rx mode %d\n"
4324 "drop_ucast 0x%x\ndrop_mcast 0x%x\ndrop_bcast 0x%x\n"
4325 "accp_ucast 0x%x\naccp_mcast 0x%x\naccp_bcast 0x%x\n"
4326 "unmatched_ucast 0x%x\n", mode,
4327 bp->mac_filters.ucast_drop_all,
4328 bp->mac_filters.mcast_drop_all,
4329 bp->mac_filters.bcast_drop_all,
4330 bp->mac_filters.ucast_accept_all,
4331 bp->mac_filters.mcast_accept_all,
4332 bp->mac_filters.bcast_accept_all,
4333 bp->mac_filters.unmatched_unicast
4334 );
4335
4336 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
4337 }
4338
4339 static void bnx2x_init_internal_common(struct bnx2x *bp)
4340 {
4341 int i;
4342
4343 if (!CHIP_IS_E1(bp)) {
4344
4345 /* xstorm needs to know whether to add ovlan to packets or not,
4346 * in switch-independent we'll write 0 to here... */
4347 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
4348 bp->mf_mode);
4349 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
4350 bp->mf_mode);
4351 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
4352 bp->mf_mode);
4353 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
4354 bp->mf_mode);
4355 }
4356
4357 if (IS_MF_SI(bp))
4358 /*
4359 * In switch independent mode, the TSTORM needs to accept
4360 * packets that failed classification, since approximate match
4361 * mac addresses aren't written to NIG LLH
4362 */
4363 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4364 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
4365
4366 /* Zero this manually as its initialization is
4367 currently missing in the initTool */
4368 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
4369 REG_WR(bp, BAR_USTRORM_INTMEM +
4370 USTORM_AGG_DATA_OFFSET + i * 4, 0);
4371 if (CHIP_IS_E2(bp)) {
4372 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
4373 CHIP_INT_MODE_IS_BC(bp) ?
4374 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
4375 }
4376 }
4377
4378 static void bnx2x_init_internal_port(struct bnx2x *bp)
4379 {
4380 /* port */
4381 bnx2x_dcb_init_intmem_pfc(bp);
4382 }
4383
4384 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4385 {
4386 switch (load_code) {
4387 case FW_MSG_CODE_DRV_LOAD_COMMON:
4388 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
4389 bnx2x_init_internal_common(bp);
4390 /* no break */
4391
4392 case FW_MSG_CODE_DRV_LOAD_PORT:
4393 bnx2x_init_internal_port(bp);
4394 /* no break */
4395
4396 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
4397 /* internal memory per function is
4398 initialized inside bnx2x_pf_init */
4399 break;
4400
4401 default:
4402 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
4403 break;
4404 }
4405 }
4406
4407 static void bnx2x_init_fp_sb(struct bnx2x *bp, int fp_idx)
4408 {
4409 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
4410
4411 fp->state = BNX2X_FP_STATE_CLOSED;
4412
4413 fp->index = fp->cid = fp_idx;
4414 fp->cl_id = BP_L_ID(bp) + fp_idx;
4415 fp->fw_sb_id = bp->base_fw_ndsb + fp->cl_id + CNIC_CONTEXT_USE;
4416 fp->igu_sb_id = bp->igu_base_sb + fp_idx + CNIC_CONTEXT_USE;
4417 /* qZone id equals to FW (per path) client id */
4418 fp->cl_qzone_id = fp->cl_id +
4419 BP_PORT(bp)*(CHIP_IS_E2(bp) ? ETH_MAX_RX_CLIENTS_E2 :
4420 ETH_MAX_RX_CLIENTS_E1H);
4421 /* init shortcut */
4422 fp->ustorm_rx_prods_offset = CHIP_IS_E2(bp) ?
4423 USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id) :
4424 USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
4425 /* Setup SB indicies */
4426 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4427 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4428
4429 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
4430 "cl_id %d fw_sb %d igu_sb %d\n",
4431 fp_idx, bp, fp->status_blk.e1x_sb, fp->cl_id, fp->fw_sb_id,
4432 fp->igu_sb_id);
4433 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
4434 fp->fw_sb_id, fp->igu_sb_id);
4435
4436 bnx2x_update_fpsb_idx(fp);
4437 }
4438
4439 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
4440 {
4441 int i;
4442
4443 for_each_eth_queue(bp, i)
4444 bnx2x_init_fp_sb(bp, i);
4445 #ifdef BCM_CNIC
4446 if (!NO_FCOE(bp))
4447 bnx2x_init_fcoe_fp(bp);
4448
4449 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
4450 BNX2X_VF_ID_INVALID, false,
4451 CNIC_SB_ID(bp), CNIC_IGU_SB_ID(bp));
4452
4453 #endif
4454
4455 /* ensure status block indices were read */
4456 rmb();
4457
4458 bnx2x_init_def_sb(bp);
4459 bnx2x_update_dsb_idx(bp);
4460 bnx2x_init_rx_rings(bp);
4461 bnx2x_init_tx_rings(bp);
4462 bnx2x_init_sp_ring(bp);
4463 bnx2x_init_eq_ring(bp);
4464 bnx2x_init_internal(bp, load_code);
4465 bnx2x_pf_init(bp);
4466 bnx2x_init_ind_table(bp);
4467 bnx2x_stats_init(bp);
4468
4469 /* At this point, we are ready for interrupts */
4470 atomic_set(&bp->intr_sem, 0);
4471
4472 /* flush all before enabling interrupts */
4473 mb();
4474 mmiowb();
4475
4476 bnx2x_int_enable(bp);
4477
4478 /* Check for SPIO5 */
4479 bnx2x_attn_int_deasserted0(bp,
4480 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
4481 AEU_INPUTS_ATTN_BITS_SPIO5);
4482 }
4483
4484 /* end of nic init */
4485
4486 /*
4487 * gzip service functions
4488 */
4489
4490 static int bnx2x_gunzip_init(struct bnx2x *bp)
4491 {
4492 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
4493 &bp->gunzip_mapping, GFP_KERNEL);
4494 if (bp->gunzip_buf == NULL)
4495 goto gunzip_nomem1;
4496
4497 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
4498 if (bp->strm == NULL)
4499 goto gunzip_nomem2;
4500
4501 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
4502 GFP_KERNEL);
4503 if (bp->strm->workspace == NULL)
4504 goto gunzip_nomem3;
4505
4506 return 0;
4507
4508 gunzip_nomem3:
4509 kfree(bp->strm);
4510 bp->strm = NULL;
4511
4512 gunzip_nomem2:
4513 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4514 bp->gunzip_mapping);
4515 bp->gunzip_buf = NULL;
4516
4517 gunzip_nomem1:
4518 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
4519 " un-compression\n");
4520 return -ENOMEM;
4521 }
4522
4523 static void bnx2x_gunzip_end(struct bnx2x *bp)
4524 {
4525 kfree(bp->strm->workspace);
4526 kfree(bp->strm);
4527 bp->strm = NULL;
4528
4529 if (bp->gunzip_buf) {
4530 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4531 bp->gunzip_mapping);
4532 bp->gunzip_buf = NULL;
4533 }
4534 }
4535
4536 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
4537 {
4538 int n, rc;
4539
4540 /* check gzip header */
4541 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
4542 BNX2X_ERR("Bad gzip header\n");
4543 return -EINVAL;
4544 }
4545
4546 n = 10;
4547
4548 #define FNAME 0x8
4549
4550 if (zbuf[3] & FNAME)
4551 while ((zbuf[n++] != 0) && (n < len));
4552
4553 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
4554 bp->strm->avail_in = len - n;
4555 bp->strm->next_out = bp->gunzip_buf;
4556 bp->strm->avail_out = FW_BUF_SIZE;
4557
4558 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
4559 if (rc != Z_OK)
4560 return rc;
4561
4562 rc = zlib_inflate(bp->strm, Z_FINISH);
4563 if ((rc != Z_OK) && (rc != Z_STREAM_END))
4564 netdev_err(bp->dev, "Firmware decompression error: %s\n",
4565 bp->strm->msg);
4566
4567 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
4568 if (bp->gunzip_outlen & 0x3)
4569 netdev_err(bp->dev, "Firmware decompression error:"
4570 " gunzip_outlen (%d) not aligned\n",
4571 bp->gunzip_outlen);
4572 bp->gunzip_outlen >>= 2;
4573
4574 zlib_inflateEnd(bp->strm);
4575
4576 if (rc == Z_STREAM_END)
4577 return 0;
4578
4579 return rc;
4580 }
4581
4582 /* nic load/unload */
4583
4584 /*
4585 * General service functions
4586 */
4587
4588 /* send a NIG loopback debug packet */
4589 static void bnx2x_lb_pckt(struct bnx2x *bp)
4590 {
4591 u32 wb_write[3];
4592
4593 /* Ethernet source and destination addresses */
4594 wb_write[0] = 0x55555555;
4595 wb_write[1] = 0x55555555;
4596 wb_write[2] = 0x20; /* SOP */
4597 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4598
4599 /* NON-IP protocol */
4600 wb_write[0] = 0x09000000;
4601 wb_write[1] = 0x55555555;
4602 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
4603 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4604 }
4605
4606 /* some of the internal memories
4607 * are not directly readable from the driver
4608 * to test them we send debug packets
4609 */
4610 static int bnx2x_int_mem_test(struct bnx2x *bp)
4611 {
4612 int factor;
4613 int count, i;
4614 u32 val = 0;
4615
4616 if (CHIP_REV_IS_FPGA(bp))
4617 factor = 120;
4618 else if (CHIP_REV_IS_EMUL(bp))
4619 factor = 200;
4620 else
4621 factor = 1;
4622
4623 /* Disable inputs of parser neighbor blocks */
4624 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4625 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4626 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4627 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
4628
4629 /* Write 0 to parser credits for CFC search request */
4630 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4631
4632 /* send Ethernet packet */
4633 bnx2x_lb_pckt(bp);
4634
4635 /* TODO do i reset NIG statistic? */
4636 /* Wait until NIG register shows 1 packet of size 0x10 */
4637 count = 1000 * factor;
4638 while (count) {
4639
4640 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4641 val = *bnx2x_sp(bp, wb_data[0]);
4642 if (val == 0x10)
4643 break;
4644
4645 msleep(10);
4646 count--;
4647 }
4648 if (val != 0x10) {
4649 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4650 return -1;
4651 }
4652
4653 /* Wait until PRS register shows 1 packet */
4654 count = 1000 * factor;
4655 while (count) {
4656 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4657 if (val == 1)
4658 break;
4659
4660 msleep(10);
4661 count--;
4662 }
4663 if (val != 0x1) {
4664 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4665 return -2;
4666 }
4667
4668 /* Reset and init BRB, PRS */
4669 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
4670 msleep(50);
4671 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
4672 msleep(50);
4673 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4674 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
4675
4676 DP(NETIF_MSG_HW, "part2\n");
4677
4678 /* Disable inputs of parser neighbor blocks */
4679 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4680 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4681 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4682 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
4683
4684 /* Write 0 to parser credits for CFC search request */
4685 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4686
4687 /* send 10 Ethernet packets */
4688 for (i = 0; i < 10; i++)
4689 bnx2x_lb_pckt(bp);
4690
4691 /* Wait until NIG register shows 10 + 1
4692 packets of size 11*0x10 = 0xb0 */
4693 count = 1000 * factor;
4694 while (count) {
4695
4696 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4697 val = *bnx2x_sp(bp, wb_data[0]);
4698 if (val == 0xb0)
4699 break;
4700
4701 msleep(10);
4702 count--;
4703 }
4704 if (val != 0xb0) {
4705 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4706 return -3;
4707 }
4708
4709 /* Wait until PRS register shows 2 packets */
4710 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4711 if (val != 2)
4712 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4713
4714 /* Write 1 to parser credits for CFC search request */
4715 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
4716
4717 /* Wait until PRS register shows 3 packets */
4718 msleep(10 * factor);
4719 /* Wait until NIG register shows 1 packet of size 0x10 */
4720 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4721 if (val != 3)
4722 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4723
4724 /* clear NIG EOP FIFO */
4725 for (i = 0; i < 11; i++)
4726 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
4727 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
4728 if (val != 1) {
4729 BNX2X_ERR("clear of NIG failed\n");
4730 return -4;
4731 }
4732
4733 /* Reset and init BRB, PRS, NIG */
4734 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
4735 msleep(50);
4736 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
4737 msleep(50);
4738 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4739 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
4740 #ifndef BCM_CNIC
4741 /* set NIC mode */
4742 REG_WR(bp, PRS_REG_NIC_MODE, 1);
4743 #endif
4744
4745 /* Enable inputs of parser neighbor blocks */
4746 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
4747 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
4748 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
4749 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
4750
4751 DP(NETIF_MSG_HW, "done\n");
4752
4753 return 0; /* OK */
4754 }
4755
4756 static void enable_blocks_attention(struct bnx2x *bp)
4757 {
4758 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
4759 if (CHIP_IS_E2(bp))
4760 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
4761 else
4762 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
4763 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
4764 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
4765 /*
4766 * mask read length error interrupts in brb for parser
4767 * (parsing unit and 'checksum and crc' unit)
4768 * these errors are legal (PU reads fixed length and CAC can cause
4769 * read length error on truncated packets)
4770 */
4771 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
4772 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
4773 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
4774 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
4775 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
4776 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
4777 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
4778 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
4779 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
4780 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
4781 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
4782 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
4783 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
4784 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
4785 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
4786 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
4787 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
4788 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
4789 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
4790
4791 if (CHIP_REV_IS_FPGA(bp))
4792 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
4793 else if (CHIP_IS_E2(bp))
4794 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
4795 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
4796 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
4797 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
4798 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
4799 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
4800 else
4801 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
4802 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
4803 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
4804 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
4805 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
4806 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
4807 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
4808 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
4809 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4810 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0X18); /* bit 3,4 masked */
4811 }
4812
4813 static const struct {
4814 u32 addr;
4815 u32 mask;
4816 } bnx2x_parity_mask[] = {
4817 {PXP_REG_PXP_PRTY_MASK, 0x3ffffff},
4818 {PXP2_REG_PXP2_PRTY_MASK_0, 0xffffffff},
4819 {PXP2_REG_PXP2_PRTY_MASK_1, 0x7f},
4820 {HC_REG_HC_PRTY_MASK, 0x7},
4821 {MISC_REG_MISC_PRTY_MASK, 0x1},
4822 {QM_REG_QM_PRTY_MASK, 0x0},
4823 {DORQ_REG_DORQ_PRTY_MASK, 0x0},
4824 {GRCBASE_UPB + PB_REG_PB_PRTY_MASK, 0x0},
4825 {GRCBASE_XPB + PB_REG_PB_PRTY_MASK, 0x0},
4826 {SRC_REG_SRC_PRTY_MASK, 0x4}, /* bit 2 */
4827 {CDU_REG_CDU_PRTY_MASK, 0x0},
4828 {CFC_REG_CFC_PRTY_MASK, 0x0},
4829 {DBG_REG_DBG_PRTY_MASK, 0x0},
4830 {DMAE_REG_DMAE_PRTY_MASK, 0x0},
4831 {BRB1_REG_BRB1_PRTY_MASK, 0x0},
4832 {PRS_REG_PRS_PRTY_MASK, (1<<6)},/* bit 6 */
4833 {TSDM_REG_TSDM_PRTY_MASK, 0x18}, /* bit 3,4 */
4834 {CSDM_REG_CSDM_PRTY_MASK, 0x8}, /* bit 3 */
4835 {USDM_REG_USDM_PRTY_MASK, 0x38}, /* bit 3,4,5 */
4836 {XSDM_REG_XSDM_PRTY_MASK, 0x8}, /* bit 3 */
4837 {TSEM_REG_TSEM_PRTY_MASK_0, 0x0},
4838 {TSEM_REG_TSEM_PRTY_MASK_1, 0x0},
4839 {USEM_REG_USEM_PRTY_MASK_0, 0x0},
4840 {USEM_REG_USEM_PRTY_MASK_1, 0x0},
4841 {CSEM_REG_CSEM_PRTY_MASK_0, 0x0},
4842 {CSEM_REG_CSEM_PRTY_MASK_1, 0x0},
4843 {XSEM_REG_XSEM_PRTY_MASK_0, 0x0},
4844 {XSEM_REG_XSEM_PRTY_MASK_1, 0x0}
4845 };
4846
4847 static void enable_blocks_parity(struct bnx2x *bp)
4848 {
4849 int i;
4850
4851 for (i = 0; i < ARRAY_SIZE(bnx2x_parity_mask); i++)
4852 REG_WR(bp, bnx2x_parity_mask[i].addr,
4853 bnx2x_parity_mask[i].mask);
4854 }
4855
4856
4857 static void bnx2x_reset_common(struct bnx2x *bp)
4858 {
4859 /* reset_common */
4860 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
4861 0xd3ffff7f);
4862 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
4863 }
4864
4865 static void bnx2x_init_pxp(struct bnx2x *bp)
4866 {
4867 u16 devctl;
4868 int r_order, w_order;
4869
4870 pci_read_config_word(bp->pdev,
4871 bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
4872 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
4873 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4874 if (bp->mrrs == -1)
4875 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4876 else {
4877 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
4878 r_order = bp->mrrs;
4879 }
4880
4881 bnx2x_init_pxp_arb(bp, r_order, w_order);
4882 }
4883
4884 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
4885 {
4886 int is_required;
4887 u32 val;
4888 int port;
4889
4890 if (BP_NOMCP(bp))
4891 return;
4892
4893 is_required = 0;
4894 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
4895 SHARED_HW_CFG_FAN_FAILURE_MASK;
4896
4897 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
4898 is_required = 1;
4899
4900 /*
4901 * The fan failure mechanism is usually related to the PHY type since
4902 * the power consumption of the board is affected by the PHY. Currently,
4903 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
4904 */
4905 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
4906 for (port = PORT_0; port < PORT_MAX; port++) {
4907 is_required |=
4908 bnx2x_fan_failure_det_req(
4909 bp,
4910 bp->common.shmem_base,
4911 bp->common.shmem2_base,
4912 port);
4913 }
4914
4915 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
4916
4917 if (is_required == 0)
4918 return;
4919
4920 /* Fan failure is indicated by SPIO 5 */
4921 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
4922 MISC_REGISTERS_SPIO_INPUT_HI_Z);
4923
4924 /* set to active low mode */
4925 val = REG_RD(bp, MISC_REG_SPIO_INT);
4926 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
4927 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
4928 REG_WR(bp, MISC_REG_SPIO_INT, val);
4929
4930 /* enable interrupt to signal the IGU */
4931 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
4932 val |= (1 << MISC_REGISTERS_SPIO_5);
4933 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
4934 }
4935
4936 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
4937 {
4938 u32 offset = 0;
4939
4940 if (CHIP_IS_E1(bp))
4941 return;
4942 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
4943 return;
4944
4945 switch (BP_ABS_FUNC(bp)) {
4946 case 0:
4947 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
4948 break;
4949 case 1:
4950 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
4951 break;
4952 case 2:
4953 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
4954 break;
4955 case 3:
4956 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
4957 break;
4958 case 4:
4959 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
4960 break;
4961 case 5:
4962 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
4963 break;
4964 case 6:
4965 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
4966 break;
4967 case 7:
4968 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
4969 break;
4970 default:
4971 return;
4972 }
4973
4974 REG_WR(bp, offset, pretend_func_num);
4975 REG_RD(bp, offset);
4976 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
4977 }
4978
4979 static void bnx2x_pf_disable(struct bnx2x *bp)
4980 {
4981 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
4982 val &= ~IGU_PF_CONF_FUNC_EN;
4983
4984 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
4985 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
4986 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
4987 }
4988
4989 static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
4990 {
4991 u32 val, i;
4992
4993 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
4994
4995 bnx2x_reset_common(bp);
4996 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
4997 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
4998
4999 bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE);
5000 if (!CHIP_IS_E1(bp))
5001 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_MF(bp));
5002
5003 if (CHIP_IS_E2(bp)) {
5004 u8 fid;
5005
5006 /**
5007 * 4-port mode or 2-port mode we need to turn of master-enable
5008 * for everyone, after that, turn it back on for self.
5009 * so, we disregard multi-function or not, and always disable
5010 * for all functions on the given path, this means 0,2,4,6 for
5011 * path 0 and 1,3,5,7 for path 1
5012 */
5013 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX*2; fid += 2) {
5014 if (fid == BP_ABS_FUNC(bp)) {
5015 REG_WR(bp,
5016 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5017 1);
5018 continue;
5019 }
5020
5021 bnx2x_pretend_func(bp, fid);
5022 /* clear pf enable */
5023 bnx2x_pf_disable(bp);
5024 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5025 }
5026 }
5027
5028 bnx2x_init_block(bp, PXP_BLOCK, COMMON_STAGE);
5029 if (CHIP_IS_E1(bp)) {
5030 /* enable HW interrupt from PXP on USDM overflow
5031 bit 16 on INT_MASK_0 */
5032 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5033 }
5034
5035 bnx2x_init_block(bp, PXP2_BLOCK, COMMON_STAGE);
5036 bnx2x_init_pxp(bp);
5037
5038 #ifdef __BIG_ENDIAN
5039 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5040 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5041 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5042 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5043 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5044 /* make sure this value is 0 */
5045 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
5046
5047 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5048 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5049 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5050 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5051 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5052 #endif
5053
5054 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5055
5056 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5057 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5058
5059 /* let the HW do it's magic ... */
5060 msleep(100);
5061 /* finish PXP init */
5062 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5063 if (val != 1) {
5064 BNX2X_ERR("PXP2 CFG failed\n");
5065 return -EBUSY;
5066 }
5067 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5068 if (val != 1) {
5069 BNX2X_ERR("PXP2 RD_INIT failed\n");
5070 return -EBUSY;
5071 }
5072
5073 /* Timers bug workaround E2 only. We need to set the entire ILT to
5074 * have entries with value "0" and valid bit on.
5075 * This needs to be done by the first PF that is loaded in a path
5076 * (i.e. common phase)
5077 */
5078 if (CHIP_IS_E2(bp)) {
5079 struct ilt_client_info ilt_cli;
5080 struct bnx2x_ilt ilt;
5081 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5082 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5083
5084 /* initalize dummy TM client */
5085 ilt_cli.start = 0;
5086 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5087 ilt_cli.client_num = ILT_CLIENT_TM;
5088
5089 /* Step 1: set zeroes to all ilt page entries with valid bit on
5090 * Step 2: set the timers first/last ilt entry to point
5091 * to the entire range to prevent ILT range error for 3rd/4th
5092 * vnic (this code assumes existance of the vnic)
5093 *
5094 * both steps performed by call to bnx2x_ilt_client_init_op()
5095 * with dummy TM client
5096 *
5097 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5098 * and his brother are split registers
5099 */
5100 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
5101 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
5102 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5103
5104 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
5105 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
5106 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
5107 }
5108
5109
5110 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5111 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5112
5113 if (CHIP_IS_E2(bp)) {
5114 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
5115 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
5116 bnx2x_init_block(bp, PGLUE_B_BLOCK, COMMON_STAGE);
5117
5118 bnx2x_init_block(bp, ATC_BLOCK, COMMON_STAGE);
5119
5120 /* let the HW do it's magic ... */
5121 do {
5122 msleep(200);
5123 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
5124 } while (factor-- && (val != 1));
5125
5126 if (val != 1) {
5127 BNX2X_ERR("ATC_INIT failed\n");
5128 return -EBUSY;
5129 }
5130 }
5131
5132 bnx2x_init_block(bp, DMAE_BLOCK, COMMON_STAGE);
5133
5134 /* clean the DMAE memory */
5135 bp->dmae_ready = 1;
5136 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
5137
5138 bnx2x_init_block(bp, TCM_BLOCK, COMMON_STAGE);
5139 bnx2x_init_block(bp, UCM_BLOCK, COMMON_STAGE);
5140 bnx2x_init_block(bp, CCM_BLOCK, COMMON_STAGE);
5141 bnx2x_init_block(bp, XCM_BLOCK, COMMON_STAGE);
5142
5143 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5144 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5145 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5146 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5147
5148 bnx2x_init_block(bp, QM_BLOCK, COMMON_STAGE);
5149
5150 if (CHIP_MODE_IS_4_PORT(bp))
5151 bnx2x_init_block(bp, QM_4PORT_BLOCK, COMMON_STAGE);
5152
5153 /* QM queues pointers table */
5154 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
5155
5156 /* soft reset pulse */
5157 REG_WR(bp, QM_REG_SOFT_RESET, 1);
5158 REG_WR(bp, QM_REG_SOFT_RESET, 0);
5159
5160 #ifdef BCM_CNIC
5161 bnx2x_init_block(bp, TIMERS_BLOCK, COMMON_STAGE);
5162 #endif
5163
5164 bnx2x_init_block(bp, DQ_BLOCK, COMMON_STAGE);
5165 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
5166
5167 if (!CHIP_REV_IS_SLOW(bp)) {
5168 /* enable hw interrupt from doorbell Q */
5169 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5170 }
5171
5172 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
5173 if (CHIP_MODE_IS_4_PORT(bp)) {
5174 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD, 248);
5175 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD, 328);
5176 }
5177
5178 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
5179 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
5180 #ifndef BCM_CNIC
5181 /* set NIC mode */
5182 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5183 #endif
5184 if (!CHIP_IS_E1(bp))
5185 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_MF_SD(bp));
5186
5187 if (CHIP_IS_E2(bp)) {
5188 /* Bit-map indicating which L2 hdrs may appear after the
5189 basic Ethernet header */
5190 int has_ovlan = IS_MF_SD(bp);
5191 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5192 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5193 }
5194
5195 bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE);
5196 bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE);
5197 bnx2x_init_block(bp, USDM_BLOCK, COMMON_STAGE);
5198 bnx2x_init_block(bp, XSDM_BLOCK, COMMON_STAGE);
5199
5200 bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5201 bnx2x_init_fill(bp, USEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5202 bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5203 bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5204
5205 bnx2x_init_block(bp, TSEM_BLOCK, COMMON_STAGE);
5206 bnx2x_init_block(bp, USEM_BLOCK, COMMON_STAGE);
5207 bnx2x_init_block(bp, CSEM_BLOCK, COMMON_STAGE);
5208 bnx2x_init_block(bp, XSEM_BLOCK, COMMON_STAGE);
5209
5210 if (CHIP_MODE_IS_4_PORT(bp))
5211 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, COMMON_STAGE);
5212
5213 /* sync semi rtc */
5214 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5215 0x80000000);
5216 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5217 0x80000000);
5218
5219 bnx2x_init_block(bp, UPB_BLOCK, COMMON_STAGE);
5220 bnx2x_init_block(bp, XPB_BLOCK, COMMON_STAGE);
5221 bnx2x_init_block(bp, PBF_BLOCK, COMMON_STAGE);
5222
5223 if (CHIP_IS_E2(bp)) {
5224 int has_ovlan = IS_MF_SD(bp);
5225 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5226 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5227 }
5228
5229 REG_WR(bp, SRC_REG_SOFT_RST, 1);
5230 for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4)
5231 REG_WR(bp, i, random32());
5232
5233 bnx2x_init_block(bp, SRCH_BLOCK, COMMON_STAGE);
5234 #ifdef BCM_CNIC
5235 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
5236 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
5237 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
5238 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
5239 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
5240 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
5241 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
5242 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
5243 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
5244 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
5245 #endif
5246 REG_WR(bp, SRC_REG_SOFT_RST, 0);
5247
5248 if (sizeof(union cdu_context) != 1024)
5249 /* we currently assume that a context is 1024 bytes */
5250 dev_alert(&bp->pdev->dev, "please adjust the size "
5251 "of cdu_context(%ld)\n",
5252 (long)sizeof(union cdu_context));
5253
5254 bnx2x_init_block(bp, CDU_BLOCK, COMMON_STAGE);
5255 val = (4 << 24) + (0 << 12) + 1024;
5256 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
5257
5258 bnx2x_init_block(bp, CFC_BLOCK, COMMON_STAGE);
5259 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
5260 /* enable context validation interrupt from CFC */
5261 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5262
5263 /* set the thresholds to prevent CFC/CDU race */
5264 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
5265
5266 bnx2x_init_block(bp, HC_BLOCK, COMMON_STAGE);
5267
5268 if (CHIP_IS_E2(bp) && BP_NOMCP(bp))
5269 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
5270
5271 bnx2x_init_block(bp, IGU_BLOCK, COMMON_STAGE);
5272 bnx2x_init_block(bp, MISC_AEU_BLOCK, COMMON_STAGE);
5273
5274 bnx2x_init_block(bp, PXPCS_BLOCK, COMMON_STAGE);
5275 /* Reset PCIE errors for debug */
5276 REG_WR(bp, 0x2814, 0xffffffff);
5277 REG_WR(bp, 0x3820, 0xffffffff);
5278
5279 if (CHIP_IS_E2(bp)) {
5280 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
5281 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
5282 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
5283 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
5284 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
5285 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
5286 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
5287 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
5288 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
5289 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
5290 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
5291 }
5292
5293 bnx2x_init_block(bp, EMAC0_BLOCK, COMMON_STAGE);
5294 bnx2x_init_block(bp, EMAC1_BLOCK, COMMON_STAGE);
5295 bnx2x_init_block(bp, DBU_BLOCK, COMMON_STAGE);
5296 bnx2x_init_block(bp, DBG_BLOCK, COMMON_STAGE);
5297
5298 bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE);
5299 if (!CHIP_IS_E1(bp)) {
5300 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
5301 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
5302 }
5303 if (CHIP_IS_E2(bp)) {
5304 /* Bit-map indicating which L2 hdrs may appear after the
5305 basic Ethernet header */
5306 REG_WR(bp, NIG_REG_P0_HDRS_AFTER_BASIC, (IS_MF_SD(bp) ? 7 : 6));
5307 }
5308
5309 if (CHIP_REV_IS_SLOW(bp))
5310 msleep(200);
5311
5312 /* finish CFC init */
5313 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5314 if (val != 1) {
5315 BNX2X_ERR("CFC LL_INIT failed\n");
5316 return -EBUSY;
5317 }
5318 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
5319 if (val != 1) {
5320 BNX2X_ERR("CFC AC_INIT failed\n");
5321 return -EBUSY;
5322 }
5323 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
5324 if (val != 1) {
5325 BNX2X_ERR("CFC CAM_INIT failed\n");
5326 return -EBUSY;
5327 }
5328 REG_WR(bp, CFC_REG_DEBUG0, 0);
5329
5330 if (CHIP_IS_E1(bp)) {
5331 /* read NIG statistic
5332 to see if this is our first up since powerup */
5333 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5334 val = *bnx2x_sp(bp, wb_data[0]);
5335
5336 /* do internal memory self test */
5337 if ((val == 0) && bnx2x_int_mem_test(bp)) {
5338 BNX2X_ERR("internal mem self test failed\n");
5339 return -EBUSY;
5340 }
5341 }
5342
5343 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
5344 bp->common.shmem_base,
5345 bp->common.shmem2_base);
5346
5347 bnx2x_setup_fan_failure_detection(bp);
5348
5349 /* clear PXP2 attentions */
5350 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
5351
5352 enable_blocks_attention(bp);
5353 if (CHIP_PARITY_SUPPORTED(bp))
5354 enable_blocks_parity(bp);
5355
5356 if (!BP_NOMCP(bp)) {
5357 /* In E2 2-PORT mode, same ext phy is used for the two paths */
5358 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
5359 CHIP_IS_E1x(bp)) {
5360 u32 shmem_base[2], shmem2_base[2];
5361 shmem_base[0] = bp->common.shmem_base;
5362 shmem2_base[0] = bp->common.shmem2_base;
5363 if (CHIP_IS_E2(bp)) {
5364 shmem_base[1] =
5365 SHMEM2_RD(bp, other_shmem_base_addr);
5366 shmem2_base[1] =
5367 SHMEM2_RD(bp, other_shmem2_base_addr);
5368 }
5369 bnx2x_acquire_phy_lock(bp);
5370 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5371 bp->common.chip_id);
5372 bnx2x_release_phy_lock(bp);
5373 }
5374 } else
5375 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
5376
5377 return 0;
5378 }
5379
5380 static int bnx2x_init_hw_port(struct bnx2x *bp)
5381 {
5382 int port = BP_PORT(bp);
5383 int init_stage = port ? PORT1_STAGE : PORT0_STAGE;
5384 u32 low, high;
5385 u32 val;
5386
5387 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
5388
5389 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
5390
5391 bnx2x_init_block(bp, PXP_BLOCK, init_stage);
5392 bnx2x_init_block(bp, PXP2_BLOCK, init_stage);
5393
5394 /* Timers bug workaround: disables the pf_master bit in pglue at
5395 * common phase, we need to enable it here before any dmae access are
5396 * attempted. Therefore we manually added the enable-master to the
5397 * port phase (it also happens in the function phase)
5398 */
5399 if (CHIP_IS_E2(bp))
5400 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5401
5402 bnx2x_init_block(bp, TCM_BLOCK, init_stage);
5403 bnx2x_init_block(bp, UCM_BLOCK, init_stage);
5404 bnx2x_init_block(bp, CCM_BLOCK, init_stage);
5405 bnx2x_init_block(bp, XCM_BLOCK, init_stage);
5406
5407 /* QM cid (connection) count */
5408 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
5409
5410 #ifdef BCM_CNIC
5411 bnx2x_init_block(bp, TIMERS_BLOCK, init_stage);
5412 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
5413 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
5414 #endif
5415
5416 bnx2x_init_block(bp, DQ_BLOCK, init_stage);
5417
5418 if (CHIP_MODE_IS_4_PORT(bp))
5419 bnx2x_init_block(bp, QM_4PORT_BLOCK, init_stage);
5420
5421 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
5422 bnx2x_init_block(bp, BRB1_BLOCK, init_stage);
5423 if (CHIP_REV_IS_SLOW(bp) && CHIP_IS_E1(bp)) {
5424 /* no pause for emulation and FPGA */
5425 low = 0;
5426 high = 513;
5427 } else {
5428 if (IS_MF(bp))
5429 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
5430 else if (bp->dev->mtu > 4096) {
5431 if (bp->flags & ONE_PORT_FLAG)
5432 low = 160;
5433 else {
5434 val = bp->dev->mtu;
5435 /* (24*1024 + val*4)/256 */
5436 low = 96 + (val/64) +
5437 ((val % 64) ? 1 : 0);
5438 }
5439 } else
5440 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
5441 high = low + 56; /* 14*1024/256 */
5442 }
5443 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
5444 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
5445 }
5446
5447 if (CHIP_MODE_IS_4_PORT(bp)) {
5448 REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 + port*8, 248);
5449 REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 + port*8, 328);
5450 REG_WR(bp, (BP_PORT(bp) ? BRB1_REG_MAC_GUARANTIED_1 :
5451 BRB1_REG_MAC_GUARANTIED_0), 40);
5452 }
5453
5454 bnx2x_init_block(bp, PRS_BLOCK, init_stage);
5455
5456 bnx2x_init_block(bp, TSDM_BLOCK, init_stage);
5457 bnx2x_init_block(bp, CSDM_BLOCK, init_stage);
5458 bnx2x_init_block(bp, USDM_BLOCK, init_stage);
5459 bnx2x_init_block(bp, XSDM_BLOCK, init_stage);
5460
5461 bnx2x_init_block(bp, TSEM_BLOCK, init_stage);
5462 bnx2x_init_block(bp, USEM_BLOCK, init_stage);
5463 bnx2x_init_block(bp, CSEM_BLOCK, init_stage);
5464 bnx2x_init_block(bp, XSEM_BLOCK, init_stage);
5465 if (CHIP_MODE_IS_4_PORT(bp))
5466 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, init_stage);
5467
5468 bnx2x_init_block(bp, UPB_BLOCK, init_stage);
5469 bnx2x_init_block(bp, XPB_BLOCK, init_stage);
5470
5471 bnx2x_init_block(bp, PBF_BLOCK, init_stage);
5472
5473 if (!CHIP_IS_E2(bp)) {
5474 /* configure PBF to work without PAUSE mtu 9000 */
5475 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
5476
5477 /* update threshold */
5478 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
5479 /* update init credit */
5480 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
5481
5482 /* probe changes */
5483 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
5484 udelay(50);
5485 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
5486 }
5487
5488 #ifdef BCM_CNIC
5489 bnx2x_init_block(bp, SRCH_BLOCK, init_stage);
5490 #endif
5491 bnx2x_init_block(bp, CDU_BLOCK, init_stage);
5492 bnx2x_init_block(bp, CFC_BLOCK, init_stage);
5493
5494 if (CHIP_IS_E1(bp)) {
5495 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5496 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5497 }
5498 bnx2x_init_block(bp, HC_BLOCK, init_stage);
5499
5500 bnx2x_init_block(bp, IGU_BLOCK, init_stage);
5501
5502 bnx2x_init_block(bp, MISC_AEU_BLOCK, init_stage);
5503 /* init aeu_mask_attn_func_0/1:
5504 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
5505 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
5506 * bits 4-7 are used for "per vn group attention" */
5507 val = IS_MF(bp) ? 0xF7 : 0x7;
5508 /* Enable DCBX attention for all but E1 */
5509 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
5510 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
5511
5512 bnx2x_init_block(bp, PXPCS_BLOCK, init_stage);
5513 bnx2x_init_block(bp, EMAC0_BLOCK, init_stage);
5514 bnx2x_init_block(bp, EMAC1_BLOCK, init_stage);
5515 bnx2x_init_block(bp, DBU_BLOCK, init_stage);
5516 bnx2x_init_block(bp, DBG_BLOCK, init_stage);
5517
5518 bnx2x_init_block(bp, NIG_BLOCK, init_stage);
5519
5520 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
5521
5522 if (!CHIP_IS_E1(bp)) {
5523 /* 0x2 disable mf_ov, 0x1 enable */
5524 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
5525 (IS_MF_SD(bp) ? 0x1 : 0x2));
5526
5527 if (CHIP_IS_E2(bp)) {
5528 val = 0;
5529 switch (bp->mf_mode) {
5530 case MULTI_FUNCTION_SD:
5531 val = 1;
5532 break;
5533 case MULTI_FUNCTION_SI:
5534 val = 2;
5535 break;
5536 }
5537
5538 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
5539 NIG_REG_LLH0_CLS_TYPE), val);
5540 }
5541 {
5542 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
5543 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
5544 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
5545 }
5546 }
5547
5548 bnx2x_init_block(bp, MCP_BLOCK, init_stage);
5549 bnx2x_init_block(bp, DMAE_BLOCK, init_stage);
5550 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
5551 bp->common.shmem_base,
5552 bp->common.shmem2_base);
5553 if (bnx2x_fan_failure_det_req(bp, bp->common.shmem_base,
5554 bp->common.shmem2_base, port)) {
5555 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5556 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5557 val = REG_RD(bp, reg_addr);
5558 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
5559 REG_WR(bp, reg_addr, val);
5560 }
5561 bnx2x__link_reset(bp);
5562
5563 return 0;
5564 }
5565
5566 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
5567 {
5568 int reg;
5569
5570 if (CHIP_IS_E1(bp))
5571 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
5572 else
5573 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
5574
5575 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
5576 }
5577
5578 static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
5579 {
5580 bnx2x_igu_clear_sb_gen(bp, idu_sb_id, true /*PF*/);
5581 }
5582
5583 static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
5584 {
5585 u32 i, base = FUNC_ILT_BASE(func);
5586 for (i = base; i < base + ILT_PER_FUNC; i++)
5587 bnx2x_ilt_wr(bp, i, 0);
5588 }
5589
5590 static int bnx2x_init_hw_func(struct bnx2x *bp)
5591 {
5592 int port = BP_PORT(bp);
5593 int func = BP_FUNC(bp);
5594 struct bnx2x_ilt *ilt = BP_ILT(bp);
5595 u16 cdu_ilt_start;
5596 u32 addr, val;
5597 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
5598 int i, main_mem_width;
5599
5600 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
5601
5602 /* set MSI reconfigure capability */
5603 if (bp->common.int_block == INT_BLOCK_HC) {
5604 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
5605 val = REG_RD(bp, addr);
5606 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
5607 REG_WR(bp, addr, val);
5608 }
5609
5610 ilt = BP_ILT(bp);
5611 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
5612
5613 for (i = 0; i < L2_ILT_LINES(bp); i++) {
5614 ilt->lines[cdu_ilt_start + i].page =
5615 bp->context.vcxt + (ILT_PAGE_CIDS * i);
5616 ilt->lines[cdu_ilt_start + i].page_mapping =
5617 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
5618 /* cdu ilt pages are allocated manually so there's no need to
5619 set the size */
5620 }
5621 bnx2x_ilt_init_op(bp, INITOP_SET);
5622
5623 #ifdef BCM_CNIC
5624 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
5625
5626 /* T1 hash bits value determines the T1 number of entries */
5627 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
5628 #endif
5629
5630 #ifndef BCM_CNIC
5631 /* set NIC mode */
5632 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5633 #endif /* BCM_CNIC */
5634
5635 if (CHIP_IS_E2(bp)) {
5636 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
5637
5638 /* Turn on a single ISR mode in IGU if driver is going to use
5639 * INT#x or MSI
5640 */
5641 if (!(bp->flags & USING_MSIX_FLAG))
5642 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
5643 /*
5644 * Timers workaround bug: function init part.
5645 * Need to wait 20msec after initializing ILT,
5646 * needed to make sure there are no requests in
5647 * one of the PXP internal queues with "old" ILT addresses
5648 */
5649 msleep(20);
5650 /*
5651 * Master enable - Due to WB DMAE writes performed before this
5652 * register is re-initialized as part of the regular function
5653 * init
5654 */
5655 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5656 /* Enable the function in IGU */
5657 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
5658 }
5659
5660 bp->dmae_ready = 1;
5661
5662 bnx2x_init_block(bp, PGLUE_B_BLOCK, FUNC0_STAGE + func);
5663
5664 if (CHIP_IS_E2(bp))
5665 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
5666
5667 bnx2x_init_block(bp, MISC_BLOCK, FUNC0_STAGE + func);
5668 bnx2x_init_block(bp, TCM_BLOCK, FUNC0_STAGE + func);
5669 bnx2x_init_block(bp, UCM_BLOCK, FUNC0_STAGE + func);
5670 bnx2x_init_block(bp, CCM_BLOCK, FUNC0_STAGE + func);
5671 bnx2x_init_block(bp, XCM_BLOCK, FUNC0_STAGE + func);
5672 bnx2x_init_block(bp, TSEM_BLOCK, FUNC0_STAGE + func);
5673 bnx2x_init_block(bp, USEM_BLOCK, FUNC0_STAGE + func);
5674 bnx2x_init_block(bp, CSEM_BLOCK, FUNC0_STAGE + func);
5675 bnx2x_init_block(bp, XSEM_BLOCK, FUNC0_STAGE + func);
5676
5677 if (CHIP_IS_E2(bp)) {
5678 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_PATH_ID_OFFSET,
5679 BP_PATH(bp));
5680 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_PATH_ID_OFFSET,
5681 BP_PATH(bp));
5682 }
5683
5684 if (CHIP_MODE_IS_4_PORT(bp))
5685 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, FUNC0_STAGE + func);
5686
5687 if (CHIP_IS_E2(bp))
5688 REG_WR(bp, QM_REG_PF_EN, 1);
5689
5690 bnx2x_init_block(bp, QM_BLOCK, FUNC0_STAGE + func);
5691
5692 if (CHIP_MODE_IS_4_PORT(bp))
5693 bnx2x_init_block(bp, QM_4PORT_BLOCK, FUNC0_STAGE + func);
5694
5695 bnx2x_init_block(bp, TIMERS_BLOCK, FUNC0_STAGE + func);
5696 bnx2x_init_block(bp, DQ_BLOCK, FUNC0_STAGE + func);
5697 bnx2x_init_block(bp, BRB1_BLOCK, FUNC0_STAGE + func);
5698 bnx2x_init_block(bp, PRS_BLOCK, FUNC0_STAGE + func);
5699 bnx2x_init_block(bp, TSDM_BLOCK, FUNC0_STAGE + func);
5700 bnx2x_init_block(bp, CSDM_BLOCK, FUNC0_STAGE + func);
5701 bnx2x_init_block(bp, USDM_BLOCK, FUNC0_STAGE + func);
5702 bnx2x_init_block(bp, XSDM_BLOCK, FUNC0_STAGE + func);
5703 bnx2x_init_block(bp, UPB_BLOCK, FUNC0_STAGE + func);
5704 bnx2x_init_block(bp, XPB_BLOCK, FUNC0_STAGE + func);
5705 bnx2x_init_block(bp, PBF_BLOCK, FUNC0_STAGE + func);
5706 if (CHIP_IS_E2(bp))
5707 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
5708
5709 bnx2x_init_block(bp, CDU_BLOCK, FUNC0_STAGE + func);
5710
5711 bnx2x_init_block(bp, CFC_BLOCK, FUNC0_STAGE + func);
5712
5713 if (CHIP_IS_E2(bp))
5714 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
5715
5716 if (IS_MF(bp)) {
5717 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
5718 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
5719 }
5720
5721 bnx2x_init_block(bp, MISC_AEU_BLOCK, FUNC0_STAGE + func);
5722
5723 /* HC init per function */
5724 if (bp->common.int_block == INT_BLOCK_HC) {
5725 if (CHIP_IS_E1H(bp)) {
5726 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5727
5728 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5729 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5730 }
5731 bnx2x_init_block(bp, HC_BLOCK, FUNC0_STAGE + func);
5732
5733 } else {
5734 int num_segs, sb_idx, prod_offset;
5735
5736 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5737
5738 if (CHIP_IS_E2(bp)) {
5739 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
5740 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
5741 }
5742
5743 bnx2x_init_block(bp, IGU_BLOCK, FUNC0_STAGE + func);
5744
5745 if (CHIP_IS_E2(bp)) {
5746 int dsb_idx = 0;
5747 /**
5748 * Producer memory:
5749 * E2 mode: address 0-135 match to the mapping memory;
5750 * 136 - PF0 default prod; 137 - PF1 default prod;
5751 * 138 - PF2 default prod; 139 - PF3 default prod;
5752 * 140 - PF0 attn prod; 141 - PF1 attn prod;
5753 * 142 - PF2 attn prod; 143 - PF3 attn prod;
5754 * 144-147 reserved.
5755 *
5756 * E1.5 mode - In backward compatible mode;
5757 * for non default SB; each even line in the memory
5758 * holds the U producer and each odd line hold
5759 * the C producer. The first 128 producers are for
5760 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
5761 * producers are for the DSB for each PF.
5762 * Each PF has five segments: (the order inside each
5763 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
5764 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
5765 * 144-147 attn prods;
5766 */
5767 /* non-default-status-blocks */
5768 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5769 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
5770 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
5771 prod_offset = (bp->igu_base_sb + sb_idx) *
5772 num_segs;
5773
5774 for (i = 0; i < num_segs; i++) {
5775 addr = IGU_REG_PROD_CONS_MEMORY +
5776 (prod_offset + i) * 4;
5777 REG_WR(bp, addr, 0);
5778 }
5779 /* send consumer update with value 0 */
5780 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
5781 USTORM_ID, 0, IGU_INT_NOP, 1);
5782 bnx2x_igu_clear_sb(bp,
5783 bp->igu_base_sb + sb_idx);
5784 }
5785
5786 /* default-status-blocks */
5787 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5788 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
5789
5790 if (CHIP_MODE_IS_4_PORT(bp))
5791 dsb_idx = BP_FUNC(bp);
5792 else
5793 dsb_idx = BP_E1HVN(bp);
5794
5795 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
5796 IGU_BC_BASE_DSB_PROD + dsb_idx :
5797 IGU_NORM_BASE_DSB_PROD + dsb_idx);
5798
5799 for (i = 0; i < (num_segs * E1HVN_MAX);
5800 i += E1HVN_MAX) {
5801 addr = IGU_REG_PROD_CONS_MEMORY +
5802 (prod_offset + i)*4;
5803 REG_WR(bp, addr, 0);
5804 }
5805 /* send consumer update with 0 */
5806 if (CHIP_INT_MODE_IS_BC(bp)) {
5807 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5808 USTORM_ID, 0, IGU_INT_NOP, 1);
5809 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5810 CSTORM_ID, 0, IGU_INT_NOP, 1);
5811 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5812 XSTORM_ID, 0, IGU_INT_NOP, 1);
5813 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5814 TSTORM_ID, 0, IGU_INT_NOP, 1);
5815 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5816 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5817 } else {
5818 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5819 USTORM_ID, 0, IGU_INT_NOP, 1);
5820 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5821 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5822 }
5823 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
5824
5825 /* !!! these should become driver const once
5826 rf-tool supports split-68 const */
5827 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
5828 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
5829 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
5830 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
5831 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
5832 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
5833 }
5834 }
5835
5836 /* Reset PCIE errors for debug */
5837 REG_WR(bp, 0x2114, 0xffffffff);
5838 REG_WR(bp, 0x2120, 0xffffffff);
5839
5840 bnx2x_init_block(bp, EMAC0_BLOCK, FUNC0_STAGE + func);
5841 bnx2x_init_block(bp, EMAC1_BLOCK, FUNC0_STAGE + func);
5842 bnx2x_init_block(bp, DBU_BLOCK, FUNC0_STAGE + func);
5843 bnx2x_init_block(bp, DBG_BLOCK, FUNC0_STAGE + func);
5844 bnx2x_init_block(bp, MCP_BLOCK, FUNC0_STAGE + func);
5845 bnx2x_init_block(bp, DMAE_BLOCK, FUNC0_STAGE + func);
5846
5847 if (CHIP_IS_E1x(bp)) {
5848 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
5849 main_mem_base = HC_REG_MAIN_MEMORY +
5850 BP_PORT(bp) * (main_mem_size * 4);
5851 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
5852 main_mem_width = 8;
5853
5854 val = REG_RD(bp, main_mem_prty_clr);
5855 if (val)
5856 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
5857 "block during "
5858 "function init (0x%x)!\n", val);
5859
5860 /* Clear "false" parity errors in MSI-X table */
5861 for (i = main_mem_base;
5862 i < main_mem_base + main_mem_size * 4;
5863 i += main_mem_width) {
5864 bnx2x_read_dmae(bp, i, main_mem_width / 4);
5865 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
5866 i, main_mem_width / 4);
5867 }
5868 /* Clear HC parity attention */
5869 REG_RD(bp, main_mem_prty_clr);
5870 }
5871
5872 bnx2x_phy_probe(&bp->link_params);
5873
5874 return 0;
5875 }
5876
5877 int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
5878 {
5879 int rc = 0;
5880
5881 DP(BNX2X_MSG_MCP, "function %d load_code %x\n",
5882 BP_ABS_FUNC(bp), load_code);
5883
5884 bp->dmae_ready = 0;
5885 mutex_init(&bp->dmae_mutex);
5886 rc = bnx2x_gunzip_init(bp);
5887 if (rc)
5888 return rc;
5889
5890 switch (load_code) {
5891 case FW_MSG_CODE_DRV_LOAD_COMMON:
5892 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5893 rc = bnx2x_init_hw_common(bp, load_code);
5894 if (rc)
5895 goto init_hw_err;
5896 /* no break */
5897
5898 case FW_MSG_CODE_DRV_LOAD_PORT:
5899 rc = bnx2x_init_hw_port(bp);
5900 if (rc)
5901 goto init_hw_err;
5902 /* no break */
5903
5904 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5905 rc = bnx2x_init_hw_func(bp);
5906 if (rc)
5907 goto init_hw_err;
5908 break;
5909
5910 default:
5911 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5912 break;
5913 }
5914
5915 if (!BP_NOMCP(bp)) {
5916 int mb_idx = BP_FW_MB_IDX(bp);
5917
5918 bp->fw_drv_pulse_wr_seq =
5919 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
5920 DRV_PULSE_SEQ_MASK);
5921 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
5922 }
5923
5924 init_hw_err:
5925 bnx2x_gunzip_end(bp);
5926
5927 return rc;
5928 }
5929
5930 void bnx2x_free_mem(struct bnx2x *bp)
5931 {
5932
5933 #define BNX2X_PCI_FREE(x, y, size) \
5934 do { \
5935 if (x) { \
5936 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \
5937 x = NULL; \
5938 y = 0; \
5939 } \
5940 } while (0)
5941
5942 #define BNX2X_FREE(x) \
5943 do { \
5944 if (x) { \
5945 kfree((void *)x); \
5946 x = NULL; \
5947 } \
5948 } while (0)
5949
5950 int i;
5951
5952 /* fastpath */
5953 /* Common */
5954 for_each_queue(bp, i) {
5955 #ifdef BCM_CNIC
5956 /* FCoE client uses default status block */
5957 if (IS_FCOE_IDX(i)) {
5958 union host_hc_status_block *sb =
5959 &bnx2x_fp(bp, i, status_blk);
5960 memset(sb, 0, sizeof(union host_hc_status_block));
5961 bnx2x_fp(bp, i, status_blk_mapping) = 0;
5962 } else {
5963 #endif
5964 /* status blocks */
5965 if (CHIP_IS_E2(bp))
5966 BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk.e2_sb),
5967 bnx2x_fp(bp, i, status_blk_mapping),
5968 sizeof(struct host_hc_status_block_e2));
5969 else
5970 BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk.e1x_sb),
5971 bnx2x_fp(bp, i, status_blk_mapping),
5972 sizeof(struct host_hc_status_block_e1x));
5973 #ifdef BCM_CNIC
5974 }
5975 #endif
5976 }
5977 /* Rx */
5978 for_each_rx_queue(bp, i) {
5979
5980 /* fastpath rx rings: rx_buf rx_desc rx_comp */
5981 BNX2X_FREE(bnx2x_fp(bp, i, rx_buf_ring));
5982 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_desc_ring),
5983 bnx2x_fp(bp, i, rx_desc_mapping),
5984 sizeof(struct eth_rx_bd) * NUM_RX_BD);
5985
5986 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_comp_ring),
5987 bnx2x_fp(bp, i, rx_comp_mapping),
5988 sizeof(struct eth_fast_path_rx_cqe) *
5989 NUM_RCQ_BD);
5990
5991 /* SGE ring */
5992 BNX2X_FREE(bnx2x_fp(bp, i, rx_page_ring));
5993 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_sge_ring),
5994 bnx2x_fp(bp, i, rx_sge_mapping),
5995 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
5996 }
5997 /* Tx */
5998 for_each_tx_queue(bp, i) {
5999
6000 /* fastpath tx rings: tx_buf tx_desc */
6001 BNX2X_FREE(bnx2x_fp(bp, i, tx_buf_ring));
6002 BNX2X_PCI_FREE(bnx2x_fp(bp, i, tx_desc_ring),
6003 bnx2x_fp(bp, i, tx_desc_mapping),
6004 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
6005 }
6006 /* end of fastpath */
6007
6008 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
6009 sizeof(struct host_sp_status_block));
6010
6011 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
6012 sizeof(struct bnx2x_slowpath));
6013
6014 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
6015 bp->context.size);
6016
6017 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
6018
6019 BNX2X_FREE(bp->ilt->lines);
6020
6021 #ifdef BCM_CNIC
6022 if (CHIP_IS_E2(bp))
6023 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
6024 sizeof(struct host_hc_status_block_e2));
6025 else
6026 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
6027 sizeof(struct host_hc_status_block_e1x));
6028
6029 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
6030 #endif
6031
6032 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
6033
6034 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
6035 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6036
6037 #undef BNX2X_PCI_FREE
6038 #undef BNX2X_KFREE
6039 }
6040
6041 static inline void set_sb_shortcuts(struct bnx2x *bp, int index)
6042 {
6043 union host_hc_status_block status_blk = bnx2x_fp(bp, index, status_blk);
6044 if (CHIP_IS_E2(bp)) {
6045 bnx2x_fp(bp, index, sb_index_values) =
6046 (__le16 *)status_blk.e2_sb->sb.index_values;
6047 bnx2x_fp(bp, index, sb_running_index) =
6048 (__le16 *)status_blk.e2_sb->sb.running_index;
6049 } else {
6050 bnx2x_fp(bp, index, sb_index_values) =
6051 (__le16 *)status_blk.e1x_sb->sb.index_values;
6052 bnx2x_fp(bp, index, sb_running_index) =
6053 (__le16 *)status_blk.e1x_sb->sb.running_index;
6054 }
6055 }
6056
6057 int bnx2x_alloc_mem(struct bnx2x *bp)
6058 {
6059 #define BNX2X_PCI_ALLOC(x, y, size) \
6060 do { \
6061 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
6062 if (x == NULL) \
6063 goto alloc_mem_err; \
6064 memset(x, 0, size); \
6065 } while (0)
6066
6067 #define BNX2X_ALLOC(x, size) \
6068 do { \
6069 x = kzalloc(size, GFP_KERNEL); \
6070 if (x == NULL) \
6071 goto alloc_mem_err; \
6072 } while (0)
6073
6074 int i;
6075
6076 /* fastpath */
6077 /* Common */
6078 for_each_queue(bp, i) {
6079 union host_hc_status_block *sb = &bnx2x_fp(bp, i, status_blk);
6080 bnx2x_fp(bp, i, bp) = bp;
6081 /* status blocks */
6082 #ifdef BCM_CNIC
6083 if (!IS_FCOE_IDX(i)) {
6084 #endif
6085 if (CHIP_IS_E2(bp))
6086 BNX2X_PCI_ALLOC(sb->e2_sb,
6087 &bnx2x_fp(bp, i, status_blk_mapping),
6088 sizeof(struct host_hc_status_block_e2));
6089 else
6090 BNX2X_PCI_ALLOC(sb->e1x_sb,
6091 &bnx2x_fp(bp, i, status_blk_mapping),
6092 sizeof(struct host_hc_status_block_e1x));
6093 #ifdef BCM_CNIC
6094 }
6095 #endif
6096 set_sb_shortcuts(bp, i);
6097 }
6098 /* Rx */
6099 for_each_queue(bp, i) {
6100
6101 /* fastpath rx rings: rx_buf rx_desc rx_comp */
6102 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_buf_ring),
6103 sizeof(struct sw_rx_bd) * NUM_RX_BD);
6104 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_desc_ring),
6105 &bnx2x_fp(bp, i, rx_desc_mapping),
6106 sizeof(struct eth_rx_bd) * NUM_RX_BD);
6107
6108 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_comp_ring),
6109 &bnx2x_fp(bp, i, rx_comp_mapping),
6110 sizeof(struct eth_fast_path_rx_cqe) *
6111 NUM_RCQ_BD);
6112
6113 /* SGE ring */
6114 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_page_ring),
6115 sizeof(struct sw_rx_page) * NUM_RX_SGE);
6116 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_sge_ring),
6117 &bnx2x_fp(bp, i, rx_sge_mapping),
6118 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
6119 }
6120 /* Tx */
6121 for_each_queue(bp, i) {
6122
6123 /* fastpath tx rings: tx_buf tx_desc */
6124 BNX2X_ALLOC(bnx2x_fp(bp, i, tx_buf_ring),
6125 sizeof(struct sw_tx_bd) * NUM_TX_BD);
6126 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, tx_desc_ring),
6127 &bnx2x_fp(bp, i, tx_desc_mapping),
6128 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
6129 }
6130 /* end of fastpath */
6131
6132 #ifdef BCM_CNIC
6133 if (CHIP_IS_E2(bp))
6134 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6135 sizeof(struct host_hc_status_block_e2));
6136 else
6137 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6138 sizeof(struct host_hc_status_block_e1x));
6139
6140 /* allocate searcher T2 table */
6141 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6142 #endif
6143
6144
6145 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6146 sizeof(struct host_sp_status_block));
6147
6148 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6149 sizeof(struct bnx2x_slowpath));
6150
6151 bp->context.size = sizeof(union cdu_context) * bp->l2_cid_count;
6152
6153 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6154 bp->context.size);
6155
6156 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
6157
6158 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6159 goto alloc_mem_err;
6160
6161 /* Slow path ring */
6162 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
6163
6164 /* EQ */
6165 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6166 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6167 return 0;
6168
6169 alloc_mem_err:
6170 bnx2x_free_mem(bp);
6171 return -ENOMEM;
6172
6173 #undef BNX2X_PCI_ALLOC
6174 #undef BNX2X_ALLOC
6175 }
6176
6177 /*
6178 * Init service functions
6179 */
6180 static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6181 int *state_p, int flags);
6182
6183 int bnx2x_func_start(struct bnx2x *bp)
6184 {
6185 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0, 0, 0, 1);
6186
6187 /* Wait for completion */
6188 return bnx2x_wait_ramrod(bp, BNX2X_STATE_FUNC_STARTED, 0, &(bp->state),
6189 WAIT_RAMROD_COMMON);
6190 }
6191
6192 static int bnx2x_func_stop(struct bnx2x *bp)
6193 {
6194 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0, 0, 1);
6195
6196 /* Wait for completion */
6197 return bnx2x_wait_ramrod(bp, BNX2X_STATE_CLOSING_WAIT4_UNLOAD,
6198 0, &(bp->state), WAIT_RAMROD_COMMON);
6199 }
6200
6201 /**
6202 * Sets a MAC in a CAM for a few L2 Clients for E1x chips
6203 *
6204 * @param bp driver descriptor
6205 * @param set set or clear an entry (1 or 0)
6206 * @param mac pointer to a buffer containing a MAC
6207 * @param cl_bit_vec bit vector of clients to register a MAC for
6208 * @param cam_offset offset in a CAM to use
6209 * @param is_bcast is the set MAC a broadcast address (for E1 only)
6210 */
6211 static void bnx2x_set_mac_addr_gen(struct bnx2x *bp, int set, const u8 *mac,
6212 u32 cl_bit_vec, u8 cam_offset,
6213 u8 is_bcast)
6214 {
6215 struct mac_configuration_cmd *config =
6216 (struct mac_configuration_cmd *)bnx2x_sp(bp, mac_config);
6217 int ramrod_flags = WAIT_RAMROD_COMMON;
6218
6219 bp->set_mac_pending = 1;
6220 smp_wmb();
6221
6222 config->hdr.length = 1;
6223 config->hdr.offset = cam_offset;
6224 config->hdr.client_id = 0xff;
6225 config->hdr.reserved1 = 0;
6226
6227 /* primary MAC */
6228 config->config_table[0].msb_mac_addr =
6229 swab16(*(u16 *)&mac[0]);
6230 config->config_table[0].middle_mac_addr =
6231 swab16(*(u16 *)&mac[2]);
6232 config->config_table[0].lsb_mac_addr =
6233 swab16(*(u16 *)&mac[4]);
6234 config->config_table[0].clients_bit_vector =
6235 cpu_to_le32(cl_bit_vec);
6236 config->config_table[0].vlan_id = 0;
6237 config->config_table[0].pf_id = BP_FUNC(bp);
6238 if (set)
6239 SET_FLAG(config->config_table[0].flags,
6240 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6241 T_ETH_MAC_COMMAND_SET);
6242 else
6243 SET_FLAG(config->config_table[0].flags,
6244 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6245 T_ETH_MAC_COMMAND_INVALIDATE);
6246
6247 if (is_bcast)
6248 SET_FLAG(config->config_table[0].flags,
6249 MAC_CONFIGURATION_ENTRY_BROADCAST, 1);
6250
6251 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x) PF_ID %d CLID mask %d\n",
6252 (set ? "setting" : "clearing"),
6253 config->config_table[0].msb_mac_addr,
6254 config->config_table[0].middle_mac_addr,
6255 config->config_table[0].lsb_mac_addr, BP_FUNC(bp), cl_bit_vec);
6256
6257 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6258 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
6259 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
6260
6261 /* Wait for a completion */
6262 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, ramrod_flags);
6263 }
6264
6265 static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6266 int *state_p, int flags)
6267 {
6268 /* can take a while if any port is running */
6269 int cnt = 5000;
6270 u8 poll = flags & WAIT_RAMROD_POLL;
6271 u8 common = flags & WAIT_RAMROD_COMMON;
6272
6273 DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
6274 poll ? "polling" : "waiting", state, idx);
6275
6276 might_sleep();
6277 while (cnt--) {
6278 if (poll) {
6279 if (common)
6280 bnx2x_eq_int(bp);
6281 else {
6282 bnx2x_rx_int(bp->fp, 10);
6283 /* if index is different from 0
6284 * the reply for some commands will
6285 * be on the non default queue
6286 */
6287 if (idx)
6288 bnx2x_rx_int(&bp->fp[idx], 10);
6289 }
6290 }
6291
6292 mb(); /* state is changed by bnx2x_sp_event() */
6293 if (*state_p == state) {
6294 #ifdef BNX2X_STOP_ON_ERROR
6295 DP(NETIF_MSG_IFUP, "exit (cnt %d)\n", 5000 - cnt);
6296 #endif
6297 return 0;
6298 }
6299
6300 msleep(1);
6301
6302 if (bp->panic)
6303 return -EIO;
6304 }
6305
6306 /* timeout! */
6307 BNX2X_ERR("timeout %s for state %x on IDX [%d]\n",
6308 poll ? "polling" : "waiting", state, idx);
6309 #ifdef BNX2X_STOP_ON_ERROR
6310 bnx2x_panic();
6311 #endif
6312
6313 return -EBUSY;
6314 }
6315
6316 static u8 bnx2x_e1h_cam_offset(struct bnx2x *bp, u8 rel_offset)
6317 {
6318 if (CHIP_IS_E1H(bp))
6319 return E1H_FUNC_MAX * rel_offset + BP_FUNC(bp);
6320 else if (CHIP_MODE_IS_4_PORT(bp))
6321 return BP_FUNC(bp) * 32 + rel_offset;
6322 else
6323 return BP_VN(bp) * 32 + rel_offset;
6324 }
6325
6326 /**
6327 * LLH CAM line allocations: currently only iSCSI and ETH macs are
6328 * relevant. In addition, current implementation is tuned for a
6329 * single ETH MAC.
6330 *
6331 * When multiple unicast ETH MACs PF configuration in switch
6332 * independent mode is required (NetQ, multiple netdev MACs,
6333 * etc.), consider better utilisation of 16 per function MAC
6334 * entries in the LLH memory.
6335 */
6336 enum {
6337 LLH_CAM_ISCSI_ETH_LINE = 0,
6338 LLH_CAM_ETH_LINE,
6339 LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE
6340 };
6341
6342 static void bnx2x_set_mac_in_nig(struct bnx2x *bp,
6343 int set,
6344 unsigned char *dev_addr,
6345 int index)
6346 {
6347 u32 wb_data[2];
6348 u32 mem_offset, ena_offset, mem_index;
6349 /**
6350 * indexes mapping:
6351 * 0..7 - goes to MEM
6352 * 8..15 - goes to MEM2
6353 */
6354
6355 if (!IS_MF_SI(bp) || index > LLH_CAM_MAX_PF_LINE)
6356 return;
6357
6358 /* calculate memory start offset according to the mapping
6359 * and index in the memory */
6360 if (index < NIG_LLH_FUNC_MEM_MAX_OFFSET) {
6361 mem_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM :
6362 NIG_REG_LLH0_FUNC_MEM;
6363 ena_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :
6364 NIG_REG_LLH0_FUNC_MEM_ENABLE;
6365 mem_index = index;
6366 } else {
6367 mem_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2 :
6368 NIG_REG_P0_LLH_FUNC_MEM2;
6369 ena_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2_ENABLE :
6370 NIG_REG_P0_LLH_FUNC_MEM2_ENABLE;
6371 mem_index = index - NIG_LLH_FUNC_MEM_MAX_OFFSET;
6372 }
6373
6374 if (set) {
6375 /* LLH_FUNC_MEM is a u64 WB register */
6376 mem_offset += 8*mem_index;
6377
6378 wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) |
6379 (dev_addr[4] << 8) | dev_addr[5]);
6380 wb_data[1] = ((dev_addr[0] << 8) | dev_addr[1]);
6381
6382 REG_WR_DMAE(bp, mem_offset, wb_data, 2);
6383 }
6384
6385 /* enable/disable the entry */
6386 REG_WR(bp, ena_offset + 4*mem_index, set);
6387
6388 }
6389
6390 void bnx2x_set_eth_mac(struct bnx2x *bp, int set)
6391 {
6392 u8 cam_offset = (CHIP_IS_E1(bp) ? (BP_PORT(bp) ? 32 : 0) :
6393 bnx2x_e1h_cam_offset(bp, CAM_ETH_LINE));
6394
6395 /* networking MAC */
6396 bnx2x_set_mac_addr_gen(bp, set, bp->dev->dev_addr,
6397 (1 << bp->fp->cl_id), cam_offset , 0);
6398
6399 bnx2x_set_mac_in_nig(bp, set, bp->dev->dev_addr, LLH_CAM_ETH_LINE);
6400
6401 if (CHIP_IS_E1(bp)) {
6402 /* broadcast MAC */
6403 static const u8 bcast[ETH_ALEN] = {
6404 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
6405 };
6406 bnx2x_set_mac_addr_gen(bp, set, bcast, 0, cam_offset + 1, 1);
6407 }
6408 }
6409 static void bnx2x_set_e1_mc_list(struct bnx2x *bp, u8 offset)
6410 {
6411 int i = 0, old;
6412 struct net_device *dev = bp->dev;
6413 struct netdev_hw_addr *ha;
6414 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6415 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6416
6417 netdev_for_each_mc_addr(ha, dev) {
6418 /* copy mac */
6419 config_cmd->config_table[i].msb_mac_addr =
6420 swab16(*(u16 *)&bnx2x_mc_addr(ha)[0]);
6421 config_cmd->config_table[i].middle_mac_addr =
6422 swab16(*(u16 *)&bnx2x_mc_addr(ha)[2]);
6423 config_cmd->config_table[i].lsb_mac_addr =
6424 swab16(*(u16 *)&bnx2x_mc_addr(ha)[4]);
6425
6426 config_cmd->config_table[i].vlan_id = 0;
6427 config_cmd->config_table[i].pf_id = BP_FUNC(bp);
6428 config_cmd->config_table[i].clients_bit_vector =
6429 cpu_to_le32(1 << BP_L_ID(bp));
6430
6431 SET_FLAG(config_cmd->config_table[i].flags,
6432 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6433 T_ETH_MAC_COMMAND_SET);
6434
6435 DP(NETIF_MSG_IFUP,
6436 "setting MCAST[%d] (%04x:%04x:%04x)\n", i,
6437 config_cmd->config_table[i].msb_mac_addr,
6438 config_cmd->config_table[i].middle_mac_addr,
6439 config_cmd->config_table[i].lsb_mac_addr);
6440 i++;
6441 }
6442 old = config_cmd->hdr.length;
6443 if (old > i) {
6444 for (; i < old; i++) {
6445 if (CAM_IS_INVALID(config_cmd->
6446 config_table[i])) {
6447 /* already invalidated */
6448 break;
6449 }
6450 /* invalidate */
6451 SET_FLAG(config_cmd->config_table[i].flags,
6452 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6453 T_ETH_MAC_COMMAND_INVALIDATE);
6454 }
6455 }
6456
6457 config_cmd->hdr.length = i;
6458 config_cmd->hdr.offset = offset;
6459 config_cmd->hdr.client_id = 0xff;
6460 config_cmd->hdr.reserved1 = 0;
6461
6462 bp->set_mac_pending = 1;
6463 smp_wmb();
6464
6465 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6466 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
6467 }
6468 static void bnx2x_invlidate_e1_mc_list(struct bnx2x *bp)
6469 {
6470 int i;
6471 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6472 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6473 int ramrod_flags = WAIT_RAMROD_COMMON;
6474
6475 bp->set_mac_pending = 1;
6476 smp_wmb();
6477
6478 for (i = 0; i < config_cmd->hdr.length; i++)
6479 SET_FLAG(config_cmd->config_table[i].flags,
6480 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6481 T_ETH_MAC_COMMAND_INVALIDATE);
6482
6483 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6484 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
6485
6486 /* Wait for a completion */
6487 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending,
6488 ramrod_flags);
6489
6490 }
6491
6492 #ifdef BCM_CNIC
6493 /**
6494 * Set iSCSI MAC(s) at the next enties in the CAM after the ETH
6495 * MAC(s). This function will wait until the ramdord completion
6496 * returns.
6497 *
6498 * @param bp driver handle
6499 * @param set set or clear the CAM entry
6500 *
6501 * @return 0 if cussess, -ENODEV if ramrod doesn't return.
6502 */
6503 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set)
6504 {
6505 u8 cam_offset = (CHIP_IS_E1(bp) ? ((BP_PORT(bp) ? 32 : 0) + 2) :
6506 bnx2x_e1h_cam_offset(bp, CAM_ISCSI_ETH_LINE));
6507 u32 iscsi_l2_cl_id = BNX2X_ISCSI_ETH_CL_ID +
6508 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
6509 u32 cl_bit_vec = (1 << iscsi_l2_cl_id);
6510
6511 /* Send a SET_MAC ramrod */
6512 bnx2x_set_mac_addr_gen(bp, set, bp->iscsi_mac, cl_bit_vec,
6513 cam_offset, 0);
6514
6515 bnx2x_set_mac_in_nig(bp, set, bp->iscsi_mac, LLH_CAM_ISCSI_ETH_LINE);
6516
6517 return 0;
6518 }
6519
6520 /**
6521 * Set FCoE L2 MAC(s) at the next enties in the CAM after the
6522 * ETH MAC(s). This function will wait until the ramdord
6523 * completion returns.
6524 *
6525 * @param bp driver handle
6526 * @param set set or clear the CAM entry
6527 *
6528 * @return 0 if cussess, -ENODEV if ramrod doesn't return.
6529 */
6530 int bnx2x_set_fip_eth_mac_addr(struct bnx2x *bp, int set)
6531 {
6532 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6533 /**
6534 * CAM allocation for E1H
6535 * eth unicasts: by func number
6536 * iscsi: by func number
6537 * fip unicast: by func number
6538 * fip multicast: by func number
6539 */
6540 bnx2x_set_mac_addr_gen(bp, set, bp->fip_mac,
6541 cl_bit_vec, bnx2x_e1h_cam_offset(bp, CAM_FIP_ETH_LINE), 0);
6542
6543 return 0;
6544 }
6545
6546 int bnx2x_set_all_enode_macs(struct bnx2x *bp, int set)
6547 {
6548 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6549
6550 /**
6551 * CAM allocation for E1H
6552 * eth unicasts: by func number
6553 * iscsi: by func number
6554 * fip unicast: by func number
6555 * fip multicast: by func number
6556 */
6557 bnx2x_set_mac_addr_gen(bp, set, ALL_ENODE_MACS, cl_bit_vec,
6558 bnx2x_e1h_cam_offset(bp, CAM_FIP_MCAST_LINE), 0);
6559
6560 return 0;
6561 }
6562 #endif
6563
6564 static void bnx2x_fill_cl_init_data(struct bnx2x *bp,
6565 struct bnx2x_client_init_params *params,
6566 u8 activate,
6567 struct client_init_ramrod_data *data)
6568 {
6569 /* Clear the buffer */
6570 memset(data, 0, sizeof(*data));
6571
6572 /* general */
6573 data->general.client_id = params->rxq_params.cl_id;
6574 data->general.statistics_counter_id = params->rxq_params.stat_id;
6575 data->general.statistics_en_flg =
6576 (params->rxq_params.flags & QUEUE_FLG_STATS) ? 1 : 0;
6577 data->general.is_fcoe_flg =
6578 (params->ramrod_params.flags & CLIENT_IS_FCOE) ? 1 : 0;
6579 data->general.activate_flg = activate;
6580 data->general.sp_client_id = params->rxq_params.spcl_id;
6581
6582 /* Rx data */
6583 data->rx.tpa_en_flg =
6584 (params->rxq_params.flags & QUEUE_FLG_TPA) ? 1 : 0;
6585 data->rx.vmqueue_mode_en_flg = 0;
6586 data->rx.cache_line_alignment_log_size =
6587 params->rxq_params.cache_line_log;
6588 data->rx.enable_dynamic_hc =
6589 (params->rxq_params.flags & QUEUE_FLG_DHC) ? 1 : 0;
6590 data->rx.max_sges_for_packet = params->rxq_params.max_sges_pkt;
6591 data->rx.client_qzone_id = params->rxq_params.cl_qzone_id;
6592 data->rx.max_agg_size = params->rxq_params.tpa_agg_sz;
6593
6594 /* We don't set drop flags */
6595 data->rx.drop_ip_cs_err_flg = 0;
6596 data->rx.drop_tcp_cs_err_flg = 0;
6597 data->rx.drop_ttl0_flg = 0;
6598 data->rx.drop_udp_cs_err_flg = 0;
6599
6600 data->rx.inner_vlan_removal_enable_flg =
6601 (params->rxq_params.flags & QUEUE_FLG_VLAN) ? 1 : 0;
6602 data->rx.outer_vlan_removal_enable_flg =
6603 (params->rxq_params.flags & QUEUE_FLG_OV) ? 1 : 0;
6604 data->rx.status_block_id = params->rxq_params.fw_sb_id;
6605 data->rx.rx_sb_index_number = params->rxq_params.sb_cq_index;
6606 data->rx.bd_buff_size = cpu_to_le16(params->rxq_params.buf_sz);
6607 data->rx.sge_buff_size = cpu_to_le16(params->rxq_params.sge_buf_sz);
6608 data->rx.mtu = cpu_to_le16(params->rxq_params.mtu);
6609 data->rx.bd_page_base.lo =
6610 cpu_to_le32(U64_LO(params->rxq_params.dscr_map));
6611 data->rx.bd_page_base.hi =
6612 cpu_to_le32(U64_HI(params->rxq_params.dscr_map));
6613 data->rx.sge_page_base.lo =
6614 cpu_to_le32(U64_LO(params->rxq_params.sge_map));
6615 data->rx.sge_page_base.hi =
6616 cpu_to_le32(U64_HI(params->rxq_params.sge_map));
6617 data->rx.cqe_page_base.lo =
6618 cpu_to_le32(U64_LO(params->rxq_params.rcq_map));
6619 data->rx.cqe_page_base.hi =
6620 cpu_to_le32(U64_HI(params->rxq_params.rcq_map));
6621 data->rx.is_leading_rss =
6622 (params->ramrod_params.flags & CLIENT_IS_LEADING_RSS) ? 1 : 0;
6623 data->rx.is_approx_mcast = data->rx.is_leading_rss;
6624
6625 /* Tx data */
6626 data->tx.enforce_security_flg = 0; /* VF specific */
6627 data->tx.tx_status_block_id = params->txq_params.fw_sb_id;
6628 data->tx.tx_sb_index_number = params->txq_params.sb_cq_index;
6629 data->tx.mtu = 0; /* VF specific */
6630 data->tx.tx_bd_page_base.lo =
6631 cpu_to_le32(U64_LO(params->txq_params.dscr_map));
6632 data->tx.tx_bd_page_base.hi =
6633 cpu_to_le32(U64_HI(params->txq_params.dscr_map));
6634
6635 /* flow control data */
6636 data->fc.cqe_pause_thr_low = cpu_to_le16(params->pause.rcq_th_lo);
6637 data->fc.cqe_pause_thr_high = cpu_to_le16(params->pause.rcq_th_hi);
6638 data->fc.bd_pause_thr_low = cpu_to_le16(params->pause.bd_th_lo);
6639 data->fc.bd_pause_thr_high = cpu_to_le16(params->pause.bd_th_hi);
6640 data->fc.sge_pause_thr_low = cpu_to_le16(params->pause.sge_th_lo);
6641 data->fc.sge_pause_thr_high = cpu_to_le16(params->pause.sge_th_hi);
6642 data->fc.rx_cos_mask = cpu_to_le16(params->pause.pri_map);
6643
6644 data->fc.safc_group_num = params->txq_params.cos;
6645 data->fc.safc_group_en_flg =
6646 (params->txq_params.flags & QUEUE_FLG_COS) ? 1 : 0;
6647 data->fc.traffic_type =
6648 (params->ramrod_params.flags & CLIENT_IS_FCOE) ?
6649 LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW;
6650 }
6651
6652 static inline void bnx2x_set_ctx_validation(struct eth_context *cxt, u32 cid)
6653 {
6654 /* ustorm cxt validation */
6655 cxt->ustorm_ag_context.cdu_usage =
6656 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_UCM_AG,
6657 ETH_CONNECTION_TYPE);
6658 /* xcontext validation */
6659 cxt->xstorm_ag_context.cdu_reserved =
6660 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_XCM_AG,
6661 ETH_CONNECTION_TYPE);
6662 }
6663
6664 static int bnx2x_setup_fw_client(struct bnx2x *bp,
6665 struct bnx2x_client_init_params *params,
6666 u8 activate,
6667 struct client_init_ramrod_data *data,
6668 dma_addr_t data_mapping)
6669 {
6670 u16 hc_usec;
6671 int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
6672 int ramrod_flags = 0, rc;
6673
6674 /* HC and context validation values */
6675 hc_usec = params->txq_params.hc_rate ?
6676 1000000 / params->txq_params.hc_rate : 0;
6677 bnx2x_update_coalesce_sb_index(bp,
6678 params->txq_params.fw_sb_id,
6679 params->txq_params.sb_cq_index,
6680 !(params->txq_params.flags & QUEUE_FLG_HC),
6681 hc_usec);
6682
6683 *(params->ramrod_params.pstate) = BNX2X_FP_STATE_OPENING;
6684
6685 hc_usec = params->rxq_params.hc_rate ?
6686 1000000 / params->rxq_params.hc_rate : 0;
6687 bnx2x_update_coalesce_sb_index(bp,
6688 params->rxq_params.fw_sb_id,
6689 params->rxq_params.sb_cq_index,
6690 !(params->rxq_params.flags & QUEUE_FLG_HC),
6691 hc_usec);
6692
6693 bnx2x_set_ctx_validation(params->rxq_params.cxt,
6694 params->rxq_params.cid);
6695
6696 /* zero stats */
6697 if (params->txq_params.flags & QUEUE_FLG_STATS)
6698 storm_memset_xstats_zero(bp, BP_PORT(bp),
6699 params->txq_params.stat_id);
6700
6701 if (params->rxq_params.flags & QUEUE_FLG_STATS) {
6702 storm_memset_ustats_zero(bp, BP_PORT(bp),
6703 params->rxq_params.stat_id);
6704 storm_memset_tstats_zero(bp, BP_PORT(bp),
6705 params->rxq_params.stat_id);
6706 }
6707
6708 /* Fill the ramrod data */
6709 bnx2x_fill_cl_init_data(bp, params, activate, data);
6710
6711 /* SETUP ramrod.
6712 *
6713 * bnx2x_sp_post() takes a spin_lock thus no other explict memory
6714 * barrier except from mmiowb() is needed to impose a
6715 * proper ordering of memory operations.
6716 */
6717 mmiowb();
6718
6719
6720 bnx2x_sp_post(bp, ramrod, params->ramrod_params.cid,
6721 U64_HI(data_mapping), U64_LO(data_mapping), 0);
6722
6723 /* Wait for completion */
6724 rc = bnx2x_wait_ramrod(bp, params->ramrod_params.state,
6725 params->ramrod_params.index,
6726 params->ramrod_params.pstate,
6727 ramrod_flags);
6728 return rc;
6729 }
6730
6731 /**
6732 * Configure interrupt mode according to current configuration.
6733 * In case of MSI-X it will also try to enable MSI-X.
6734 *
6735 * @param bp
6736 *
6737 * @return int
6738 */
6739 static int __devinit bnx2x_set_int_mode(struct bnx2x *bp)
6740 {
6741 int rc = 0;
6742
6743 switch (bp->int_mode) {
6744 case INT_MODE_MSI:
6745 bnx2x_enable_msi(bp);
6746 /* falling through... */
6747 case INT_MODE_INTx:
6748 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
6749 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
6750 break;
6751 default:
6752 /* Set number of queues according to bp->multi_mode value */
6753 bnx2x_set_num_queues(bp);
6754
6755 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
6756 bp->num_queues);
6757
6758 /* if we can't use MSI-X we only need one fp,
6759 * so try to enable MSI-X with the requested number of fp's
6760 * and fallback to MSI or legacy INTx with one fp
6761 */
6762 rc = bnx2x_enable_msix(bp);
6763 if (rc) {
6764 /* failed to enable MSI-X */
6765 if (bp->multi_mode)
6766 DP(NETIF_MSG_IFUP,
6767 "Multi requested but failed to "
6768 "enable MSI-X (%d), "
6769 "set number of queues to %d\n",
6770 bp->num_queues,
6771 1 + NONE_ETH_CONTEXT_USE);
6772 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
6773
6774 if (!(bp->flags & DISABLE_MSI_FLAG))
6775 bnx2x_enable_msi(bp);
6776 }
6777
6778 break;
6779 }
6780
6781 return rc;
6782 }
6783
6784 /* must be called prioir to any HW initializations */
6785 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
6786 {
6787 return L2_ILT_LINES(bp);
6788 }
6789
6790 void bnx2x_ilt_set_info(struct bnx2x *bp)
6791 {
6792 struct ilt_client_info *ilt_client;
6793 struct bnx2x_ilt *ilt = BP_ILT(bp);
6794 u16 line = 0;
6795
6796 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
6797 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
6798
6799 /* CDU */
6800 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
6801 ilt_client->client_num = ILT_CLIENT_CDU;
6802 ilt_client->page_size = CDU_ILT_PAGE_SZ;
6803 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
6804 ilt_client->start = line;
6805 line += L2_ILT_LINES(bp);
6806 #ifdef BCM_CNIC
6807 line += CNIC_ILT_LINES;
6808 #endif
6809 ilt_client->end = line - 1;
6810
6811 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
6812 "flags 0x%x, hw psz %d\n",
6813 ilt_client->start,
6814 ilt_client->end,
6815 ilt_client->page_size,
6816 ilt_client->flags,
6817 ilog2(ilt_client->page_size >> 12));
6818
6819 /* QM */
6820 if (QM_INIT(bp->qm_cid_count)) {
6821 ilt_client = &ilt->clients[ILT_CLIENT_QM];
6822 ilt_client->client_num = ILT_CLIENT_QM;
6823 ilt_client->page_size = QM_ILT_PAGE_SZ;
6824 ilt_client->flags = 0;
6825 ilt_client->start = line;
6826
6827 /* 4 bytes for each cid */
6828 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
6829 QM_ILT_PAGE_SZ);
6830
6831 ilt_client->end = line - 1;
6832
6833 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
6834 "flags 0x%x, hw psz %d\n",
6835 ilt_client->start,
6836 ilt_client->end,
6837 ilt_client->page_size,
6838 ilt_client->flags,
6839 ilog2(ilt_client->page_size >> 12));
6840
6841 }
6842 /* SRC */
6843 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
6844 #ifdef BCM_CNIC
6845 ilt_client->client_num = ILT_CLIENT_SRC;
6846 ilt_client->page_size = SRC_ILT_PAGE_SZ;
6847 ilt_client->flags = 0;
6848 ilt_client->start = line;
6849 line += SRC_ILT_LINES;
6850 ilt_client->end = line - 1;
6851
6852 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
6853 "flags 0x%x, hw psz %d\n",
6854 ilt_client->start,
6855 ilt_client->end,
6856 ilt_client->page_size,
6857 ilt_client->flags,
6858 ilog2(ilt_client->page_size >> 12));
6859
6860 #else
6861 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6862 #endif
6863
6864 /* TM */
6865 ilt_client = &ilt->clients[ILT_CLIENT_TM];
6866 #ifdef BCM_CNIC
6867 ilt_client->client_num = ILT_CLIENT_TM;
6868 ilt_client->page_size = TM_ILT_PAGE_SZ;
6869 ilt_client->flags = 0;
6870 ilt_client->start = line;
6871 line += TM_ILT_LINES;
6872 ilt_client->end = line - 1;
6873
6874 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
6875 "flags 0x%x, hw psz %d\n",
6876 ilt_client->start,
6877 ilt_client->end,
6878 ilt_client->page_size,
6879 ilt_client->flags,
6880 ilog2(ilt_client->page_size >> 12));
6881
6882 #else
6883 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6884 #endif
6885 }
6886
6887 int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6888 int is_leading)
6889 {
6890 struct bnx2x_client_init_params params = { {0} };
6891 int rc;
6892
6893 /* reset IGU state skip FCoE L2 queue */
6894 if (!IS_FCOE_FP(fp))
6895 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
6896 IGU_INT_ENABLE, 0);
6897
6898 params.ramrod_params.pstate = &fp->state;
6899 params.ramrod_params.state = BNX2X_FP_STATE_OPEN;
6900 params.ramrod_params.index = fp->index;
6901 params.ramrod_params.cid = fp->cid;
6902
6903 #ifdef BCM_CNIC
6904 if (IS_FCOE_FP(fp))
6905 params.ramrod_params.flags |= CLIENT_IS_FCOE;
6906
6907 #endif
6908
6909 if (is_leading)
6910 params.ramrod_params.flags |= CLIENT_IS_LEADING_RSS;
6911
6912 bnx2x_pf_rx_cl_prep(bp, fp, &params.pause, &params.rxq_params);
6913
6914 bnx2x_pf_tx_cl_prep(bp, fp, &params.txq_params);
6915
6916 rc = bnx2x_setup_fw_client(bp, &params, 1,
6917 bnx2x_sp(bp, client_init_data),
6918 bnx2x_sp_mapping(bp, client_init_data));
6919 return rc;
6920 }
6921
6922 static int bnx2x_stop_fw_client(struct bnx2x *bp,
6923 struct bnx2x_client_ramrod_params *p)
6924 {
6925 int rc;
6926
6927 int poll_flag = p->poll ? WAIT_RAMROD_POLL : 0;
6928
6929 /* halt the connection */
6930 *p->pstate = BNX2X_FP_STATE_HALTING;
6931 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, p->cid, 0,
6932 p->cl_id, 0);
6933
6934 /* Wait for completion */
6935 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, p->index,
6936 p->pstate, poll_flag);
6937 if (rc) /* timeout */
6938 return rc;
6939
6940 *p->pstate = BNX2X_FP_STATE_TERMINATING;
6941 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TERMINATE, p->cid, 0,
6942 p->cl_id, 0);
6943 /* Wait for completion */
6944 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_TERMINATED, p->index,
6945 p->pstate, poll_flag);
6946 if (rc) /* timeout */
6947 return rc;
6948
6949
6950 /* delete cfc entry */
6951 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_CFC_DEL, p->cid, 0, 0, 1);
6952
6953 /* Wait for completion */
6954 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, p->index,
6955 p->pstate, WAIT_RAMROD_COMMON);
6956 return rc;
6957 }
6958
6959 static int bnx2x_stop_client(struct bnx2x *bp, int index)
6960 {
6961 struct bnx2x_client_ramrod_params client_stop = {0};
6962 struct bnx2x_fastpath *fp = &bp->fp[index];
6963
6964 client_stop.index = index;
6965 client_stop.cid = fp->cid;
6966 client_stop.cl_id = fp->cl_id;
6967 client_stop.pstate = &(fp->state);
6968 client_stop.poll = 0;
6969
6970 return bnx2x_stop_fw_client(bp, &client_stop);
6971 }
6972
6973
6974 static void bnx2x_reset_func(struct bnx2x *bp)
6975 {
6976 int port = BP_PORT(bp);
6977 int func = BP_FUNC(bp);
6978 int i;
6979 int pfunc_offset_fp = offsetof(struct hc_sb_data, p_func) +
6980 (CHIP_IS_E2(bp) ?
6981 offsetof(struct hc_status_block_data_e2, common) :
6982 offsetof(struct hc_status_block_data_e1x, common));
6983 int pfunc_offset_sp = offsetof(struct hc_sp_status_block_data, p_func);
6984 int pfid_offset = offsetof(struct pci_entity, pf_id);
6985
6986 /* Disable the function in the FW */
6987 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
6988 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
6989 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
6990 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
6991
6992 /* FP SBs */
6993 for_each_eth_queue(bp, i) {
6994 struct bnx2x_fastpath *fp = &bp->fp[i];
6995 REG_WR8(bp,
6996 BAR_CSTRORM_INTMEM +
6997 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id)
6998 + pfunc_offset_fp + pfid_offset,
6999 HC_FUNCTION_DISABLED);
7000 }
7001
7002 /* SP SB */
7003 REG_WR8(bp,
7004 BAR_CSTRORM_INTMEM +
7005 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
7006 pfunc_offset_sp + pfid_offset,
7007 HC_FUNCTION_DISABLED);
7008
7009
7010 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7011 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7012 0);
7013
7014 /* Configure IGU */
7015 if (bp->common.int_block == INT_BLOCK_HC) {
7016 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7017 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7018 } else {
7019 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7020 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7021 }
7022
7023 #ifdef BCM_CNIC
7024 /* Disable Timer scan */
7025 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7026 /*
7027 * Wait for at least 10ms and up to 2 second for the timers scan to
7028 * complete
7029 */
7030 for (i = 0; i < 200; i++) {
7031 msleep(10);
7032 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7033 break;
7034 }
7035 #endif
7036 /* Clear ILT */
7037 bnx2x_clear_func_ilt(bp, func);
7038
7039 /* Timers workaround bug for E2: if this is vnic-3,
7040 * we need to set the entire ilt range for this timers.
7041 */
7042 if (CHIP_IS_E2(bp) && BP_VN(bp) == 3) {
7043 struct ilt_client_info ilt_cli;
7044 /* use dummy TM client */
7045 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7046 ilt_cli.start = 0;
7047 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7048 ilt_cli.client_num = ILT_CLIENT_TM;
7049
7050 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7051 }
7052
7053 /* this assumes that reset_port() called before reset_func()*/
7054 if (CHIP_IS_E2(bp))
7055 bnx2x_pf_disable(bp);
7056
7057 bp->dmae_ready = 0;
7058 }
7059
7060 static void bnx2x_reset_port(struct bnx2x *bp)
7061 {
7062 int port = BP_PORT(bp);
7063 u32 val;
7064
7065 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7066
7067 /* Do not rcv packets to BRB */
7068 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7069 /* Do not direct rcv packets that are not for MCP to the BRB */
7070 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7071 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7072
7073 /* Configure AEU */
7074 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7075
7076 msleep(100);
7077 /* Check for BRB port occupancy */
7078 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7079 if (val)
7080 DP(NETIF_MSG_IFDOWN,
7081 "BRB1 is not empty %d blocks are occupied\n", val);
7082
7083 /* TODO: Close Doorbell port? */
7084 }
7085
7086 static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
7087 {
7088 DP(BNX2X_MSG_MCP, "function %d reset_code %x\n",
7089 BP_ABS_FUNC(bp), reset_code);
7090
7091 switch (reset_code) {
7092 case FW_MSG_CODE_DRV_UNLOAD_COMMON:
7093 bnx2x_reset_port(bp);
7094 bnx2x_reset_func(bp);
7095 bnx2x_reset_common(bp);
7096 break;
7097
7098 case FW_MSG_CODE_DRV_UNLOAD_PORT:
7099 bnx2x_reset_port(bp);
7100 bnx2x_reset_func(bp);
7101 break;
7102
7103 case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
7104 bnx2x_reset_func(bp);
7105 break;
7106
7107 default:
7108 BNX2X_ERR("Unknown reset_code (0x%x) from MCP\n", reset_code);
7109 break;
7110 }
7111 }
7112
7113 #ifdef BCM_CNIC
7114 static inline void bnx2x_del_fcoe_eth_macs(struct bnx2x *bp)
7115 {
7116 if (bp->flags & FCOE_MACS_SET) {
7117 if (!IS_MF_SD(bp))
7118 bnx2x_set_fip_eth_mac_addr(bp, 0);
7119
7120 bnx2x_set_all_enode_macs(bp, 0);
7121
7122 bp->flags &= ~FCOE_MACS_SET;
7123 }
7124 }
7125 #endif
7126
7127 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7128 {
7129 int port = BP_PORT(bp);
7130 u32 reset_code = 0;
7131 int i, cnt, rc;
7132
7133 /* Wait until tx fastpath tasks complete */
7134 for_each_tx_queue(bp, i) {
7135 struct bnx2x_fastpath *fp = &bp->fp[i];
7136
7137 cnt = 1000;
7138 while (bnx2x_has_tx_work_unload(fp)) {
7139
7140 if (!cnt) {
7141 BNX2X_ERR("timeout waiting for queue[%d]\n",
7142 i);
7143 #ifdef BNX2X_STOP_ON_ERROR
7144 bnx2x_panic();
7145 return -EBUSY;
7146 #else
7147 break;
7148 #endif
7149 }
7150 cnt--;
7151 msleep(1);
7152 }
7153 }
7154 /* Give HW time to discard old tx messages */
7155 msleep(1);
7156
7157 if (CHIP_IS_E1(bp)) {
7158 /* invalidate mc list,
7159 * wait and poll (interrupts are off)
7160 */
7161 bnx2x_invlidate_e1_mc_list(bp);
7162 bnx2x_set_eth_mac(bp, 0);
7163
7164 } else {
7165 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7166
7167 bnx2x_set_eth_mac(bp, 0);
7168
7169 for (i = 0; i < MC_HASH_SIZE; i++)
7170 REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
7171 }
7172
7173 #ifdef BCM_CNIC
7174 bnx2x_del_fcoe_eth_macs(bp);
7175 #endif
7176
7177 if (unload_mode == UNLOAD_NORMAL)
7178 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7179
7180 else if (bp->flags & NO_WOL_FLAG)
7181 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
7182
7183 else if (bp->wol) {
7184 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7185 u8 *mac_addr = bp->dev->dev_addr;
7186 u32 val;
7187 /* The mac address is written to entries 1-4 to
7188 preserve entry 0 which is used by the PMF */
7189 u8 entry = (BP_E1HVN(bp) + 1)*8;
7190
7191 val = (mac_addr[0] << 8) | mac_addr[1];
7192 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7193
7194 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7195 (mac_addr[4] << 8) | mac_addr[5];
7196 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7197
7198 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7199
7200 } else
7201 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7202
7203 /* Close multi and leading connections
7204 Completions for ramrods are collected in a synchronous way */
7205 for_each_queue(bp, i)
7206
7207 if (bnx2x_stop_client(bp, i))
7208 #ifdef BNX2X_STOP_ON_ERROR
7209 return;
7210 #else
7211 goto unload_error;
7212 #endif
7213
7214 rc = bnx2x_func_stop(bp);
7215 if (rc) {
7216 BNX2X_ERR("Function stop failed!\n");
7217 #ifdef BNX2X_STOP_ON_ERROR
7218 return;
7219 #else
7220 goto unload_error;
7221 #endif
7222 }
7223 #ifndef BNX2X_STOP_ON_ERROR
7224 unload_error:
7225 #endif
7226 if (!BP_NOMCP(bp))
7227 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7228 else {
7229 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7230 "%d, %d, %d\n", BP_PATH(bp),
7231 load_count[BP_PATH(bp)][0],
7232 load_count[BP_PATH(bp)][1],
7233 load_count[BP_PATH(bp)][2]);
7234 load_count[BP_PATH(bp)][0]--;
7235 load_count[BP_PATH(bp)][1 + port]--;
7236 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7237 "%d, %d, %d\n", BP_PATH(bp),
7238 load_count[BP_PATH(bp)][0], load_count[BP_PATH(bp)][1],
7239 load_count[BP_PATH(bp)][2]);
7240 if (load_count[BP_PATH(bp)][0] == 0)
7241 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7242 else if (load_count[BP_PATH(bp)][1 + port] == 0)
7243 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7244 else
7245 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7246 }
7247
7248 if ((reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) ||
7249 (reset_code == FW_MSG_CODE_DRV_UNLOAD_PORT))
7250 bnx2x__link_reset(bp);
7251
7252 /* Disable HW interrupts, NAPI */
7253 bnx2x_netif_stop(bp, 1);
7254
7255 /* Release IRQs */
7256 bnx2x_free_irq(bp);
7257
7258 /* Reset the chip */
7259 bnx2x_reset_chip(bp, reset_code);
7260
7261 /* Report UNLOAD_DONE to MCP */
7262 if (!BP_NOMCP(bp))
7263 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7264
7265 }
7266
7267 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
7268 {
7269 u32 val;
7270
7271 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7272
7273 if (CHIP_IS_E1(bp)) {
7274 int port = BP_PORT(bp);
7275 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7276 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7277
7278 val = REG_RD(bp, addr);
7279 val &= ~(0x300);
7280 REG_WR(bp, addr, val);
7281 } else if (CHIP_IS_E1H(bp)) {
7282 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7283 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7284 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7285 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7286 }
7287 }
7288
7289 /* Close gates #2, #3 and #4: */
7290 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7291 {
7292 u32 val, addr;
7293
7294 /* Gates #2 and #4a are closed/opened for "not E1" only */
7295 if (!CHIP_IS_E1(bp)) {
7296 /* #4 */
7297 val = REG_RD(bp, PXP_REG_HST_DISCARD_DOORBELLS);
7298 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS,
7299 close ? (val | 0x1) : (val & (~(u32)1)));
7300 /* #2 */
7301 val = REG_RD(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES);
7302 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES,
7303 close ? (val | 0x1) : (val & (~(u32)1)));
7304 }
7305
7306 /* #3 */
7307 addr = BP_PORT(bp) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
7308 val = REG_RD(bp, addr);
7309 REG_WR(bp, addr, (!close) ? (val | 0x1) : (val & (~(u32)1)));
7310
7311 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7312 close ? "closing" : "opening");
7313 mmiowb();
7314 }
7315
7316 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7317
7318 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7319 {
7320 /* Do some magic... */
7321 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7322 *magic_val = val & SHARED_MF_CLP_MAGIC;
7323 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7324 }
7325
7326 /* Restore the value of the `magic' bit.
7327 *
7328 * @param pdev Device handle.
7329 * @param magic_val Old value of the `magic' bit.
7330 */
7331 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7332 {
7333 /* Restore the `magic' bit value... */
7334 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7335 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7336 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7337 }
7338
7339 /**
7340 * Prepares for MCP reset: takes care of CLP configurations.
7341 *
7342 * @param bp
7343 * @param magic_val Old value of 'magic' bit.
7344 */
7345 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7346 {
7347 u32 shmem;
7348 u32 validity_offset;
7349
7350 DP(NETIF_MSG_HW, "Starting\n");
7351
7352 /* Set `magic' bit in order to save MF config */
7353 if (!CHIP_IS_E1(bp))
7354 bnx2x_clp_reset_prep(bp, magic_val);
7355
7356 /* Get shmem offset */
7357 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7358 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7359
7360 /* Clear validity map flags */
7361 if (shmem > 0)
7362 REG_WR(bp, shmem + validity_offset, 0);
7363 }
7364
7365 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7366 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
7367
7368 /* Waits for MCP_ONE_TIMEOUT or MCP_ONE_TIMEOUT*10,
7369 * depending on the HW type.
7370 *
7371 * @param bp
7372 */
7373 static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7374 {
7375 /* special handling for emulation and FPGA,
7376 wait 10 times longer */
7377 if (CHIP_REV_IS_SLOW(bp))
7378 msleep(MCP_ONE_TIMEOUT*10);
7379 else
7380 msleep(MCP_ONE_TIMEOUT);
7381 }
7382
7383 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7384 {
7385 u32 shmem, cnt, validity_offset, val;
7386 int rc = 0;
7387
7388 msleep(100);
7389
7390 /* Get shmem offset */
7391 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7392 if (shmem == 0) {
7393 BNX2X_ERR("Shmem 0 return failure\n");
7394 rc = -ENOTTY;
7395 goto exit_lbl;
7396 }
7397
7398 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7399
7400 /* Wait for MCP to come up */
7401 for (cnt = 0; cnt < (MCP_TIMEOUT / MCP_ONE_TIMEOUT); cnt++) {
7402 /* TBD: its best to check validity map of last port.
7403 * currently checks on port 0.
7404 */
7405 val = REG_RD(bp, shmem + validity_offset);
7406 DP(NETIF_MSG_HW, "shmem 0x%x validity map(0x%x)=0x%x\n", shmem,
7407 shmem + validity_offset, val);
7408
7409 /* check that shared memory is valid. */
7410 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7411 == (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7412 break;
7413
7414 bnx2x_mcp_wait_one(bp);
7415 }
7416
7417 DP(NETIF_MSG_HW, "Cnt=%d Shmem validity map 0x%x\n", cnt, val);
7418
7419 /* Check that shared memory is valid. This indicates that MCP is up. */
7420 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
7421 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
7422 BNX2X_ERR("Shmem signature not present. MCP is not up !!\n");
7423 rc = -ENOTTY;
7424 goto exit_lbl;
7425 }
7426
7427 exit_lbl:
7428 /* Restore the `magic' bit value */
7429 if (!CHIP_IS_E1(bp))
7430 bnx2x_clp_reset_done(bp, magic_val);
7431
7432 return rc;
7433 }
7434
7435 static void bnx2x_pxp_prep(struct bnx2x *bp)
7436 {
7437 if (!CHIP_IS_E1(bp)) {
7438 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
7439 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
7440 REG_WR(bp, PXP2_REG_RQ_CFG_DONE, 0);
7441 mmiowb();
7442 }
7443 }
7444
7445 /*
7446 * Reset the whole chip except for:
7447 * - PCIE core
7448 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
7449 * one reset bit)
7450 * - IGU
7451 * - MISC (including AEU)
7452 * - GRC
7453 * - RBCN, RBCP
7454 */
7455 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp)
7456 {
7457 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
7458
7459 not_reset_mask1 =
7460 MISC_REGISTERS_RESET_REG_1_RST_HC |
7461 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
7462 MISC_REGISTERS_RESET_REG_1_RST_PXP;
7463
7464 not_reset_mask2 =
7465 MISC_REGISTERS_RESET_REG_2_RST_MDIO |
7466 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
7467 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
7468 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
7469 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
7470 MISC_REGISTERS_RESET_REG_2_RST_GRC |
7471 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
7472 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B;
7473
7474 reset_mask1 = 0xffffffff;
7475
7476 if (CHIP_IS_E1(bp))
7477 reset_mask2 = 0xffff;
7478 else
7479 reset_mask2 = 0x1ffff;
7480
7481 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7482 reset_mask1 & (~not_reset_mask1));
7483 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7484 reset_mask2 & (~not_reset_mask2));
7485
7486 barrier();
7487 mmiowb();
7488
7489 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
7490 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
7491 mmiowb();
7492 }
7493
7494 static int bnx2x_process_kill(struct bnx2x *bp)
7495 {
7496 int cnt = 1000;
7497 u32 val = 0;
7498 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
7499
7500
7501 /* Empty the Tetris buffer, wait for 1s */
7502 do {
7503 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
7504 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
7505 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
7506 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
7507 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
7508 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
7509 ((port_is_idle_0 & 0x1) == 0x1) &&
7510 ((port_is_idle_1 & 0x1) == 0x1) &&
7511 (pgl_exp_rom2 == 0xffffffff))
7512 break;
7513 msleep(1);
7514 } while (cnt-- > 0);
7515
7516 if (cnt <= 0) {
7517 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
7518 " are still"
7519 " outstanding read requests after 1s!\n");
7520 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
7521 " port_is_idle_0=0x%08x,"
7522 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
7523 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
7524 pgl_exp_rom2);
7525 return -EAGAIN;
7526 }
7527
7528 barrier();
7529
7530 /* Close gates #2, #3 and #4 */
7531 bnx2x_set_234_gates(bp, true);
7532
7533 /* TBD: Indicate that "process kill" is in progress to MCP */
7534
7535 /* Clear "unprepared" bit */
7536 REG_WR(bp, MISC_REG_UNPREPARED, 0);
7537 barrier();
7538
7539 /* Make sure all is written to the chip before the reset */
7540 mmiowb();
7541
7542 /* Wait for 1ms to empty GLUE and PCI-E core queues,
7543 * PSWHST, GRC and PSWRD Tetris buffer.
7544 */
7545 msleep(1);
7546
7547 /* Prepare to chip reset: */
7548 /* MCP */
7549 bnx2x_reset_mcp_prep(bp, &val);
7550
7551 /* PXP */
7552 bnx2x_pxp_prep(bp);
7553 barrier();
7554
7555 /* reset the chip */
7556 bnx2x_process_kill_chip_reset(bp);
7557 barrier();
7558
7559 /* Recover after reset: */
7560 /* MCP */
7561 if (bnx2x_reset_mcp_comp(bp, val))
7562 return -EAGAIN;
7563
7564 /* PXP */
7565 bnx2x_pxp_prep(bp);
7566
7567 /* Open the gates #2, #3 and #4 */
7568 bnx2x_set_234_gates(bp, false);
7569
7570 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
7571 * reset state, re-enable attentions. */
7572
7573 return 0;
7574 }
7575
7576 static int bnx2x_leader_reset(struct bnx2x *bp)
7577 {
7578 int rc = 0;
7579 /* Try to recover after the failure */
7580 if (bnx2x_process_kill(bp)) {
7581 printk(KERN_ERR "%s: Something bad had happen! Aii!\n",
7582 bp->dev->name);
7583 rc = -EAGAIN;
7584 goto exit_leader_reset;
7585 }
7586
7587 /* Clear "reset is in progress" bit and update the driver state */
7588 bnx2x_set_reset_done(bp);
7589 bp->recovery_state = BNX2X_RECOVERY_DONE;
7590
7591 exit_leader_reset:
7592 bp->is_leader = 0;
7593 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESERVED_08);
7594 smp_wmb();
7595 return rc;
7596 }
7597
7598 /* Assumption: runs under rtnl lock. This together with the fact
7599 * that it's called only from bnx2x_reset_task() ensure that it
7600 * will never be called when netif_running(bp->dev) is false.
7601 */
7602 static void bnx2x_parity_recover(struct bnx2x *bp)
7603 {
7604 DP(NETIF_MSG_HW, "Handling parity\n");
7605 while (1) {
7606 switch (bp->recovery_state) {
7607 case BNX2X_RECOVERY_INIT:
7608 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
7609 /* Try to get a LEADER_LOCK HW lock */
7610 if (bnx2x_trylock_hw_lock(bp,
7611 HW_LOCK_RESOURCE_RESERVED_08))
7612 bp->is_leader = 1;
7613
7614 /* Stop the driver */
7615 /* If interface has been removed - break */
7616 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
7617 return;
7618
7619 bp->recovery_state = BNX2X_RECOVERY_WAIT;
7620 /* Ensure "is_leader" and "recovery_state"
7621 * update values are seen on other CPUs
7622 */
7623 smp_wmb();
7624 break;
7625
7626 case BNX2X_RECOVERY_WAIT:
7627 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
7628 if (bp->is_leader) {
7629 u32 load_counter = bnx2x_get_load_cnt(bp);
7630 if (load_counter) {
7631 /* Wait until all other functions get
7632 * down.
7633 */
7634 schedule_delayed_work(&bp->reset_task,
7635 HZ/10);
7636 return;
7637 } else {
7638 /* If all other functions got down -
7639 * try to bring the chip back to
7640 * normal. In any case it's an exit
7641 * point for a leader.
7642 */
7643 if (bnx2x_leader_reset(bp) ||
7644 bnx2x_nic_load(bp, LOAD_NORMAL)) {
7645 printk(KERN_ERR"%s: Recovery "
7646 "has failed. Power cycle is "
7647 "needed.\n", bp->dev->name);
7648 /* Disconnect this device */
7649 netif_device_detach(bp->dev);
7650 /* Block ifup for all function
7651 * of this ASIC until
7652 * "process kill" or power
7653 * cycle.
7654 */
7655 bnx2x_set_reset_in_progress(bp);
7656 /* Shut down the power */
7657 bnx2x_set_power_state(bp,
7658 PCI_D3hot);
7659 return;
7660 }
7661
7662 return;
7663 }
7664 } else { /* non-leader */
7665 if (!bnx2x_reset_is_done(bp)) {
7666 /* Try to get a LEADER_LOCK HW lock as
7667 * long as a former leader may have
7668 * been unloaded by the user or
7669 * released a leadership by another
7670 * reason.
7671 */
7672 if (bnx2x_trylock_hw_lock(bp,
7673 HW_LOCK_RESOURCE_RESERVED_08)) {
7674 /* I'm a leader now! Restart a
7675 * switch case.
7676 */
7677 bp->is_leader = 1;
7678 break;
7679 }
7680
7681 schedule_delayed_work(&bp->reset_task,
7682 HZ/10);
7683 return;
7684
7685 } else { /* A leader has completed
7686 * the "process kill". It's an exit
7687 * point for a non-leader.
7688 */
7689 bnx2x_nic_load(bp, LOAD_NORMAL);
7690 bp->recovery_state =
7691 BNX2X_RECOVERY_DONE;
7692 smp_wmb();
7693 return;
7694 }
7695 }
7696 default:
7697 return;
7698 }
7699 }
7700 }
7701
7702 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
7703 * scheduled on a general queue in order to prevent a dead lock.
7704 */
7705 static void bnx2x_reset_task(struct work_struct *work)
7706 {
7707 struct bnx2x *bp = container_of(work, struct bnx2x, reset_task.work);
7708
7709 #ifdef BNX2X_STOP_ON_ERROR
7710 BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
7711 " so reset not done to allow debug dump,\n"
7712 KERN_ERR " you will need to reboot when done\n");
7713 return;
7714 #endif
7715
7716 rtnl_lock();
7717
7718 if (!netif_running(bp->dev))
7719 goto reset_task_exit;
7720
7721 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE))
7722 bnx2x_parity_recover(bp);
7723 else {
7724 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
7725 bnx2x_nic_load(bp, LOAD_NORMAL);
7726 }
7727
7728 reset_task_exit:
7729 rtnl_unlock();
7730 }
7731
7732 /* end of nic load/unload */
7733
7734 /*
7735 * Init service functions
7736 */
7737
7738 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
7739 {
7740 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
7741 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
7742 return base + (BP_ABS_FUNC(bp)) * stride;
7743 }
7744
7745 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
7746 {
7747 u32 reg = bnx2x_get_pretend_reg(bp);
7748
7749 /* Flush all outstanding writes */
7750 mmiowb();
7751
7752 /* Pretend to be function 0 */
7753 REG_WR(bp, reg, 0);
7754 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
7755
7756 /* From now we are in the "like-E1" mode */
7757 bnx2x_int_disable(bp);
7758
7759 /* Flush all outstanding writes */
7760 mmiowb();
7761
7762 /* Restore the original function */
7763 REG_WR(bp, reg, BP_ABS_FUNC(bp));
7764 REG_RD(bp, reg);
7765 }
7766
7767 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
7768 {
7769 if (CHIP_IS_E1(bp))
7770 bnx2x_int_disable(bp);
7771 else
7772 bnx2x_undi_int_disable_e1h(bp);
7773 }
7774
7775 static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
7776 {
7777 u32 val;
7778
7779 /* Check if there is any driver already loaded */
7780 val = REG_RD(bp, MISC_REG_UNPREPARED);
7781 if (val == 0x1) {
7782 /* Check if it is the UNDI driver
7783 * UNDI driver initializes CID offset for normal bell to 0x7
7784 */
7785 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7786 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
7787 if (val == 0x7) {
7788 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7789 /* save our pf_num */
7790 int orig_pf_num = bp->pf_num;
7791 u32 swap_en;
7792 u32 swap_val;
7793
7794 /* clear the UNDI indication */
7795 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
7796
7797 BNX2X_DEV_INFO("UNDI is active! reset device\n");
7798
7799 /* try unload UNDI on port 0 */
7800 bp->pf_num = 0;
7801 bp->fw_seq =
7802 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
7803 DRV_MSG_SEQ_NUMBER_MASK);
7804 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7805
7806 /* if UNDI is loaded on the other port */
7807 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
7808
7809 /* send "DONE" for previous unload */
7810 bnx2x_fw_command(bp,
7811 DRV_MSG_CODE_UNLOAD_DONE, 0);
7812
7813 /* unload UNDI on port 1 */
7814 bp->pf_num = 1;
7815 bp->fw_seq =
7816 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
7817 DRV_MSG_SEQ_NUMBER_MASK);
7818 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7819
7820 bnx2x_fw_command(bp, reset_code, 0);
7821 }
7822
7823 /* now it's safe to release the lock */
7824 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7825
7826 bnx2x_undi_int_disable(bp);
7827
7828 /* close input traffic and wait for it */
7829 /* Do not rcv packets to BRB */
7830 REG_WR(bp,
7831 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_DRV_MASK :
7832 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
7833 /* Do not direct rcv packets that are not for MCP to
7834 * the BRB */
7835 REG_WR(bp,
7836 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_NOT_MCP :
7837 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7838 /* clear AEU */
7839 REG_WR(bp,
7840 (BP_PORT(bp) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7841 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
7842 msleep(10);
7843
7844 /* save NIG port swap info */
7845 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7846 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7847 /* reset device */
7848 REG_WR(bp,
7849 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7850 0xd3ffffff);
7851 REG_WR(bp,
7852 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7853 0x1403);
7854 /* take the NIG out of reset and restore swap values */
7855 REG_WR(bp,
7856 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7857 MISC_REGISTERS_RESET_REG_1_RST_NIG);
7858 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
7859 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
7860
7861 /* send unload done to the MCP */
7862 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7863
7864 /* restore our func and fw_seq */
7865 bp->pf_num = orig_pf_num;
7866 bp->fw_seq =
7867 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
7868 DRV_MSG_SEQ_NUMBER_MASK);
7869 } else
7870 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7871 }
7872 }
7873
7874 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
7875 {
7876 u32 val, val2, val3, val4, id;
7877 u16 pmc;
7878
7879 /* Get the chip revision id and number. */
7880 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
7881 val = REG_RD(bp, MISC_REG_CHIP_NUM);
7882 id = ((val & 0xffff) << 16);
7883 val = REG_RD(bp, MISC_REG_CHIP_REV);
7884 id |= ((val & 0xf) << 12);
7885 val = REG_RD(bp, MISC_REG_CHIP_METAL);
7886 id |= ((val & 0xff) << 4);
7887 val = REG_RD(bp, MISC_REG_BOND_ID);
7888 id |= (val & 0xf);
7889 bp->common.chip_id = id;
7890
7891 /* Set doorbell size */
7892 bp->db_size = (1 << BNX2X_DB_SHIFT);
7893
7894 if (CHIP_IS_E2(bp)) {
7895 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
7896 if ((val & 1) == 0)
7897 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
7898 else
7899 val = (val >> 1) & 1;
7900 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
7901 "2_PORT_MODE");
7902 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
7903 CHIP_2_PORT_MODE;
7904
7905 if (CHIP_MODE_IS_4_PORT(bp))
7906 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
7907 else
7908 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
7909 } else {
7910 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
7911 bp->pfid = bp->pf_num; /* 0..7 */
7912 }
7913
7914 /*
7915 * set base FW non-default (fast path) status block id, this value is
7916 * used to initialize the fw_sb_id saved on the fp/queue structure to
7917 * determine the id used by the FW.
7918 */
7919 if (CHIP_IS_E1x(bp))
7920 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x;
7921 else /* E2 */
7922 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E2;
7923
7924 bp->link_params.chip_id = bp->common.chip_id;
7925 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
7926
7927 val = (REG_RD(bp, 0x2874) & 0x55);
7928 if ((bp->common.chip_id & 0x1) ||
7929 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
7930 bp->flags |= ONE_PORT_FLAG;
7931 BNX2X_DEV_INFO("single port device\n");
7932 }
7933
7934 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
7935 bp->common.flash_size = (NVRAM_1MB_SIZE <<
7936 (val & MCPR_NVM_CFG4_FLASH_SIZE));
7937 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
7938 bp->common.flash_size, bp->common.flash_size);
7939
7940 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7941 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
7942 MISC_REG_GENERIC_CR_1 :
7943 MISC_REG_GENERIC_CR_0));
7944 bp->link_params.shmem_base = bp->common.shmem_base;
7945 bp->link_params.shmem2_base = bp->common.shmem2_base;
7946 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
7947 bp->common.shmem_base, bp->common.shmem2_base);
7948
7949 if (!bp->common.shmem_base) {
7950 BNX2X_DEV_INFO("MCP not active\n");
7951 bp->flags |= NO_MCP_FLAG;
7952 return;
7953 }
7954
7955 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7956 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7957 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7958 BNX2X_ERR("BAD MCP validity signature\n");
7959
7960 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
7961 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
7962
7963 bp->link_params.hw_led_mode = ((bp->common.hw_config &
7964 SHARED_HW_CFG_LED_MODE_MASK) >>
7965 SHARED_HW_CFG_LED_MODE_SHIFT);
7966
7967 bp->link_params.feature_config_flags = 0;
7968 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
7969 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
7970 bp->link_params.feature_config_flags |=
7971 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7972 else
7973 bp->link_params.feature_config_flags &=
7974 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7975
7976 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
7977 bp->common.bc_ver = val;
7978 BNX2X_DEV_INFO("bc_ver %X\n", val);
7979 if (val < BNX2X_BC_VER) {
7980 /* for now only warn
7981 * later we might need to enforce this */
7982 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
7983 "please upgrade BC\n", BNX2X_BC_VER, val);
7984 }
7985 bp->link_params.feature_config_flags |=
7986 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
7987 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
7988
7989 bp->link_params.feature_config_flags |=
7990 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
7991 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
7992
7993 if (BP_E1HVN(bp) == 0) {
7994 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
7995 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
7996 } else {
7997 /* no WOL capability for E1HVN != 0 */
7998 bp->flags |= NO_WOL_FLAG;
7999 }
8000 BNX2X_DEV_INFO("%sWoL capable\n",
8001 (bp->flags & NO_WOL_FLAG) ? "not " : "");
8002
8003 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
8004 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
8005 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
8006 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
8007
8008 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
8009 val, val2, val3, val4);
8010 }
8011
8012 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8013 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8014
8015 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
8016 {
8017 int pfid = BP_FUNC(bp);
8018 int vn = BP_E1HVN(bp);
8019 int igu_sb_id;
8020 u32 val;
8021 u8 fid;
8022
8023 bp->igu_base_sb = 0xff;
8024 bp->igu_sb_cnt = 0;
8025 if (CHIP_INT_MODE_IS_BC(bp)) {
8026 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
8027 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
8028
8029 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
8030 FP_SB_MAX_E1x;
8031
8032 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
8033 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
8034
8035 return;
8036 }
8037
8038 /* IGU in normal mode - read CAM */
8039 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
8040 igu_sb_id++) {
8041 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8042 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
8043 continue;
8044 fid = IGU_FID(val);
8045 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8046 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
8047 continue;
8048 if (IGU_VEC(val) == 0)
8049 /* default status block */
8050 bp->igu_dsb_id = igu_sb_id;
8051 else {
8052 if (bp->igu_base_sb == 0xff)
8053 bp->igu_base_sb = igu_sb_id;
8054 bp->igu_sb_cnt++;
8055 }
8056 }
8057 }
8058 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
8059 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
8060 if (bp->igu_sb_cnt == 0)
8061 BNX2X_ERR("CAM configuration error\n");
8062 }
8063
8064 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
8065 u32 switch_cfg)
8066 {
8067 int cfg_size = 0, idx, port = BP_PORT(bp);
8068
8069 /* Aggregation of supported attributes of all external phys */
8070 bp->port.supported[0] = 0;
8071 bp->port.supported[1] = 0;
8072 switch (bp->link_params.num_phys) {
8073 case 1:
8074 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
8075 cfg_size = 1;
8076 break;
8077 case 2:
8078 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
8079 cfg_size = 1;
8080 break;
8081 case 3:
8082 if (bp->link_params.multi_phy_config &
8083 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8084 bp->port.supported[1] =
8085 bp->link_params.phy[EXT_PHY1].supported;
8086 bp->port.supported[0] =
8087 bp->link_params.phy[EXT_PHY2].supported;
8088 } else {
8089 bp->port.supported[0] =
8090 bp->link_params.phy[EXT_PHY1].supported;
8091 bp->port.supported[1] =
8092 bp->link_params.phy[EXT_PHY2].supported;
8093 }
8094 cfg_size = 2;
8095 break;
8096 }
8097
8098 if (!(bp->port.supported[0] || bp->port.supported[1])) {
8099 BNX2X_ERR("NVRAM config error. BAD phy config."
8100 "PHY1 config 0x%x, PHY2 config 0x%x\n",
8101 SHMEM_RD(bp,
8102 dev_info.port_hw_config[port].external_phy_config),
8103 SHMEM_RD(bp,
8104 dev_info.port_hw_config[port].external_phy_config2));
8105 return;
8106 }
8107
8108 switch (switch_cfg) {
8109 case SWITCH_CFG_1G:
8110 bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
8111 port*0x10);
8112 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8113 break;
8114
8115 case SWITCH_CFG_10G:
8116 bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
8117 port*0x18);
8118 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8119 break;
8120
8121 default:
8122 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8123 bp->port.link_config[0]);
8124 return;
8125 }
8126 /* mask what we support according to speed_cap_mask per configuration */
8127 for (idx = 0; idx < cfg_size; idx++) {
8128 if (!(bp->link_params.speed_cap_mask[idx] &
8129 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
8130 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
8131
8132 if (!(bp->link_params.speed_cap_mask[idx] &
8133 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
8134 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
8135
8136 if (!(bp->link_params.speed_cap_mask[idx] &
8137 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
8138 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
8139
8140 if (!(bp->link_params.speed_cap_mask[idx] &
8141 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
8142 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
8143
8144 if (!(bp->link_params.speed_cap_mask[idx] &
8145 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
8146 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
8147 SUPPORTED_1000baseT_Full);
8148
8149 if (!(bp->link_params.speed_cap_mask[idx] &
8150 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8151 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
8152
8153 if (!(bp->link_params.speed_cap_mask[idx] &
8154 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
8155 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8156
8157 }
8158
8159 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8160 bp->port.supported[1]);
8161 }
8162
8163 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
8164 {
8165 u32 link_config, idx, cfg_size = 0;
8166 bp->port.advertising[0] = 0;
8167 bp->port.advertising[1] = 0;
8168 switch (bp->link_params.num_phys) {
8169 case 1:
8170 case 2:
8171 cfg_size = 1;
8172 break;
8173 case 3:
8174 cfg_size = 2;
8175 break;
8176 }
8177 for (idx = 0; idx < cfg_size; idx++) {
8178 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8179 link_config = bp->port.link_config[idx];
8180 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8181 case PORT_FEATURE_LINK_SPEED_AUTO:
8182 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8183 bp->link_params.req_line_speed[idx] =
8184 SPEED_AUTO_NEG;
8185 bp->port.advertising[idx] |=
8186 bp->port.supported[idx];
8187 } else {
8188 /* force 10G, no AN */
8189 bp->link_params.req_line_speed[idx] =
8190 SPEED_10000;
8191 bp->port.advertising[idx] |=
8192 (ADVERTISED_10000baseT_Full |
8193 ADVERTISED_FIBRE);
8194 continue;
8195 }
8196 break;
8197
8198 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8199 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8200 bp->link_params.req_line_speed[idx] =
8201 SPEED_10;
8202 bp->port.advertising[idx] |=
8203 (ADVERTISED_10baseT_Full |
8204 ADVERTISED_TP);
8205 } else {
8206 BNX2X_ERROR("NVRAM config error. "
8207 "Invalid link_config 0x%x"
8208 " speed_cap_mask 0x%x\n",
8209 link_config,
8210 bp->link_params.speed_cap_mask[idx]);
8211 return;
8212 }
8213 break;
8214
8215 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8216 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
8217 bp->link_params.req_line_speed[idx] =
8218 SPEED_10;
8219 bp->link_params.req_duplex[idx] =
8220 DUPLEX_HALF;
8221 bp->port.advertising[idx] |=
8222 (ADVERTISED_10baseT_Half |
8223 ADVERTISED_TP);
8224 } else {
8225 BNX2X_ERROR("NVRAM config error. "
8226 "Invalid link_config 0x%x"
8227 " speed_cap_mask 0x%x\n",
8228 link_config,
8229 bp->link_params.speed_cap_mask[idx]);
8230 return;
8231 }
8232 break;
8233
8234 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8235 if (bp->port.supported[idx] &
8236 SUPPORTED_100baseT_Full) {
8237 bp->link_params.req_line_speed[idx] =
8238 SPEED_100;
8239 bp->port.advertising[idx] |=
8240 (ADVERTISED_100baseT_Full |
8241 ADVERTISED_TP);
8242 } else {
8243 BNX2X_ERROR("NVRAM config error. "
8244 "Invalid link_config 0x%x"
8245 " speed_cap_mask 0x%x\n",
8246 link_config,
8247 bp->link_params.speed_cap_mask[idx]);
8248 return;
8249 }
8250 break;
8251
8252 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8253 if (bp->port.supported[idx] &
8254 SUPPORTED_100baseT_Half) {
8255 bp->link_params.req_line_speed[idx] =
8256 SPEED_100;
8257 bp->link_params.req_duplex[idx] =
8258 DUPLEX_HALF;
8259 bp->port.advertising[idx] |=
8260 (ADVERTISED_100baseT_Half |
8261 ADVERTISED_TP);
8262 } else {
8263 BNX2X_ERROR("NVRAM config error. "
8264 "Invalid link_config 0x%x"
8265 " speed_cap_mask 0x%x\n",
8266 link_config,
8267 bp->link_params.speed_cap_mask[idx]);
8268 return;
8269 }
8270 break;
8271
8272 case PORT_FEATURE_LINK_SPEED_1G:
8273 if (bp->port.supported[idx] &
8274 SUPPORTED_1000baseT_Full) {
8275 bp->link_params.req_line_speed[idx] =
8276 SPEED_1000;
8277 bp->port.advertising[idx] |=
8278 (ADVERTISED_1000baseT_Full |
8279 ADVERTISED_TP);
8280 } else {
8281 BNX2X_ERROR("NVRAM config error. "
8282 "Invalid link_config 0x%x"
8283 " speed_cap_mask 0x%x\n",
8284 link_config,
8285 bp->link_params.speed_cap_mask[idx]);
8286 return;
8287 }
8288 break;
8289
8290 case PORT_FEATURE_LINK_SPEED_2_5G:
8291 if (bp->port.supported[idx] &
8292 SUPPORTED_2500baseX_Full) {
8293 bp->link_params.req_line_speed[idx] =
8294 SPEED_2500;
8295 bp->port.advertising[idx] |=
8296 (ADVERTISED_2500baseX_Full |
8297 ADVERTISED_TP);
8298 } else {
8299 BNX2X_ERROR("NVRAM config error. "
8300 "Invalid link_config 0x%x"
8301 " speed_cap_mask 0x%x\n",
8302 link_config,
8303 bp->link_params.speed_cap_mask[idx]);
8304 return;
8305 }
8306 break;
8307
8308 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8309 case PORT_FEATURE_LINK_SPEED_10G_KX4:
8310 case PORT_FEATURE_LINK_SPEED_10G_KR:
8311 if (bp->port.supported[idx] &
8312 SUPPORTED_10000baseT_Full) {
8313 bp->link_params.req_line_speed[idx] =
8314 SPEED_10000;
8315 bp->port.advertising[idx] |=
8316 (ADVERTISED_10000baseT_Full |
8317 ADVERTISED_FIBRE);
8318 } else {
8319 BNX2X_ERROR("NVRAM config error. "
8320 "Invalid link_config 0x%x"
8321 " speed_cap_mask 0x%x\n",
8322 link_config,
8323 bp->link_params.speed_cap_mask[idx]);
8324 return;
8325 }
8326 break;
8327
8328 default:
8329 BNX2X_ERROR("NVRAM config error. "
8330 "BAD link speed link_config 0x%x\n",
8331 link_config);
8332 bp->link_params.req_line_speed[idx] =
8333 SPEED_AUTO_NEG;
8334 bp->port.advertising[idx] =
8335 bp->port.supported[idx];
8336 break;
8337 }
8338
8339 bp->link_params.req_flow_ctrl[idx] = (link_config &
8340 PORT_FEATURE_FLOW_CONTROL_MASK);
8341 if ((bp->link_params.req_flow_ctrl[idx] ==
8342 BNX2X_FLOW_CTRL_AUTO) &&
8343 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
8344 bp->link_params.req_flow_ctrl[idx] =
8345 BNX2X_FLOW_CTRL_NONE;
8346 }
8347
8348 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
8349 " 0x%x advertising 0x%x\n",
8350 bp->link_params.req_line_speed[idx],
8351 bp->link_params.req_duplex[idx],
8352 bp->link_params.req_flow_ctrl[idx],
8353 bp->port.advertising[idx]);
8354 }
8355 }
8356
8357 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
8358 {
8359 mac_hi = cpu_to_be16(mac_hi);
8360 mac_lo = cpu_to_be32(mac_lo);
8361 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
8362 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
8363 }
8364
8365 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
8366 {
8367 int port = BP_PORT(bp);
8368 u32 config;
8369 u32 ext_phy_type, ext_phy_config;
8370
8371 bp->link_params.bp = bp;
8372 bp->link_params.port = port;
8373
8374 bp->link_params.lane_config =
8375 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
8376
8377 bp->link_params.speed_cap_mask[0] =
8378 SHMEM_RD(bp,
8379 dev_info.port_hw_config[port].speed_capability_mask);
8380 bp->link_params.speed_cap_mask[1] =
8381 SHMEM_RD(bp,
8382 dev_info.port_hw_config[port].speed_capability_mask2);
8383 bp->port.link_config[0] =
8384 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
8385
8386 bp->port.link_config[1] =
8387 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
8388
8389 bp->link_params.multi_phy_config =
8390 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
8391 /* If the device is capable of WoL, set the default state according
8392 * to the HW
8393 */
8394 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
8395 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
8396 (config & PORT_FEATURE_WOL_ENABLED));
8397
8398 BNX2X_DEV_INFO("lane_config 0x%08x "
8399 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
8400 bp->link_params.lane_config,
8401 bp->link_params.speed_cap_mask[0],
8402 bp->port.link_config[0]);
8403
8404 bp->link_params.switch_cfg = (bp->port.link_config[0] &
8405 PORT_FEATURE_CONNECTED_SWITCH_MASK);
8406 bnx2x_phy_probe(&bp->link_params);
8407 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
8408
8409 bnx2x_link_settings_requested(bp);
8410
8411 /*
8412 * If connected directly, work with the internal PHY, otherwise, work
8413 * with the external PHY
8414 */
8415 ext_phy_config =
8416 SHMEM_RD(bp,
8417 dev_info.port_hw_config[port].external_phy_config);
8418 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
8419 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8420 bp->mdio.prtad = bp->port.phy_addr;
8421
8422 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
8423 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
8424 bp->mdio.prtad =
8425 XGXS_EXT_PHY_ADDR(ext_phy_config);
8426 }
8427
8428 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
8429 {
8430 u32 val, val2;
8431 int func = BP_ABS_FUNC(bp);
8432 int port = BP_PORT(bp);
8433
8434 if (BP_NOMCP(bp)) {
8435 BNX2X_ERROR("warning: random MAC workaround active\n");
8436 random_ether_addr(bp->dev->dev_addr);
8437 } else if (IS_MF(bp)) {
8438 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
8439 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
8440 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
8441 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
8442 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8443
8444 #ifdef BCM_CNIC
8445 /* iSCSI NPAR MAC */
8446 if (IS_MF_SI(bp)) {
8447 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
8448 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
8449 val2 = MF_CFG_RD(bp, func_ext_config[func].
8450 iscsi_mac_addr_upper);
8451 val = MF_CFG_RD(bp, func_ext_config[func].
8452 iscsi_mac_addr_lower);
8453 bnx2x_set_mac_buf(bp->iscsi_mac, val, val2);
8454 }
8455 }
8456 #endif
8457 } else {
8458 /* in SF read MACs from port configuration */
8459 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
8460 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
8461 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8462
8463 #ifdef BCM_CNIC
8464 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
8465 iscsi_mac_upper);
8466 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
8467 iscsi_mac_lower);
8468 bnx2x_set_mac_buf(bp->iscsi_mac, val, val2);
8469 #endif
8470 }
8471
8472 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
8473 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
8474
8475 #ifdef BCM_CNIC
8476 /* Inform the upper layers about FCoE MAC */
8477 if (!CHIP_IS_E1x(bp)) {
8478 if (IS_MF_SD(bp))
8479 memcpy(bp->fip_mac, bp->dev->dev_addr,
8480 sizeof(bp->fip_mac));
8481 else
8482 memcpy(bp->fip_mac, bp->iscsi_mac,
8483 sizeof(bp->fip_mac));
8484 }
8485 #endif
8486 }
8487
8488 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
8489 {
8490 int /*abs*/func = BP_ABS_FUNC(bp);
8491 int vn, port;
8492 u32 val = 0;
8493 int rc = 0;
8494
8495 bnx2x_get_common_hwinfo(bp);
8496
8497 if (CHIP_IS_E1x(bp)) {
8498 bp->common.int_block = INT_BLOCK_HC;
8499
8500 bp->igu_dsb_id = DEF_SB_IGU_ID;
8501 bp->igu_base_sb = 0;
8502 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
8503 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
8504 } else {
8505 bp->common.int_block = INT_BLOCK_IGU;
8506 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8507 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8508 DP(NETIF_MSG_PROBE, "IGU Backward Compatible Mode\n");
8509 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
8510 } else
8511 DP(NETIF_MSG_PROBE, "IGU Normal Mode\n");
8512
8513 bnx2x_get_igu_cam_info(bp);
8514
8515 }
8516 DP(NETIF_MSG_PROBE, "igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n",
8517 bp->igu_dsb_id, bp->igu_base_sb, bp->igu_sb_cnt);
8518
8519 /*
8520 * Initialize MF configuration
8521 */
8522
8523 bp->mf_ov = 0;
8524 bp->mf_mode = 0;
8525 vn = BP_E1HVN(bp);
8526 port = BP_PORT(bp);
8527
8528 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
8529 DP(NETIF_MSG_PROBE,
8530 "shmem2base 0x%x, size %d, mfcfg offset %d\n",
8531 bp->common.shmem2_base, SHMEM2_RD(bp, size),
8532 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
8533 if (SHMEM2_HAS(bp, mf_cfg_addr))
8534 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
8535 else
8536 bp->common.mf_cfg_base = bp->common.shmem_base +
8537 offsetof(struct shmem_region, func_mb) +
8538 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
8539 /*
8540 * get mf configuration:
8541 * 1. existance of MF configuration
8542 * 2. MAC address must be legal (check only upper bytes)
8543 * for Switch-Independent mode;
8544 * OVLAN must be legal for Switch-Dependent mode
8545 * 3. SF_MODE configures specific MF mode
8546 */
8547 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
8548 /* get mf configuration */
8549 val = SHMEM_RD(bp,
8550 dev_info.shared_feature_config.config);
8551 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
8552
8553 switch (val) {
8554 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
8555 val = MF_CFG_RD(bp, func_mf_config[func].
8556 mac_upper);
8557 /* check for legal mac (upper bytes)*/
8558 if (val != 0xffff) {
8559 bp->mf_mode = MULTI_FUNCTION_SI;
8560 bp->mf_config[vn] = MF_CFG_RD(bp,
8561 func_mf_config[func].config);
8562 } else
8563 DP(NETIF_MSG_PROBE, "illegal MAC "
8564 "address for SI\n");
8565 break;
8566 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
8567 /* get OV configuration */
8568 val = MF_CFG_RD(bp,
8569 func_mf_config[FUNC_0].e1hov_tag);
8570 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
8571
8572 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8573 bp->mf_mode = MULTI_FUNCTION_SD;
8574 bp->mf_config[vn] = MF_CFG_RD(bp,
8575 func_mf_config[func].config);
8576 } else
8577 DP(NETIF_MSG_PROBE, "illegal OV for "
8578 "SD\n");
8579 break;
8580 default:
8581 /* Unknown configuration: reset mf_config */
8582 bp->mf_config[vn] = 0;
8583 DP(NETIF_MSG_PROBE, "Unkown MF mode 0x%x\n",
8584 val);
8585 }
8586 }
8587
8588 BNX2X_DEV_INFO("%s function mode\n",
8589 IS_MF(bp) ? "multi" : "single");
8590
8591 switch (bp->mf_mode) {
8592 case MULTI_FUNCTION_SD:
8593 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
8594 FUNC_MF_CFG_E1HOV_TAG_MASK;
8595 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8596 bp->mf_ov = val;
8597 BNX2X_DEV_INFO("MF OV for func %d is %d"
8598 " (0x%04x)\n", func,
8599 bp->mf_ov, bp->mf_ov);
8600 } else {
8601 BNX2X_ERR("No valid MF OV for func %d,"
8602 " aborting\n", func);
8603 rc = -EPERM;
8604 }
8605 break;
8606 case MULTI_FUNCTION_SI:
8607 BNX2X_DEV_INFO("func %d is in MF "
8608 "switch-independent mode\n", func);
8609 break;
8610 default:
8611 if (vn) {
8612 BNX2X_ERR("VN %d in single function mode,"
8613 " aborting\n", vn);
8614 rc = -EPERM;
8615 }
8616 break;
8617 }
8618
8619 }
8620
8621 /* adjust igu_sb_cnt to MF for E1x */
8622 if (CHIP_IS_E1x(bp) && IS_MF(bp))
8623 bp->igu_sb_cnt /= E1HVN_MAX;
8624
8625 /*
8626 * adjust E2 sb count: to be removed when FW will support
8627 * more then 16 L2 clients
8628 */
8629 #define MAX_L2_CLIENTS 16
8630 if (CHIP_IS_E2(bp))
8631 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
8632 MAX_L2_CLIENTS / (IS_MF(bp) ? 4 : 1));
8633
8634 if (!BP_NOMCP(bp)) {
8635 bnx2x_get_port_hwinfo(bp);
8636
8637 bp->fw_seq =
8638 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
8639 DRV_MSG_SEQ_NUMBER_MASK);
8640 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
8641 }
8642
8643 /* Get MAC addresses */
8644 bnx2x_get_mac_hwinfo(bp);
8645
8646 return rc;
8647 }
8648
8649 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
8650 {
8651 int cnt, i, block_end, rodi;
8652 char vpd_data[BNX2X_VPD_LEN+1];
8653 char str_id_reg[VENDOR_ID_LEN+1];
8654 char str_id_cap[VENDOR_ID_LEN+1];
8655 u8 len;
8656
8657 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
8658 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
8659
8660 if (cnt < BNX2X_VPD_LEN)
8661 goto out_not_found;
8662
8663 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
8664 PCI_VPD_LRDT_RO_DATA);
8665 if (i < 0)
8666 goto out_not_found;
8667
8668
8669 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
8670 pci_vpd_lrdt_size(&vpd_data[i]);
8671
8672 i += PCI_VPD_LRDT_TAG_SIZE;
8673
8674 if (block_end > BNX2X_VPD_LEN)
8675 goto out_not_found;
8676
8677 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8678 PCI_VPD_RO_KEYWORD_MFR_ID);
8679 if (rodi < 0)
8680 goto out_not_found;
8681
8682 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8683
8684 if (len != VENDOR_ID_LEN)
8685 goto out_not_found;
8686
8687 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8688
8689 /* vendor specific info */
8690 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
8691 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
8692 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
8693 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
8694
8695 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8696 PCI_VPD_RO_KEYWORD_VENDOR0);
8697 if (rodi >= 0) {
8698 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8699
8700 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8701
8702 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
8703 memcpy(bp->fw_ver, &vpd_data[rodi], len);
8704 bp->fw_ver[len] = ' ';
8705 }
8706 }
8707 return;
8708 }
8709 out_not_found:
8710 return;
8711 }
8712
8713 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
8714 {
8715 int func;
8716 int timer_interval;
8717 int rc;
8718
8719 /* Disable interrupt handling until HW is initialized */
8720 atomic_set(&bp->intr_sem, 1);
8721 smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
8722
8723 mutex_init(&bp->port.phy_mutex);
8724 mutex_init(&bp->fw_mb_mutex);
8725 spin_lock_init(&bp->stats_lock);
8726 #ifdef BCM_CNIC
8727 mutex_init(&bp->cnic_mutex);
8728 #endif
8729
8730 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
8731 INIT_DELAYED_WORK(&bp->reset_task, bnx2x_reset_task);
8732
8733 rc = bnx2x_get_hwinfo(bp);
8734
8735 if (!rc)
8736 rc = bnx2x_alloc_mem_bp(bp);
8737
8738 bnx2x_read_fwinfo(bp);
8739
8740 func = BP_FUNC(bp);
8741
8742 /* need to reset chip if undi was active */
8743 if (!BP_NOMCP(bp))
8744 bnx2x_undi_unload(bp);
8745
8746 if (CHIP_REV_IS_FPGA(bp))
8747 dev_err(&bp->pdev->dev, "FPGA detected\n");
8748
8749 if (BP_NOMCP(bp) && (func == 0))
8750 dev_err(&bp->pdev->dev, "MCP disabled, "
8751 "must load devices in order!\n");
8752
8753 /* Set multi queue mode */
8754 if ((multi_mode != ETH_RSS_MODE_DISABLED) &&
8755 ((int_mode == INT_MODE_INTx) || (int_mode == INT_MODE_MSI))) {
8756 dev_err(&bp->pdev->dev, "Multi disabled since int_mode "
8757 "requested is not MSI-X\n");
8758 multi_mode = ETH_RSS_MODE_DISABLED;
8759 }
8760 bp->multi_mode = multi_mode;
8761 bp->int_mode = int_mode;
8762
8763 bp->dev->features |= NETIF_F_GRO;
8764
8765 /* Set TPA flags */
8766 if (disable_tpa) {
8767 bp->flags &= ~TPA_ENABLE_FLAG;
8768 bp->dev->features &= ~NETIF_F_LRO;
8769 } else {
8770 bp->flags |= TPA_ENABLE_FLAG;
8771 bp->dev->features |= NETIF_F_LRO;
8772 }
8773 bp->disable_tpa = disable_tpa;
8774
8775 if (CHIP_IS_E1(bp))
8776 bp->dropless_fc = 0;
8777 else
8778 bp->dropless_fc = dropless_fc;
8779
8780 bp->mrrs = mrrs;
8781
8782 bp->tx_ring_size = MAX_TX_AVAIL;
8783
8784 bp->rx_csum = 1;
8785
8786 /* make sure that the numbers are in the right granularity */
8787 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
8788 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
8789
8790 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
8791 bp->current_interval = (poll ? poll : timer_interval);
8792
8793 init_timer(&bp->timer);
8794 bp->timer.expires = jiffies + bp->current_interval;
8795 bp->timer.data = (unsigned long) bp;
8796 bp->timer.function = bnx2x_timer;
8797
8798 bnx2x_dcbx_init_params(bp);
8799
8800 return rc;
8801 }
8802
8803
8804 /****************************************************************************
8805 * General service functions
8806 ****************************************************************************/
8807
8808 /* called with rtnl_lock */
8809 static int bnx2x_open(struct net_device *dev)
8810 {
8811 struct bnx2x *bp = netdev_priv(dev);
8812
8813 netif_carrier_off(dev);
8814
8815 bnx2x_set_power_state(bp, PCI_D0);
8816
8817 if (!bnx2x_reset_is_done(bp)) {
8818 do {
8819 /* Reset MCP mail box sequence if there is on going
8820 * recovery
8821 */
8822 bp->fw_seq = 0;
8823
8824 /* If it's the first function to load and reset done
8825 * is still not cleared it may mean that. We don't
8826 * check the attention state here because it may have
8827 * already been cleared by a "common" reset but we
8828 * shell proceed with "process kill" anyway.
8829 */
8830 if ((bnx2x_get_load_cnt(bp) == 0) &&
8831 bnx2x_trylock_hw_lock(bp,
8832 HW_LOCK_RESOURCE_RESERVED_08) &&
8833 (!bnx2x_leader_reset(bp))) {
8834 DP(NETIF_MSG_HW, "Recovered in open\n");
8835 break;
8836 }
8837
8838 bnx2x_set_power_state(bp, PCI_D3hot);
8839
8840 printk(KERN_ERR"%s: Recovery flow hasn't been properly"
8841 " completed yet. Try again later. If u still see this"
8842 " message after a few retries then power cycle is"
8843 " required.\n", bp->dev->name);
8844
8845 return -EAGAIN;
8846 } while (0);
8847 }
8848
8849 bp->recovery_state = BNX2X_RECOVERY_DONE;
8850
8851 return bnx2x_nic_load(bp, LOAD_OPEN);
8852 }
8853
8854 /* called with rtnl_lock */
8855 static int bnx2x_close(struct net_device *dev)
8856 {
8857 struct bnx2x *bp = netdev_priv(dev);
8858
8859 /* Unload the driver, release IRQs */
8860 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
8861 bnx2x_set_power_state(bp, PCI_D3hot);
8862
8863 return 0;
8864 }
8865
8866 /* called with netif_tx_lock from dev_mcast.c */
8867 void bnx2x_set_rx_mode(struct net_device *dev)
8868 {
8869 struct bnx2x *bp = netdev_priv(dev);
8870 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
8871 int port = BP_PORT(bp);
8872
8873 if (bp->state != BNX2X_STATE_OPEN) {
8874 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
8875 return;
8876 }
8877
8878 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);
8879
8880 if (dev->flags & IFF_PROMISC)
8881 rx_mode = BNX2X_RX_MODE_PROMISC;
8882 else if ((dev->flags & IFF_ALLMULTI) ||
8883 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
8884 CHIP_IS_E1(bp)))
8885 rx_mode = BNX2X_RX_MODE_ALLMULTI;
8886 else { /* some multicasts */
8887 if (CHIP_IS_E1(bp)) {
8888 /*
8889 * set mc list, do not wait as wait implies sleep
8890 * and set_rx_mode can be invoked from non-sleepable
8891 * context
8892 */
8893 u8 offset = (CHIP_REV_IS_SLOW(bp) ?
8894 BNX2X_MAX_EMUL_MULTI*(1 + port) :
8895 BNX2X_MAX_MULTICAST*(1 + port));
8896
8897 bnx2x_set_e1_mc_list(bp, offset);
8898 } else { /* E1H */
8899 /* Accept one or more multicasts */
8900 struct netdev_hw_addr *ha;
8901 u32 mc_filter[MC_HASH_SIZE];
8902 u32 crc, bit, regidx;
8903 int i;
8904
8905 memset(mc_filter, 0, 4 * MC_HASH_SIZE);
8906
8907 netdev_for_each_mc_addr(ha, dev) {
8908 DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
8909 bnx2x_mc_addr(ha));
8910
8911 crc = crc32c_le(0, bnx2x_mc_addr(ha),
8912 ETH_ALEN);
8913 bit = (crc >> 24) & 0xff;
8914 regidx = bit >> 5;
8915 bit &= 0x1f;
8916 mc_filter[regidx] |= (1 << bit);
8917 }
8918
8919 for (i = 0; i < MC_HASH_SIZE; i++)
8920 REG_WR(bp, MC_HASH_OFFSET(bp, i),
8921 mc_filter[i]);
8922 }
8923 }
8924
8925 bp->rx_mode = rx_mode;
8926 bnx2x_set_storm_rx_mode(bp);
8927 }
8928
8929 /* called with rtnl_lock */
8930 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
8931 int devad, u16 addr)
8932 {
8933 struct bnx2x *bp = netdev_priv(netdev);
8934 u16 value;
8935 int rc;
8936
8937 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
8938 prtad, devad, addr);
8939
8940 /* The HW expects different devad if CL22 is used */
8941 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
8942
8943 bnx2x_acquire_phy_lock(bp);
8944 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
8945 bnx2x_release_phy_lock(bp);
8946 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
8947
8948 if (!rc)
8949 rc = value;
8950 return rc;
8951 }
8952
8953 /* called with rtnl_lock */
8954 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
8955 u16 addr, u16 value)
8956 {
8957 struct bnx2x *bp = netdev_priv(netdev);
8958 int rc;
8959
8960 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
8961 " value 0x%x\n", prtad, devad, addr, value);
8962
8963 /* The HW expects different devad if CL22 is used */
8964 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
8965
8966 bnx2x_acquire_phy_lock(bp);
8967 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
8968 bnx2x_release_phy_lock(bp);
8969 return rc;
8970 }
8971
8972 /* called with rtnl_lock */
8973 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8974 {
8975 struct bnx2x *bp = netdev_priv(dev);
8976 struct mii_ioctl_data *mdio = if_mii(ifr);
8977
8978 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
8979 mdio->phy_id, mdio->reg_num, mdio->val_in);
8980
8981 if (!netif_running(dev))
8982 return -EAGAIN;
8983
8984 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
8985 }
8986
8987 #ifdef CONFIG_NET_POLL_CONTROLLER
8988 static void poll_bnx2x(struct net_device *dev)
8989 {
8990 struct bnx2x *bp = netdev_priv(dev);
8991
8992 disable_irq(bp->pdev->irq);
8993 bnx2x_interrupt(bp->pdev->irq, dev);
8994 enable_irq(bp->pdev->irq);
8995 }
8996 #endif
8997
8998 static const struct net_device_ops bnx2x_netdev_ops = {
8999 .ndo_open = bnx2x_open,
9000 .ndo_stop = bnx2x_close,
9001 .ndo_start_xmit = bnx2x_start_xmit,
9002 .ndo_select_queue = bnx2x_select_queue,
9003 .ndo_set_multicast_list = bnx2x_set_rx_mode,
9004 .ndo_set_mac_address = bnx2x_change_mac_addr,
9005 .ndo_validate_addr = eth_validate_addr,
9006 .ndo_do_ioctl = bnx2x_ioctl,
9007 .ndo_change_mtu = bnx2x_change_mtu,
9008 .ndo_tx_timeout = bnx2x_tx_timeout,
9009 #ifdef CONFIG_NET_POLL_CONTROLLER
9010 .ndo_poll_controller = poll_bnx2x,
9011 #endif
9012 };
9013
9014 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
9015 struct net_device *dev)
9016 {
9017 struct bnx2x *bp;
9018 int rc;
9019
9020 SET_NETDEV_DEV(dev, &pdev->dev);
9021 bp = netdev_priv(dev);
9022
9023 bp->dev = dev;
9024 bp->pdev = pdev;
9025 bp->flags = 0;
9026 bp->pf_num = PCI_FUNC(pdev->devfn);
9027
9028 rc = pci_enable_device(pdev);
9029 if (rc) {
9030 dev_err(&bp->pdev->dev,
9031 "Cannot enable PCI device, aborting\n");
9032 goto err_out;
9033 }
9034
9035 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9036 dev_err(&bp->pdev->dev,
9037 "Cannot find PCI device base address, aborting\n");
9038 rc = -ENODEV;
9039 goto err_out_disable;
9040 }
9041
9042 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9043 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
9044 " base address, aborting\n");
9045 rc = -ENODEV;
9046 goto err_out_disable;
9047 }
9048
9049 if (atomic_read(&pdev->enable_cnt) == 1) {
9050 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9051 if (rc) {
9052 dev_err(&bp->pdev->dev,
9053 "Cannot obtain PCI resources, aborting\n");
9054 goto err_out_disable;
9055 }
9056
9057 pci_set_master(pdev);
9058 pci_save_state(pdev);
9059 }
9060
9061 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9062 if (bp->pm_cap == 0) {
9063 dev_err(&bp->pdev->dev,
9064 "Cannot find power management capability, aborting\n");
9065 rc = -EIO;
9066 goto err_out_release;
9067 }
9068
9069 bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9070 if (bp->pcie_cap == 0) {
9071 dev_err(&bp->pdev->dev,
9072 "Cannot find PCI Express capability, aborting\n");
9073 rc = -EIO;
9074 goto err_out_release;
9075 }
9076
9077 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) == 0) {
9078 bp->flags |= USING_DAC_FLAG;
9079 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)) != 0) {
9080 dev_err(&bp->pdev->dev, "dma_set_coherent_mask"
9081 " failed, aborting\n");
9082 rc = -EIO;
9083 goto err_out_release;
9084 }
9085
9086 } else if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
9087 dev_err(&bp->pdev->dev,
9088 "System does not support DMA, aborting\n");
9089 rc = -EIO;
9090 goto err_out_release;
9091 }
9092
9093 dev->mem_start = pci_resource_start(pdev, 0);
9094 dev->base_addr = dev->mem_start;
9095 dev->mem_end = pci_resource_end(pdev, 0);
9096
9097 dev->irq = pdev->irq;
9098
9099 bp->regview = pci_ioremap_bar(pdev, 0);
9100 if (!bp->regview) {
9101 dev_err(&bp->pdev->dev,
9102 "Cannot map register space, aborting\n");
9103 rc = -ENOMEM;
9104 goto err_out_release;
9105 }
9106
9107 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
9108 min_t(u64, BNX2X_DB_SIZE(bp),
9109 pci_resource_len(pdev, 2)));
9110 if (!bp->doorbells) {
9111 dev_err(&bp->pdev->dev,
9112 "Cannot map doorbell space, aborting\n");
9113 rc = -ENOMEM;
9114 goto err_out_unmap;
9115 }
9116
9117 bnx2x_set_power_state(bp, PCI_D0);
9118
9119 /* clean indirect addresses */
9120 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
9121 PCICFG_VENDOR_ID_OFFSET);
9122 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
9123 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
9124 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
9125 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
9126
9127 /* Reset the load counter */
9128 bnx2x_clear_load_cnt(bp);
9129
9130 dev->watchdog_timeo = TX_TIMEOUT;
9131
9132 dev->netdev_ops = &bnx2x_netdev_ops;
9133 bnx2x_set_ethtool_ops(dev);
9134 dev->features |= NETIF_F_SG;
9135 dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
9136 if (bp->flags & USING_DAC_FLAG)
9137 dev->features |= NETIF_F_HIGHDMA;
9138 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
9139 dev->features |= NETIF_F_TSO6;
9140 dev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
9141
9142 dev->vlan_features |= NETIF_F_SG;
9143 dev->vlan_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
9144 if (bp->flags & USING_DAC_FLAG)
9145 dev->vlan_features |= NETIF_F_HIGHDMA;
9146 dev->vlan_features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
9147 dev->vlan_features |= NETIF_F_TSO6;
9148
9149 /* get_port_hwinfo() will set prtad and mmds properly */
9150 bp->mdio.prtad = MDIO_PRTAD_NONE;
9151 bp->mdio.mmds = 0;
9152 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
9153 bp->mdio.dev = dev;
9154 bp->mdio.mdio_read = bnx2x_mdio_read;
9155 bp->mdio.mdio_write = bnx2x_mdio_write;
9156
9157 return 0;
9158
9159 err_out_unmap:
9160 if (bp->regview) {
9161 iounmap(bp->regview);
9162 bp->regview = NULL;
9163 }
9164 if (bp->doorbells) {
9165 iounmap(bp->doorbells);
9166 bp->doorbells = NULL;
9167 }
9168
9169 err_out_release:
9170 if (atomic_read(&pdev->enable_cnt) == 1)
9171 pci_release_regions(pdev);
9172
9173 err_out_disable:
9174 pci_disable_device(pdev);
9175 pci_set_drvdata(pdev, NULL);
9176
9177 err_out:
9178 return rc;
9179 }
9180
9181 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
9182 int *width, int *speed)
9183 {
9184 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
9185
9186 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
9187
9188 /* return value of 1=2.5GHz 2=5GHz */
9189 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
9190 }
9191
9192 static int bnx2x_check_firmware(struct bnx2x *bp)
9193 {
9194 const struct firmware *firmware = bp->firmware;
9195 struct bnx2x_fw_file_hdr *fw_hdr;
9196 struct bnx2x_fw_file_section *sections;
9197 u32 offset, len, num_ops;
9198 u16 *ops_offsets;
9199 int i;
9200 const u8 *fw_ver;
9201
9202 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
9203 return -EINVAL;
9204
9205 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
9206 sections = (struct bnx2x_fw_file_section *)fw_hdr;
9207
9208 /* Make sure none of the offsets and sizes make us read beyond
9209 * the end of the firmware data */
9210 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
9211 offset = be32_to_cpu(sections[i].offset);
9212 len = be32_to_cpu(sections[i].len);
9213 if (offset + len > firmware->size) {
9214 dev_err(&bp->pdev->dev,
9215 "Section %d length is out of bounds\n", i);
9216 return -EINVAL;
9217 }
9218 }
9219
9220 /* Likewise for the init_ops offsets */
9221 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
9222 ops_offsets = (u16 *)(firmware->data + offset);
9223 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
9224
9225 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
9226 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
9227 dev_err(&bp->pdev->dev,
9228 "Section offset %d is out of bounds\n", i);
9229 return -EINVAL;
9230 }
9231 }
9232
9233 /* Check FW version */
9234 offset = be32_to_cpu(fw_hdr->fw_version.offset);
9235 fw_ver = firmware->data + offset;
9236 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
9237 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
9238 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
9239 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
9240 dev_err(&bp->pdev->dev,
9241 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
9242 fw_ver[0], fw_ver[1], fw_ver[2],
9243 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
9244 BCM_5710_FW_MINOR_VERSION,
9245 BCM_5710_FW_REVISION_VERSION,
9246 BCM_5710_FW_ENGINEERING_VERSION);
9247 return -EINVAL;
9248 }
9249
9250 return 0;
9251 }
9252
9253 static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
9254 {
9255 const __be32 *source = (const __be32 *)_source;
9256 u32 *target = (u32 *)_target;
9257 u32 i;
9258
9259 for (i = 0; i < n/4; i++)
9260 target[i] = be32_to_cpu(source[i]);
9261 }
9262
9263 /*
9264 Ops array is stored in the following format:
9265 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
9266 */
9267 static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
9268 {
9269 const __be32 *source = (const __be32 *)_source;
9270 struct raw_op *target = (struct raw_op *)_target;
9271 u32 i, j, tmp;
9272
9273 for (i = 0, j = 0; i < n/8; i++, j += 2) {
9274 tmp = be32_to_cpu(source[j]);
9275 target[i].op = (tmp >> 24) & 0xff;
9276 target[i].offset = tmp & 0xffffff;
9277 target[i].raw_data = be32_to_cpu(source[j + 1]);
9278 }
9279 }
9280
9281 /**
9282 * IRO array is stored in the following format:
9283 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
9284 */
9285 static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
9286 {
9287 const __be32 *source = (const __be32 *)_source;
9288 struct iro *target = (struct iro *)_target;
9289 u32 i, j, tmp;
9290
9291 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
9292 target[i].base = be32_to_cpu(source[j]);
9293 j++;
9294 tmp = be32_to_cpu(source[j]);
9295 target[i].m1 = (tmp >> 16) & 0xffff;
9296 target[i].m2 = tmp & 0xffff;
9297 j++;
9298 tmp = be32_to_cpu(source[j]);
9299 target[i].m3 = (tmp >> 16) & 0xffff;
9300 target[i].size = tmp & 0xffff;
9301 j++;
9302 }
9303 }
9304
9305 static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
9306 {
9307 const __be16 *source = (const __be16 *)_source;
9308 u16 *target = (u16 *)_target;
9309 u32 i;
9310
9311 for (i = 0; i < n/2; i++)
9312 target[i] = be16_to_cpu(source[i]);
9313 }
9314
9315 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
9316 do { \
9317 u32 len = be32_to_cpu(fw_hdr->arr.len); \
9318 bp->arr = kmalloc(len, GFP_KERNEL); \
9319 if (!bp->arr) { \
9320 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
9321 goto lbl; \
9322 } \
9323 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
9324 (u8 *)bp->arr, len); \
9325 } while (0)
9326
9327 int bnx2x_init_firmware(struct bnx2x *bp)
9328 {
9329 const char *fw_file_name;
9330 struct bnx2x_fw_file_hdr *fw_hdr;
9331 int rc;
9332
9333 if (CHIP_IS_E1(bp))
9334 fw_file_name = FW_FILE_NAME_E1;
9335 else if (CHIP_IS_E1H(bp))
9336 fw_file_name = FW_FILE_NAME_E1H;
9337 else if (CHIP_IS_E2(bp))
9338 fw_file_name = FW_FILE_NAME_E2;
9339 else {
9340 BNX2X_ERR("Unsupported chip revision\n");
9341 return -EINVAL;
9342 }
9343
9344 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
9345
9346 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
9347 if (rc) {
9348 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
9349 goto request_firmware_exit;
9350 }
9351
9352 rc = bnx2x_check_firmware(bp);
9353 if (rc) {
9354 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
9355 goto request_firmware_exit;
9356 }
9357
9358 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
9359
9360 /* Initialize the pointers to the init arrays */
9361 /* Blob */
9362 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
9363
9364 /* Opcodes */
9365 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
9366
9367 /* Offsets */
9368 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
9369 be16_to_cpu_n);
9370
9371 /* STORMs firmware */
9372 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9373 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
9374 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
9375 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
9376 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9377 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
9378 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
9379 be32_to_cpu(fw_hdr->usem_pram_data.offset);
9380 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9381 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
9382 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
9383 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
9384 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9385 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
9386 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
9387 be32_to_cpu(fw_hdr->csem_pram_data.offset);
9388 /* IRO */
9389 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
9390
9391 return 0;
9392
9393 iro_alloc_err:
9394 kfree(bp->init_ops_offsets);
9395 init_offsets_alloc_err:
9396 kfree(bp->init_ops);
9397 init_ops_alloc_err:
9398 kfree(bp->init_data);
9399 request_firmware_exit:
9400 release_firmware(bp->firmware);
9401
9402 return rc;
9403 }
9404
9405 static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp, int l2_cid_count)
9406 {
9407 int cid_count = L2_FP_COUNT(l2_cid_count);
9408
9409 #ifdef BCM_CNIC
9410 cid_count += CNIC_CID_MAX;
9411 #endif
9412 return roundup(cid_count, QM_CID_ROUND);
9413 }
9414
9415 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
9416 const struct pci_device_id *ent)
9417 {
9418 struct net_device *dev = NULL;
9419 struct bnx2x *bp;
9420 int pcie_width, pcie_speed;
9421 int rc, cid_count;
9422
9423 switch (ent->driver_data) {
9424 case BCM57710:
9425 case BCM57711:
9426 case BCM57711E:
9427 cid_count = FP_SB_MAX_E1x;
9428 break;
9429
9430 case BCM57712:
9431 case BCM57712E:
9432 cid_count = FP_SB_MAX_E2;
9433 break;
9434
9435 default:
9436 pr_err("Unknown board_type (%ld), aborting\n",
9437 ent->driver_data);
9438 return -ENODEV;
9439 }
9440
9441 cid_count += NONE_ETH_CONTEXT_USE + CNIC_CONTEXT_USE;
9442
9443 /* dev zeroed in init_etherdev */
9444 dev = alloc_etherdev_mq(sizeof(*bp), cid_count);
9445 if (!dev) {
9446 dev_err(&pdev->dev, "Cannot allocate net device\n");
9447 return -ENOMEM;
9448 }
9449
9450 bp = netdev_priv(dev);
9451 bp->msg_enable = debug;
9452
9453 pci_set_drvdata(pdev, dev);
9454
9455 bp->l2_cid_count = cid_count;
9456
9457 rc = bnx2x_init_dev(pdev, dev);
9458 if (rc < 0) {
9459 free_netdev(dev);
9460 return rc;
9461 }
9462
9463 rc = bnx2x_init_bp(bp);
9464 if (rc)
9465 goto init_one_exit;
9466
9467 /* calc qm_cid_count */
9468 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp, cid_count);
9469
9470 #ifdef BCM_CNIC
9471 /* disable FCOE L2 queue for E1x*/
9472 if (CHIP_IS_E1x(bp))
9473 bp->flags |= NO_FCOE_FLAG;
9474
9475 #endif
9476
9477 /* Configure interupt mode: try to enable MSI-X/MSI if
9478 * needed, set bp->num_queues appropriately.
9479 */
9480 bnx2x_set_int_mode(bp);
9481
9482 /* Add all NAPI objects */
9483 bnx2x_add_all_napi(bp);
9484
9485 rc = register_netdev(dev);
9486 if (rc) {
9487 dev_err(&pdev->dev, "Cannot register net device\n");
9488 goto init_one_exit;
9489 }
9490
9491 #ifdef BCM_CNIC
9492 if (!NO_FCOE(bp)) {
9493 /* Add storage MAC address */
9494 rtnl_lock();
9495 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9496 rtnl_unlock();
9497 }
9498 #endif
9499
9500 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
9501
9502 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
9503 " IRQ %d, ", board_info[ent->driver_data].name,
9504 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
9505 pcie_width,
9506 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
9507 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
9508 "5GHz (Gen2)" : "2.5GHz",
9509 dev->base_addr, bp->pdev->irq);
9510 pr_cont("node addr %pM\n", dev->dev_addr);
9511
9512 return 0;
9513
9514 init_one_exit:
9515 if (bp->regview)
9516 iounmap(bp->regview);
9517
9518 if (bp->doorbells)
9519 iounmap(bp->doorbells);
9520
9521 free_netdev(dev);
9522
9523 if (atomic_read(&pdev->enable_cnt) == 1)
9524 pci_release_regions(pdev);
9525
9526 pci_disable_device(pdev);
9527 pci_set_drvdata(pdev, NULL);
9528
9529 return rc;
9530 }
9531
9532 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
9533 {
9534 struct net_device *dev = pci_get_drvdata(pdev);
9535 struct bnx2x *bp;
9536
9537 if (!dev) {
9538 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
9539 return;
9540 }
9541 bp = netdev_priv(dev);
9542
9543 #ifdef BCM_CNIC
9544 /* Delete storage MAC address */
9545 if (!NO_FCOE(bp)) {
9546 rtnl_lock();
9547 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9548 rtnl_unlock();
9549 }
9550 #endif
9551
9552 unregister_netdev(dev);
9553
9554 /* Delete all NAPI objects */
9555 bnx2x_del_all_napi(bp);
9556
9557 /* Disable MSI/MSI-X */
9558 bnx2x_disable_msi(bp);
9559
9560 /* Make sure RESET task is not scheduled before continuing */
9561 cancel_delayed_work_sync(&bp->reset_task);
9562
9563 if (bp->regview)
9564 iounmap(bp->regview);
9565
9566 if (bp->doorbells)
9567 iounmap(bp->doorbells);
9568
9569 bnx2x_free_mem_bp(bp);
9570
9571 free_netdev(dev);
9572
9573 if (atomic_read(&pdev->enable_cnt) == 1)
9574 pci_release_regions(pdev);
9575
9576 pci_disable_device(pdev);
9577 pci_set_drvdata(pdev, NULL);
9578 }
9579
9580 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
9581 {
9582 int i;
9583
9584 bp->state = BNX2X_STATE_ERROR;
9585
9586 bp->rx_mode = BNX2X_RX_MODE_NONE;
9587
9588 bnx2x_netif_stop(bp, 0);
9589 netif_carrier_off(bp->dev);
9590
9591 del_timer_sync(&bp->timer);
9592 bp->stats_state = STATS_STATE_DISABLED;
9593 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
9594
9595 /* Release IRQs */
9596 bnx2x_free_irq(bp);
9597
9598 /* Free SKBs, SGEs, TPA pool and driver internals */
9599 bnx2x_free_skbs(bp);
9600
9601 for_each_rx_queue(bp, i)
9602 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
9603
9604 bnx2x_free_mem(bp);
9605
9606 bp->state = BNX2X_STATE_CLOSED;
9607
9608 return 0;
9609 }
9610
9611 static void bnx2x_eeh_recover(struct bnx2x *bp)
9612 {
9613 u32 val;
9614
9615 mutex_init(&bp->port.phy_mutex);
9616
9617 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9618 bp->link_params.shmem_base = bp->common.shmem_base;
9619 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
9620
9621 if (!bp->common.shmem_base ||
9622 (bp->common.shmem_base < 0xA0000) ||
9623 (bp->common.shmem_base >= 0xC0000)) {
9624 BNX2X_DEV_INFO("MCP not active\n");
9625 bp->flags |= NO_MCP_FLAG;
9626 return;
9627 }
9628
9629 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9630 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9631 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9632 BNX2X_ERR("BAD MCP validity signature\n");
9633
9634 if (!BP_NOMCP(bp)) {
9635 bp->fw_seq =
9636 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9637 DRV_MSG_SEQ_NUMBER_MASK);
9638 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9639 }
9640 }
9641
9642 /**
9643 * bnx2x_io_error_detected - called when PCI error is detected
9644 * @pdev: Pointer to PCI device
9645 * @state: The current pci connection state
9646 *
9647 * This function is called after a PCI bus error affecting
9648 * this device has been detected.
9649 */
9650 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
9651 pci_channel_state_t state)
9652 {
9653 struct net_device *dev = pci_get_drvdata(pdev);
9654 struct bnx2x *bp = netdev_priv(dev);
9655
9656 rtnl_lock();
9657
9658 netif_device_detach(dev);
9659
9660 if (state == pci_channel_io_perm_failure) {
9661 rtnl_unlock();
9662 return PCI_ERS_RESULT_DISCONNECT;
9663 }
9664
9665 if (netif_running(dev))
9666 bnx2x_eeh_nic_unload(bp);
9667
9668 pci_disable_device(pdev);
9669
9670 rtnl_unlock();
9671
9672 /* Request a slot reset */
9673 return PCI_ERS_RESULT_NEED_RESET;
9674 }
9675
9676 /**
9677 * bnx2x_io_slot_reset - called after the PCI bus has been reset
9678 * @pdev: Pointer to PCI device
9679 *
9680 * Restart the card from scratch, as if from a cold-boot.
9681 */
9682 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
9683 {
9684 struct net_device *dev = pci_get_drvdata(pdev);
9685 struct bnx2x *bp = netdev_priv(dev);
9686
9687 rtnl_lock();
9688
9689 if (pci_enable_device(pdev)) {
9690 dev_err(&pdev->dev,
9691 "Cannot re-enable PCI device after reset\n");
9692 rtnl_unlock();
9693 return PCI_ERS_RESULT_DISCONNECT;
9694 }
9695
9696 pci_set_master(pdev);
9697 pci_restore_state(pdev);
9698
9699 if (netif_running(dev))
9700 bnx2x_set_power_state(bp, PCI_D0);
9701
9702 rtnl_unlock();
9703
9704 return PCI_ERS_RESULT_RECOVERED;
9705 }
9706
9707 /**
9708 * bnx2x_io_resume - called when traffic can start flowing again
9709 * @pdev: Pointer to PCI device
9710 *
9711 * This callback is called when the error recovery driver tells us that
9712 * its OK to resume normal operation.
9713 */
9714 static void bnx2x_io_resume(struct pci_dev *pdev)
9715 {
9716 struct net_device *dev = pci_get_drvdata(pdev);
9717 struct bnx2x *bp = netdev_priv(dev);
9718
9719 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
9720 printk(KERN_ERR "Handling parity error recovery. "
9721 "Try again later\n");
9722 return;
9723 }
9724
9725 rtnl_lock();
9726
9727 bnx2x_eeh_recover(bp);
9728
9729 if (netif_running(dev))
9730 bnx2x_nic_load(bp, LOAD_NORMAL);
9731
9732 netif_device_attach(dev);
9733
9734 rtnl_unlock();
9735 }
9736
9737 static struct pci_error_handlers bnx2x_err_handler = {
9738 .error_detected = bnx2x_io_error_detected,
9739 .slot_reset = bnx2x_io_slot_reset,
9740 .resume = bnx2x_io_resume,
9741 };
9742
9743 static struct pci_driver bnx2x_pci_driver = {
9744 .name = DRV_MODULE_NAME,
9745 .id_table = bnx2x_pci_tbl,
9746 .probe = bnx2x_init_one,
9747 .remove = __devexit_p(bnx2x_remove_one),
9748 .suspend = bnx2x_suspend,
9749 .resume = bnx2x_resume,
9750 .err_handler = &bnx2x_err_handler,
9751 };
9752
9753 static int __init bnx2x_init(void)
9754 {
9755 int ret;
9756
9757 pr_info("%s", version);
9758
9759 bnx2x_wq = create_singlethread_workqueue("bnx2x");
9760 if (bnx2x_wq == NULL) {
9761 pr_err("Cannot create workqueue\n");
9762 return -ENOMEM;
9763 }
9764
9765 ret = pci_register_driver(&bnx2x_pci_driver);
9766 if (ret) {
9767 pr_err("Cannot register driver\n");
9768 destroy_workqueue(bnx2x_wq);
9769 }
9770 return ret;
9771 }
9772
9773 static void __exit bnx2x_cleanup(void)
9774 {
9775 pci_unregister_driver(&bnx2x_pci_driver);
9776
9777 destroy_workqueue(bnx2x_wq);
9778 }
9779
9780 module_init(bnx2x_init);
9781 module_exit(bnx2x_cleanup);
9782
9783 #ifdef BCM_CNIC
9784
9785 /* count denotes the number of new completions we have seen */
9786 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
9787 {
9788 struct eth_spe *spe;
9789
9790 #ifdef BNX2X_STOP_ON_ERROR
9791 if (unlikely(bp->panic))
9792 return;
9793 #endif
9794
9795 spin_lock_bh(&bp->spq_lock);
9796 BUG_ON(bp->cnic_spq_pending < count);
9797 bp->cnic_spq_pending -= count;
9798
9799
9800 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
9801 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
9802 & SPE_HDR_CONN_TYPE) >>
9803 SPE_HDR_CONN_TYPE_SHIFT;
9804
9805 /* Set validation for iSCSI L2 client before sending SETUP
9806 * ramrod
9807 */
9808 if (type == ETH_CONNECTION_TYPE) {
9809 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->
9810 hdr.conn_and_cmd_data) >>
9811 SPE_HDR_CMD_ID_SHIFT) & 0xff;
9812
9813 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
9814 bnx2x_set_ctx_validation(&bp->context.
9815 vcxt[BNX2X_ISCSI_ETH_CID].eth,
9816 HW_CID(bp, BNX2X_ISCSI_ETH_CID));
9817 }
9818
9819 /* There may be not more than 8 L2 and COMMON SPEs and not more
9820 * than 8 L5 SPEs in the air.
9821 */
9822 if ((type == NONE_CONNECTION_TYPE) ||
9823 (type == ETH_CONNECTION_TYPE)) {
9824 if (!atomic_read(&bp->spq_left))
9825 break;
9826 else
9827 atomic_dec(&bp->spq_left);
9828 } else if ((type == ISCSI_CONNECTION_TYPE) ||
9829 (type == FCOE_CONNECTION_TYPE)) {
9830 if (bp->cnic_spq_pending >=
9831 bp->cnic_eth_dev.max_kwqe_pending)
9832 break;
9833 else
9834 bp->cnic_spq_pending++;
9835 } else {
9836 BNX2X_ERR("Unknown SPE type: %d\n", type);
9837 bnx2x_panic();
9838 break;
9839 }
9840
9841 spe = bnx2x_sp_get_next(bp);
9842 *spe = *bp->cnic_kwq_cons;
9843
9844 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
9845 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
9846
9847 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
9848 bp->cnic_kwq_cons = bp->cnic_kwq;
9849 else
9850 bp->cnic_kwq_cons++;
9851 }
9852 bnx2x_sp_prod_update(bp);
9853 spin_unlock_bh(&bp->spq_lock);
9854 }
9855
9856 static int bnx2x_cnic_sp_queue(struct net_device *dev,
9857 struct kwqe_16 *kwqes[], u32 count)
9858 {
9859 struct bnx2x *bp = netdev_priv(dev);
9860 int i;
9861
9862 #ifdef BNX2X_STOP_ON_ERROR
9863 if (unlikely(bp->panic))
9864 return -EIO;
9865 #endif
9866
9867 spin_lock_bh(&bp->spq_lock);
9868
9869 for (i = 0; i < count; i++) {
9870 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
9871
9872 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
9873 break;
9874
9875 *bp->cnic_kwq_prod = *spe;
9876
9877 bp->cnic_kwq_pending++;
9878
9879 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
9880 spe->hdr.conn_and_cmd_data, spe->hdr.type,
9881 spe->data.update_data_addr.hi,
9882 spe->data.update_data_addr.lo,
9883 bp->cnic_kwq_pending);
9884
9885 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
9886 bp->cnic_kwq_prod = bp->cnic_kwq;
9887 else
9888 bp->cnic_kwq_prod++;
9889 }
9890
9891 spin_unlock_bh(&bp->spq_lock);
9892
9893 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
9894 bnx2x_cnic_sp_post(bp, 0);
9895
9896 return i;
9897 }
9898
9899 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
9900 {
9901 struct cnic_ops *c_ops;
9902 int rc = 0;
9903
9904 mutex_lock(&bp->cnic_mutex);
9905 c_ops = bp->cnic_ops;
9906 if (c_ops)
9907 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
9908 mutex_unlock(&bp->cnic_mutex);
9909
9910 return rc;
9911 }
9912
9913 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
9914 {
9915 struct cnic_ops *c_ops;
9916 int rc = 0;
9917
9918 rcu_read_lock();
9919 c_ops = rcu_dereference(bp->cnic_ops);
9920 if (c_ops)
9921 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
9922 rcu_read_unlock();
9923
9924 return rc;
9925 }
9926
9927 /*
9928 * for commands that have no data
9929 */
9930 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
9931 {
9932 struct cnic_ctl_info ctl = {0};
9933
9934 ctl.cmd = cmd;
9935
9936 return bnx2x_cnic_ctl_send(bp, &ctl);
9937 }
9938
9939 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid)
9940 {
9941 struct cnic_ctl_info ctl;
9942
9943 /* first we tell CNIC and only then we count this as a completion */
9944 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
9945 ctl.data.comp.cid = cid;
9946
9947 bnx2x_cnic_ctl_send_bh(bp, &ctl);
9948 bnx2x_cnic_sp_post(bp, 0);
9949 }
9950
9951 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
9952 {
9953 struct bnx2x *bp = netdev_priv(dev);
9954 int rc = 0;
9955
9956 switch (ctl->cmd) {
9957 case DRV_CTL_CTXTBL_WR_CMD: {
9958 u32 index = ctl->data.io.offset;
9959 dma_addr_t addr = ctl->data.io.dma_addr;
9960
9961 bnx2x_ilt_wr(bp, index, addr);
9962 break;
9963 }
9964
9965 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
9966 int count = ctl->data.credit.credit_count;
9967
9968 bnx2x_cnic_sp_post(bp, count);
9969 break;
9970 }
9971
9972 /* rtnl_lock is held. */
9973 case DRV_CTL_START_L2_CMD: {
9974 u32 cli = ctl->data.ring.client_id;
9975
9976 /* Clear FCoE FIP and ALL ENODE MACs addresses first */
9977 bnx2x_del_fcoe_eth_macs(bp);
9978
9979 /* Set iSCSI MAC address */
9980 bnx2x_set_iscsi_eth_mac_addr(bp, 1);
9981
9982 mmiowb();
9983 barrier();
9984
9985 /* Start accepting on iSCSI L2 ring. Accept all multicasts
9986 * because it's the only way for UIO Client to accept
9987 * multicasts (in non-promiscuous mode only one Client per
9988 * function will receive multicast packets (leading in our
9989 * case).
9990 */
9991 bnx2x_rxq_set_mac_filters(bp, cli,
9992 BNX2X_ACCEPT_UNICAST |
9993 BNX2X_ACCEPT_BROADCAST |
9994 BNX2X_ACCEPT_ALL_MULTICAST);
9995 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
9996
9997 break;
9998 }
9999
10000 /* rtnl_lock is held. */
10001 case DRV_CTL_STOP_L2_CMD: {
10002 u32 cli = ctl->data.ring.client_id;
10003
10004 /* Stop accepting on iSCSI L2 ring */
10005 bnx2x_rxq_set_mac_filters(bp, cli, BNX2X_ACCEPT_NONE);
10006 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
10007
10008 mmiowb();
10009 barrier();
10010
10011 /* Unset iSCSI L2 MAC */
10012 bnx2x_set_iscsi_eth_mac_addr(bp, 0);
10013 break;
10014 }
10015 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
10016 int count = ctl->data.credit.credit_count;
10017
10018 smp_mb__before_atomic_inc();
10019 atomic_add(count, &bp->spq_left);
10020 smp_mb__after_atomic_inc();
10021 break;
10022 }
10023
10024 default:
10025 BNX2X_ERR("unknown command %x\n", ctl->cmd);
10026 rc = -EINVAL;
10027 }
10028
10029 return rc;
10030 }
10031
10032 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
10033 {
10034 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10035
10036 if (bp->flags & USING_MSIX_FLAG) {
10037 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
10038 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
10039 cp->irq_arr[0].vector = bp->msix_table[1].vector;
10040 } else {
10041 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
10042 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
10043 }
10044 if (CHIP_IS_E2(bp))
10045 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
10046 else
10047 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
10048
10049 cp->irq_arr[0].status_blk_num = CNIC_SB_ID(bp);
10050 cp->irq_arr[0].status_blk_num2 = CNIC_IGU_SB_ID(bp);
10051 cp->irq_arr[1].status_blk = bp->def_status_blk;
10052 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
10053 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
10054
10055 cp->num_irq = 2;
10056 }
10057
10058 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
10059 void *data)
10060 {
10061 struct bnx2x *bp = netdev_priv(dev);
10062 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10063
10064 if (ops == NULL)
10065 return -EINVAL;
10066
10067 if (atomic_read(&bp->intr_sem) != 0)
10068 return -EBUSY;
10069
10070 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
10071 if (!bp->cnic_kwq)
10072 return -ENOMEM;
10073
10074 bp->cnic_kwq_cons = bp->cnic_kwq;
10075 bp->cnic_kwq_prod = bp->cnic_kwq;
10076 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
10077
10078 bp->cnic_spq_pending = 0;
10079 bp->cnic_kwq_pending = 0;
10080
10081 bp->cnic_data = data;
10082
10083 cp->num_irq = 0;
10084 cp->drv_state = CNIC_DRV_STATE_REGD;
10085 cp->iro_arr = bp->iro_arr;
10086
10087 bnx2x_setup_cnic_irq_info(bp);
10088
10089 rcu_assign_pointer(bp->cnic_ops, ops);
10090
10091 return 0;
10092 }
10093
10094 static int bnx2x_unregister_cnic(struct net_device *dev)
10095 {
10096 struct bnx2x *bp = netdev_priv(dev);
10097 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10098
10099 mutex_lock(&bp->cnic_mutex);
10100 cp->drv_state = 0;
10101 rcu_assign_pointer(bp->cnic_ops, NULL);
10102 mutex_unlock(&bp->cnic_mutex);
10103 synchronize_rcu();
10104 kfree(bp->cnic_kwq);
10105 bp->cnic_kwq = NULL;
10106
10107 return 0;
10108 }
10109
10110 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
10111 {
10112 struct bnx2x *bp = netdev_priv(dev);
10113 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10114
10115 cp->drv_owner = THIS_MODULE;
10116 cp->chip_id = CHIP_ID(bp);
10117 cp->pdev = bp->pdev;
10118 cp->io_base = bp->regview;
10119 cp->io_base2 = bp->doorbells;
10120 cp->max_kwqe_pending = 8;
10121 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
10122 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
10123 bnx2x_cid_ilt_lines(bp);
10124 cp->ctx_tbl_len = CNIC_ILT_LINES;
10125 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
10126 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
10127 cp->drv_ctl = bnx2x_drv_ctl;
10128 cp->drv_register_cnic = bnx2x_register_cnic;
10129 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
10130 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
10131 cp->iscsi_l2_client_id = BNX2X_ISCSI_ETH_CL_ID +
10132 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
10133 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
10134
10135 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
10136 "starting cid %d\n",
10137 cp->ctx_blk_size,
10138 cp->ctx_tbl_offset,
10139 cp->ctx_tbl_len,
10140 cp->starting_cid);
10141 return cp;
10142 }
10143 EXPORT_SYMBOL(bnx2x_cnic_probe);
10144
10145 #endif /* BCM_CNIC */
10146
x86 "subsystem" repository