2 * OMAP3 Power Management Routines
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/suspend.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/list.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/clk.h>
30 #include <plat/sram.h>
31 #include <plat/clockdomain.h>
32 #include <plat/powerdomain.h>
33 #include <plat/control.h>
34 #include <plat/serial.h>
35 #include <plat/sdrc.h>
36 #include <plat/prcm.h>
37 #include <plat/gpmc.h>
39 #include <plat/dmtimer.h>
41 #include <asm/tlbflush.h>
44 #include "cm-regbits-34xx.h"
45 #include "prm-regbits-34xx.h"
51 /* Scratchpad offsets */
52 #define OMAP343X_TABLE_ADDRESS_OFFSET 0x31
53 #define OMAP343X_TABLE_VALUE_OFFSET 0x30
54 #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32
58 u32 wakeup_timer_seconds
;
61 struct powerdomain
*pwrdm
;
66 struct list_head node
;
69 static LIST_HEAD(pwrst_list
);
71 static void (*_omap_sram_idle
)(u32
*addr
, int save_state
);
73 static int (*_omap_save_secure_sram
)(u32
*addr
);
75 static struct powerdomain
*mpu_pwrdm
, *neon_pwrdm
;
76 static struct powerdomain
*core_pwrdm
, *per_pwrdm
;
77 static struct powerdomain
*cam_pwrdm
;
79 static inline void omap3_per_save_context(void)
81 omap_gpio_save_context();
84 static inline void omap3_per_restore_context(void)
86 omap_gpio_restore_context();
89 static void omap3_enable_io_chain(void)
93 if (omap_rev() >= OMAP3430_REV_ES3_1
) {
94 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN
, WKUP_MOD
, PM_WKEN
);
95 /* Do a readback to assure write has been done */
96 prm_read_mod_reg(WKUP_MOD
, PM_WKEN
);
98 while (!(prm_read_mod_reg(WKUP_MOD
, PM_WKST
) &
99 OMAP3430_ST_IO_CHAIN
)) {
101 if (timeout
> 1000) {
102 printk(KERN_ERR
"Wake up daisy chain "
103 "activation failed.\n");
106 prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN
,
112 static void omap3_disable_io_chain(void)
114 if (omap_rev() >= OMAP3430_REV_ES3_1
)
115 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN
, WKUP_MOD
, PM_WKEN
);
118 static void omap3_core_save_context(void)
120 u32 control_padconf_off
;
122 /* Save the padconf registers */
123 control_padconf_off
= omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF
);
124 control_padconf_off
|= START_PADCONF_SAVE
;
125 omap_ctrl_writel(control_padconf_off
, OMAP343X_CONTROL_PADCONF_OFF
);
126 /* wait for the save to complete */
127 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS
)
128 & PADCONF_SAVE_DONE
))
130 /* Save the Interrupt controller context */
131 omap_intc_save_context();
132 /* Save the GPMC context */
133 omap3_gpmc_save_context();
134 /* Save the system control module context, padconf already save above*/
135 omap3_control_save_context();
136 omap_dma_global_context_save();
139 static void omap3_core_restore_context(void)
141 /* Restore the control module context, padconf restored by h/w */
142 omap3_control_restore_context();
143 /* Restore the GPMC context */
144 omap3_gpmc_restore_context();
145 /* Restore the interrupt controller context */
146 omap_intc_restore_context();
147 omap_dma_global_context_restore();
151 * FIXME: This function should be called before entering off-mode after
152 * OMAP3 secure services have been accessed. Currently it is only called
153 * once during boot sequence, but this works as we are not using secure
156 static void omap3_save_secure_ram_context(u32 target_mpu_state
)
160 if (omap_type() != OMAP2_DEVICE_TYPE_GP
) {
162 * MPU next state must be set to POWER_ON temporarily,
163 * otherwise the WFI executed inside the ROM code
164 * will hang the system.
166 pwrdm_set_next_pwrst(mpu_pwrdm
, PWRDM_POWER_ON
);
167 ret
= _omap_save_secure_sram((u32
*)
168 __pa(omap3_secure_ram_storage
));
169 pwrdm_set_next_pwrst(mpu_pwrdm
, target_mpu_state
);
170 /* Following is for error tracking, it should not happen */
172 printk(KERN_ERR
"save_secure_sram() returns %08x\n",
181 * PRCM Interrupt Handler Helper Function
183 * The purpose of this function is to clear any wake-up events latched
184 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
185 * may occur whilst attempting to clear a PM_WKST_x register and thus
186 * set another bit in this register. A while loop is used to ensure
187 * that any peripheral wake-up events occurring while attempting to
188 * clear the PM_WKST_x are detected and cleared.
190 static int prcm_clear_mod_irqs(s16 module
, u8 regs
)
192 u32 wkst
, fclk
, iclk
, clken
;
193 u16 wkst_off
= (regs
== 3) ? OMAP3430ES2_PM_WKST3
: PM_WKST1
;
194 u16 fclk_off
= (regs
== 3) ? OMAP3430ES2_CM_FCLKEN3
: CM_FCLKEN1
;
195 u16 iclk_off
= (regs
== 3) ? CM_ICLKEN3
: CM_ICLKEN1
;
196 u16 grpsel_off
= (regs
== 3) ?
197 OMAP3430ES2_PM_MPUGRPSEL3
: OMAP3430_PM_MPUGRPSEL
;
200 wkst
= prm_read_mod_reg(module
, wkst_off
);
201 wkst
&= prm_read_mod_reg(module
, grpsel_off
);
203 iclk
= cm_read_mod_reg(module
, iclk_off
);
204 fclk
= cm_read_mod_reg(module
, fclk_off
);
207 cm_set_mod_reg_bits(clken
, module
, iclk_off
);
209 * For USBHOST, we don't know whether HOST1 or
210 * HOST2 woke us up, so enable both f-clocks
212 if (module
== OMAP3430ES2_USBHOST_MOD
)
213 clken
|= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT
;
214 cm_set_mod_reg_bits(clken
, module
, fclk_off
);
215 prm_write_mod_reg(wkst
, module
, wkst_off
);
216 wkst
= prm_read_mod_reg(module
, wkst_off
);
219 cm_write_mod_reg(iclk
, module
, iclk_off
);
220 cm_write_mod_reg(fclk
, module
, fclk_off
);
226 static int _prcm_int_handle_wakeup(void)
230 c
= prcm_clear_mod_irqs(WKUP_MOD
, 1);
231 c
+= prcm_clear_mod_irqs(CORE_MOD
, 1);
232 c
+= prcm_clear_mod_irqs(OMAP3430_PER_MOD
, 1);
233 if (omap_rev() > OMAP3430_REV_ES1_0
) {
234 c
+= prcm_clear_mod_irqs(CORE_MOD
, 3);
235 c
+= prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD
, 1);
242 * PRCM Interrupt Handler
244 * The PRM_IRQSTATUS_MPU register indicates if there are any pending
245 * interrupts from the PRCM for the MPU. These bits must be cleared in
246 * order to clear the PRCM interrupt. The PRCM interrupt handler is
247 * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
248 * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
249 * register indicates that a wake-up event is pending for the MPU and
250 * this bit can only be cleared if the all the wake-up events latched
251 * in the various PM_WKST_x registers have been cleared. The interrupt
252 * handler is implemented using a do-while loop so that if a wake-up
253 * event occurred during the processing of the prcm interrupt handler
254 * (setting a bit in the corresponding PM_WKST_x register and thus
255 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
256 * this would be handled.
258 static irqreturn_t
prcm_interrupt_handler (int irq
, void *dev_id
)
264 irqstatus_mpu
= prm_read_mod_reg(OCP_MOD
,
265 OMAP3_PRM_IRQSTATUS_MPU_OFFSET
);
267 if (irqstatus_mpu
& (OMAP3430_WKUP_ST
| OMAP3430_IO_ST
)) {
268 c
= _prcm_int_handle_wakeup();
271 * Is the MPU PRCM interrupt handler racing with the
272 * IVA2 PRCM interrupt handler ?
274 WARN(c
== 0, "prcm: WARNING: PRCM indicated MPU wakeup "
275 "but no wakeup sources are marked\n");
277 /* XXX we need to expand our PRCM interrupt handler */
278 WARN(1, "prcm: WARNING: PRCM interrupt received, but "
279 "no code to handle it (%08x)\n", irqstatus_mpu
);
282 prm_write_mod_reg(irqstatus_mpu
, OCP_MOD
,
283 OMAP3_PRM_IRQSTATUS_MPU_OFFSET
);
285 } while (prm_read_mod_reg(OCP_MOD
, OMAP3_PRM_IRQSTATUS_MPU_OFFSET
));
290 static void restore_control_register(u32 val
)
292 __asm__
__volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val
));
295 /* Function to restore the table entry that was modified for enabling MMU */
296 static void restore_table_entry(void)
298 u32
*scratchpad_address
;
299 u32 previous_value
, control_reg_value
;
302 scratchpad_address
= OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD
);
304 /* Get address of entry that was modified */
305 address
= (u32
*)__raw_readl(scratchpad_address
+
306 OMAP343X_TABLE_ADDRESS_OFFSET
);
307 /* Get the previous value which needs to be restored */
308 previous_value
= __raw_readl(scratchpad_address
+
309 OMAP343X_TABLE_VALUE_OFFSET
);
310 address
= __va(address
);
311 *address
= previous_value
;
313 control_reg_value
= __raw_readl(scratchpad_address
314 + OMAP343X_CONTROL_REG_VALUE_OFFSET
);
315 /* This will enable caches and prediction */
316 restore_control_register(control_reg_value
);
319 void omap_sram_idle(void)
321 /* Variable to tell what needs to be saved and restored
322 * in omap_sram_idle*/
323 /* save_state = 0 => Nothing to save and restored */
324 /* save_state = 1 => Only L1 and logic lost */
325 /* save_state = 2 => Only L2 lost */
326 /* save_state = 3 => L1, L2 and logic lost */
328 int mpu_next_state
= PWRDM_POWER_ON
;
329 int per_next_state
= PWRDM_POWER_ON
;
330 int core_next_state
= PWRDM_POWER_ON
;
331 int core_prev_state
, per_prev_state
;
333 int per_state_modified
= 0;
335 if (!_omap_sram_idle
)
338 pwrdm_clear_all_prev_pwrst(mpu_pwrdm
);
339 pwrdm_clear_all_prev_pwrst(neon_pwrdm
);
340 pwrdm_clear_all_prev_pwrst(core_pwrdm
);
341 pwrdm_clear_all_prev_pwrst(per_pwrdm
);
343 mpu_next_state
= pwrdm_read_next_pwrst(mpu_pwrdm
);
344 switch (mpu_next_state
) {
346 case PWRDM_POWER_RET
:
347 /* No need to save context */
350 case PWRDM_POWER_OFF
:
355 printk(KERN_ERR
"Invalid mpu state in sram_idle\n");
358 pwrdm_pre_transition();
361 if (pwrdm_read_pwrst(neon_pwrdm
) == PWRDM_POWER_ON
)
362 pwrdm_set_next_pwrst(neon_pwrdm
, mpu_next_state
);
365 per_next_state
= pwrdm_read_next_pwrst(per_pwrdm
);
366 core_next_state
= pwrdm_read_next_pwrst(core_pwrdm
);
367 if (per_next_state
< PWRDM_POWER_ON
) {
368 omap_uart_prepare_idle(2);
369 omap2_gpio_prepare_for_retention();
370 if (per_next_state
== PWRDM_POWER_OFF
) {
371 if (core_next_state
== PWRDM_POWER_ON
) {
372 per_next_state
= PWRDM_POWER_RET
;
373 pwrdm_set_next_pwrst(per_pwrdm
, per_next_state
);
374 per_state_modified
= 1;
376 omap3_per_save_context();
380 if (pwrdm_read_pwrst(cam_pwrdm
) == PWRDM_POWER_ON
)
381 omap2_clkdm_deny_idle(mpu_pwrdm
->pwrdm_clkdms
[0]);
384 if (core_next_state
< PWRDM_POWER_ON
) {
385 omap_uart_prepare_idle(0);
386 omap_uart_prepare_idle(1);
387 if (core_next_state
== PWRDM_POWER_OFF
) {
388 omap3_core_save_context();
389 omap3_prcm_save_context();
391 /* Enable IO-PAD and IO-CHAIN wakeups */
392 prm_set_mod_reg_bits(OMAP3430_EN_IO
, WKUP_MOD
, PM_WKEN
);
393 omap3_enable_io_chain();
397 * On EMU/HS devices ROM code restores a SRDC value
398 * from scratchpad which has automatic self refresh on timeout
399 * of AUTO_CNT = 1 enabled. This takes care of errata 1.142.
400 * Hence store/restore the SDRC_POWER register here.
402 if (omap_rev() >= OMAP3430_REV_ES3_0
&&
403 omap_type() != OMAP2_DEVICE_TYPE_GP
&&
404 core_next_state
== PWRDM_POWER_OFF
)
405 sdrc_pwr
= sdrc_read_reg(SDRC_POWER
);
408 * omap3_arm_context is the location where ARM registers
409 * get saved. The restore path then reads from this
410 * location and restores them back.
412 _omap_sram_idle(omap3_arm_context
, save_state
);
415 /* Restore normal SDRC POWER settings */
416 if (omap_rev() >= OMAP3430_REV_ES3_0
&&
417 omap_type() != OMAP2_DEVICE_TYPE_GP
&&
418 core_next_state
== PWRDM_POWER_OFF
)
419 sdrc_write_reg(sdrc_pwr
, SDRC_POWER
);
421 /* Restore table entry modified during MMU restoration */
422 if (pwrdm_read_prev_pwrst(mpu_pwrdm
) == PWRDM_POWER_OFF
)
423 restore_table_entry();
426 if (core_next_state
< PWRDM_POWER_ON
) {
427 core_prev_state
= pwrdm_read_prev_pwrst(core_pwrdm
);
428 if (core_prev_state
== PWRDM_POWER_OFF
) {
429 omap3_core_restore_context();
430 omap3_prcm_restore_context();
431 omap3_sram_restore_context();
432 omap2_sms_restore_context();
434 omap_uart_resume_idle(0);
435 omap_uart_resume_idle(1);
436 if (core_next_state
== PWRDM_POWER_OFF
)
437 prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF
,
439 OMAP3_PRM_VOLTCTRL_OFFSET
);
443 if (per_next_state
< PWRDM_POWER_ON
) {
444 per_prev_state
= pwrdm_read_prev_pwrst(per_pwrdm
);
445 if (per_prev_state
== PWRDM_POWER_OFF
)
446 omap3_per_restore_context();
447 omap2_gpio_resume_after_retention();
448 omap_uart_resume_idle(2);
449 if (per_state_modified
)
450 pwrdm_set_next_pwrst(per_pwrdm
, PWRDM_POWER_OFF
);
453 /* Disable IO-PAD and IO-CHAIN wakeup */
454 if (core_next_state
< PWRDM_POWER_ON
) {
455 prm_clear_mod_reg_bits(OMAP3430_EN_IO
, WKUP_MOD
, PM_WKEN
);
456 omap3_disable_io_chain();
459 pwrdm_post_transition();
461 omap2_clkdm_allow_idle(mpu_pwrdm
->pwrdm_clkdms
[0]);
464 int omap3_can_sleep(void)
466 if (!sleep_while_idle
)
468 if (!omap_uart_can_sleep())
473 /* This sets pwrdm state (other than mpu & core. Currently only ON &
474 * RET are supported. Function is assuming that clkdm doesn't have
475 * hw_sup mode enabled. */
476 int set_pwrdm_state(struct powerdomain
*pwrdm
, u32 state
)
479 int sleep_switch
= 0;
482 if (pwrdm
== NULL
|| IS_ERR(pwrdm
))
485 while (!(pwrdm
->pwrsts
& (1 << state
))) {
486 if (state
== PWRDM_POWER_OFF
)
491 cur_state
= pwrdm_read_next_pwrst(pwrdm
);
492 if (cur_state
== state
)
495 if (pwrdm_read_pwrst(pwrdm
) < PWRDM_POWER_ON
) {
496 omap2_clkdm_wakeup(pwrdm
->pwrdm_clkdms
[0]);
498 pwrdm_wait_transition(pwrdm
);
501 ret
= pwrdm_set_next_pwrst(pwrdm
, state
);
503 printk(KERN_ERR
"Unable to set state of powerdomain: %s\n",
509 omap2_clkdm_allow_idle(pwrdm
->pwrdm_clkdms
[0]);
510 pwrdm_wait_transition(pwrdm
);
511 pwrdm_state_switch(pwrdm
);
518 static void omap3_pm_idle(void)
523 if (!omap3_can_sleep())
526 if (omap_irq_pending() || need_resched())
536 #ifdef CONFIG_SUSPEND
537 static suspend_state_t suspend_state
;
539 static void omap2_pm_wakeup_on_timer(u32 seconds
)
541 u32 tick_rate
, cycles
;
546 tick_rate
= clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup
));
547 cycles
= tick_rate
* seconds
;
548 omap_dm_timer_stop(gptimer_wakeup
);
549 omap_dm_timer_set_load_start(gptimer_wakeup
, 0, 0xffffffff - cycles
);
551 pr_info("PM: Resume timer in %d secs (%d ticks at %d ticks/sec.)\n",
552 seconds
, cycles
, tick_rate
);
555 static int omap3_pm_prepare(void)
561 static int omap3_pm_suspend(void)
563 struct power_state
*pwrst
;
566 if (wakeup_timer_seconds
)
567 omap2_pm_wakeup_on_timer(wakeup_timer_seconds
);
569 /* Read current next_pwrsts */
570 list_for_each_entry(pwrst
, &pwrst_list
, node
)
571 pwrst
->saved_state
= pwrdm_read_next_pwrst(pwrst
->pwrdm
);
572 /* Set ones wanted by suspend */
573 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
574 if (set_pwrdm_state(pwrst
->pwrdm
, pwrst
->next_state
))
576 if (pwrdm_clear_all_prev_pwrst(pwrst
->pwrdm
))
580 omap_uart_prepare_suspend();
584 /* Restore next_pwrsts */
585 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
586 state
= pwrdm_read_prev_pwrst(pwrst
->pwrdm
);
587 if (state
> pwrst
->next_state
) {
588 printk(KERN_INFO
"Powerdomain (%s) didn't enter "
590 pwrst
->pwrdm
->name
, pwrst
->next_state
);
593 set_pwrdm_state(pwrst
->pwrdm
, pwrst
->saved_state
);
596 printk(KERN_ERR
"Could not enter target state in pm_suspend\n");
598 printk(KERN_INFO
"Successfully put all powerdomains "
599 "to target state\n");
604 static int omap3_pm_enter(suspend_state_t unused
)
608 switch (suspend_state
) {
609 case PM_SUSPEND_STANDBY
:
611 ret
= omap3_pm_suspend();
620 static void omap3_pm_finish(void)
625 /* Hooks to enable / disable UART interrupts during suspend */
626 static int omap3_pm_begin(suspend_state_t state
)
628 suspend_state
= state
;
629 omap_uart_enable_irqs(0);
633 static void omap3_pm_end(void)
635 suspend_state
= PM_SUSPEND_ON
;
636 omap_uart_enable_irqs(1);
640 static struct platform_suspend_ops omap_pm_ops
= {
641 .begin
= omap3_pm_begin
,
643 .prepare
= omap3_pm_prepare
,
644 .enter
= omap3_pm_enter
,
645 .finish
= omap3_pm_finish
,
646 .valid
= suspend_valid_only_mem
,
648 #endif /* CONFIG_SUSPEND */
652 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
655 * In cases where IVA2 is activated by bootcode, it may prevent
656 * full-chip retention or off-mode because it is not idle. This
657 * function forces the IVA2 into idle state so it can go
658 * into retention/off and thus allow full-chip retention/off.
661 static void __init
omap3_iva_idle(void)
663 /* ensure IVA2 clock is disabled */
664 cm_write_mod_reg(0, OMAP3430_IVA2_MOD
, CM_FCLKEN
);
666 /* if no clock activity, nothing else to do */
667 if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD
, OMAP3430_CM_CLKSTST
) &
668 OMAP3430_CLKACTIVITY_IVA2_MASK
))
672 prm_write_mod_reg(OMAP3430_RST1_IVA2
|
675 OMAP3430_IVA2_MOD
, RM_RSTCTRL
);
677 /* Enable IVA2 clock */
678 cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2
,
679 OMAP3430_IVA2_MOD
, CM_FCLKEN
);
681 /* Set IVA2 boot mode to 'idle' */
682 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE
,
683 OMAP343X_CONTROL_IVA2_BOOTMOD
);
686 prm_write_mod_reg(0, OMAP3430_IVA2_MOD
, RM_RSTCTRL
);
688 /* Disable IVA2 clock */
689 cm_write_mod_reg(0, OMAP3430_IVA2_MOD
, CM_FCLKEN
);
692 prm_write_mod_reg(OMAP3430_RST1_IVA2
|
695 OMAP3430_IVA2_MOD
, RM_RSTCTRL
);
698 static void __init
omap3_d2d_idle(void)
702 /* In a stand alone OMAP3430 where there is not a stacked
703 * modem for the D2D Idle Ack and D2D MStandby must be pulled
704 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
705 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
706 mask
= (1 << 4) | (1 << 3); /* pull-up, enabled */
707 padconf
= omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY
);
709 omap_ctrl_writew(padconf
, OMAP3_PADCONF_SAD2D_MSTANDBY
);
711 padconf
= omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK
);
713 omap_ctrl_writew(padconf
, OMAP3_PADCONF_SAD2D_IDLEACK
);
716 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON
|
717 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST
,
718 CORE_MOD
, RM_RSTCTRL
);
719 prm_write_mod_reg(0, CORE_MOD
, RM_RSTCTRL
);
722 static void __init
prcm_setup_regs(void)
724 /* XXX Reset all wkdeps. This should be done when initializing
726 prm_write_mod_reg(0, OMAP3430_IVA2_MOD
, PM_WKDEP
);
727 prm_write_mod_reg(0, MPU_MOD
, PM_WKDEP
);
728 prm_write_mod_reg(0, OMAP3430_DSS_MOD
, PM_WKDEP
);
729 prm_write_mod_reg(0, OMAP3430_NEON_MOD
, PM_WKDEP
);
730 prm_write_mod_reg(0, OMAP3430_CAM_MOD
, PM_WKDEP
);
731 prm_write_mod_reg(0, OMAP3430_PER_MOD
, PM_WKDEP
);
732 if (omap_rev() > OMAP3430_REV_ES1_0
) {
733 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD
, PM_WKDEP
);
734 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD
, PM_WKDEP
);
736 prm_write_mod_reg(0, GFX_MOD
, PM_WKDEP
);
739 * Enable interface clock autoidle for all modules.
740 * Note that in the long run this should be done by clockfw
743 OMAP3430_AUTO_MODEM
|
744 OMAP3430ES2_AUTO_MMC3
|
745 OMAP3430ES2_AUTO_ICR
|
747 OMAP3430_AUTO_SHA12
|
751 OMAP3430_AUTO_MSPRO
|
753 OMAP3430_AUTO_MCSPI4
|
754 OMAP3430_AUTO_MCSPI3
|
755 OMAP3430_AUTO_MCSPI2
|
756 OMAP3430_AUTO_MCSPI1
|
760 OMAP3430_AUTO_UART2
|
761 OMAP3430_AUTO_UART1
|
762 OMAP3430_AUTO_GPT11
|
763 OMAP3430_AUTO_GPT10
|
764 OMAP3430_AUTO_MCBSP5
|
765 OMAP3430_AUTO_MCBSP1
|
766 OMAP3430ES1_AUTO_FAC
| /* This is es1 only */
767 OMAP3430_AUTO_MAILBOXES
|
768 OMAP3430_AUTO_OMAPCTRL
|
769 OMAP3430ES1_AUTO_FSHOSTUSB
|
770 OMAP3430_AUTO_HSOTGUSB
|
771 OMAP3430_AUTO_SAD2D
|
773 CORE_MOD
, CM_AUTOIDLE1
);
779 OMAP3430_AUTO_SHA11
|
781 CORE_MOD
, CM_AUTOIDLE2
);
783 if (omap_rev() > OMAP3430_REV_ES1_0
) {
785 OMAP3430_AUTO_MAD2D
|
786 OMAP3430ES2_AUTO_USBTLL
,
787 CORE_MOD
, CM_AUTOIDLE3
);
793 OMAP3430_AUTO_GPIO1
|
794 OMAP3430_AUTO_32KSYNC
|
795 OMAP3430_AUTO_GPT12
|
797 WKUP_MOD
, CM_AUTOIDLE
);
810 OMAP3430_AUTO_GPIO6
|
811 OMAP3430_AUTO_GPIO5
|
812 OMAP3430_AUTO_GPIO4
|
813 OMAP3430_AUTO_GPIO3
|
814 OMAP3430_AUTO_GPIO2
|
816 OMAP3430_AUTO_UART3
|
825 OMAP3430_AUTO_MCBSP4
|
826 OMAP3430_AUTO_MCBSP3
|
827 OMAP3430_AUTO_MCBSP2
,
831 if (omap_rev() > OMAP3430_REV_ES1_0
) {
833 OMAP3430ES2_AUTO_USBHOST
,
834 OMAP3430ES2_USBHOST_MOD
,
839 * Set all plls to autoidle. This is needed until autoidle is
842 cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT
,
843 OMAP3430_IVA2_MOD
, CM_AUTOIDLE2
);
844 cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT
,
847 cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT
) |
848 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT
),
851 cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT
,
856 * Enable control of expternal oscillator through
857 * sys_clkreq. In the long run clock framework should
860 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK
,
861 1 << OMAP_AUTOEXTCLKMODE_SHIFT
,
863 OMAP3_PRM_CLKSRC_CTRL_OFFSET
);
865 /* setup wakup source */
866 prm_write_mod_reg(OMAP3430_EN_IO
| OMAP3430_EN_GPIO1
|
867 OMAP3430_EN_GPT1
| OMAP3430_EN_GPT12
,
869 /* No need to write EN_IO, that is always enabled */
870 prm_write_mod_reg(OMAP3430_EN_GPIO1
| OMAP3430_EN_GPT1
|
872 WKUP_MOD
, OMAP3430_PM_MPUGRPSEL
);
873 /* For some reason IO doesn't generate wakeup event even if
874 * it is selected to mpu wakeup goup */
875 prm_write_mod_reg(OMAP3430_IO_EN
| OMAP3430_WKUP_EN
,
876 OCP_MOD
, OMAP3_PRM_IRQENABLE_MPU_OFFSET
);
878 /* Enable wakeups in PER */
879 prm_write_mod_reg(OMAP3430_EN_GPIO2
| OMAP3430_EN_GPIO3
|
880 OMAP3430_EN_GPIO4
| OMAP3430_EN_GPIO5
|
881 OMAP3430_EN_GPIO6
| OMAP3430_EN_UART3
,
882 OMAP3430_PER_MOD
, PM_WKEN
);
883 /* and allow them to wake up MPU */
884 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2
| OMAP3430_EN_GPIO3
|
885 OMAP3430_GRPSEL_GPIO4
| OMAP3430_EN_GPIO5
|
886 OMAP3430_GRPSEL_GPIO6
| OMAP3430_EN_UART3
,
887 OMAP3430_PER_MOD
, OMAP3430_PM_MPUGRPSEL
);
889 /* Don't attach IVA interrupts */
890 prm_write_mod_reg(0, WKUP_MOD
, OMAP3430_PM_IVAGRPSEL
);
891 prm_write_mod_reg(0, CORE_MOD
, OMAP3430_PM_IVAGRPSEL1
);
892 prm_write_mod_reg(0, CORE_MOD
, OMAP3430ES2_PM_IVAGRPSEL3
);
893 prm_write_mod_reg(0, OMAP3430_PER_MOD
, OMAP3430_PM_IVAGRPSEL
);
895 /* Clear any pending 'reset' flags */
896 prm_write_mod_reg(0xffffffff, MPU_MOD
, RM_RSTST
);
897 prm_write_mod_reg(0xffffffff, CORE_MOD
, RM_RSTST
);
898 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD
, RM_RSTST
);
899 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD
, RM_RSTST
);
900 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD
, RM_RSTST
);
901 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD
, RM_RSTST
);
902 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD
, RM_RSTST
);
904 /* Clear any pending PRCM interrupts */
905 prm_write_mod_reg(0, OCP_MOD
, OMAP3_PRM_IRQSTATUS_MPU_OFFSET
);
907 /* Don't attach IVA interrupts */
908 prm_write_mod_reg(0, WKUP_MOD
, OMAP3430_PM_IVAGRPSEL
);
909 prm_write_mod_reg(0, CORE_MOD
, OMAP3430_PM_IVAGRPSEL1
);
910 prm_write_mod_reg(0, CORE_MOD
, OMAP3430ES2_PM_IVAGRPSEL3
);
911 prm_write_mod_reg(0, OMAP3430_PER_MOD
, OMAP3430_PM_IVAGRPSEL
);
913 /* Clear any pending 'reset' flags */
914 prm_write_mod_reg(0xffffffff, MPU_MOD
, RM_RSTST
);
915 prm_write_mod_reg(0xffffffff, CORE_MOD
, RM_RSTST
);
916 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD
, RM_RSTST
);
917 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD
, RM_RSTST
);
918 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD
, RM_RSTST
);
919 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD
, RM_RSTST
);
920 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD
, RM_RSTST
);
922 /* Clear any pending PRCM interrupts */
923 prm_write_mod_reg(0, OCP_MOD
, OMAP3_PRM_IRQSTATUS_MPU_OFFSET
);
929 void omap3_pm_off_mode_enable(int enable
)
931 struct power_state
*pwrst
;
935 state
= PWRDM_POWER_OFF
;
937 state
= PWRDM_POWER_RET
;
939 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
940 pwrst
->next_state
= state
;
941 set_pwrdm_state(pwrst
->pwrdm
, state
);
945 int omap3_pm_get_suspend_state(struct powerdomain
*pwrdm
)
947 struct power_state
*pwrst
;
949 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
950 if (pwrst
->pwrdm
== pwrdm
)
951 return pwrst
->next_state
;
956 int omap3_pm_set_suspend_state(struct powerdomain
*pwrdm
, int state
)
958 struct power_state
*pwrst
;
960 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
961 if (pwrst
->pwrdm
== pwrdm
) {
962 pwrst
->next_state
= state
;
969 static int __init
pwrdms_setup(struct powerdomain
*pwrdm
, void *unused
)
971 struct power_state
*pwrst
;
976 pwrst
= kmalloc(sizeof(struct power_state
), GFP_ATOMIC
);
979 pwrst
->pwrdm
= pwrdm
;
980 pwrst
->next_state
= PWRDM_POWER_RET
;
981 list_add(&pwrst
->node
, &pwrst_list
);
983 if (pwrdm_has_hdwr_sar(pwrdm
))
984 pwrdm_enable_hdwr_sar(pwrdm
);
986 return set_pwrdm_state(pwrst
->pwrdm
, pwrst
->next_state
);
990 * Enable hw supervised mode for all clockdomains if it's
991 * supported. Initiate sleep transition for other clockdomains, if
994 static int __init
clkdms_setup(struct clockdomain
*clkdm
, void *unused
)
996 if (clkdm
->flags
& CLKDM_CAN_ENABLE_AUTO
)
997 omap2_clkdm_allow_idle(clkdm
);
998 else if (clkdm
->flags
& CLKDM_CAN_FORCE_SLEEP
&&
999 atomic_read(&clkdm
->usecount
) == 0)
1000 omap2_clkdm_sleep(clkdm
);
1004 void omap_push_sram_idle(void)
1006 _omap_sram_idle
= omap_sram_push(omap34xx_cpu_suspend
,
1007 omap34xx_cpu_suspend_sz
);
1008 if (omap_type() != OMAP2_DEVICE_TYPE_GP
)
1009 _omap_save_secure_sram
= omap_sram_push(save_secure_ram_context
,
1010 save_secure_ram_context_sz
);
1013 static int __init
omap3_pm_init(void)
1015 struct power_state
*pwrst
, *tmp
;
1018 if (!cpu_is_omap34xx())
1021 printk(KERN_ERR
"Power Management for TI OMAP3.\n");
1023 /* XXX prcm_setup_regs needs to be before enabling hw
1024 * supervised mode for powerdomains */
1027 ret
= request_irq(INT_34XX_PRCM_MPU_IRQ
,
1028 (irq_handler_t
)prcm_interrupt_handler
,
1029 IRQF_DISABLED
, "prcm", NULL
);
1031 printk(KERN_ERR
"request_irq failed to register for 0x%x\n",
1032 INT_34XX_PRCM_MPU_IRQ
);
1036 ret
= pwrdm_for_each(pwrdms_setup
, NULL
);
1038 printk(KERN_ERR
"Failed to setup powerdomains\n");
1042 (void) clkdm_for_each(clkdms_setup
, NULL
);
1044 mpu_pwrdm
= pwrdm_lookup("mpu_pwrdm");
1045 if (mpu_pwrdm
== NULL
) {
1046 printk(KERN_ERR
"Failed to get mpu_pwrdm\n");
1050 neon_pwrdm
= pwrdm_lookup("neon_pwrdm");
1051 per_pwrdm
= pwrdm_lookup("per_pwrdm");
1052 core_pwrdm
= pwrdm_lookup("core_pwrdm");
1053 cam_pwrdm
= pwrdm_lookup("cam_pwrdm");
1055 omap_push_sram_idle();
1056 #ifdef CONFIG_SUSPEND
1057 suspend_set_ops(&omap_pm_ops
);
1058 #endif /* CONFIG_SUSPEND */
1060 pm_idle
= omap3_pm_idle
;
1063 pwrdm_add_wkdep(neon_pwrdm
, mpu_pwrdm
);
1065 * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for
1066 * IO-pad wakeup. Otherwise it will unnecessarily waste power
1067 * waking up PER with every CORE wakeup - see
1068 * http://marc.info/?l=linux-omap&m=121852150710062&w=2
1070 pwrdm_add_wkdep(per_pwrdm
, core_pwrdm
);
1072 if (omap_type() != OMAP2_DEVICE_TYPE_GP
) {
1073 omap3_secure_ram_storage
=
1074 kmalloc(0x803F, GFP_KERNEL
);
1075 if (!omap3_secure_ram_storage
)
1076 printk(KERN_ERR
"Memory allocation failed when"
1077 "allocating for secure sram context\n");
1079 local_irq_disable();
1080 local_fiq_disable();
1082 omap_dma_global_context_save();
1083 omap3_save_secure_ram_context(PWRDM_POWER_ON
);
1084 omap_dma_global_context_restore();
1090 omap3_save_scratchpad_contents();
1094 free_irq(INT_34XX_PRCM_MPU_IRQ
, NULL
);
1095 list_for_each_entry_safe(pwrst
, tmp
, &pwrst_list
, node
) {
1096 list_del(&pwrst
->node
);
1102 late_initcall(omap3_pm_init
);