| blob | e618fc4cbc9e911e76d56050978b37cc170beb0c |
1 /*
2 * Device Tree Source for AMCC Glacier (460GT)
3 *
4 * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
11 /dts-v1/;
13 / {
14 #address-cells = <2>;
15 #size-cells = <1>;
16 model = "amcc,glacier";
17 compatible = "amcc,glacier";
18 dcr-parent = <&{/cpus/cpu@0}>;
20 aliases {
21 ethernet0 = &EMAC0;
22 ethernet1 = &EMAC1;
23 ethernet2 = &EMAC2;
24 ethernet3 = &EMAC3;
25 serial0 = &UART0;
26 serial1 = &UART1;
27 };
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
33 cpu@0 {
34 device_type = "cpu";
35 model = "PowerPC,460GT";
36 reg = <0x00000000>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
40 d-cache-line-size = <32>;
41 i-cache-size = <32768>;
42 d-cache-size = <32768>;
43 dcr-controller;
44 dcr-access-method = "native";
45 next-level-cache = <&L2C0>;
46 };
47 };
49 memory {
50 device_type = "memory";
51 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
52 };
54 UIC0: interrupt-controller0 {
55 compatible = "ibm,uic-460gt","ibm,uic";
56 interrupt-controller;
57 cell-index = <0>;
58 dcr-reg = <0x0c0 0x009>;
59 #address-cells = <0>;
60 #size-cells = <0>;
61 #interrupt-cells = <2>;
62 };
64 UIC1: interrupt-controller1 {
65 compatible = "ibm,uic-460gt","ibm,uic";
66 interrupt-controller;
67 cell-index = <1>;
68 dcr-reg = <0x0d0 0x009>;
69 #address-cells = <0>;
70 #size-cells = <0>;
71 #interrupt-cells = <2>;
72 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
73 interrupt-parent = <&UIC0>;
74 };
76 UIC2: interrupt-controller2 {
77 compatible = "ibm,uic-460gt","ibm,uic";
78 interrupt-controller;
79 cell-index = <2>;
80 dcr-reg = <0x0e0 0x009>;
81 #address-cells = <0>;
82 #size-cells = <0>;
83 #interrupt-cells = <2>;
84 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
85 interrupt-parent = <&UIC0>;
86 };
88 UIC3: interrupt-controller3 {
89 compatible = "ibm,uic-460gt","ibm,uic";
90 interrupt-controller;
91 cell-index = <3>;
92 dcr-reg = <0x0f0 0x009>;
93 #address-cells = <0>;
94 #size-cells = <0>;
95 #interrupt-cells = <2>;
96 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
97 interrupt-parent = <&UIC0>;
98 };
100 SDR0: sdr {
101 compatible = "ibm,sdr-460gt";
102 dcr-reg = <0x00e 0x002>;
103 };
105 CPR0: cpr {
106 compatible = "ibm,cpr-460gt";
107 dcr-reg = <0x00c 0x002>;
108 };
110 L2C0: l2c {
111 compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
112 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
113 0x030 0x008>; /* L2 cache DCR's */
114 cache-line-size = <32>; /* 32 bytes */
115 cache-size = <262144>; /* L2, 256K */
116 interrupt-parent = <&UIC1>;
117 interrupts = <11 1>;
118 };
120 plb {
121 compatible = "ibm,plb-460gt", "ibm,plb4";
122 #address-cells = <2>;
123 #size-cells = <1>;
124 ranges;
125 clock-frequency = <0>; /* Filled in by U-Boot */
127 SDRAM0: sdram {
128 compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
129 dcr-reg = <0x010 0x002>;
130 };
132 CRYPTO: crypto@180000 {
133 compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto";
134 reg = <4 0x00180000 0x80400>;
135 interrupt-parent = <&UIC0>;
136 interrupts = <0x1d 0x4>;
137 };
139 MAL0: mcmal {
140 compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
141 dcr-reg = <0x180 0x062>;
142 num-tx-chans = <4>;
143 num-rx-chans = <32>;
144 #address-cells = <0>;
145 #size-cells = <0>;
146 interrupt-parent = <&UIC2>;
147 interrupts = < /*TXEOB*/ 0x6 0x4
148 /*RXEOB*/ 0x7 0x4
149 /*SERR*/ 0x3 0x4
150 /*TXDE*/ 0x4 0x4
151 /*RXDE*/ 0x5 0x4>;
152 desc-base-addr-high = <0x8>;
153 };
155 POB0: opb {
156 compatible = "ibm,opb-460gt", "ibm,opb";
157 #address-cells = <1>;
158 #size-cells = <1>;
159 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
160 clock-frequency = <0>; /* Filled in by U-Boot */
162 EBC0: ebc {
163 compatible = "ibm,ebc-460gt", "ibm,ebc";
164 dcr-reg = <0x012 0x002>;
165 #address-cells = <2>;
166 #size-cells = <1>;
167 clock-frequency = <0>; /* Filled in by U-Boot */
168 /* ranges property is supplied by U-Boot */
169 interrupts = <0x6 0x4>;
170 interrupt-parent = <&UIC1>;
172 nor_flash@0,0 {
173 compatible = "amd,s29gl512n", "cfi-flash";
174 bank-width = <2>;
175 reg = <0x00000000 0x00000000 0x04000000>;
176 #address-cells = <1>;
177 #size-cells = <1>;
178 partition@0 {
179 label = "kernel";
180 reg = <0x00000000 0x001e0000>;
181 };
182 partition@1e0000 {
183 label = "dtb";
184 reg = <0x001e0000 0x00020000>;
185 };
186 partition@200000 {
187 label = "ramdisk";
188 reg = <0x00200000 0x01400000>;
189 };
190 partition@1600000 {
191 label = "jffs2";
192 reg = <0x01600000 0x00400000>;
193 };
194 partition@1a00000 {
195 label = "user";
196 reg = <0x01a00000 0x02560000>;
197 };
198 partition@3f60000 {
199 label = "env";
200 reg = <0x03f60000 0x00040000>;
201 };
202 partition@3fa0000 {
203 label = "u-boot";
204 reg = <0x03fa0000 0x00060000>;
205 };
206 };
208 ndfc@3,0 {
209 compatible = "ibm,ndfc";
210 reg = <0x00000003 0x00000000 0x00002000>;
211 ccr = <0x00001000>;
212 bank-settings = <0x80002222>;
213 #address-cells = <1>;
214 #size-cells = <1>;
216 nand {
217 #address-cells = <1>;
218 #size-cells = <1>;
220 partition@0 {
221 label = "u-boot";
222 reg = <0x00000000 0x00100000>;
223 };
224 partition@100000 {
225 label = "user";
226 reg = <0x00000000 0x03f00000>;
227 };
228 };
229 };
230 };
232 UART0: serial@ef600300 {
233 device_type = "serial";
234 compatible = "ns16550";
235 reg = <0xef600300 0x00000008>;
236 virtual-reg = <0xef600300>;
237 clock-frequency = <0>; /* Filled in by U-Boot */
238 current-speed = <0>; /* Filled in by U-Boot */
239 interrupt-parent = <&UIC1>;
240 interrupts = <0x1 0x4>;
241 };
243 UART1: serial@ef600400 {
244 device_type = "serial";
245 compatible = "ns16550";
246 reg = <0xef600400 0x00000008>;
247 virtual-reg = <0xef600400>;
248 clock-frequency = <0>; /* Filled in by U-Boot */
249 current-speed = <0>; /* Filled in by U-Boot */
250 interrupt-parent = <&UIC0>;
251 interrupts = <0x1 0x4>;
252 };
254 UART2: serial@ef600500 {
255 device_type = "serial";
256 compatible = "ns16550";
257 reg = <0xef600500 0x00000008>;
258 virtual-reg = <0xef600500>;
259 clock-frequency = <0>; /* Filled in by U-Boot */
260 current-speed = <0>; /* Filled in by U-Boot */
261 interrupt-parent = <&UIC1>;
262 interrupts = <28 0x4>;
263 };
265 UART3: serial@ef600600 {
266 device_type = "serial";
267 compatible = "ns16550";
268 reg = <0xef600600 0x00000008>;
269 virtual-reg = <0xef600600>;
270 clock-frequency = <0>; /* Filled in by U-Boot */
271 current-speed = <0>; /* Filled in by U-Boot */
272 interrupt-parent = <&UIC1>;
273 interrupts = <29 0x4>;
274 };
276 IIC0: i2c@ef600700 {
277 compatible = "ibm,iic-460gt", "ibm,iic";
278 reg = <0xef600700 0x00000014>;
279 interrupt-parent = <&UIC0>;
280 interrupts = <0x2 0x4>;
281 #address-cells = <1>;
282 #size-cells = <0>;
283 rtc@68 {
284 compatible = "stm,m41t80";
285 reg = <0x68>;
286 interrupt-parent = <&UIC2>;
287 interrupts = <0x19 0x8>;
288 };
289 sttm@48 {
290 compatible = "ad,ad7414";
291 reg = <0x48>;
292 interrupt-parent = <&UIC1>;
293 interrupts = <0x14 0x8>;
294 };
295 };
297 IIC1: i2c@ef600800 {
298 compatible = "ibm,iic-460gt", "ibm,iic";
299 reg = <0xef600800 0x00000014>;
300 interrupt-parent = <&UIC0>;
301 interrupts = <0x3 0x4>;
302 };
304 ZMII0: emac-zmii@ef600d00 {
305 compatible = "ibm,zmii-460gt", "ibm,zmii";
306 reg = <0xef600d00 0x0000000c>;
307 };
309 RGMII0: emac-rgmii@ef601500 {
310 compatible = "ibm,rgmii-460gt", "ibm,rgmii";
311 reg = <0xef601500 0x00000008>;
312 has-mdio;
313 };
315 RGMII1: emac-rgmii@ef601600 {
316 compatible = "ibm,rgmii-460gt", "ibm,rgmii";
317 reg = <0xef601600 0x00000008>;
318 has-mdio;
319 };
321 TAH0: emac-tah@ef601350 {
322 compatible = "ibm,tah-460gt", "ibm,tah";
323 reg = <0xef601350 0x00000030>;
324 };
326 TAH1: emac-tah@ef601450 {
327 compatible = "ibm,tah-460gt", "ibm,tah";
328 reg = <0xef601450 0x00000030>;
329 };
331 EMAC0: ethernet@ef600e00 {
332 device_type = "network";
333 compatible = "ibm,emac-460gt", "ibm,emac4sync";
334 interrupt-parent = <&EMAC0>;
335 interrupts = <0x0 0x1>;
336 #interrupt-cells = <1>;
337 #address-cells = <0>;
338 #size-cells = <0>;
339 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
340 /*Wake*/ 0x1 &UIC2 0x14 0x4>;
341 reg = <0xef600e00 0x000000c4>;
342 local-mac-address = [000000000000]; /* Filled in by U-Boot */
343 mal-device = <&MAL0>;
344 mal-tx-channel = <0>;
345 mal-rx-channel = <0>;
346 cell-index = <0>;
347 max-frame-size = <9000>;
348 rx-fifo-size = <4096>;
349 tx-fifo-size = <2048>;
350 rx-fifo-size-gige = <16384>;
351 phy-mode = "rgmii";
352 phy-map = <0x00000000>;
353 rgmii-device = <&RGMII0>;
354 rgmii-channel = <0>;
355 tah-device = <&TAH0>;
356 tah-channel = <0>;
357 has-inverted-stacr-oc;
358 has-new-stacr-staopc;
359 };
361 EMAC1: ethernet@ef600f00 {
362 device_type = "network";
363 compatible = "ibm,emac-460gt", "ibm,emac4sync";
364 interrupt-parent = <&EMAC1>;
365 interrupts = <0x0 0x1>;
366 #interrupt-cells = <1>;
367 #address-cells = <0>;
368 #size-cells = <0>;
369 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
370 /*Wake*/ 0x1 &UIC2 0x15 0x4>;
371 reg = <0xef600f00 0x000000c4>;
372 local-mac-address = [000000000000]; /* Filled in by U-Boot */
373 mal-device = <&MAL0>;
374 mal-tx-channel = <1>;
375 mal-rx-channel = <8>;
376 cell-index = <1>;
377 max-frame-size = <9000>;
378 rx-fifo-size = <4096>;
379 tx-fifo-size = <2048>;
380 rx-fifo-size-gige = <16384>;
381 phy-mode = "rgmii";
382 phy-map = <0x00000000>;
383 rgmii-device = <&RGMII0>;
384 rgmii-channel = <1>;
385 tah-device = <&TAH1>;
386 tah-channel = <1>;
387 has-inverted-stacr-oc;
388 has-new-stacr-staopc;
389 mdio-device = <&EMAC0>;
390 };
392 EMAC2: ethernet@ef601100 {
393 device_type = "network";
394 compatible = "ibm,emac-460gt", "ibm,emac4sync";
395 interrupt-parent = <&EMAC2>;
396 interrupts = <0x0 0x1>;
397 #interrupt-cells = <1>;
398 #address-cells = <0>;
399 #size-cells = <0>;
400 interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
401 /*Wake*/ 0x1 &UIC2 0x16 0x4>;
402 reg = <0xef601100 0x000000c4>;
403 local-mac-address = [000000000000]; /* Filled in by U-Boot */
404 mal-device = <&MAL0>;
405 mal-tx-channel = <2>;
406 mal-rx-channel = <16>;
407 cell-index = <2>;
408 max-frame-size = <9000>;
409 rx-fifo-size = <4096>;
410 tx-fifo-size = <2048>;
411 rx-fifo-size-gige = <16384>;
412 tx-fifo-size-gige = <16384>; /* emac2&3 only */
413 phy-mode = "rgmii";
414 phy-map = <0x00000000>;
415 rgmii-device = <&RGMII1>;
416 rgmii-channel = <0>;
417 has-inverted-stacr-oc;
418 has-new-stacr-staopc;
419 mdio-device = <&EMAC0>;
420 };
422 EMAC3: ethernet@ef601200 {
423 device_type = "network";
424 compatible = "ibm,emac-460gt", "ibm,emac4sync";
425 interrupt-parent = <&EMAC3>;
426 interrupts = <0x0 0x1>;
427 #interrupt-cells = <1>;
428 #address-cells = <0>;
429 #size-cells = <0>;
430 interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4
431 /*Wake*/ 0x1 &UIC2 0x17 0x4>;
432 reg = <0xef601200 0x000000c4>;
433 local-mac-address = [000000000000]; /* Filled in by U-Boot */
434 mal-device = <&MAL0>;
435 mal-tx-channel = <3>;
436 mal-rx-channel = <24>;
437 cell-index = <3>;
438 max-frame-size = <9000>;
439 rx-fifo-size = <4096>;
440 tx-fifo-size = <2048>;
441 rx-fifo-size-gige = <16384>;
442 tx-fifo-size-gige = <16384>; /* emac2&3 only */
443 phy-mode = "rgmii";
444 phy-map = <0x00000000>;
445 rgmii-device = <&RGMII1>;
446 rgmii-channel = <1>;
447 has-inverted-stacr-oc;
448 has-new-stacr-staopc;
449 mdio-device = <&EMAC0>;
450 };
451 };
453 PCIX0: pci@c0ec00000 {
454 device_type = "pci";
455 #interrupt-cells = <1>;
456 #size-cells = <2>;
457 #address-cells = <3>;
458 compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix";
459 primary;
460 large-inbound-windows;
461 enable-msi-hole;
462 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
463 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
464 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
465 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
466 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
468 /* Outbound ranges, one memory and one IO,
469 * later cannot be changed
470 */
471 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
472 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
473 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
475 /* Inbound 2GB range starting at 0 */
476 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
478 /* This drives busses 0 to 0x3f */
479 bus-range = <0x0 0x3f>;
481 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
482 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
483 interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
484 };
486 PCIE0: pciex@d00000000 {
487 device_type = "pci";
488 #interrupt-cells = <1>;
489 #size-cells = <2>;
490 #address-cells = <3>;
491 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
492 primary;
493 port = <0x0>; /* port number */
494 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
495 0x0000000c 0x08010000 0x00001000>; /* Registers */
496 dcr-reg = <0x100 0x020>;
497 sdr-base = <0x300>;
499 /* Outbound ranges, one memory and one IO,
500 * later cannot be changed
501 */
502 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
503 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
504 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
506 /* Inbound 2GB range starting at 0 */
507 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
509 /* This drives busses 40 to 0x7f */
510 bus-range = <0x40 0x7f>;
512 /* Legacy interrupts (note the weird polarity, the bridge seems
513 * to invert PCIe legacy interrupts).
514 * We are de-swizzling here because the numbers are actually for
515 * port of the root complex virtual P2P bridge. But I want
516 * to avoid putting a node for it in the tree, so the numbers
517 * below are basically de-swizzled numbers.
518 * The real slot is on idsel 0, so the swizzling is 1:1
519 */
520 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
521 interrupt-map = <
522 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
523 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
524 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
525 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
526 };
528 PCIE1: pciex@d20000000 {
529 device_type = "pci";
530 #interrupt-cells = <1>;
531 #size-cells = <2>;
532 #address-cells = <3>;
533 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
534 primary;
535 port = <0x1>; /* port number */
536 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
537 0x0000000c 0x08011000 0x00001000>; /* Registers */
538 dcr-reg = <0x120 0x020>;
539 sdr-base = <0x340>;
541 /* Outbound ranges, one memory and one IO,
542 * later cannot be changed
543 */
544 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
545 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
546 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
548 /* Inbound 2GB range starting at 0 */
549 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
551 /* This drives busses 80 to 0xbf */
552 bus-range = <0x80 0xbf>;
554 /* Legacy interrupts (note the weird polarity, the bridge seems
555 * to invert PCIe legacy interrupts).
556 * We are de-swizzling here because the numbers are actually for
557 * port of the root complex virtual P2P bridge. But I want
558 * to avoid putting a node for it in the tree, so the numbers
559 * below are basically de-swizzled numbers.
560 * The real slot is on idsel 0, so the swizzling is 1:1
561 */
562 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
563 interrupt-map = <
564 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
565 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
566 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
567 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
568 };
569 };
570 };