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ath9k: remove ah->mask_reg, it's never used properly
[linux-2.6/x86.git] / drivers / net / wireless / ath / ath9k / hw.c
blobe716b600dec5b1d16d741ba7cb91c9da710584a6
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "hw.h"
21 #include "rc.h"
22 #include "initvals.h"
23
24 #define ATH9K_CLOCK_RATE_CCK 22
25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
27
28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
29 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
30 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
31 struct ar5416_eeprom_def *pEepData,
32 u32 reg, u32 value);
33
34 MODULE_AUTHOR("Atheros Communications");
35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37 MODULE_LICENSE("Dual BSD/GPL");
38
39 static int __init ath9k_init(void)
40 {
41 return 0;
42 }
43 module_init(ath9k_init);
44
45 static void __exit ath9k_exit(void)
46 {
47 return;
48 }
49 module_exit(ath9k_exit);
50
51 /********************/
52 /* Helper Functions */
53 /********************/
54
55 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
56 {
57 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
58
59 if (!ah->curchan) /* should really check for CCK instead */
60 return usecs *ATH9K_CLOCK_RATE_CCK;
61 if (conf->channel->band == IEEE80211_BAND_2GHZ)
62 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
63 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
64 }
65
66 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
67 {
68 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
69
70 if (conf_is_ht40(conf))
71 return ath9k_hw_mac_clks(ah, usecs) * 2;
72 else
73 return ath9k_hw_mac_clks(ah, usecs);
74 }
75
76 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
77 {
78 int i;
79
80 BUG_ON(timeout < AH_TIME_QUANTUM);
81
82 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
83 if ((REG_READ(ah, reg) & mask) == val)
84 return true;
85
86 udelay(AH_TIME_QUANTUM);
87 }
88
89 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
90 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
91 timeout, reg, REG_READ(ah, reg), mask, val);
92
93 return false;
94 }
95 EXPORT_SYMBOL(ath9k_hw_wait);
96
97 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
98 {
99 u32 retval;
100 int i;
101
102 for (i = 0, retval = 0; i < n; i++) {
103 retval = (retval << 1) | (val & 1);
104 val >>= 1;
105 }
106 return retval;
107 }
108
109 bool ath9k_get_channel_edges(struct ath_hw *ah,
110 u16 flags, u16 *low,
111 u16 *high)
112 {
113 struct ath9k_hw_capabilities *pCap = &ah->caps;
114
115 if (flags & CHANNEL_5GHZ) {
116 *low = pCap->low_5ghz_chan;
117 *high = pCap->high_5ghz_chan;
118 return true;
119 }
120 if ((flags & CHANNEL_2GHZ)) {
121 *low = pCap->low_2ghz_chan;
122 *high = pCap->high_2ghz_chan;
123 return true;
124 }
125 return false;
126 }
127
128 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
129 u8 phy, int kbps,
130 u32 frameLen, u16 rateix,
131 bool shortPreamble)
132 {
133 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
134
135 if (kbps == 0)
136 return 0;
137
138 switch (phy) {
139 case WLAN_RC_PHY_CCK:
140 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
141 if (shortPreamble)
142 phyTime >>= 1;
143 numBits = frameLen << 3;
144 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
145 break;
146 case WLAN_RC_PHY_OFDM:
147 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
148 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
149 numBits = OFDM_PLCP_BITS + (frameLen << 3);
150 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
151 txTime = OFDM_SIFS_TIME_QUARTER
152 + OFDM_PREAMBLE_TIME_QUARTER
153 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
154 } else if (ah->curchan &&
155 IS_CHAN_HALF_RATE(ah->curchan)) {
156 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
157 numBits = OFDM_PLCP_BITS + (frameLen << 3);
158 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
159 txTime = OFDM_SIFS_TIME_HALF +
160 OFDM_PREAMBLE_TIME_HALF
161 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
162 } else {
163 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
164 numBits = OFDM_PLCP_BITS + (frameLen << 3);
165 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
166 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
167 + (numSymbols * OFDM_SYMBOL_TIME);
168 }
169 break;
170 default:
171 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
172 "Unknown phy %u (rate ix %u)\n", phy, rateix);
173 txTime = 0;
174 break;
175 }
176
177 return txTime;
178 }
179 EXPORT_SYMBOL(ath9k_hw_computetxtime);
180
181 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
182 struct ath9k_channel *chan,
183 struct chan_centers *centers)
184 {
185 int8_t extoff;
186
187 if (!IS_CHAN_HT40(chan)) {
188 centers->ctl_center = centers->ext_center =
189 centers->synth_center = chan->channel;
190 return;
191 }
192
193 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
194 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
195 centers->synth_center =
196 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
197 extoff = 1;
198 } else {
199 centers->synth_center =
200 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
201 extoff = -1;
202 }
203
204 centers->ctl_center =
205 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
206 /* 25 MHz spacing is supported by hw but not on upper layers */
207 centers->ext_center =
208 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
209 }
210
211 /******************/
212 /* Chip Revisions */
213 /******************/
214
215 static void ath9k_hw_read_revisions(struct ath_hw *ah)
216 {
217 u32 val;
218
219 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
220
221 if (val == 0xFF) {
222 val = REG_READ(ah, AR_SREV);
223 ah->hw_version.macVersion =
224 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
225 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
226 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
227 } else {
228 if (!AR_SREV_9100(ah))
229 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
230
231 ah->hw_version.macRev = val & AR_SREV_REVISION;
232
233 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
234 ah->is_pciexpress = true;
235 }
236 }
237
238 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
239 {
240 u32 val;
241 int i;
242
243 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
244
245 for (i = 0; i < 8; i++)
246 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
247 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
248 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
249
250 return ath9k_hw_reverse_bits(val, 8);
251 }
252
253 /************************************/
254 /* HW Attach, Detach, Init Routines */
255 /************************************/
256
257 static void ath9k_hw_disablepcie(struct ath_hw *ah)
258 {
259 if (AR_SREV_9100(ah))
260 return;
261
262 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
263 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
264 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
265 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
266 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
267 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
268 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
269 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
270 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
271
272 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
273 }
274
275 static bool ath9k_hw_chip_test(struct ath_hw *ah)
276 {
277 struct ath_common *common = ath9k_hw_common(ah);
278 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
279 u32 regHold[2];
280 u32 patternData[4] = { 0x55555555,
281 0xaaaaaaaa,
282 0x66666666,
283 0x99999999 };
284 int i, j;
285
286 for (i = 0; i < 2; i++) {
287 u32 addr = regAddr[i];
288 u32 wrData, rdData;
289
290 regHold[i] = REG_READ(ah, addr);
291 for (j = 0; j < 0x100; j++) {
292 wrData = (j << 16) | j;
293 REG_WRITE(ah, addr, wrData);
294 rdData = REG_READ(ah, addr);
295 if (rdData != wrData) {
296 ath_print(common, ATH_DBG_FATAL,
297 "address test failed "
298 "addr: 0x%08x - wr:0x%08x != "
299 "rd:0x%08x\n",
300 addr, wrData, rdData);
301 return false;
302 }
303 }
304 for (j = 0; j < 4; j++) {
305 wrData = patternData[j];
306 REG_WRITE(ah, addr, wrData);
307 rdData = REG_READ(ah, addr);
308 if (wrData != rdData) {
309 ath_print(common, ATH_DBG_FATAL,
310 "address test failed "
311 "addr: 0x%08x - wr:0x%08x != "
312 "rd:0x%08x\n",
313 addr, wrData, rdData);
314 return false;
315 }
316 }
317 REG_WRITE(ah, regAddr[i], regHold[i]);
318 }
319 udelay(100);
320
321 return true;
322 }
323
324 static void ath9k_hw_init_config(struct ath_hw *ah)
325 {
326 int i;
327
328 ah->config.dma_beacon_response_time = 2;
329 ah->config.sw_beacon_response_time = 10;
330 ah->config.additional_swba_backoff = 0;
331 ah->config.ack_6mb = 0x0;
332 ah->config.cwm_ignore_extcca = 0;
333 ah->config.pcie_powersave_enable = 0;
334 ah->config.pcie_clock_req = 0;
335 ah->config.pcie_waen = 0;
336 ah->config.analog_shiftreg = 1;
337 ah->config.ofdm_trig_low = 200;
338 ah->config.ofdm_trig_high = 500;
339 ah->config.cck_trig_high = 200;
340 ah->config.cck_trig_low = 100;
341 ah->config.enable_ani = 1;
342
343 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
344 ah->config.spurchans[i][0] = AR_NO_SPUR;
345 ah->config.spurchans[i][1] = AR_NO_SPUR;
346 }
347
348 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
349 ah->config.ht_enable = 1;
350 else
351 ah->config.ht_enable = 0;
352
353 ah->config.rx_intr_mitigation = true;
354
355 /*
356 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
357 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
358 * This means we use it for all AR5416 devices, and the few
359 * minor PCI AR9280 devices out there.
360 *
361 * Serialization is required because these devices do not handle
362 * well the case of two concurrent reads/writes due to the latency
363 * involved. During one read/write another read/write can be issued
364 * on another CPU while the previous read/write may still be working
365 * on our hardware, if we hit this case the hardware poops in a loop.
366 * We prevent this by serializing reads and writes.
367 *
368 * This issue is not present on PCI-Express devices or pre-AR5416
369 * devices (legacy, 802.11abg).
370 */
371 if (num_possible_cpus() > 1)
372 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
373 }
374 EXPORT_SYMBOL(ath9k_hw_init);
375
376 static void ath9k_hw_init_defaults(struct ath_hw *ah)
377 {
378 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
379
380 regulatory->country_code = CTRY_DEFAULT;
381 regulatory->power_limit = MAX_RATE_POWER;
382 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
383
384 ah->hw_version.magic = AR5416_MAGIC;
385 ah->hw_version.subvendorid = 0;
386
387 ah->ah_flags = 0;
388 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
389 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
390 if (!AR_SREV_9100(ah))
391 ah->ah_flags = AH_USE_EEPROM;
392
393 ah->atim_window = 0;
394 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
395 ah->beacon_interval = 100;
396 ah->enable_32kHz_clock = DONT_USE_32KHZ;
397 ah->slottime = (u32) -1;
398 ah->globaltxtimeout = (u32) -1;
399 ah->power_mode = ATH9K_PM_UNDEFINED;
400 }
401
402 static int ath9k_hw_rf_claim(struct ath_hw *ah)
403 {
404 u32 val;
405
406 REG_WRITE(ah, AR_PHY(0), 0x00000007);
407
408 val = ath9k_hw_get_radiorev(ah);
409 switch (val & AR_RADIO_SREV_MAJOR) {
410 case 0:
411 val = AR_RAD5133_SREV_MAJOR;
412 break;
413 case AR_RAD5133_SREV_MAJOR:
414 case AR_RAD5122_SREV_MAJOR:
415 case AR_RAD2133_SREV_MAJOR:
416 case AR_RAD2122_SREV_MAJOR:
417 break;
418 default:
419 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
420 "Radio Chip Rev 0x%02X not supported\n",
421 val & AR_RADIO_SREV_MAJOR);
422 return -EOPNOTSUPP;
423 }
424
425 ah->hw_version.analog5GhzRev = val;
426
427 return 0;
428 }
429
430 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
431 {
432 struct ath_common *common = ath9k_hw_common(ah);
433 u32 sum;
434 int i;
435 u16 eeval;
436
437 sum = 0;
438 for (i = 0; i < 3; i++) {
439 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
440 sum += eeval;
441 common->macaddr[2 * i] = eeval >> 8;
442 common->macaddr[2 * i + 1] = eeval & 0xff;
443 }
444 if (sum == 0 || sum == 0xffff * 3)
445 return -EADDRNOTAVAIL;
446
447 return 0;
448 }
449
450 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
451 {
452 u32 rxgain_type;
453
454 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
455 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
456
457 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
458 INIT_INI_ARRAY(&ah->iniModesRxGain,
459 ar9280Modes_backoff_13db_rxgain_9280_2,
460 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
461 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
462 INIT_INI_ARRAY(&ah->iniModesRxGain,
463 ar9280Modes_backoff_23db_rxgain_9280_2,
464 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
465 else
466 INIT_INI_ARRAY(&ah->iniModesRxGain,
467 ar9280Modes_original_rxgain_9280_2,
468 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
469 } else {
470 INIT_INI_ARRAY(&ah->iniModesRxGain,
471 ar9280Modes_original_rxgain_9280_2,
472 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
473 }
474 }
475
476 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
477 {
478 u32 txgain_type;
479
480 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
481 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
482
483 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
484 INIT_INI_ARRAY(&ah->iniModesTxGain,
485 ar9280Modes_high_power_tx_gain_9280_2,
486 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
487 else
488 INIT_INI_ARRAY(&ah->iniModesTxGain,
489 ar9280Modes_original_tx_gain_9280_2,
490 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
491 } else {
492 INIT_INI_ARRAY(&ah->iniModesTxGain,
493 ar9280Modes_original_tx_gain_9280_2,
494 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
495 }
496 }
497
498 static int ath9k_hw_post_init(struct ath_hw *ah)
499 {
500 int ecode;
501
502 if (!AR_SREV_9271(ah)) {
503 if (!ath9k_hw_chip_test(ah))
504 return -ENODEV;
505 }
506
507 ecode = ath9k_hw_rf_claim(ah);
508 if (ecode != 0)
509 return ecode;
510
511 ecode = ath9k_hw_eeprom_init(ah);
512 if (ecode != 0)
513 return ecode;
514
515 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
516 "Eeprom VER: %d, REV: %d\n",
517 ah->eep_ops->get_eeprom_ver(ah),
518 ah->eep_ops->get_eeprom_rev(ah));
519
520 if (!AR_SREV_9280_10_OR_LATER(ah)) {
521 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
522 if (ecode) {
523 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
524 "Failed allocating banks for "
525 "external radio\n");
526 return ecode;
527 }
528 }
529
530 if (!AR_SREV_9100(ah)) {
531 ath9k_hw_ani_setup(ah);
532 ath9k_hw_ani_init(ah);
533 }
534
535 return 0;
536 }
537
538 static bool ath9k_hw_devid_supported(u16 devid)
539 {
540 switch (devid) {
541 case AR5416_DEVID_PCI:
542 case AR5416_DEVID_PCIE:
543 case AR5416_AR9100_DEVID:
544 case AR9160_DEVID_PCI:
545 case AR9280_DEVID_PCI:
546 case AR9280_DEVID_PCIE:
547 case AR9285_DEVID_PCIE:
548 case AR5416_DEVID_AR9287_PCI:
549 case AR5416_DEVID_AR9287_PCIE:
550 case AR9271_USB:
551 case AR2427_DEVID_PCIE:
552 return true;
553 default:
554 break;
555 }
556 return false;
557 }
558
559 static bool ath9k_hw_macversion_supported(u32 macversion)
560 {
561 switch (macversion) {
562 case AR_SREV_VERSION_5416_PCI:
563 case AR_SREV_VERSION_5416_PCIE:
564 case AR_SREV_VERSION_9160:
565 case AR_SREV_VERSION_9100:
566 case AR_SREV_VERSION_9280:
567 case AR_SREV_VERSION_9285:
568 case AR_SREV_VERSION_9287:
569 case AR_SREV_VERSION_9271:
570 return true;
571 default:
572 break;
573 }
574 return false;
575 }
576
577 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
578 {
579 if (AR_SREV_9160_10_OR_LATER(ah)) {
580 if (AR_SREV_9280_10_OR_LATER(ah)) {
581 ah->iq_caldata.calData = &iq_cal_single_sample;
582 ah->adcgain_caldata.calData =
583 &adc_gain_cal_single_sample;
584 ah->adcdc_caldata.calData =
585 &adc_dc_cal_single_sample;
586 ah->adcdc_calinitdata.calData =
587 &adc_init_dc_cal;
588 } else {
589 ah->iq_caldata.calData = &iq_cal_multi_sample;
590 ah->adcgain_caldata.calData =
591 &adc_gain_cal_multi_sample;
592 ah->adcdc_caldata.calData =
593 &adc_dc_cal_multi_sample;
594 ah->adcdc_calinitdata.calData =
595 &adc_init_dc_cal;
596 }
597 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
598 }
599 }
600
601 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
602 {
603 if (AR_SREV_9271(ah)) {
604 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
605 ARRAY_SIZE(ar9271Modes_9271), 6);
606 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
607 ARRAY_SIZE(ar9271Common_9271), 2);
608 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
609 ar9271Common_normal_cck_fir_coeff_9271,
610 ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
611 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
612 ar9271Common_japan_2484_cck_fir_coeff_9271,
613 ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
614 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
615 ar9271Modes_9271_1_0_only,
616 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
617 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
618 ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
619 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
620 ar9271Modes_high_power_tx_gain_9271,
621 ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
622 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
623 ar9271Modes_normal_power_tx_gain_9271,
624 ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
625 return;
626 }
627
628 if (AR_SREV_9287_11_OR_LATER(ah)) {
629 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
630 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
631 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
632 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
633 if (ah->config.pcie_clock_req)
634 INIT_INI_ARRAY(&ah->iniPcieSerdes,
635 ar9287PciePhy_clkreq_off_L1_9287_1_1,
636 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
637 else
638 INIT_INI_ARRAY(&ah->iniPcieSerdes,
639 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
640 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
641 2);
642 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
643 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
644 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
645 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
646 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
647
648 if (ah->config.pcie_clock_req)
649 INIT_INI_ARRAY(&ah->iniPcieSerdes,
650 ar9287PciePhy_clkreq_off_L1_9287_1_0,
651 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
652 else
653 INIT_INI_ARRAY(&ah->iniPcieSerdes,
654 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
655 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
656 2);
657 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
658
659
660 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
661 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
662 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
663 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
664
665 if (ah->config.pcie_clock_req) {
666 INIT_INI_ARRAY(&ah->iniPcieSerdes,
667 ar9285PciePhy_clkreq_off_L1_9285_1_2,
668 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
669 } else {
670 INIT_INI_ARRAY(&ah->iniPcieSerdes,
671 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
672 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
673 2);
674 }
675 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
676 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
677 ARRAY_SIZE(ar9285Modes_9285), 6);
678 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
679 ARRAY_SIZE(ar9285Common_9285), 2);
680
681 if (ah->config.pcie_clock_req) {
682 INIT_INI_ARRAY(&ah->iniPcieSerdes,
683 ar9285PciePhy_clkreq_off_L1_9285,
684 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
685 } else {
686 INIT_INI_ARRAY(&ah->iniPcieSerdes,
687 ar9285PciePhy_clkreq_always_on_L1_9285,
688 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
689 }
690 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
691 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
692 ARRAY_SIZE(ar9280Modes_9280_2), 6);
693 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
694 ARRAY_SIZE(ar9280Common_9280_2), 2);
695
696 if (ah->config.pcie_clock_req) {
697 INIT_INI_ARRAY(&ah->iniPcieSerdes,
698 ar9280PciePhy_clkreq_off_L1_9280,
699 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
700 } else {
701 INIT_INI_ARRAY(&ah->iniPcieSerdes,
702 ar9280PciePhy_clkreq_always_on_L1_9280,
703 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
704 }
705 INIT_INI_ARRAY(&ah->iniModesAdditional,
706 ar9280Modes_fast_clock_9280_2,
707 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
708 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
709 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
710 ARRAY_SIZE(ar9280Modes_9280), 6);
711 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
712 ARRAY_SIZE(ar9280Common_9280), 2);
713 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
714 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
715 ARRAY_SIZE(ar5416Modes_9160), 6);
716 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
717 ARRAY_SIZE(ar5416Common_9160), 2);
718 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
719 ARRAY_SIZE(ar5416Bank0_9160), 2);
720 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
721 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
722 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
723 ARRAY_SIZE(ar5416Bank1_9160), 2);
724 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
725 ARRAY_SIZE(ar5416Bank2_9160), 2);
726 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
727 ARRAY_SIZE(ar5416Bank3_9160), 3);
728 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
729 ARRAY_SIZE(ar5416Bank6_9160), 3);
730 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
731 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
732 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
733 ARRAY_SIZE(ar5416Bank7_9160), 2);
734 if (AR_SREV_9160_11(ah)) {
735 INIT_INI_ARRAY(&ah->iniAddac,
736 ar5416Addac_91601_1,
737 ARRAY_SIZE(ar5416Addac_91601_1), 2);
738 } else {
739 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
740 ARRAY_SIZE(ar5416Addac_9160), 2);
741 }
742 } else if (AR_SREV_9100_OR_LATER(ah)) {
743 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
744 ARRAY_SIZE(ar5416Modes_9100), 6);
745 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
746 ARRAY_SIZE(ar5416Common_9100), 2);
747 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
748 ARRAY_SIZE(ar5416Bank0_9100), 2);
749 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
750 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
751 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
752 ARRAY_SIZE(ar5416Bank1_9100), 2);
753 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
754 ARRAY_SIZE(ar5416Bank2_9100), 2);
755 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
756 ARRAY_SIZE(ar5416Bank3_9100), 3);
757 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
758 ARRAY_SIZE(ar5416Bank6_9100), 3);
759 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
760 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
761 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
762 ARRAY_SIZE(ar5416Bank7_9100), 2);
763 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
764 ARRAY_SIZE(ar5416Addac_9100), 2);
765 } else {
766 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
767 ARRAY_SIZE(ar5416Modes), 6);
768 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
769 ARRAY_SIZE(ar5416Common), 2);
770 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
771 ARRAY_SIZE(ar5416Bank0), 2);
772 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
773 ARRAY_SIZE(ar5416BB_RfGain), 3);
774 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
775 ARRAY_SIZE(ar5416Bank1), 2);
776 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
777 ARRAY_SIZE(ar5416Bank2), 2);
778 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
779 ARRAY_SIZE(ar5416Bank3), 3);
780 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
781 ARRAY_SIZE(ar5416Bank6), 3);
782 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
783 ARRAY_SIZE(ar5416Bank6TPC), 3);
784 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
785 ARRAY_SIZE(ar5416Bank7), 2);
786 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
787 ARRAY_SIZE(ar5416Addac), 2);
788 }
789 }
790
791 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
792 {
793 if (AR_SREV_9287_11_OR_LATER(ah))
794 INIT_INI_ARRAY(&ah->iniModesRxGain,
795 ar9287Modes_rx_gain_9287_1_1,
796 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
797 else if (AR_SREV_9287_10(ah))
798 INIT_INI_ARRAY(&ah->iniModesRxGain,
799 ar9287Modes_rx_gain_9287_1_0,
800 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
801 else if (AR_SREV_9280_20(ah))
802 ath9k_hw_init_rxgain_ini(ah);
803
804 if (AR_SREV_9287_11_OR_LATER(ah)) {
805 INIT_INI_ARRAY(&ah->iniModesTxGain,
806 ar9287Modes_tx_gain_9287_1_1,
807 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
808 } else if (AR_SREV_9287_10(ah)) {
809 INIT_INI_ARRAY(&ah->iniModesTxGain,
810 ar9287Modes_tx_gain_9287_1_0,
811 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
812 } else if (AR_SREV_9280_20(ah)) {
813 ath9k_hw_init_txgain_ini(ah);
814 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
815 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
816
817 /* txgain table */
818 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
819 INIT_INI_ARRAY(&ah->iniModesTxGain,
820 ar9285Modes_high_power_tx_gain_9285_1_2,
821 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
822 } else {
823 INIT_INI_ARRAY(&ah->iniModesTxGain,
824 ar9285Modes_original_tx_gain_9285_1_2,
825 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
826 }
827
828 }
829 }
830
831 static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
832 {
833 u32 i, j;
834
835 if (ah->hw_version.devid == AR9280_DEVID_PCI) {
836
837 /* EEPROM Fixup */
838 for (i = 0; i < ah->iniModes.ia_rows; i++) {
839 u32 reg = INI_RA(&ah->iniModes, i, 0);
840
841 for (j = 1; j < ah->iniModes.ia_columns; j++) {
842 u32 val = INI_RA(&ah->iniModes, i, j);
843
844 INI_RA(&ah->iniModes, i, j) =
845 ath9k_hw_ini_fixup(ah,
846 &ah->eeprom.def,
847 reg, val);
848 }
849 }
850 }
851 }
852
853 int ath9k_hw_init(struct ath_hw *ah)
854 {
855 struct ath_common *common = ath9k_hw_common(ah);
856 int r = 0;
857
858 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
859 ath_print(common, ATH_DBG_FATAL,
860 "Unsupported device ID: 0x%0x\n",
861 ah->hw_version.devid);
862 return -EOPNOTSUPP;
863 }
864
865 ath9k_hw_init_defaults(ah);
866 ath9k_hw_init_config(ah);
867
868 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
869 ath_print(common, ATH_DBG_FATAL,
870 "Couldn't reset chip\n");
871 return -EIO;
872 }
873
874 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
875 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
876 return -EIO;
877 }
878
879 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
880 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
881 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
882 ah->config.serialize_regmode =
883 SER_REG_MODE_ON;
884 } else {
885 ah->config.serialize_regmode =
886 SER_REG_MODE_OFF;
887 }
888 }
889
890 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
891 ah->config.serialize_regmode);
892
893 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
894 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
895 else
896 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
897
898 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
899 ath_print(common, ATH_DBG_FATAL,
900 "Mac Chip Rev 0x%02x.%x is not supported by "
901 "this driver\n", ah->hw_version.macVersion,
902 ah->hw_version.macRev);
903 return -EOPNOTSUPP;
904 }
905
906 if (AR_SREV_9100(ah)) {
907 ah->iq_caldata.calData = &iq_cal_multi_sample;
908 ah->supp_cals = IQ_MISMATCH_CAL;
909 ah->is_pciexpress = false;
910 }
911
912 if (AR_SREV_9271(ah))
913 ah->is_pciexpress = false;
914
915 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
916
917 ath9k_hw_init_cal_settings(ah);
918
919 ah->ani_function = ATH9K_ANI_ALL;
920 if (AR_SREV_9280_10_OR_LATER(ah)) {
921 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
922 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
923 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
924 } else {
925 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
926 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
927 }
928
929 ath9k_hw_init_mode_regs(ah);
930
931 if (ah->is_pciexpress)
932 ath9k_hw_configpcipowersave(ah, 0, 0);
933 else
934 ath9k_hw_disablepcie(ah);
935
936 /* Support for Japan ch.14 (2484) spread */
937 if (AR_SREV_9287_11_OR_LATER(ah)) {
938 INIT_INI_ARRAY(&ah->iniCckfirNormal,
939 ar9287Common_normal_cck_fir_coeff_92871_1,
940 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
941 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
942 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
943 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
944 }
945
946 r = ath9k_hw_post_init(ah);
947 if (r)
948 return r;
949
950 ath9k_hw_init_mode_gain_regs(ah);
951 r = ath9k_hw_fill_cap_info(ah);
952 if (r)
953 return r;
954
955 ath9k_hw_init_eeprom_fix(ah);
956
957 r = ath9k_hw_init_macaddr(ah);
958 if (r) {
959 ath_print(common, ATH_DBG_FATAL,
960 "Failed to initialize MAC address\n");
961 return r;
962 }
963
964 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
965 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
966 else
967 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
968
969 ath9k_init_nfcal_hist_buffer(ah);
970
971 common->state = ATH_HW_INITIALIZED;
972
973 return 0;
974 }
975
976 static void ath9k_hw_init_bb(struct ath_hw *ah,
977 struct ath9k_channel *chan)
978 {
979 u32 synthDelay;
980
981 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
982 if (IS_CHAN_B(chan))
983 synthDelay = (4 * synthDelay) / 22;
984 else
985 synthDelay /= 10;
986
987 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
988
989 udelay(synthDelay + BASE_ACTIVATE_DELAY);
990 }
991
992 static void ath9k_hw_init_qos(struct ath_hw *ah)
993 {
994 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
995 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
996
997 REG_WRITE(ah, AR_QOS_NO_ACK,
998 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
999 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1000 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1001
1002 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1003 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1004 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1005 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1006 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1007 }
1008
1009 static void ath9k_hw_init_pll(struct ath_hw *ah,
1010 struct ath9k_channel *chan)
1011 {
1012 u32 pll;
1013
1014 if (AR_SREV_9100(ah)) {
1015 if (chan && IS_CHAN_5GHZ(chan))
1016 pll = 0x1450;
1017 else
1018 pll = 0x1458;
1019 } else {
1020 if (AR_SREV_9280_10_OR_LATER(ah)) {
1021 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1022
1023 if (chan && IS_CHAN_HALF_RATE(chan))
1024 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1025 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1026 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1027
1028 if (chan && IS_CHAN_5GHZ(chan)) {
1029 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1030
1031
1032 if (AR_SREV_9280_20(ah)) {
1033 if (((chan->channel % 20) == 0)
1034 || ((chan->channel % 10) == 0))
1035 pll = 0x2850;
1036 else
1037 pll = 0x142c;
1038 }
1039 } else {
1040 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1041 }
1042
1043 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1044
1045 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1046
1047 if (chan && IS_CHAN_HALF_RATE(chan))
1048 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1049 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1050 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1051
1052 if (chan && IS_CHAN_5GHZ(chan))
1053 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1054 else
1055 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1056 } else {
1057 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1058
1059 if (chan && IS_CHAN_HALF_RATE(chan))
1060 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1061 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1062 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1063
1064 if (chan && IS_CHAN_5GHZ(chan))
1065 pll |= SM(0xa, AR_RTC_PLL_DIV);
1066 else
1067 pll |= SM(0xb, AR_RTC_PLL_DIV);
1068 }
1069 }
1070 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1071
1072 /* Switch the core clock for ar9271 to 117Mhz */
1073 if (AR_SREV_9271(ah)) {
1074 udelay(500);
1075 REG_WRITE(ah, 0x50040, 0x304);
1076 }
1077
1078 udelay(RTC_PLL_SETTLE_DELAY);
1079
1080 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1081 }
1082
1083 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1084 {
1085 int rx_chainmask, tx_chainmask;
1086
1087 rx_chainmask = ah->rxchainmask;
1088 tx_chainmask = ah->txchainmask;
1089
1090 switch (rx_chainmask) {
1091 case 0x5:
1092 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1093 AR_PHY_SWAP_ALT_CHAIN);
1094 case 0x3:
1095 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1096 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1097 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1098 break;
1099 }
1100 case 0x1:
1101 case 0x2:
1102 case 0x7:
1103 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1104 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1105 break;
1106 default:
1107 break;
1108 }
1109
1110 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1111 if (tx_chainmask == 0x5) {
1112 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1113 AR_PHY_SWAP_ALT_CHAIN);
1114 }
1115 if (AR_SREV_9100(ah))
1116 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1117 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1118 }
1119
1120 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1121 enum nl80211_iftype opmode)
1122 {
1123 u32 imr_reg = AR_IMR_TXERR |
1124 AR_IMR_TXURN |
1125 AR_IMR_RXERR |
1126 AR_IMR_RXORN |
1127 AR_IMR_BCNMISC;
1128
1129 if (ah->config.rx_intr_mitigation)
1130 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1131 else
1132 imr_reg |= AR_IMR_RXOK;
1133
1134 imr_reg |= AR_IMR_TXOK;
1135
1136 if (opmode == NL80211_IFTYPE_AP)
1137 imr_reg |= AR_IMR_MIB;
1138
1139 REG_WRITE(ah, AR_IMR, imr_reg);
1140 ah->imrs2_reg |= AR_IMR_S2_GTT;
1141 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
1142
1143 if (!AR_SREV_9100(ah)) {
1144 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1145 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1146 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1147 }
1148 }
1149
1150 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1151 {
1152 u32 val = ath9k_hw_mac_to_clks(ah, us);
1153 val = min(val, (u32) 0xFFFF);
1154 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1155 }
1156
1157 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1158 {
1159 u32 val = ath9k_hw_mac_to_clks(ah, us);
1160 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1161 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1162 }
1163
1164 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1165 {
1166 u32 val = ath9k_hw_mac_to_clks(ah, us);
1167 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1168 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1169 }
1170
1171 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1172 {
1173 if (tu > 0xFFFF) {
1174 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1175 "bad global tx timeout %u\n", tu);
1176 ah->globaltxtimeout = (u32) -1;
1177 return false;
1178 } else {
1179 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1180 ah->globaltxtimeout = tu;
1181 return true;
1182 }
1183 }
1184
1185 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1186 {
1187 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
1188 int acktimeout;
1189 int slottime;
1190 int sifstime;
1191
1192 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1193 ah->misc_mode);
1194
1195 if (ah->misc_mode != 0)
1196 REG_WRITE(ah, AR_PCU_MISC,
1197 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1198
1199 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
1200 sifstime = 16;
1201 else
1202 sifstime = 10;
1203
1204 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1205 slottime = ah->slottime + 3 * ah->coverage_class;
1206 acktimeout = slottime + sifstime;
1207
1208 /*
1209 * Workaround for early ACK timeouts, add an offset to match the
1210 * initval's 64us ack timeout value.
1211 * This was initially only meant to work around an issue with delayed
1212 * BA frames in some implementations, but it has been found to fix ACK
1213 * timeout issues in other cases as well.
1214 */
1215 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1216 acktimeout += 64 - sifstime - ah->slottime;
1217
1218 ath9k_hw_setslottime(ah, slottime);
1219 ath9k_hw_set_ack_timeout(ah, acktimeout);
1220 ath9k_hw_set_cts_timeout(ah, acktimeout);
1221 if (ah->globaltxtimeout != (u32) -1)
1222 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1223 }
1224 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1225
1226 void ath9k_hw_deinit(struct ath_hw *ah)
1227 {
1228 struct ath_common *common = ath9k_hw_common(ah);
1229
1230 if (common->state < ATH_HW_INITIALIZED)
1231 goto free_hw;
1232
1233 if (!AR_SREV_9100(ah))
1234 ath9k_hw_ani_disable(ah);
1235
1236 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1237
1238 free_hw:
1239 if (!AR_SREV_9280_10_OR_LATER(ah))
1240 ath9k_hw_rf_free_ext_banks(ah);
1241 }
1242 EXPORT_SYMBOL(ath9k_hw_deinit);
1243
1244 /*******/
1245 /* INI */
1246 /*******/
1247
1248 static void ath9k_hw_override_ini(struct ath_hw *ah,
1249 struct ath9k_channel *chan)
1250 {
1251 u32 val;
1252
1253 /*
1254 * Set the RX_ABORT and RX_DIS and clear if off only after
1255 * RXE is set for MAC. This prevents frames with corrupted
1256 * descriptor status.
1257 */
1258 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1259
1260 if (AR_SREV_9280_10_OR_LATER(ah)) {
1261 val = REG_READ(ah, AR_PCU_MISC_MODE2);
1262
1263 if (!AR_SREV_9271(ah))
1264 val &= ~AR_PCU_MISC_MODE2_HWWAR1;
1265
1266 if (AR_SREV_9287_10_OR_LATER(ah))
1267 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1268
1269 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1270 }
1271
1272 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1273 AR_SREV_9280_10_OR_LATER(ah))
1274 return;
1275 /*
1276 * Disable BB clock gating
1277 * Necessary to avoid issues on AR5416 2.0
1278 */
1279 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1280
1281 /*
1282 * Disable RIFS search on some chips to avoid baseband
1283 * hang issues.
1284 */
1285 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
1286 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
1287 val &= ~AR_PHY_RIFS_INIT_DELAY;
1288 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
1289 }
1290 }
1291
1292 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1293 struct ar5416_eeprom_def *pEepData,
1294 u32 reg, u32 value)
1295 {
1296 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1297 struct ath_common *common = ath9k_hw_common(ah);
1298
1299 switch (ah->hw_version.devid) {
1300 case AR9280_DEVID_PCI:
1301 if (reg == 0x7894) {
1302 ath_print(common, ATH_DBG_EEPROM,
1303 "ini VAL: %x EEPROM: %x\n", value,
1304 (pBase->version & 0xff));
1305
1306 if ((pBase->version & 0xff) > 0x0a) {
1307 ath_print(common, ATH_DBG_EEPROM,
1308 "PWDCLKIND: %d\n",
1309 pBase->pwdclkind);
1310 value &= ~AR_AN_TOP2_PWDCLKIND;
1311 value |= AR_AN_TOP2_PWDCLKIND &
1312 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1313 } else {
1314 ath_print(common, ATH_DBG_EEPROM,
1315 "PWDCLKIND Earlier Rev\n");
1316 }
1317
1318 ath_print(common, ATH_DBG_EEPROM,
1319 "final ini VAL: %x\n", value);
1320 }
1321 break;
1322 }
1323
1324 return value;
1325 }
1326
1327 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1328 struct ar5416_eeprom_def *pEepData,
1329 u32 reg, u32 value)
1330 {
1331 if (ah->eep_map == EEP_MAP_4KBITS)
1332 return value;
1333 else
1334 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1335 }
1336
1337 static void ath9k_olc_init(struct ath_hw *ah)
1338 {
1339 u32 i;
1340
1341 if (OLC_FOR_AR9287_10_LATER) {
1342 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1343 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1344 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1345 AR9287_AN_TXPC0_TXPCMODE,
1346 AR9287_AN_TXPC0_TXPCMODE_S,
1347 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1348 udelay(100);
1349 } else {
1350 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1351 ah->originalGain[i] =
1352 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1353 AR_PHY_TX_GAIN);
1354 ah->PDADCdelta = 0;
1355 }
1356 }
1357
1358 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1359 struct ath9k_channel *chan)
1360 {
1361 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1362
1363 if (IS_CHAN_B(chan))
1364 ctl |= CTL_11B;
1365 else if (IS_CHAN_G(chan))
1366 ctl |= CTL_11G;
1367 else
1368 ctl |= CTL_11A;
1369
1370 return ctl;
1371 }
1372
1373 static int ath9k_hw_process_ini(struct ath_hw *ah,
1374 struct ath9k_channel *chan)
1375 {
1376 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1377 int i, regWrites = 0;
1378 struct ieee80211_channel *channel = chan->chan;
1379 u32 modesIndex, freqIndex;
1380
1381 switch (chan->chanmode) {
1382 case CHANNEL_A:
1383 case CHANNEL_A_HT20:
1384 modesIndex = 1;
1385 freqIndex = 1;
1386 break;
1387 case CHANNEL_A_HT40PLUS:
1388 case CHANNEL_A_HT40MINUS:
1389 modesIndex = 2;
1390 freqIndex = 1;
1391 break;
1392 case CHANNEL_G:
1393 case CHANNEL_G_HT20:
1394 case CHANNEL_B:
1395 modesIndex = 4;
1396 freqIndex = 2;
1397 break;
1398 case CHANNEL_G_HT40PLUS:
1399 case CHANNEL_G_HT40MINUS:
1400 modesIndex = 3;
1401 freqIndex = 2;
1402 break;
1403
1404 default:
1405 return -EINVAL;
1406 }
1407
1408 /* Set correct baseband to analog shift setting to access analog chips */
1409 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1410
1411 /* Write ADDAC shifts */
1412 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1413 ah->eep_ops->set_addac(ah, chan);
1414
1415 if (AR_SREV_5416_22_OR_LATER(ah)) {
1416 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1417 } else {
1418 struct ar5416IniArray temp;
1419 u32 addacSize =
1420 sizeof(u32) * ah->iniAddac.ia_rows *
1421 ah->iniAddac.ia_columns;
1422
1423 /* For AR5416 2.0/2.1 */
1424 memcpy(ah->addac5416_21,
1425 ah->iniAddac.ia_array, addacSize);
1426
1427 /* override CLKDRV value at [row, column] = [31, 1] */
1428 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1429
1430 temp.ia_array = ah->addac5416_21;
1431 temp.ia_columns = ah->iniAddac.ia_columns;
1432 temp.ia_rows = ah->iniAddac.ia_rows;
1433 REG_WRITE_ARRAY(&temp, 1, regWrites);
1434 }
1435
1436 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1437
1438 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1439 u32 reg = INI_RA(&ah->iniModes, i, 0);
1440 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1441
1442 REG_WRITE(ah, reg, val);
1443
1444 if (reg >= 0x7800 && reg < 0x78a0
1445 && ah->config.analog_shiftreg) {
1446 udelay(100);
1447 }
1448
1449 DO_DELAY(regWrites);
1450 }
1451
1452 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1453 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1454
1455 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1456 AR_SREV_9287_10_OR_LATER(ah))
1457 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1458
1459 if (AR_SREV_9271_10(ah))
1460 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1461 modesIndex, regWrites);
1462
1463 /* Write common array parameters */
1464 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1465 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1466 u32 val = INI_RA(&ah->iniCommon, i, 1);
1467
1468 REG_WRITE(ah, reg, val);
1469
1470 if (reg >= 0x7800 && reg < 0x78a0
1471 && ah->config.analog_shiftreg) {
1472 udelay(100);
1473 }
1474
1475 DO_DELAY(regWrites);
1476 }
1477
1478 if (AR_SREV_9271(ah)) {
1479 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
1480 REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
1481 modesIndex, regWrites);
1482 else
1483 REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
1484 modesIndex, regWrites);
1485 }
1486
1487 ath9k_hw_write_regs(ah, freqIndex, regWrites);
1488
1489 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1490 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1491 regWrites);
1492 }
1493
1494 ath9k_hw_override_ini(ah, chan);
1495 ath9k_hw_set_regs(ah, chan);
1496 ath9k_hw_init_chain_masks(ah);
1497
1498 if (OLC_FOR_AR9280_20_LATER)
1499 ath9k_olc_init(ah);
1500
1501 /* Set TX power */
1502 ah->eep_ops->set_txpower(ah, chan,
1503 ath9k_regd_get_ctl(regulatory, chan),
1504 channel->max_antenna_gain * 2,
1505 channel->max_power * 2,
1506 min((u32) MAX_RATE_POWER,
1507 (u32) regulatory->power_limit));
1508
1509 /* Write analog registers */
1510 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1511 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1512 "ar5416SetRfRegs failed\n");
1513 return -EIO;
1514 }
1515
1516 return 0;
1517 }
1518
1519 /****************************************/
1520 /* Reset and Channel Switching Routines */
1521 /****************************************/
1522
1523 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1524 {
1525 u32 rfMode = 0;
1526
1527 if (chan == NULL)
1528 return;
1529
1530 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1531 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1532
1533 if (!AR_SREV_9280_10_OR_LATER(ah))
1534 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1535 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1536
1537 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1538 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1539
1540 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1541 }
1542
1543 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1544 {
1545 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1546 }
1547
1548 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1549 {
1550 u32 regval;
1551
1552 /*
1553 * set AHB_MODE not to do cacheline prefetches
1554 */
1555 regval = REG_READ(ah, AR_AHB_MODE);
1556 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1557
1558 /*
1559 * let mac dma reads be in 128 byte chunks
1560 */
1561 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1562 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1563
1564 /*
1565 * Restore TX Trigger Level to its pre-reset value.
1566 * The initial value depends on whether aggregation is enabled, and is
1567 * adjusted whenever underruns are detected.
1568 */
1569 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1570
1571 /*
1572 * let mac dma writes be in 128 byte chunks
1573 */
1574 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1575 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1576
1577 /*
1578 * Setup receive FIFO threshold to hold off TX activities
1579 */
1580 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1581
1582 /*
1583 * reduce the number of usable entries in PCU TXBUF to avoid
1584 * wrap around issues.
1585 */
1586 if (AR_SREV_9285(ah)) {
1587 /* For AR9285 the number of Fifos are reduced to half.
1588 * So set the usable tx buf size also to half to
1589 * avoid data/delimiter underruns
1590 */
1591 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1592 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1593 } else if (!AR_SREV_9271(ah)) {
1594 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1595 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1596 }
1597 }
1598
1599 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1600 {
1601 u32 val;
1602
1603 val = REG_READ(ah, AR_STA_ID1);
1604 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1605 switch (opmode) {
1606 case NL80211_IFTYPE_AP:
1607 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1608 | AR_STA_ID1_KSRCH_MODE);
1609 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1610 break;
1611 case NL80211_IFTYPE_ADHOC:
1612 case NL80211_IFTYPE_MESH_POINT:
1613 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1614 | AR_STA_ID1_KSRCH_MODE);
1615 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1616 break;
1617 case NL80211_IFTYPE_STATION:
1618 case NL80211_IFTYPE_MONITOR:
1619 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1620 break;
1621 }
1622 }
1623
1624 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1625 u32 coef_scaled,
1626 u32 *coef_mantissa,
1627 u32 *coef_exponent)
1628 {
1629 u32 coef_exp, coef_man;
1630
1631 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1632 if ((coef_scaled >> coef_exp) & 0x1)
1633 break;
1634
1635 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1636
1637 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1638
1639 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1640 *coef_exponent = coef_exp - 16;
1641 }
1642
1643 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1644 struct ath9k_channel *chan)
1645 {
1646 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1647 u32 clockMhzScaled = 0x64000000;
1648 struct chan_centers centers;
1649
1650 if (IS_CHAN_HALF_RATE(chan))
1651 clockMhzScaled = clockMhzScaled >> 1;
1652 else if (IS_CHAN_QUARTER_RATE(chan))
1653 clockMhzScaled = clockMhzScaled >> 2;
1654
1655 ath9k_hw_get_channel_centers(ah, chan, &centers);
1656 coef_scaled = clockMhzScaled / centers.synth_center;
1657
1658 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1659 &ds_coef_exp);
1660
1661 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1662 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1663 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1664 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1665
1666 coef_scaled = (9 * coef_scaled) / 10;
1667
1668 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1669 &ds_coef_exp);
1670
1671 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1672 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1673 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1674 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1675 }
1676
1677 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1678 {
1679 u32 rst_flags;
1680 u32 tmpReg;
1681
1682 if (AR_SREV_9100(ah)) {
1683 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1684 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1685 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1686 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1687 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1688 }
1689
1690 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1691 AR_RTC_FORCE_WAKE_ON_INT);
1692
1693 if (AR_SREV_9100(ah)) {
1694 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1695 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1696 } else {
1697 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1698 if (tmpReg &
1699 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1700 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1701 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1702 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1703 } else {
1704 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1705 }
1706
1707 rst_flags = AR_RTC_RC_MAC_WARM;
1708 if (type == ATH9K_RESET_COLD)
1709 rst_flags |= AR_RTC_RC_MAC_COLD;
1710 }
1711
1712 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1713 udelay(50);
1714
1715 REG_WRITE(ah, AR_RTC_RC, 0);
1716 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1717 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1718 "RTC stuck in MAC reset\n");
1719 return false;
1720 }
1721
1722 if (!AR_SREV_9100(ah))
1723 REG_WRITE(ah, AR_RC, 0);
1724
1725 if (AR_SREV_9100(ah))
1726 udelay(50);
1727
1728 return true;
1729 }
1730
1731 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1732 {
1733 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1734 AR_RTC_FORCE_WAKE_ON_INT);
1735
1736 if (!AR_SREV_9100(ah))
1737 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1738
1739 REG_WRITE(ah, AR_RTC_RESET, 0);
1740 udelay(2);
1741
1742 if (!AR_SREV_9100(ah))
1743 REG_WRITE(ah, AR_RC, 0);
1744
1745 REG_WRITE(ah, AR_RTC_RESET, 1);
1746
1747 if (!ath9k_hw_wait(ah,
1748 AR_RTC_STATUS,
1749 AR_RTC_STATUS_M,
1750 AR_RTC_STATUS_ON,
1751 AH_WAIT_TIMEOUT)) {
1752 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1753 "RTC not waking up\n");
1754 return false;
1755 }
1756
1757 ath9k_hw_read_revisions(ah);
1758
1759 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1760 }
1761
1762 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1763 {
1764 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1765 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1766
1767 switch (type) {
1768 case ATH9K_RESET_POWER_ON:
1769 return ath9k_hw_set_reset_power_on(ah);
1770 case ATH9K_RESET_WARM:
1771 case ATH9K_RESET_COLD:
1772 return ath9k_hw_set_reset(ah, type);
1773 default:
1774 return false;
1775 }
1776 }
1777
1778 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1779 {
1780 u32 phymode;
1781 u32 enableDacFifo = 0;
1782
1783 if (AR_SREV_9285_10_OR_LATER(ah))
1784 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1785 AR_PHY_FC_ENABLE_DAC_FIFO);
1786
1787 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1788 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1789
1790 if (IS_CHAN_HT40(chan)) {
1791 phymode |= AR_PHY_FC_DYN2040_EN;
1792
1793 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1794 (chan->chanmode == CHANNEL_G_HT40PLUS))
1795 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1796
1797 }
1798 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1799
1800 ath9k_hw_set11nmac2040(ah);
1801
1802 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1803 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1804 }
1805
1806 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1807 struct ath9k_channel *chan)
1808 {
1809 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1810 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1811 return false;
1812 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1813 return false;
1814
1815 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1816 return false;
1817
1818 ah->chip_fullsleep = false;
1819 ath9k_hw_init_pll(ah, chan);
1820 ath9k_hw_set_rfmode(ah, chan);
1821
1822 return true;
1823 }
1824
1825 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1826 struct ath9k_channel *chan)
1827 {
1828 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1829 struct ath_common *common = ath9k_hw_common(ah);
1830 struct ieee80211_channel *channel = chan->chan;
1831 u32 synthDelay, qnum;
1832 int r;
1833
1834 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1835 if (ath9k_hw_numtxpending(ah, qnum)) {
1836 ath_print(common, ATH_DBG_QUEUE,
1837 "Transmit frames pending on "
1838 "queue %d\n", qnum);
1839 return false;
1840 }
1841 }
1842
1843 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1844 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1845 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1846 ath_print(common, ATH_DBG_FATAL,
1847 "Could not kill baseband RX\n");
1848 return false;
1849 }
1850
1851 ath9k_hw_set_regs(ah, chan);
1852
1853 r = ah->ath9k_hw_rf_set_freq(ah, chan);
1854 if (r) {
1855 ath_print(common, ATH_DBG_FATAL,
1856 "Failed to set channel\n");
1857 return false;
1858 }
1859
1860 ah->eep_ops->set_txpower(ah, chan,
1861 ath9k_regd_get_ctl(regulatory, chan),
1862 channel->max_antenna_gain * 2,
1863 channel->max_power * 2,
1864 min((u32) MAX_RATE_POWER,
1865 (u32) regulatory->power_limit));
1866
1867 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1868 if (IS_CHAN_B(chan))
1869 synthDelay = (4 * synthDelay) / 22;
1870 else
1871 synthDelay /= 10;
1872
1873 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1874
1875 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1876
1877 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1878 ath9k_hw_set_delta_slope(ah, chan);
1879
1880 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
1881
1882 if (!chan->oneTimeCalsDone)
1883 chan->oneTimeCalsDone = true;
1884
1885 return true;
1886 }
1887
1888 static void ath9k_enable_rfkill(struct ath_hw *ah)
1889 {
1890 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1891 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1892
1893 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1894 AR_GPIO_INPUT_MUX2_RFSILENT);
1895
1896 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1897 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1898 }
1899
1900 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1901 bool bChannelChange)
1902 {
1903 struct ath_common *common = ath9k_hw_common(ah);
1904 u32 saveLedState;
1905 struct ath9k_channel *curchan = ah->curchan;
1906 u32 saveDefAntenna;
1907 u32 macStaId1;
1908 u64 tsf = 0;
1909 int i, rx_chainmask, r;
1910
1911 ah->txchainmask = common->tx_chainmask;
1912 ah->rxchainmask = common->rx_chainmask;
1913
1914 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1915 return -EIO;
1916
1917 if (curchan && !ah->chip_fullsleep)
1918 ath9k_hw_getnf(ah, curchan);
1919
1920 if (bChannelChange &&
1921 (ah->chip_fullsleep != true) &&
1922 (ah->curchan != NULL) &&
1923 (chan->channel != ah->curchan->channel) &&
1924 ((chan->channelFlags & CHANNEL_ALL) ==
1925 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1926 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1927 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1928
1929 if (ath9k_hw_channel_change(ah, chan)) {
1930 ath9k_hw_loadnf(ah, ah->curchan);
1931 ath9k_hw_start_nfcal(ah);
1932 return 0;
1933 }
1934 }
1935
1936 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1937 if (saveDefAntenna == 0)
1938 saveDefAntenna = 1;
1939
1940 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1941
1942 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1943 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1944 tsf = ath9k_hw_gettsf64(ah);
1945
1946 saveLedState = REG_READ(ah, AR_CFG_LED) &
1947 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1948 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1949
1950 ath9k_hw_mark_phy_inactive(ah);
1951
1952 /* Only required on the first reset */
1953 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1954 REG_WRITE(ah,
1955 AR9271_RESET_POWER_DOWN_CONTROL,
1956 AR9271_RADIO_RF_RST);
1957 udelay(50);
1958 }
1959
1960 if (!ath9k_hw_chip_reset(ah, chan)) {
1961 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1962 return -EINVAL;
1963 }
1964
1965 /* Only required on the first reset */
1966 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1967 ah->htc_reset_init = false;
1968 REG_WRITE(ah,
1969 AR9271_RESET_POWER_DOWN_CONTROL,
1970 AR9271_GATE_MAC_CTL);
1971 udelay(50);
1972 }
1973
1974 /* Restore TSF */
1975 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1976 ath9k_hw_settsf64(ah, tsf);
1977
1978 if (AR_SREV_9280_10_OR_LATER(ah))
1979 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1980
1981 if (AR_SREV_9287_12_OR_LATER(ah)) {
1982 /* Enable ASYNC FIFO */
1983 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1984 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
1985 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
1986 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1987 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1988 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1989 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1990 }
1991 r = ath9k_hw_process_ini(ah, chan);
1992 if (r)
1993 return r;
1994
1995 /* Setup MFP options for CCMP */
1996 if (AR_SREV_9280_20_OR_LATER(ah)) {
1997 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1998 * frames when constructing CCMP AAD. */
1999 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2000 0xc7ff);
2001 ah->sw_mgmt_crypto = false;
2002 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2003 /* Disable hardware crypto for management frames */
2004 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2005 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2006 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2007 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2008 ah->sw_mgmt_crypto = true;
2009 } else
2010 ah->sw_mgmt_crypto = true;
2011
2012 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2013 ath9k_hw_set_delta_slope(ah, chan);
2014
2015 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
2016 ah->eep_ops->set_board_values(ah, chan);
2017
2018 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2019 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2020 | macStaId1
2021 | AR_STA_ID1_RTS_USE_DEF
2022 | (ah->config.
2023 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2024 | ah->sta_id1_defaults);
2025 ath9k_hw_set_operating_mode(ah, ah->opmode);
2026
2027 ath_hw_setbssidmask(common);
2028
2029 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2030
2031 ath9k_hw_write_associd(ah);
2032
2033 REG_WRITE(ah, AR_ISR, ~0);
2034
2035 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2036
2037 r = ah->ath9k_hw_rf_set_freq(ah, chan);
2038 if (r)
2039 return r;
2040
2041 for (i = 0; i < AR_NUM_DCU; i++)
2042 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2043
2044 ah->intr_txqs = 0;
2045 for (i = 0; i < ah->caps.total_queues; i++)
2046 ath9k_hw_resettxqueue(ah, i);
2047
2048 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2049 ath9k_hw_init_qos(ah);
2050
2051 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2052 ath9k_enable_rfkill(ah);
2053
2054 ath9k_hw_init_global_settings(ah);
2055
2056 if (AR_SREV_9287_12_OR_LATER(ah)) {
2057 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2058 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2059 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2060 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2061 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2062 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2063
2064 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2065 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2066
2067 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2068 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2069 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2070 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2071 }
2072 if (AR_SREV_9287_12_OR_LATER(ah)) {
2073 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2074 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2075 }
2076
2077 REG_WRITE(ah, AR_STA_ID1,
2078 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2079
2080 ath9k_hw_set_dma(ah);
2081
2082 REG_WRITE(ah, AR_OBS, 8);
2083
2084 if (ah->config.rx_intr_mitigation) {
2085 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2086 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2087 }
2088
2089 ath9k_hw_init_bb(ah, chan);
2090
2091 if (!ath9k_hw_init_cal(ah, chan))
2092 return -EIO;
2093
2094 rx_chainmask = ah->rxchainmask;
2095 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2096 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2097 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2098 }
2099
2100 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2101
2102 /*
2103 * For big endian systems turn on swapping for descriptors
2104 */
2105 if (AR_SREV_9100(ah)) {
2106 u32 mask;
2107 mask = REG_READ(ah, AR_CFG);
2108 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2109 ath_print(common, ATH_DBG_RESET,
2110 "CFG Byte Swap Set 0x%x\n", mask);
2111 } else {
2112 mask =
2113 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2114 REG_WRITE(ah, AR_CFG, mask);
2115 ath_print(common, ATH_DBG_RESET,
2116 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2117 }
2118 } else {
2119 /* Configure AR9271 target WLAN */
2120 if (AR_SREV_9271(ah))
2121 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2122 #ifdef __BIG_ENDIAN
2123 else
2124 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2125 #endif
2126 }
2127
2128 if (ah->btcoex_hw.enabled)
2129 ath9k_hw_btcoex_enable(ah);
2130
2131 return 0;
2132 }
2133 EXPORT_SYMBOL(ath9k_hw_reset);
2134
2135 /************************/
2136 /* Key Cache Management */
2137 /************************/
2138
2139 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2140 {
2141 u32 keyType;
2142
2143 if (entry >= ah->caps.keycache_size) {
2144 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2145 "keychache entry %u out of range\n", entry);
2146 return false;
2147 }
2148
2149 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2150
2151 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2152 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2153 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2154 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2155 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2156 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2157 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2158 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2159
2160 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2161 u16 micentry = entry + 64;
2162
2163 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2164 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2165 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2166 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2167
2168 }
2169
2170 return true;
2171 }
2172 EXPORT_SYMBOL(ath9k_hw_keyreset);
2173
2174 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2175 {
2176 u32 macHi, macLo;
2177
2178 if (entry >= ah->caps.keycache_size) {
2179 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2180 "keychache entry %u out of range\n", entry);
2181 return false;
2182 }
2183
2184 if (mac != NULL) {
2185 macHi = (mac[5] << 8) | mac[4];
2186 macLo = (mac[3] << 24) |
2187 (mac[2] << 16) |
2188 (mac[1] << 8) |
2189 mac[0];
2190 macLo >>= 1;
2191 macLo |= (macHi & 1) << 31;
2192 macHi >>= 1;
2193 } else {
2194 macLo = macHi = 0;
2195 }
2196 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2197 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2198
2199 return true;
2200 }
2201 EXPORT_SYMBOL(ath9k_hw_keysetmac);
2202
2203 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2204 const struct ath9k_keyval *k,
2205 const u8 *mac)
2206 {
2207 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2208 struct ath_common *common = ath9k_hw_common(ah);
2209 u32 key0, key1, key2, key3, key4;
2210 u32 keyType;
2211
2212 if (entry >= pCap->keycache_size) {
2213 ath_print(common, ATH_DBG_FATAL,
2214 "keycache entry %u out of range\n", entry);
2215 return false;
2216 }
2217
2218 switch (k->kv_type) {
2219 case ATH9K_CIPHER_AES_OCB:
2220 keyType = AR_KEYTABLE_TYPE_AES;
2221 break;
2222 case ATH9K_CIPHER_AES_CCM:
2223 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2224 ath_print(common, ATH_DBG_ANY,
2225 "AES-CCM not supported by mac rev 0x%x\n",
2226 ah->hw_version.macRev);
2227 return false;
2228 }
2229 keyType = AR_KEYTABLE_TYPE_CCM;
2230 break;
2231 case ATH9K_CIPHER_TKIP:
2232 keyType = AR_KEYTABLE_TYPE_TKIP;
2233 if (ATH9K_IS_MIC_ENABLED(ah)
2234 && entry + 64 >= pCap->keycache_size) {
2235 ath_print(common, ATH_DBG_ANY,
2236 "entry %u inappropriate for TKIP\n", entry);
2237 return false;
2238 }
2239 break;
2240 case ATH9K_CIPHER_WEP:
2241 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2242 ath_print(common, ATH_DBG_ANY,
2243 "WEP key length %u too small\n", k->kv_len);
2244 return false;
2245 }
2246 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2247 keyType = AR_KEYTABLE_TYPE_40;
2248 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2249 keyType = AR_KEYTABLE_TYPE_104;
2250 else
2251 keyType = AR_KEYTABLE_TYPE_128;
2252 break;
2253 case ATH9K_CIPHER_CLR:
2254 keyType = AR_KEYTABLE_TYPE_CLR;
2255 break;
2256 default:
2257 ath_print(common, ATH_DBG_FATAL,
2258 "cipher %u not supported\n", k->kv_type);
2259 return false;
2260 }
2261
2262 key0 = get_unaligned_le32(k->kv_val + 0);
2263 key1 = get_unaligned_le16(k->kv_val + 4);
2264 key2 = get_unaligned_le32(k->kv_val + 6);
2265 key3 = get_unaligned_le16(k->kv_val + 10);
2266 key4 = get_unaligned_le32(k->kv_val + 12);
2267 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2268 key4 &= 0xff;
2269
2270 /*
2271 * Note: Key cache registers access special memory area that requires
2272 * two 32-bit writes to actually update the values in the internal
2273 * memory. Consequently, the exact order and pairs used here must be
2274 * maintained.
2275 */
2276
2277 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2278 u16 micentry = entry + 64;
2279
2280 /*
2281 * Write inverted key[47:0] first to avoid Michael MIC errors
2282 * on frames that could be sent or received at the same time.
2283 * The correct key will be written in the end once everything
2284 * else is ready.
2285 */
2286 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2287 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2288
2289 /* Write key[95:48] */
2290 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2291 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2292
2293 /* Write key[127:96] and key type */
2294 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2295 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2296
2297 /* Write MAC address for the entry */
2298 (void) ath9k_hw_keysetmac(ah, entry, mac);
2299
2300 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2301 /*
2302 * TKIP uses two key cache entries:
2303 * Michael MIC TX/RX keys in the same key cache entry
2304 * (idx = main index + 64):
2305 * key0 [31:0] = RX key [31:0]
2306 * key1 [15:0] = TX key [31:16]
2307 * key1 [31:16] = reserved
2308 * key2 [31:0] = RX key [63:32]
2309 * key3 [15:0] = TX key [15:0]
2310 * key3 [31:16] = reserved
2311 * key4 [31:0] = TX key [63:32]
2312 */
2313 u32 mic0, mic1, mic2, mic3, mic4;
2314
2315 mic0 = get_unaligned_le32(k->kv_mic + 0);
2316 mic2 = get_unaligned_le32(k->kv_mic + 4);
2317 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2318 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2319 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2320
2321 /* Write RX[31:0] and TX[31:16] */
2322 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2323 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2324
2325 /* Write RX[63:32] and TX[15:0] */
2326 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2327 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2328
2329 /* Write TX[63:32] and keyType(reserved) */
2330 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2331 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2332 AR_KEYTABLE_TYPE_CLR);
2333
2334 } else {
2335 /*
2336 * TKIP uses four key cache entries (two for group
2337 * keys):
2338 * Michael MIC TX/RX keys are in different key cache
2339 * entries (idx = main index + 64 for TX and
2340 * main index + 32 + 96 for RX):
2341 * key0 [31:0] = TX/RX MIC key [31:0]
2342 * key1 [31:0] = reserved
2343 * key2 [31:0] = TX/RX MIC key [63:32]
2344 * key3 [31:0] = reserved
2345 * key4 [31:0] = reserved
2346 *
2347 * Upper layer code will call this function separately
2348 * for TX and RX keys when these registers offsets are
2349 * used.
2350 */
2351 u32 mic0, mic2;
2352
2353 mic0 = get_unaligned_le32(k->kv_mic + 0);
2354 mic2 = get_unaligned_le32(k->kv_mic + 4);
2355
2356 /* Write MIC key[31:0] */
2357 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2358 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2359
2360 /* Write MIC key[63:32] */
2361 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2362 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2363
2364 /* Write TX[63:32] and keyType(reserved) */
2365 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2366 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2367 AR_KEYTABLE_TYPE_CLR);
2368 }
2369
2370 /* MAC address registers are reserved for the MIC entry */
2371 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2372 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2373
2374 /*
2375 * Write the correct (un-inverted) key[47:0] last to enable
2376 * TKIP now that all other registers are set with correct
2377 * values.
2378 */
2379 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2380 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2381 } else {
2382 /* Write key[47:0] */
2383 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2384 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2385
2386 /* Write key[95:48] */
2387 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2388 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2389
2390 /* Write key[127:96] and key type */
2391 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2392 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2393
2394 /* Write MAC address for the entry */
2395 (void) ath9k_hw_keysetmac(ah, entry, mac);
2396 }
2397
2398 return true;
2399 }
2400 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2401
2402 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2403 {
2404 if (entry < ah->caps.keycache_size) {
2405 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2406 if (val & AR_KEYTABLE_VALID)
2407 return true;
2408 }
2409 return false;
2410 }
2411 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2412
2413 /******************************/
2414 /* Power Management (Chipset) */
2415 /******************************/
2416
2417 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2418 {
2419 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2420 if (setChip) {
2421 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2422 AR_RTC_FORCE_WAKE_EN);
2423 if (!AR_SREV_9100(ah))
2424 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2425
2426 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
2427 REG_CLR_BIT(ah, (AR_RTC_RESET),
2428 AR_RTC_RESET_EN);
2429 }
2430 }
2431
2432 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2433 {
2434 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2435 if (setChip) {
2436 struct ath9k_hw_capabilities *pCap = &ah->caps;
2437
2438 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2439 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2440 AR_RTC_FORCE_WAKE_ON_INT);
2441 } else {
2442 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2443 AR_RTC_FORCE_WAKE_EN);
2444 }
2445 }
2446 }
2447
2448 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2449 {
2450 u32 val;
2451 int i;
2452
2453 if (setChip) {
2454 if ((REG_READ(ah, AR_RTC_STATUS) &
2455 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2456 if (ath9k_hw_set_reset_reg(ah,
2457 ATH9K_RESET_POWER_ON) != true) {
2458 return false;
2459 }
2460 ath9k_hw_init_pll(ah, NULL);
2461 }
2462 if (AR_SREV_9100(ah))
2463 REG_SET_BIT(ah, AR_RTC_RESET,
2464 AR_RTC_RESET_EN);
2465
2466 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2467 AR_RTC_FORCE_WAKE_EN);
2468 udelay(50);
2469
2470 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2471 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2472 if (val == AR_RTC_STATUS_ON)
2473 break;
2474 udelay(50);
2475 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2476 AR_RTC_FORCE_WAKE_EN);
2477 }
2478 if (i == 0) {
2479 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2480 "Failed to wakeup in %uus\n",
2481 POWER_UP_TIME / 20);
2482 return false;
2483 }
2484 }
2485
2486 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2487
2488 return true;
2489 }
2490
2491 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2492 {
2493 struct ath_common *common = ath9k_hw_common(ah);
2494 int status = true, setChip = true;
2495 static const char *modes[] = {
2496 "AWAKE",
2497 "FULL-SLEEP",
2498 "NETWORK SLEEP",
2499 "UNDEFINED"
2500 };
2501
2502 if (ah->power_mode == mode)
2503 return status;
2504
2505 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2506 modes[ah->power_mode], modes[mode]);
2507
2508 switch (mode) {
2509 case ATH9K_PM_AWAKE:
2510 status = ath9k_hw_set_power_awake(ah, setChip);
2511 break;
2512 case ATH9K_PM_FULL_SLEEP:
2513 ath9k_set_power_sleep(ah, setChip);
2514 ah->chip_fullsleep = true;
2515 break;
2516 case ATH9K_PM_NETWORK_SLEEP:
2517 ath9k_set_power_network_sleep(ah, setChip);
2518 break;
2519 default:
2520 ath_print(common, ATH_DBG_FATAL,
2521 "Unknown power mode %u\n", mode);
2522 return false;
2523 }
2524 ah->power_mode = mode;
2525
2526 return status;
2527 }
2528 EXPORT_SYMBOL(ath9k_hw_setpower);
2529
2530 /*
2531 * Helper for ASPM support.
2532 *
2533 * Disable PLL when in L0s as well as receiver clock when in L1.
2534 * This power saving option must be enabled through the SerDes.
2535 *
2536 * Programming the SerDes must go through the same 288 bit serial shift
2537 * register as the other analog registers. Hence the 9 writes.
2538 */
2539 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2540 {
2541 u8 i;
2542 u32 val;
2543
2544 if (ah->is_pciexpress != true)
2545 return;
2546
2547 /* Do not touch SerDes registers */
2548 if (ah->config.pcie_powersave_enable == 2)
2549 return;
2550
2551 /* Nothing to do on restore for 11N */
2552 if (!restore) {
2553 if (AR_SREV_9280_20_OR_LATER(ah)) {
2554 /*
2555 * AR9280 2.0 or later chips use SerDes values from the
2556 * initvals.h initialized depending on chipset during
2557 * ath9k_hw_init()
2558 */
2559 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2560 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2561 INI_RA(&ah->iniPcieSerdes, i, 1));
2562 }
2563 } else if (AR_SREV_9280(ah) &&
2564 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2565 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2566 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2567
2568 /* RX shut off when elecidle is asserted */
2569 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2570 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2571 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2572
2573 /* Shut off CLKREQ active in L1 */
2574 if (ah->config.pcie_clock_req)
2575 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2576 else
2577 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2578
2579 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2580 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2581 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2582
2583 /* Load the new settings */
2584 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2585
2586 } else {
2587 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2588 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2589
2590 /* RX shut off when elecidle is asserted */
2591 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2592 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2593 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2594
2595 /*
2596 * Ignore ah->ah_config.pcie_clock_req setting for
2597 * pre-AR9280 11n
2598 */
2599 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2600
2601 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2602 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2603 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2604
2605 /* Load the new settings */
2606 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2607 }
2608
2609 udelay(1000);
2610
2611 /* set bit 19 to allow forcing of pcie core into L1 state */
2612 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2613
2614 /* Several PCIe massages to ensure proper behaviour */
2615 if (ah->config.pcie_waen) {
2616 val = ah->config.pcie_waen;
2617 if (!power_off)
2618 val &= (~AR_WA_D3_L1_DISABLE);
2619 } else {
2620 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2621 AR_SREV_9287(ah)) {
2622 val = AR9285_WA_DEFAULT;
2623 if (!power_off)
2624 val &= (~AR_WA_D3_L1_DISABLE);
2625 } else if (AR_SREV_9280(ah)) {
2626 /*
2627 * On AR9280 chips bit 22 of 0x4004 needs to be
2628 * set otherwise card may disappear.
2629 */
2630 val = AR9280_WA_DEFAULT;
2631 if (!power_off)
2632 val &= (~AR_WA_D3_L1_DISABLE);
2633 } else
2634 val = AR_WA_DEFAULT;
2635 }
2636
2637 REG_WRITE(ah, AR_WA, val);
2638 }
2639
2640 if (power_off) {
2641 /*
2642 * Set PCIe workaround bits
2643 * bit 14 in WA register (disable L1) should only
2644 * be set when device enters D3 and be cleared
2645 * when device comes back to D0.
2646 */
2647 if (ah->config.pcie_waen) {
2648 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2649 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2650 } else {
2651 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2652 AR_SREV_9287(ah)) &&
2653 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2654 (AR_SREV_9280(ah) &&
2655 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2656 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2657 }
2658 }
2659 }
2660 }
2661 EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
2662
2663 /**********************/
2664 /* Interrupt Handling */
2665 /**********************/
2666
2667 bool ath9k_hw_intrpend(struct ath_hw *ah)
2668 {
2669 u32 host_isr;
2670
2671 if (AR_SREV_9100(ah))
2672 return true;
2673
2674 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2675 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2676 return true;
2677
2678 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2679 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2680 && (host_isr != AR_INTR_SPURIOUS))
2681 return true;
2682
2683 return false;
2684 }
2685 EXPORT_SYMBOL(ath9k_hw_intrpend);
2686
2687 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2688 {
2689 u32 isr = 0;
2690 u32 mask2 = 0;
2691 struct ath9k_hw_capabilities *pCap = &ah->caps;
2692 u32 sync_cause = 0;
2693 bool fatal_int = false;
2694 struct ath_common *common = ath9k_hw_common(ah);
2695
2696 if (!AR_SREV_9100(ah)) {
2697 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2698 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2699 == AR_RTC_STATUS_ON) {
2700 isr = REG_READ(ah, AR_ISR);
2701 }
2702 }
2703
2704 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2705 AR_INTR_SYNC_DEFAULT;
2706
2707 *masked = 0;
2708
2709 if (!isr && !sync_cause)
2710 return false;
2711 } else {
2712 *masked = 0;
2713 isr = REG_READ(ah, AR_ISR);
2714 }
2715
2716 if (isr) {
2717 if (isr & AR_ISR_BCNMISC) {
2718 u32 isr2;
2719 isr2 = REG_READ(ah, AR_ISR_S2);
2720 if (isr2 & AR_ISR_S2_TIM)
2721 mask2 |= ATH9K_INT_TIM;
2722 if (isr2 & AR_ISR_S2_DTIM)
2723 mask2 |= ATH9K_INT_DTIM;
2724 if (isr2 & AR_ISR_S2_DTIMSYNC)
2725 mask2 |= ATH9K_INT_DTIMSYNC;
2726 if (isr2 & (AR_ISR_S2_CABEND))
2727 mask2 |= ATH9K_INT_CABEND;
2728 if (isr2 & AR_ISR_S2_GTT)
2729 mask2 |= ATH9K_INT_GTT;
2730 if (isr2 & AR_ISR_S2_CST)
2731 mask2 |= ATH9K_INT_CST;
2732 if (isr2 & AR_ISR_S2_TSFOOR)
2733 mask2 |= ATH9K_INT_TSFOOR;
2734 }
2735
2736 isr = REG_READ(ah, AR_ISR_RAC);
2737 if (isr == 0xffffffff) {
2738 *masked = 0;
2739 return false;
2740 }
2741
2742 *masked = isr & ATH9K_INT_COMMON;
2743
2744 if (ah->config.rx_intr_mitigation) {
2745 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2746 *masked |= ATH9K_INT_RX;
2747 }
2748
2749 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2750 *masked |= ATH9K_INT_RX;
2751 if (isr &
2752 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2753 AR_ISR_TXEOL)) {
2754 u32 s0_s, s1_s;
2755
2756 *masked |= ATH9K_INT_TX;
2757
2758 s0_s = REG_READ(ah, AR_ISR_S0_S);
2759 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2760 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2761
2762 s1_s = REG_READ(ah, AR_ISR_S1_S);
2763 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2764 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2765 }
2766
2767 if (isr & AR_ISR_RXORN) {
2768 ath_print(common, ATH_DBG_INTERRUPT,
2769 "receive FIFO overrun interrupt\n");
2770 }
2771
2772 if (!AR_SREV_9100(ah)) {
2773 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2774 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2775 if (isr5 & AR_ISR_S5_TIM_TIMER)
2776 *masked |= ATH9K_INT_TIM_TIMER;
2777 }
2778 }
2779
2780 *masked |= mask2;
2781 }
2782
2783 if (AR_SREV_9100(ah))
2784 return true;
2785
2786 if (isr & AR_ISR_GENTMR) {
2787 u32 s5_s;
2788
2789 s5_s = REG_READ(ah, AR_ISR_S5_S);
2790 if (isr & AR_ISR_GENTMR) {
2791 ah->intr_gen_timer_trigger =
2792 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2793
2794 ah->intr_gen_timer_thresh =
2795 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2796
2797 if (ah->intr_gen_timer_trigger)
2798 *masked |= ATH9K_INT_GENTIMER;
2799
2800 }
2801 }
2802
2803 if (sync_cause) {
2804 fatal_int =
2805 (sync_cause &
2806 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2807 ? true : false;
2808
2809 if (fatal_int) {
2810 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2811 ath_print(common, ATH_DBG_ANY,
2812 "received PCI FATAL interrupt\n");
2813 }
2814 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2815 ath_print(common, ATH_DBG_ANY,
2816 "received PCI PERR interrupt\n");
2817 }
2818 *masked |= ATH9K_INT_FATAL;
2819 }
2820 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2821 ath_print(common, ATH_DBG_INTERRUPT,
2822 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2823 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2824 REG_WRITE(ah, AR_RC, 0);
2825 *masked |= ATH9K_INT_FATAL;
2826 }
2827 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2828 ath_print(common, ATH_DBG_INTERRUPT,
2829 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2830 }
2831
2832 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2833 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2834 }
2835
2836 return true;
2837 }
2838 EXPORT_SYMBOL(ath9k_hw_getisr);
2839
2840 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2841 {
2842 enum ath9k_int omask = ah->imask;
2843 u32 mask, mask2;
2844 struct ath9k_hw_capabilities *pCap = &ah->caps;
2845 struct ath_common *common = ath9k_hw_common(ah);
2846
2847 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2848
2849 if (omask & ATH9K_INT_GLOBAL) {
2850 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2851 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2852 (void) REG_READ(ah, AR_IER);
2853 if (!AR_SREV_9100(ah)) {
2854 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2855 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2856
2857 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2858 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2859 }
2860 }
2861
2862 mask = ints & ATH9K_INT_COMMON;
2863 mask2 = 0;
2864
2865 if (ints & ATH9K_INT_TX) {
2866 if (ah->txok_interrupt_mask)
2867 mask |= AR_IMR_TXOK;
2868 if (ah->txdesc_interrupt_mask)
2869 mask |= AR_IMR_TXDESC;
2870 if (ah->txerr_interrupt_mask)
2871 mask |= AR_IMR_TXERR;
2872 if (ah->txeol_interrupt_mask)
2873 mask |= AR_IMR_TXEOL;
2874 }
2875 if (ints & ATH9K_INT_RX) {
2876 mask |= AR_IMR_RXERR;
2877 if (ah->config.rx_intr_mitigation)
2878 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2879 else
2880 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2881 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2882 mask |= AR_IMR_GENTMR;
2883 }
2884
2885 if (ints & (ATH9K_INT_BMISC)) {
2886 mask |= AR_IMR_BCNMISC;
2887 if (ints & ATH9K_INT_TIM)
2888 mask2 |= AR_IMR_S2_TIM;
2889 if (ints & ATH9K_INT_DTIM)
2890 mask2 |= AR_IMR_S2_DTIM;
2891 if (ints & ATH9K_INT_DTIMSYNC)
2892 mask2 |= AR_IMR_S2_DTIMSYNC;
2893 if (ints & ATH9K_INT_CABEND)
2894 mask2 |= AR_IMR_S2_CABEND;
2895 if (ints & ATH9K_INT_TSFOOR)
2896 mask2 |= AR_IMR_S2_TSFOOR;
2897 }
2898
2899 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2900 mask |= AR_IMR_BCNMISC;
2901 if (ints & ATH9K_INT_GTT)
2902 mask2 |= AR_IMR_S2_GTT;
2903 if (ints & ATH9K_INT_CST)
2904 mask2 |= AR_IMR_S2_CST;
2905 }
2906
2907 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2908 REG_WRITE(ah, AR_IMR, mask);
2909 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
2910 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
2911 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
2912 ah->imrs2_reg |= mask2;
2913 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
2914
2915 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2916 if (ints & ATH9K_INT_TIM_TIMER)
2917 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2918 else
2919 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2920 }
2921
2922 if (ints & ATH9K_INT_GLOBAL) {
2923 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2924 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2925 if (!AR_SREV_9100(ah)) {
2926 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2927 AR_INTR_MAC_IRQ);
2928 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2929
2930
2931 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2932 AR_INTR_SYNC_DEFAULT);
2933 REG_WRITE(ah, AR_INTR_SYNC_MASK,
2934 AR_INTR_SYNC_DEFAULT);
2935 }
2936 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2937 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2938 }
2939
2940 return omask;
2941 }
2942 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2943
2944 /*******************/
2945 /* Beacon Handling */
2946 /*******************/
2947
2948 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2949 {
2950 int flags = 0;
2951
2952 ah->beacon_interval = beacon_period;
2953
2954 switch (ah->opmode) {
2955 case NL80211_IFTYPE_STATION:
2956 case NL80211_IFTYPE_MONITOR:
2957 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2958 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2959 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2960 flags |= AR_TBTT_TIMER_EN;
2961 break;
2962 case NL80211_IFTYPE_ADHOC:
2963 case NL80211_IFTYPE_MESH_POINT:
2964 REG_SET_BIT(ah, AR_TXCFG,
2965 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2966 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2967 TU_TO_USEC(next_beacon +
2968 (ah->atim_window ? ah->
2969 atim_window : 1)));
2970 flags |= AR_NDP_TIMER_EN;
2971 case NL80211_IFTYPE_AP:
2972 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2973 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2974 TU_TO_USEC(next_beacon -
2975 ah->config.
2976 dma_beacon_response_time));
2977 REG_WRITE(ah, AR_NEXT_SWBA,
2978 TU_TO_USEC(next_beacon -
2979 ah->config.
2980 sw_beacon_response_time));
2981 flags |=
2982 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2983 break;
2984 default:
2985 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
2986 "%s: unsupported opmode: %d\n",
2987 __func__, ah->opmode);
2988 return;
2989 break;
2990 }
2991
2992 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2993 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2994 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
2995 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
2996
2997 beacon_period &= ~ATH9K_BEACON_ENA;
2998 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
2999 ath9k_hw_reset_tsf(ah);
3000 }
3001
3002 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3003 }
3004 EXPORT_SYMBOL(ath9k_hw_beaconinit);
3005
3006 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3007 const struct ath9k_beacon_state *bs)
3008 {
3009 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3010 struct ath9k_hw_capabilities *pCap = &ah->caps;
3011 struct ath_common *common = ath9k_hw_common(ah);
3012
3013 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3014
3015 REG_WRITE(ah, AR_BEACON_PERIOD,
3016 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3017 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3018 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3019
3020 REG_RMW_FIELD(ah, AR_RSSI_THR,
3021 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3022
3023 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3024
3025 if (bs->bs_sleepduration > beaconintval)
3026 beaconintval = bs->bs_sleepduration;
3027
3028 dtimperiod = bs->bs_dtimperiod;
3029 if (bs->bs_sleepduration > dtimperiod)
3030 dtimperiod = bs->bs_sleepduration;
3031
3032 if (beaconintval == dtimperiod)
3033 nextTbtt = bs->bs_nextdtim;
3034 else
3035 nextTbtt = bs->bs_nexttbtt;
3036
3037 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3038 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3039 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3040 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3041
3042 REG_WRITE(ah, AR_NEXT_DTIM,
3043 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3044 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3045
3046 REG_WRITE(ah, AR_SLEEP1,
3047 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3048 | AR_SLEEP1_ASSUME_DTIM);
3049
3050 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3051 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3052 else
3053 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3054
3055 REG_WRITE(ah, AR_SLEEP2,
3056 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3057
3058 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3059 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3060
3061 REG_SET_BIT(ah, AR_TIMER_MODE,
3062 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3063 AR_DTIM_TIMER_EN);
3064
3065 /* TSF Out of Range Threshold */
3066 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3067 }
3068 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3069
3070 /*******************/
3071 /* HW Capabilities */
3072 /*******************/
3073
3074 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
3075 {
3076 struct ath9k_hw_capabilities *pCap = &ah->caps;
3077 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3078 struct ath_common *common = ath9k_hw_common(ah);
3079 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3080
3081 u16 capField = 0, eeval;
3082
3083 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3084 regulatory->current_rd = eeval;
3085
3086 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3087 if (AR_SREV_9285_10_OR_LATER(ah))
3088 eeval |= AR9285_RDEXT_DEFAULT;
3089 regulatory->current_rd_ext = eeval;
3090
3091 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3092
3093 if (ah->opmode != NL80211_IFTYPE_AP &&
3094 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3095 if (regulatory->current_rd == 0x64 ||
3096 regulatory->current_rd == 0x65)
3097 regulatory->current_rd += 5;
3098 else if (regulatory->current_rd == 0x41)
3099 regulatory->current_rd = 0x43;
3100 ath_print(common, ATH_DBG_REGULATORY,
3101 "regdomain mapped to 0x%x\n", regulatory->current_rd);
3102 }
3103
3104 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3105 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3106 ath_print(common, ATH_DBG_FATAL,
3107 "no band has been marked as supported in EEPROM.\n");
3108 return -EINVAL;
3109 }
3110
3111 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3112
3113 if (eeval & AR5416_OPFLAGS_11A) {
3114 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3115 if (ah->config.ht_enable) {
3116 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3117 set_bit(ATH9K_MODE_11NA_HT20,
3118 pCap->wireless_modes);
3119 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3120 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3121 pCap->wireless_modes);
3122 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3123 pCap->wireless_modes);
3124 }
3125 }
3126 }
3127
3128 if (eeval & AR5416_OPFLAGS_11G) {
3129 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3130 if (ah->config.ht_enable) {
3131 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3132 set_bit(ATH9K_MODE_11NG_HT20,
3133 pCap->wireless_modes);
3134 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3135 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3136 pCap->wireless_modes);
3137 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3138 pCap->wireless_modes);
3139 }
3140 }
3141 }
3142
3143 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3144 /*
3145 * For AR9271 we will temporarilly uses the rx chainmax as read from
3146 * the EEPROM.
3147 */
3148 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3149 !(eeval & AR5416_OPFLAGS_11A) &&
3150 !(AR_SREV_9271(ah)))
3151 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3152 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3153 else
3154 /* Use rx_chainmask from EEPROM. */
3155 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3156
3157 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3158 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3159
3160 pCap->low_2ghz_chan = 2312;
3161 pCap->high_2ghz_chan = 2732;
3162
3163 pCap->low_5ghz_chan = 4920;
3164 pCap->high_5ghz_chan = 6100;
3165
3166 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3167 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3168 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3169
3170 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3171 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3172 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3173
3174 if (ah->config.ht_enable)
3175 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3176 else
3177 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3178
3179 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3180 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3181 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3182 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3183
3184 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3185 pCap->total_queues =
3186 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3187 else
3188 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3189
3190 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3191 pCap->keycache_size =
3192 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3193 else
3194 pCap->keycache_size = AR_KEYTABLE_SIZE;
3195
3196 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3197
3198 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
3199 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
3200 else
3201 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3202
3203 if (AR_SREV_9271(ah))
3204 pCap->num_gpio_pins = AR9271_NUM_GPIO;
3205 else if (AR_SREV_9285_10_OR_LATER(ah))
3206 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3207 else if (AR_SREV_9280_10_OR_LATER(ah))
3208 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3209 else
3210 pCap->num_gpio_pins = AR_NUM_GPIO;
3211
3212 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3213 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3214 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3215 } else {
3216 pCap->rts_aggr_limit = (8 * 1024);
3217 }
3218
3219 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3220
3221 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3222 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3223 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3224 ah->rfkill_gpio =
3225 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3226 ah->rfkill_polarity =
3227 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3228
3229 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3230 }
3231 #endif
3232
3233 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3234
3235 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3236 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3237 else
3238 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3239
3240 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3241 pCap->reg_cap =
3242 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3243 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3244 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3245 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3246 } else {
3247 pCap->reg_cap =
3248 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3249 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3250 }
3251
3252 /* Advertise midband for AR5416 with FCC midband set in eeprom */
3253 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3254 AR_SREV_5416(ah))
3255 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3256
3257 pCap->num_antcfg_5ghz =
3258 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3259 pCap->num_antcfg_2ghz =
3260 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3261
3262 if (AR_SREV_9280_10_OR_LATER(ah) &&
3263 ath9k_hw_btcoex_supported(ah)) {
3264 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3265 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3266
3267 if (AR_SREV_9285(ah)) {
3268 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3269 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3270 } else {
3271 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3272 }
3273 } else {
3274 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3275 }
3276
3277 return 0;
3278 }
3279
3280 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3281 u32 capability, u32 *result)
3282 {
3283 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3284 switch (type) {
3285 case ATH9K_CAP_CIPHER:
3286 switch (capability) {
3287 case ATH9K_CIPHER_AES_CCM:
3288 case ATH9K_CIPHER_AES_OCB:
3289 case ATH9K_CIPHER_TKIP:
3290 case ATH9K_CIPHER_WEP:
3291 case ATH9K_CIPHER_MIC:
3292 case ATH9K_CIPHER_CLR:
3293 return true;
3294 default:
3295 return false;
3296 }
3297 case ATH9K_CAP_TKIP_MIC:
3298 switch (capability) {
3299 case 0:
3300 return true;
3301 case 1:
3302 return (ah->sta_id1_defaults &
3303 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3304 false;
3305 }
3306 case ATH9K_CAP_TKIP_SPLIT:
3307 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3308 false : true;
3309 case ATH9K_CAP_DIVERSITY:
3310 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3311 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3312 true : false;
3313 case ATH9K_CAP_MCAST_KEYSRCH:
3314 switch (capability) {
3315 case 0:
3316 return true;
3317 case 1:
3318 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3319 return false;
3320 } else {
3321 return (ah->sta_id1_defaults &
3322 AR_STA_ID1_MCAST_KSRCH) ? true :
3323 false;
3324 }
3325 }
3326 return false;
3327 case ATH9K_CAP_TXPOW:
3328 switch (capability) {
3329 case 0:
3330 return 0;
3331 case 1:
3332 *result = regulatory->power_limit;
3333 return 0;
3334 case 2:
3335 *result = regulatory->max_power_level;
3336 return 0;
3337 case 3:
3338 *result = regulatory->tp_scale;
3339 return 0;
3340 }
3341 return false;
3342 case ATH9K_CAP_DS:
3343 return (AR_SREV_9280_20_OR_LATER(ah) &&
3344 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3345 ? false : true;
3346 default:
3347 return false;
3348 }
3349 }
3350 EXPORT_SYMBOL(ath9k_hw_getcapability);
3351
3352 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3353 u32 capability, u32 setting, int *status)
3354 {
3355 u32 v;
3356
3357 switch (type) {
3358 case ATH9K_CAP_TKIP_MIC:
3359 if (setting)
3360 ah->sta_id1_defaults |=
3361 AR_STA_ID1_CRPT_MIC_ENABLE;
3362 else
3363 ah->sta_id1_defaults &=
3364 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3365 return true;
3366 case ATH9K_CAP_DIVERSITY:
3367 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3368 if (setting)
3369 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3370 else
3371 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3372 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3373 return true;
3374 case ATH9K_CAP_MCAST_KEYSRCH:
3375 if (setting)
3376 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3377 else
3378 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3379 return true;
3380 default:
3381 return false;
3382 }
3383 }
3384 EXPORT_SYMBOL(ath9k_hw_setcapability);
3385
3386 /****************************/
3387 /* GPIO / RFKILL / Antennae */
3388 /****************************/
3389
3390 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3391 u32 gpio, u32 type)
3392 {
3393 int addr;
3394 u32 gpio_shift, tmp;
3395
3396 if (gpio > 11)
3397 addr = AR_GPIO_OUTPUT_MUX3;
3398 else if (gpio > 5)
3399 addr = AR_GPIO_OUTPUT_MUX2;
3400 else
3401 addr = AR_GPIO_OUTPUT_MUX1;
3402
3403 gpio_shift = (gpio % 6) * 5;
3404
3405 if (AR_SREV_9280_20_OR_LATER(ah)
3406 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3407 REG_RMW(ah, addr, (type << gpio_shift),
3408 (0x1f << gpio_shift));
3409 } else {
3410 tmp = REG_READ(ah, addr);
3411 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3412 tmp &= ~(0x1f << gpio_shift);
3413 tmp |= (type << gpio_shift);
3414 REG_WRITE(ah, addr, tmp);
3415 }
3416 }
3417
3418 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3419 {
3420 u32 gpio_shift;
3421
3422 BUG_ON(gpio >= ah->caps.num_gpio_pins);
3423
3424 gpio_shift = gpio << 1;
3425
3426 REG_RMW(ah,
3427 AR_GPIO_OE_OUT,
3428 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3429 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3430 }
3431 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3432
3433 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3434 {
3435 #define MS_REG_READ(x, y) \
3436 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3437
3438 if (gpio >= ah->caps.num_gpio_pins)
3439 return 0xffffffff;
3440
3441 if (AR_SREV_9271(ah))
3442 return MS_REG_READ(AR9271, gpio) != 0;
3443 else if (AR_SREV_9287_10_OR_LATER(ah))
3444 return MS_REG_READ(AR9287, gpio) != 0;
3445 else if (AR_SREV_9285_10_OR_LATER(ah))
3446 return MS_REG_READ(AR9285, gpio) != 0;
3447 else if (AR_SREV_9280_10_OR_LATER(ah))
3448 return MS_REG_READ(AR928X, gpio) != 0;
3449 else
3450 return MS_REG_READ(AR, gpio) != 0;
3451 }
3452 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3453
3454 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3455 u32 ah_signal_type)
3456 {
3457 u32 gpio_shift;
3458
3459 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3460
3461 gpio_shift = 2 * gpio;
3462
3463 REG_RMW(ah,
3464 AR_GPIO_OE_OUT,
3465 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3466 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3467 }
3468 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3469
3470 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3471 {
3472 if (AR_SREV_9271(ah))
3473 val = ~val;
3474
3475 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3476 AR_GPIO_BIT(gpio));
3477 }
3478 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3479
3480 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3481 {
3482 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3483 }
3484 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3485
3486 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3487 {
3488 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3489 }
3490 EXPORT_SYMBOL(ath9k_hw_setantenna);
3491
3492 /*********************/
3493 /* General Operation */
3494 /*********************/
3495
3496 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3497 {
3498 u32 bits = REG_READ(ah, AR_RX_FILTER);
3499 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3500
3501 if (phybits & AR_PHY_ERR_RADAR)
3502 bits |= ATH9K_RX_FILTER_PHYRADAR;
3503 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3504 bits |= ATH9K_RX_FILTER_PHYERR;
3505
3506 return bits;
3507 }
3508 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3509
3510 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3511 {
3512 u32 phybits;
3513
3514 REG_WRITE(ah, AR_RX_FILTER, bits);
3515
3516 phybits = 0;
3517 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3518 phybits |= AR_PHY_ERR_RADAR;
3519 if (bits & ATH9K_RX_FILTER_PHYERR)
3520 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3521 REG_WRITE(ah, AR_PHY_ERR, phybits);
3522
3523 if (phybits)
3524 REG_WRITE(ah, AR_RXCFG,
3525 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3526 else
3527 REG_WRITE(ah, AR_RXCFG,
3528 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3529 }
3530 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3531
3532 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3533 {
3534 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3535 return false;
3536
3537 ath9k_hw_init_pll(ah, NULL);
3538 return true;
3539 }
3540 EXPORT_SYMBOL(ath9k_hw_phy_disable);
3541
3542 bool ath9k_hw_disable(struct ath_hw *ah)
3543 {
3544 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3545 return false;
3546
3547 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3548 return false;
3549
3550 ath9k_hw_init_pll(ah, NULL);
3551 return true;
3552 }
3553 EXPORT_SYMBOL(ath9k_hw_disable);
3554
3555 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3556 {
3557 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3558 struct ath9k_channel *chan = ah->curchan;
3559 struct ieee80211_channel *channel = chan->chan;
3560
3561 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3562
3563 ah->eep_ops->set_txpower(ah, chan,
3564 ath9k_regd_get_ctl(regulatory, chan),
3565 channel->max_antenna_gain * 2,
3566 channel->max_power * 2,
3567 min((u32) MAX_RATE_POWER,
3568 (u32) regulatory->power_limit));
3569 }
3570 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
3571
3572 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3573 {
3574 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3575 }
3576 EXPORT_SYMBOL(ath9k_hw_setmac);
3577
3578 void ath9k_hw_setopmode(struct ath_hw *ah)
3579 {
3580 ath9k_hw_set_operating_mode(ah, ah->opmode);
3581 }
3582 EXPORT_SYMBOL(ath9k_hw_setopmode);
3583
3584 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3585 {
3586 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3587 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3588 }
3589 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
3590
3591 void ath9k_hw_write_associd(struct ath_hw *ah)
3592 {
3593 struct ath_common *common = ath9k_hw_common(ah);
3594
3595 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3596 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3597 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3598 }
3599 EXPORT_SYMBOL(ath9k_hw_write_associd);
3600
3601 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3602 {
3603 u64 tsf;
3604
3605 tsf = REG_READ(ah, AR_TSF_U32);
3606 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3607
3608 return tsf;
3609 }
3610 EXPORT_SYMBOL(ath9k_hw_gettsf64);
3611
3612 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3613 {
3614 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3615 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3616 }
3617 EXPORT_SYMBOL(ath9k_hw_settsf64);
3618
3619 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3620 {
3621 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3622 AH_TSF_WRITE_TIMEOUT))
3623 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3624 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3625
3626 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3627 }
3628 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3629
3630 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3631 {
3632 if (setting)
3633 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3634 else
3635 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3636 }
3637 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3638
3639 /*
3640 * Extend 15-bit time stamp from rx descriptor to
3641 * a full 64-bit TSF using the current h/w TSF.
3642 */
3643 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3644 {
3645 u64 tsf;
3646
3647 tsf = ath9k_hw_gettsf64(ah);
3648 if ((tsf & 0x7fff) < rstamp)
3649 tsf -= 0x8000;
3650 return (tsf & ~0x7fff) | rstamp;
3651 }
3652 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3653
3654 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
3655 {
3656 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3657 u32 macmode;
3658
3659 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
3660 macmode = AR_2040_JOINED_RX_CLEAR;
3661 else
3662 macmode = 0;
3663
3664 REG_WRITE(ah, AR_2040_MODE, macmode);
3665 }
3666
3667 /* HW Generic timers configuration */
3668
3669 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3670 {
3671 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3672 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3673 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3674 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3675 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3676 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3677 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3678 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3679 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3680 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3681 AR_NDP2_TIMER_MODE, 0x0002},
3682 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3683 AR_NDP2_TIMER_MODE, 0x0004},
3684 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3685 AR_NDP2_TIMER_MODE, 0x0008},
3686 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3687 AR_NDP2_TIMER_MODE, 0x0010},
3688 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3689 AR_NDP2_TIMER_MODE, 0x0020},
3690 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3691 AR_NDP2_TIMER_MODE, 0x0040},
3692 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3693 AR_NDP2_TIMER_MODE, 0x0080}
3694 };
3695
3696 /* HW generic timer primitives */
3697
3698 /* compute and clear index of rightmost 1 */
3699 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3700 {
3701 u32 b;
3702
3703 b = *mask;
3704 b &= (0-b);
3705 *mask &= ~b;
3706 b *= debruijn32;
3707 b >>= 27;
3708
3709 return timer_table->gen_timer_index[b];
3710 }
3711
3712 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3713 {
3714 return REG_READ(ah, AR_TSF_L32);
3715 }
3716 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3717
3718 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3719 void (*trigger)(void *),
3720 void (*overflow)(void *),
3721 void *arg,
3722 u8 timer_index)
3723 {
3724 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3725 struct ath_gen_timer *timer;
3726
3727 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3728
3729 if (timer == NULL) {
3730 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3731 "Failed to allocate memory"
3732 "for hw timer[%d]\n", timer_index);
3733 return NULL;
3734 }
3735
3736 /* allocate a hardware generic timer slot */
3737 timer_table->timers[timer_index] = timer;
3738 timer->index = timer_index;
3739 timer->trigger = trigger;
3740 timer->overflow = overflow;
3741 timer->arg = arg;
3742
3743 return timer;
3744 }
3745 EXPORT_SYMBOL(ath_gen_timer_alloc);
3746
3747 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3748 struct ath_gen_timer *timer,
3749 u32 timer_next,
3750 u32 timer_period)
3751 {
3752 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3753 u32 tsf;
3754
3755 BUG_ON(!timer_period);
3756
3757 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3758
3759 tsf = ath9k_hw_gettsf32(ah);
3760
3761 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3762 "curent tsf %x period %x"
3763 "timer_next %x\n", tsf, timer_period, timer_next);
3764
3765 /*
3766 * Pull timer_next forward if the current TSF already passed it
3767 * because of software latency
3768 */
3769 if (timer_next < tsf)
3770 timer_next = tsf + timer_period;
3771
3772 /*
3773 * Program generic timer registers
3774 */
3775 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3776 timer_next);
3777 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3778 timer_period);
3779 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3780 gen_tmr_configuration[timer->index].mode_mask);
3781
3782 /* Enable both trigger and thresh interrupt masks */
3783 REG_SET_BIT(ah, AR_IMR_S5,
3784 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3785 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3786 }
3787 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3788
3789 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3790 {
3791 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3792
3793 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3794 (timer->index >= ATH_MAX_GEN_TIMER)) {
3795 return;
3796 }
3797
3798 /* Clear generic timer enable bits. */
3799 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3800 gen_tmr_configuration[timer->index].mode_mask);
3801
3802 /* Disable both trigger and thresh interrupt masks */
3803 REG_CLR_BIT(ah, AR_IMR_S5,
3804 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3805 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3806
3807 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3808 }
3809 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3810
3811 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3812 {
3813 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3814
3815 /* free the hardware generic timer slot */
3816 timer_table->timers[timer->index] = NULL;
3817 kfree(timer);
3818 }
3819 EXPORT_SYMBOL(ath_gen_timer_free);
3820
3821 /*
3822 * Generic Timer Interrupts handling
3823 */
3824 void ath_gen_timer_isr(struct ath_hw *ah)
3825 {
3826 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3827 struct ath_gen_timer *timer;
3828 struct ath_common *common = ath9k_hw_common(ah);
3829 u32 trigger_mask, thresh_mask, index;
3830
3831 /* get hardware generic timer interrupt status */
3832 trigger_mask = ah->intr_gen_timer_trigger;
3833 thresh_mask = ah->intr_gen_timer_thresh;
3834 trigger_mask &= timer_table->timer_mask.val;
3835 thresh_mask &= timer_table->timer_mask.val;
3836
3837 trigger_mask &= ~thresh_mask;
3838
3839 while (thresh_mask) {
3840 index = rightmost_index(timer_table, &thresh_mask);
3841 timer = timer_table->timers[index];
3842 BUG_ON(!timer);
3843 ath_print(common, ATH_DBG_HWTIMER,
3844 "TSF overflow for Gen timer %d\n", index);
3845 timer->overflow(timer->arg);
3846 }
3847
3848 while (trigger_mask) {
3849 index = rightmost_index(timer_table, &trigger_mask);
3850 timer = timer_table->timers[index];
3851 BUG_ON(!timer);
3852 ath_print(common, ATH_DBG_HWTIMER,
3853 "Gen timer[%d] trigger\n", index);
3854 timer->trigger(timer->arg);
3855 }
3856 }
3857 EXPORT_SYMBOL(ath_gen_timer_isr);
3858
3859 /********/
3860 /* HTC */
3861 /********/
3862
3863 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
3864 {
3865 ah->htc_reset_init = true;
3866 }
3867 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
3868
3869 static struct {
3870 u32 version;
3871 const char * name;
3872 } ath_mac_bb_names[] = {
3873 /* Devices with external radios */
3874 { AR_SREV_VERSION_5416_PCI, "5416" },
3875 { AR_SREV_VERSION_5416_PCIE, "5418" },
3876 { AR_SREV_VERSION_9100, "9100" },
3877 { AR_SREV_VERSION_9160, "9160" },
3878 /* Single-chip solutions */
3879 { AR_SREV_VERSION_9280, "9280" },
3880 { AR_SREV_VERSION_9285, "9285" },
3881 { AR_SREV_VERSION_9287, "9287" },
3882 { AR_SREV_VERSION_9271, "9271" },
3883 };
3884
3885 /* For devices with external radios */
3886 static struct {
3887 u16 version;
3888 const char * name;
3889 } ath_rf_names[] = {
3890 { 0, "5133" },
3891 { AR_RAD5133_SREV_MAJOR, "5133" },
3892 { AR_RAD5122_SREV_MAJOR, "5122" },
3893 { AR_RAD2133_SREV_MAJOR, "2133" },
3894 { AR_RAD2122_SREV_MAJOR, "2122" }
3895 };
3896
3897 /*
3898 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3899 */
3900 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3901 {
3902 int i;
3903
3904 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3905 if (ath_mac_bb_names[i].version == mac_bb_version) {
3906 return ath_mac_bb_names[i].name;
3907 }
3908 }
3909
3910 return "????";
3911 }
3912
3913 /*
3914 * Return the RF name. "????" is returned if the RF is unknown.
3915 * Used for devices with external radios.
3916 */
3917 static const char *ath9k_hw_rf_name(u16 rf_version)
3918 {
3919 int i;
3920
3921 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3922 if (ath_rf_names[i].version == rf_version) {
3923 return ath_rf_names[i].name;
3924 }
3925 }
3926
3927 return "????";
3928 }
3929
3930 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3931 {
3932 int used;
3933
3934 /* chipsets >= AR9280 are single-chip */
3935 if (AR_SREV_9280_10_OR_LATER(ah)) {
3936 used = snprintf(hw_name, len,
3937 "Atheros AR%s Rev:%x",
3938 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3939 ah->hw_version.macRev);
3940 }
3941 else {
3942 used = snprintf(hw_name, len,
3943 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3944 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3945 ah->hw_version.macRev,
3946 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3947 AR_RADIO_SREV_MAJOR)),
3948 ah->hw_version.phyRev);
3949 }
3950
3951 hw_name[used] = '\0';
3952 }
3953 EXPORT_SYMBOL(ath9k_hw_name);
x86 "subsystem" repository