arch/powerpc/platforms/celleb/scc_epci.c

   1 /*
   2  * Support for SCC external PCI
   3  *
   4  * (C) Copyright 2004-2007 TOSHIBA CORPORATION
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21 #undef DEBUG
  22
  23 #include <linux/kernel.h>
  24 #include <linux/threads.h>
  25 #include <linux/pci.h>
  26 #include <linux/init.h>
  27 #include <linux/pci_regs.h>
  28 #include <linux/bootmem.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/prom.h>
  33 #include <asm/machdep.h>
  34 #include <asm/pci-bridge.h>
  35 #include <asm/ppc-pci.h>
  36
  37 #include "scc.h"
  38 #include "../cell/celleb_pci.h"
  39 #include "interrupt.h"
  40
  41 #define MAX_PCI_DEVICES   32
  42 #define MAX_PCI_FUNCTIONS  8
  43
  44 #define iob()  __asm__ __volatile__("eieio; sync":::"memory")
  45
  46 static inline PCI_IO_ADDR celleb_epci_get_epci_base(
  47                                         struct pci_controller *hose)
  48 {
  49         /*
  50          * Note:
  51          * Celleb epci uses cfg_addr as a base address for
  52          * epci control registers.
  53          */
  54
  55         return hose->cfg_addr;
  56 }
  57
  58 static inline PCI_IO_ADDR celleb_epci_get_epci_cfg(
  59                                         struct pci_controller *hose)
  60 {
  61         /*
  62          * Note:
  63          * Celleb epci uses cfg_data as a base address for
  64          * configuration area for epci devices.
  65          */
  66
  67         return hose->cfg_data;
  68 }
  69
  70 static inline void clear_and_disable_master_abort_interrupt(
  71                                         struct pci_controller *hose)
  72 {
  73         PCI_IO_ADDR epci_base;
  74         PCI_IO_ADDR reg;
  75         epci_base = celleb_epci_get_epci_base(hose);
  76         reg = epci_base + PCI_COMMAND;
  77         out_be32(reg, in_be32(reg) | (PCI_STATUS_REC_MASTER_ABORT << 16));
  78 }
  79
  80 static int celleb_epci_check_abort(struct pci_controller *hose,
  81                                    PCI_IO_ADDR addr)
  82 {
  83         PCI_IO_ADDR reg;
  84         PCI_IO_ADDR epci_base;
  85         u32 val;
  86
  87         iob();
  88         epci_base = celleb_epci_get_epci_base(hose);
  89
  90         reg = epci_base + PCI_COMMAND;
  91         val = in_be32(reg);
  92
  93         if (val & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
  94                 out_be32(reg,
  95                          (val & 0xffff) | (PCI_STATUS_REC_MASTER_ABORT << 16));
  96
  97                 /* clear PCI Controller error, FRE, PMFE */
  98                 reg = epci_base + SCC_EPCI_STATUS;
  99                 out_be32(reg, SCC_EPCI_INT_PAI);
 100
 101                 reg = epci_base + SCC_EPCI_VCSR;
 102                 val = in_be32(reg) & 0xffff;
 103                 val |= SCC_EPCI_VCSR_FRE;
 104                 out_be32(reg, val);
 105
 106                 reg = epci_base + SCC_EPCI_VISTAT;
 107                 out_be32(reg, SCC_EPCI_VISTAT_PMFE);
 108                 return PCIBIOS_DEVICE_NOT_FOUND;
 109         }
 110
 111         return PCIBIOS_SUCCESSFUL;
 112 }
 113
 114 static PCI_IO_ADDR celleb_epci_make_config_addr(
 115                                         struct pci_bus *bus,
 116                                         struct pci_controller *hose,
 117                                         unsigned int devfn, int where)
 118 {
 119         PCI_IO_ADDR addr;
 120
 121         if (bus != hose->bus)
 122                 addr = celleb_epci_get_epci_cfg(hose) +
 123                        (((bus->number & 0xff) << 16)
 124                         | ((devfn & 0xff) << 8)
 125                         | (where & 0xff)
 126                         | 0x01000000);
 127         else
 128                 addr = celleb_epci_get_epci_cfg(hose) +
 129                        (((devfn & 0xff) << 8) | (where & 0xff));
 130
 131         pr_debug("EPCI: config_addr = 0x%p\n", addr);
 132
 133         return addr;
 134 }
 135
 136 static int celleb_epci_read_config(struct pci_bus *bus,
 137                         unsigned int devfn, int where, int size, u32 *val)
 138 {
 139         PCI_IO_ADDR epci_base;
 140         PCI_IO_ADDR addr;
 141         struct device_node *node;
 142         struct pci_controller *hose;
 143
 144         /* allignment check */
 145         BUG_ON(where % size);
 146
 147         node = (struct device_node *)bus->sysdata;
 148         hose = pci_find_hose_for_OF_device(node);
 149
 150         if (!celleb_epci_get_epci_cfg(hose))
 151                 return PCIBIOS_DEVICE_NOT_FOUND;
 152
 153         if (bus->number == hose->first_busno && devfn == 0) {
 154                 /* EPCI controller self */
 155
 156                 epci_base = celleb_epci_get_epci_base(hose);
 157                 addr = epci_base + where;
 158
 159                 switch (size) {
 160                 case 1:
 161                         *val = in_8(addr);
 162                         break;
 163                 case 2:
 164                         *val = in_be16(addr);
 165                         break;
 166                 case 4:
 167                         *val = in_be32(addr);
 168                         break;
 169                 default:
 170                         return PCIBIOS_DEVICE_NOT_FOUND;
 171                 }
 172
 173         } else {
 174
 175                 clear_and_disable_master_abort_interrupt(hose);
 176                 addr = celleb_epci_make_config_addr(bus, hose, devfn, where);
 177
 178                 switch (size) {
 179                 case 1:
 180                         *val = in_8(addr);
 181                         break;
 182                 case 2:
 183                         *val = in_le16(addr);
 184                         break;
 185                 case 4:
 186                         *val = in_le32(addr);
 187                         break;
 188                 default:
 189                         return PCIBIOS_DEVICE_NOT_FOUND;
 190                 }
 191         }
 192
 193         pr_debug("EPCI: "
 194                  "addr=0x%p, devfn=0x%x, where=0x%x, size=0x%x, val=0x%x\n",
 195                  addr, devfn, where, size, *val);
 196
 197         return celleb_epci_check_abort(hose, NULL);
 198 }
 199
 200 static int celleb_epci_write_config(struct pci_bus *bus,
 201                         unsigned int devfn, int where, int size, u32 val)
 202 {
 203         PCI_IO_ADDR epci_base;
 204         PCI_IO_ADDR addr;
 205         struct device_node *node;
 206         struct pci_controller *hose;
 207
 208         /* allignment check */
 209         BUG_ON(where % size);
 210
 211         node = (struct device_node *)bus->sysdata;
 212         hose = pci_find_hose_for_OF_device(node);
 213
 214
 215         if (!celleb_epci_get_epci_cfg(hose))
 216                 return PCIBIOS_DEVICE_NOT_FOUND;
 217
 218         if (bus->number == hose->first_busno && devfn == 0) {
 219                 /* EPCI controller self */
 220
 221                 epci_base = celleb_epci_get_epci_base(hose);
 222                 addr = epci_base + where;
 223
 224                 switch (size) {
 225                 case 1:
 226                         out_8(addr, val);
 227                         break;
 228                 case 2:
 229                         out_be16(addr, val);
 230                         break;
 231                 case 4:
 232                         out_be32(addr, val);
 233                         break;
 234                 default:
 235                         return PCIBIOS_DEVICE_NOT_FOUND;
 236                 }
 237
 238         } else {
 239
 240                 clear_and_disable_master_abort_interrupt(hose);
 241                 addr = celleb_epci_make_config_addr(bus, hose, devfn, where);
 242
 243                 switch (size) {
 244                 case 1:
 245                         out_8(addr, val);
 246                         break;
 247                 case 2:
 248                         out_le16(addr, val);
 249                         break;
 250                 case 4:
 251                         out_le32(addr, val);
 252                         break;
 253                 default:
 254                         return PCIBIOS_DEVICE_NOT_FOUND;
 255                 }
 256         }
 257
 258         return celleb_epci_check_abort(hose, addr);
 259 }
 260
 261 struct pci_ops celleb_epci_ops = {
 262         .read = celleb_epci_read_config,
 263         .write = celleb_epci_write_config,
 264 };
 265
 266 /* to be moved in FW */
 267 static int __init celleb_epci_init(struct pci_controller *hose)
 268 {
 269         u32 val;
 270         PCI_IO_ADDR reg;
 271         PCI_IO_ADDR epci_base;
 272         int hwres = 0;
 273
 274         epci_base = celleb_epci_get_epci_base(hose);
 275
 276         /* PCI core reset(Internal bus and PCI clock) */
 277         reg = epci_base + SCC_EPCI_CKCTRL;
 278         val = in_be32(reg);
 279         if (val == 0x00030101)
 280                 hwres = 1;
 281         else {
 282                 val &= ~(SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
 283                 out_be32(reg, val);
 284
 285                 /* set PCI core clock */
 286                 val = in_be32(reg);
 287                 val |= (SCC_EPCI_CKCTRL_OCLKEN | SCC_EPCI_CKCTRL_LCLKEN);
 288                 out_be32(reg, val);
 289
 290                 /* release PCI core reset (internal bus) */
 291                 val = in_be32(reg);
 292                 val |= SCC_EPCI_CKCTRL_CRST0;
 293                 out_be32(reg, val);
 294
 295                 /* set PCI clock select */
 296                 reg = epci_base + SCC_EPCI_CLKRST;
 297                 val = in_be32(reg);
 298                 val &= ~SCC_EPCI_CLKRST_CKS_MASK;
 299                 val |= SCC_EPCI_CLKRST_CKS_2;
 300                 out_be32(reg, val);
 301
 302                 /* set arbiter */
 303                 reg = epci_base + SCC_EPCI_ABTSET;
 304                 out_be32(reg, 0x0f1f001f);      /* temporary value */
 305
 306                 /* buffer on */
 307                 reg = epci_base + SCC_EPCI_CLKRST;
 308                 val = in_be32(reg);
 309                 val |= SCC_EPCI_CLKRST_BC;
 310                 out_be32(reg, val);
 311
 312                 /* PCI clock enable */
 313                 val = in_be32(reg);
 314                 val |= SCC_EPCI_CLKRST_PCKEN;
 315                 out_be32(reg, val);
 316
 317                 /* release PCI core reset (all) */
 318                 reg = epci_base + SCC_EPCI_CKCTRL;
 319                 val = in_be32(reg);
 320                 val |= (SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
 321                 out_be32(reg, val);
 322
 323                 /* set base translation registers. (already set by Beat) */
 324
 325                 /* set base address masks. (already set by Beat) */
 326         }
 327
 328         /* release interrupt masks and clear all interrupts */
 329         reg = epci_base + SCC_EPCI_INTSET;
 330         out_be32(reg, 0x013f011f);      /* all interrupts enable */
 331         reg = epci_base + SCC_EPCI_VIENAB;
 332         val = SCC_EPCI_VIENAB_PMPEE | SCC_EPCI_VIENAB_PMFEE;
 333         out_be32(reg, val);
 334         reg = epci_base + SCC_EPCI_STATUS;
 335         out_be32(reg, 0xffffffff);
 336         reg = epci_base + SCC_EPCI_VISTAT;
 337         out_be32(reg, 0xffffffff);
 338
 339         /* disable PCI->IB address translation */
 340         reg = epci_base + SCC_EPCI_VCSR;
 341         val = in_be32(reg);
 342         val &= ~(SCC_EPCI_VCSR_DR | SCC_EPCI_VCSR_AT);
 343         out_be32(reg, val);
 344
 345         /* set base addresses. (no need to set?) */
 346
 347         /* memory space, bus master enable */
 348         reg = epci_base + PCI_COMMAND;
 349         val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 350         out_be32(reg, val);
 351
 352         /* endian mode setup */
 353         reg = epci_base + SCC_EPCI_ECMODE;
 354         val = 0x00550155;
 355         out_be32(reg, val);
 356
 357         /* set control option */
 358         reg = epci_base + SCC_EPCI_CNTOPT;
 359         val = in_be32(reg);
 360         val |= SCC_EPCI_CNTOPT_O2PMB;
 361         out_be32(reg, val);
 362
 363         /* XXX: temporay: set registers for address conversion setup */
 364         reg = epci_base + SCC_EPCI_CNF10_REG;
 365         out_be32(reg, 0x80000008);
 366         reg = epci_base + SCC_EPCI_CNF14_REG;
 367         out_be32(reg, 0x40000008);
 368
 369         reg = epci_base + SCC_EPCI_BAM0;
 370         out_be32(reg, 0x80000000);
 371         reg = epci_base + SCC_EPCI_BAM1;
 372         out_be32(reg, 0xe0000000);
 373
 374         reg = epci_base + SCC_EPCI_PVBAT;
 375         out_be32(reg, 0x80000000);
 376
 377         if (!hwres) {
 378                 /* release external PCI reset */
 379                 reg = epci_base + SCC_EPCI_CLKRST;
 380                 val = in_be32(reg);
 381                 val |= SCC_EPCI_CLKRST_PCIRST;
 382                 out_be32(reg, val);
 383         }
 384
 385         return 0;
 386 }
 387
 388 static int __init celleb_setup_epci(struct device_node *node,
 389                                     struct pci_controller *hose)
 390 {
 391         struct resource r;
 392
 393         pr_debug("PCI: celleb_setup_epci()\n");
 394
 395         /*
 396          * Note:
 397          * Celleb epci uses cfg_addr and cfg_data member of
 398          * pci_controller structure in irregular way.
 399          *
 400          * cfg_addr is used to map for control registers of
 401          * celleb epci.
 402          *
 403          * cfg_data is used for configuration area of devices
 404          * on Celleb epci buses.
 405          */
 406
 407         if (of_address_to_resource(node, 0, &r))
 408                 goto error;
 409         hose->cfg_addr = ioremap(r.start, (r.end - r.start + 1));
 410         if (!hose->cfg_addr)
 411                 goto error;
 412         pr_debug("EPCI: cfg_addr map 0x%016lx->0x%016lx + 0x%016lx\n",
 413                  r.start, (unsigned long)hose->cfg_addr,
 414                 (r.end - r.start + 1));
 415
 416         if (of_address_to_resource(node, 2, &r))
 417                 goto error;
 418         hose->cfg_data = ioremap(r.start, (r.end - r.start + 1));
 419         if (!hose->cfg_data)
 420                 goto error;
 421         pr_debug("EPCI: cfg_data map 0x%016lx->0x%016lx + 0x%016lx\n",
 422                  r.start, (unsigned long)hose->cfg_data,
 423                 (r.end - r.start + 1));
 424
 425         hose->ops = &celleb_epci_ops;
 426         celleb_epci_init(hose);
 427
 428         return 0;
 429
 430 error:
 431         if (hose->cfg_addr)
 432                 iounmap(hose->cfg_addr);
 433
 434         if (hose->cfg_data)
 435                 iounmap(hose->cfg_data);
 436         return 1;
 437 }
 438
 439 struct celleb_phb_spec celleb_epci_spec __initdata = {
 440         .setup = celleb_setup_epci,
 441         .ops = &spiderpci_ops,
 442         .iowa_init = &spiderpci_iowa_init,
 443         .iowa_data = (void *)0,
 444 };