?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
perf/core, x86: Remove cpu_hw_events.interrupts
[linux-2.6/x86.git] / arch / x86 / kernel / cpu / perf_event.c
blob104292a58c2b27f37e4fdb889e630695431d3f06
1 /*
2 * Performance events x86 architecture code
3 *
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
11 *
12 * For licencing details see kernel-base/COPYING
13 */
14
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/highmem.h>
25 #include <linux/cpu.h>
26 #include <linux/bitops.h>
27
28 #include <asm/apic.h>
29 #include <asm/stacktrace.h>
30 #include <asm/nmi.h>
31
32 #if 0
33 #undef wrmsrl
34 #define wrmsrl(msr, val) \
35 do { \
36 trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
37 (unsigned long)(val)); \
38 native_write_msr((msr), (u32)((u64)(val)), \
39 (u32)((u64)(val) >> 32)); \
40 } while (0)
41 #endif
42
43 /*
44 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
45 */
46 static unsigned long
47 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
48 {
49 unsigned long offset, addr = (unsigned long)from;
50 int type = in_nmi() ? KM_NMI : KM_IRQ0;
51 unsigned long size, len = 0;
52 struct page *page;
53 void *map;
54 int ret;
55
56 do {
57 ret = __get_user_pages_fast(addr, 1, 0, &page);
58 if (!ret)
59 break;
60
61 offset = addr & (PAGE_SIZE - 1);
62 size = min(PAGE_SIZE - offset, n - len);
63
64 map = kmap_atomic(page, type);
65 memcpy(to, map+offset, size);
66 kunmap_atomic(map, type);
67 put_page(page);
68
69 len += size;
70 to += size;
71 addr += size;
72
73 } while (len < n);
74
75 return len;
76 }
77
78 static u64 perf_event_mask __read_mostly;
79
80 struct event_constraint {
81 union {
82 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
83 u64 idxmsk64;
84 };
85 u64 code;
86 u64 cmask;
87 int weight;
88 };
89
90 struct amd_nb {
91 int nb_id; /* NorthBridge id */
92 int refcnt; /* reference count */
93 struct perf_event *owners[X86_PMC_IDX_MAX];
94 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
95 };
96
97 #define MAX_LBR_ENTRIES 16
98
99 struct cpu_hw_events {
100 /*
101 * Generic x86 PMC bits
102 */
103 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
104 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
105 int enabled;
106
107 int n_events;
108 int n_added;
109 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
110 u64 tags[X86_PMC_IDX_MAX];
111 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
112
113 /*
114 * Intel DebugStore bits
115 */
116 struct debug_store *ds;
117 u64 pebs_enabled;
118
119 /*
120 * Intel LBR bits
121 */
122 int lbr_users;
123 void *lbr_context;
124 struct perf_branch_stack lbr_stack;
125 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
126
127 /*
128 * AMD specific bits
129 */
130 struct amd_nb *amd_nb;
131 };
132
133 #define __EVENT_CONSTRAINT(c, n, m, w) {\
134 { .idxmsk64 = (n) }, \
135 .code = (c), \
136 .cmask = (m), \
137 .weight = (w), \
138 }
139
140 #define EVENT_CONSTRAINT(c, n, m) \
141 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
142
143 /*
144 * Constraint on the Event code.
145 */
146 #define INTEL_EVENT_CONSTRAINT(c, n) \
147 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVTSEL_MASK)
148
149 /*
150 * Constraint on the Event code + UMask + fixed-mask
151 */
152 #define FIXED_EVENT_CONSTRAINT(c, n) \
153 EVENT_CONSTRAINT(c, (1ULL << (32+n)), INTEL_ARCH_FIXED_MASK)
154
155 /*
156 * Constraint on the Event code + UMask
157 */
158 #define PEBS_EVENT_CONSTRAINT(c, n) \
159 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
160
161 #define EVENT_CONSTRAINT_END \
162 EVENT_CONSTRAINT(0, 0, 0)
163
164 #define for_each_event_constraint(e, c) \
165 for ((e) = (c); (e)->cmask; (e)++)
166
167 union perf_capabilities {
168 struct {
169 u64 lbr_format : 6;
170 u64 pebs_trap : 1;
171 u64 pebs_arch_reg : 1;
172 u64 pebs_format : 4;
173 u64 smm_freeze : 1;
174 };
175 u64 capabilities;
176 };
177
178 /*
179 * struct x86_pmu - generic x86 pmu
180 */
181 struct x86_pmu {
182 /*
183 * Generic x86 PMC bits
184 */
185 const char *name;
186 int version;
187 int (*handle_irq)(struct pt_regs *);
188 void (*disable_all)(void);
189 void (*enable_all)(void);
190 void (*enable)(struct perf_event *);
191 void (*disable)(struct perf_event *);
192 int (*hw_config)(struct perf_event_attr *attr, struct hw_perf_event *hwc);
193 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
194 unsigned eventsel;
195 unsigned perfctr;
196 u64 (*event_map)(int);
197 u64 (*raw_event)(u64);
198 int max_events;
199 int num_events;
200 int num_events_fixed;
201 int event_bits;
202 u64 event_mask;
203 int apic;
204 u64 max_period;
205 struct event_constraint *
206 (*get_event_constraints)(struct cpu_hw_events *cpuc,
207 struct perf_event *event);
208
209 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
210 struct perf_event *event);
211 struct event_constraint *event_constraints;
212 void (*quirks)(void);
213
214 void (*cpu_prepare)(int cpu);
215 void (*cpu_starting)(int cpu);
216 void (*cpu_dying)(int cpu);
217 void (*cpu_dead)(int cpu);
218
219 /*
220 * Intel Arch Perfmon v2+
221 */
222 u64 intel_ctrl;
223 union perf_capabilities intel_cap;
224
225 /*
226 * Intel DebugStore bits
227 */
228 int bts, pebs;
229 int pebs_record_size;
230 void (*drain_pebs)(struct pt_regs *regs);
231 struct event_constraint *pebs_constraints;
232
233 /*
234 * Intel LBR
235 */
236 unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
237 int lbr_nr; /* hardware stack size */
238 };
239
240 static struct x86_pmu x86_pmu __read_mostly;
241
242 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
243 .enabled = 1,
244 };
245
246 static int x86_perf_event_set_period(struct perf_event *event);
247
248 /*
249 * Generalized hw caching related hw_event table, filled
250 * in on a per model basis. A value of 0 means
251 * 'not supported', -1 means 'hw_event makes no sense on
252 * this CPU', any other value means the raw hw_event
253 * ID.
254 */
255
256 #define C(x) PERF_COUNT_HW_CACHE_##x
257
258 static u64 __read_mostly hw_cache_event_ids
259 [PERF_COUNT_HW_CACHE_MAX]
260 [PERF_COUNT_HW_CACHE_OP_MAX]
261 [PERF_COUNT_HW_CACHE_RESULT_MAX];
262
263 /*
264 * Propagate event elapsed time into the generic event.
265 * Can only be executed on the CPU where the event is active.
266 * Returns the delta events processed.
267 */
268 static u64
269 x86_perf_event_update(struct perf_event *event)
270 {
271 struct hw_perf_event *hwc = &event->hw;
272 int shift = 64 - x86_pmu.event_bits;
273 u64 prev_raw_count, new_raw_count;
274 int idx = hwc->idx;
275 s64 delta;
276
277 if (idx == X86_PMC_IDX_FIXED_BTS)
278 return 0;
279
280 /*
281 * Careful: an NMI might modify the previous event value.
282 *
283 * Our tactic to handle this is to first atomically read and
284 * exchange a new raw count - then add that new-prev delta
285 * count to the generic event atomically:
286 */
287 again:
288 prev_raw_count = atomic64_read(&hwc->prev_count);
289 rdmsrl(hwc->event_base + idx, new_raw_count);
290
291 if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
292 new_raw_count) != prev_raw_count)
293 goto again;
294
295 /*
296 * Now we have the new raw value and have updated the prev
297 * timestamp already. We can now calculate the elapsed delta
298 * (event-)time and add that to the generic event.
299 *
300 * Careful, not all hw sign-extends above the physical width
301 * of the count.
302 */
303 delta = (new_raw_count << shift) - (prev_raw_count << shift);
304 delta >>= shift;
305
306 atomic64_add(delta, &event->count);
307 atomic64_sub(delta, &hwc->period_left);
308
309 return new_raw_count;
310 }
311
312 static atomic_t active_events;
313 static DEFINE_MUTEX(pmc_reserve_mutex);
314
315 #ifdef CONFIG_X86_LOCAL_APIC
316
317 static bool reserve_pmc_hardware(void)
318 {
319 int i;
320
321 if (nmi_watchdog == NMI_LOCAL_APIC)
322 disable_lapic_nmi_watchdog();
323
324 for (i = 0; i < x86_pmu.num_events; i++) {
325 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
326 goto perfctr_fail;
327 }
328
329 for (i = 0; i < x86_pmu.num_events; i++) {
330 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
331 goto eventsel_fail;
332 }
333
334 return true;
335
336 eventsel_fail:
337 for (i--; i >= 0; i--)
338 release_evntsel_nmi(x86_pmu.eventsel + i);
339
340 i = x86_pmu.num_events;
341
342 perfctr_fail:
343 for (i--; i >= 0; i--)
344 release_perfctr_nmi(x86_pmu.perfctr + i);
345
346 if (nmi_watchdog == NMI_LOCAL_APIC)
347 enable_lapic_nmi_watchdog();
348
349 return false;
350 }
351
352 static void release_pmc_hardware(void)
353 {
354 int i;
355
356 for (i = 0; i < x86_pmu.num_events; i++) {
357 release_perfctr_nmi(x86_pmu.perfctr + i);
358 release_evntsel_nmi(x86_pmu.eventsel + i);
359 }
360
361 if (nmi_watchdog == NMI_LOCAL_APIC)
362 enable_lapic_nmi_watchdog();
363 }
364
365 #else
366
367 static bool reserve_pmc_hardware(void) { return true; }
368 static void release_pmc_hardware(void) {}
369
370 #endif
371
372 static int reserve_ds_buffers(void);
373 static void release_ds_buffers(void);
374
375 static void hw_perf_event_destroy(struct perf_event *event)
376 {
377 if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
378 release_pmc_hardware();
379 release_ds_buffers();
380 mutex_unlock(&pmc_reserve_mutex);
381 }
382 }
383
384 static inline int x86_pmu_initialized(void)
385 {
386 return x86_pmu.handle_irq != NULL;
387 }
388
389 static inline int
390 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
391 {
392 unsigned int cache_type, cache_op, cache_result;
393 u64 config, val;
394
395 config = attr->config;
396
397 cache_type = (config >> 0) & 0xff;
398 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
399 return -EINVAL;
400
401 cache_op = (config >> 8) & 0xff;
402 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
403 return -EINVAL;
404
405 cache_result = (config >> 16) & 0xff;
406 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
407 return -EINVAL;
408
409 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
410
411 if (val == 0)
412 return -ENOENT;
413
414 if (val == -1)
415 return -EINVAL;
416
417 hwc->config |= val;
418
419 return 0;
420 }
421
422 static int x86_hw_config(struct perf_event_attr *attr, struct hw_perf_event *hwc)
423 {
424 /*
425 * Generate PMC IRQs:
426 * (keep 'enabled' bit clear for now)
427 */
428 hwc->config = ARCH_PERFMON_EVENTSEL_INT;
429
430 /*
431 * Count user and OS events unless requested not to
432 */
433 if (!attr->exclude_user)
434 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
435 if (!attr->exclude_kernel)
436 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
437
438 return 0;
439 }
440
441 /*
442 * Setup the hardware configuration for a given attr_type
443 */
444 static int __hw_perf_event_init(struct perf_event *event)
445 {
446 struct perf_event_attr *attr = &event->attr;
447 struct hw_perf_event *hwc = &event->hw;
448 u64 config;
449 int err;
450
451 if (!x86_pmu_initialized())
452 return -ENODEV;
453
454 err = 0;
455 if (!atomic_inc_not_zero(&active_events)) {
456 mutex_lock(&pmc_reserve_mutex);
457 if (atomic_read(&active_events) == 0) {
458 if (!reserve_pmc_hardware())
459 err = -EBUSY;
460 else
461 err = reserve_ds_buffers();
462 }
463 if (!err)
464 atomic_inc(&active_events);
465 mutex_unlock(&pmc_reserve_mutex);
466 }
467 if (err)
468 return err;
469
470 event->destroy = hw_perf_event_destroy;
471
472 hwc->idx = -1;
473 hwc->last_cpu = -1;
474 hwc->last_tag = ~0ULL;
475
476 /* Processor specifics */
477 err = x86_pmu.hw_config(attr, hwc);
478 if (err)
479 return err;
480
481 if (!hwc->sample_period) {
482 hwc->sample_period = x86_pmu.max_period;
483 hwc->last_period = hwc->sample_period;
484 atomic64_set(&hwc->period_left, hwc->sample_period);
485 } else {
486 /*
487 * If we have a PMU initialized but no APIC
488 * interrupts, we cannot sample hardware
489 * events (user-space has to fall back and
490 * sample via a hrtimer based software event):
491 */
492 if (!x86_pmu.apic)
493 return -EOPNOTSUPP;
494 }
495
496 /*
497 * Raw hw_event type provide the config in the hw_event structure
498 */
499 if (attr->type == PERF_TYPE_RAW) {
500 hwc->config |= x86_pmu.raw_event(attr->config);
501 if ((hwc->config & ARCH_PERFMON_EVENTSEL_ANY) &&
502 perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
503 return -EACCES;
504 return 0;
505 }
506
507 if (attr->type == PERF_TYPE_HW_CACHE)
508 return set_ext_hw_attr(hwc, attr);
509
510 if (attr->config >= x86_pmu.max_events)
511 return -EINVAL;
512
513 /*
514 * The generic map:
515 */
516 config = x86_pmu.event_map(attr->config);
517
518 if (config == 0)
519 return -ENOENT;
520
521 if (config == -1LL)
522 return -EINVAL;
523
524 /*
525 * Branch tracing:
526 */
527 if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
528 (hwc->sample_period == 1)) {
529 /* BTS is not supported by this architecture. */
530 if (!x86_pmu.bts)
531 return -EOPNOTSUPP;
532
533 /* BTS is currently only allowed for user-mode. */
534 if (!attr->exclude_kernel)
535 return -EOPNOTSUPP;
536 }
537
538 hwc->config |= config;
539
540 return 0;
541 }
542
543 static void x86_pmu_disable_all(void)
544 {
545 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
546 int idx;
547
548 for (idx = 0; idx < x86_pmu.num_events; idx++) {
549 u64 val;
550
551 if (!test_bit(idx, cpuc->active_mask))
552 continue;
553 rdmsrl(x86_pmu.eventsel + idx, val);
554 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
555 continue;
556 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
557 wrmsrl(x86_pmu.eventsel + idx, val);
558 }
559 }
560
561 void hw_perf_disable(void)
562 {
563 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
564
565 if (!x86_pmu_initialized())
566 return;
567
568 if (!cpuc->enabled)
569 return;
570
571 cpuc->n_added = 0;
572 cpuc->enabled = 0;
573 barrier();
574
575 x86_pmu.disable_all();
576 }
577
578 static void x86_pmu_enable_all(void)
579 {
580 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
581 int idx;
582
583 for (idx = 0; idx < x86_pmu.num_events; idx++) {
584 struct perf_event *event = cpuc->events[idx];
585 u64 val;
586
587 if (!test_bit(idx, cpuc->active_mask))
588 continue;
589
590 val = event->hw.config;
591 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
592 wrmsrl(x86_pmu.eventsel + idx, val);
593 }
594 }
595
596 static const struct pmu pmu;
597
598 static inline int is_x86_event(struct perf_event *event)
599 {
600 return event->pmu == &pmu;
601 }
602
603 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
604 {
605 struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
606 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
607 int i, j, w, wmax, num = 0;
608 struct hw_perf_event *hwc;
609
610 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
611
612 for (i = 0; i < n; i++) {
613 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
614 constraints[i] = c;
615 }
616
617 /*
618 * fastpath, try to reuse previous register
619 */
620 for (i = 0; i < n; i++) {
621 hwc = &cpuc->event_list[i]->hw;
622 c = constraints[i];
623
624 /* never assigned */
625 if (hwc->idx == -1)
626 break;
627
628 /* constraint still honored */
629 if (!test_bit(hwc->idx, c->idxmsk))
630 break;
631
632 /* not already used */
633 if (test_bit(hwc->idx, used_mask))
634 break;
635
636 __set_bit(hwc->idx, used_mask);
637 if (assign)
638 assign[i] = hwc->idx;
639 }
640 if (i == n)
641 goto done;
642
643 /*
644 * begin slow path
645 */
646
647 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
648
649 /*
650 * weight = number of possible counters
651 *
652 * 1 = most constrained, only works on one counter
653 * wmax = least constrained, works on any counter
654 *
655 * assign events to counters starting with most
656 * constrained events.
657 */
658 wmax = x86_pmu.num_events;
659
660 /*
661 * when fixed event counters are present,
662 * wmax is incremented by 1 to account
663 * for one more choice
664 */
665 if (x86_pmu.num_events_fixed)
666 wmax++;
667
668 for (w = 1, num = n; num && w <= wmax; w++) {
669 /* for each event */
670 for (i = 0; num && i < n; i++) {
671 c = constraints[i];
672 hwc = &cpuc->event_list[i]->hw;
673
674 if (c->weight != w)
675 continue;
676
677 for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
678 if (!test_bit(j, used_mask))
679 break;
680 }
681
682 if (j == X86_PMC_IDX_MAX)
683 break;
684
685 __set_bit(j, used_mask);
686
687 if (assign)
688 assign[i] = j;
689 num--;
690 }
691 }
692 done:
693 /*
694 * scheduling failed or is just a simulation,
695 * free resources if necessary
696 */
697 if (!assign || num) {
698 for (i = 0; i < n; i++) {
699 if (x86_pmu.put_event_constraints)
700 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
701 }
702 }
703 return num ? -ENOSPC : 0;
704 }
705
706 /*
707 * dogrp: true if must collect siblings events (group)
708 * returns total number of events and error code
709 */
710 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
711 {
712 struct perf_event *event;
713 int n, max_count;
714
715 max_count = x86_pmu.num_events + x86_pmu.num_events_fixed;
716
717 /* current number of events already accepted */
718 n = cpuc->n_events;
719
720 if (is_x86_event(leader)) {
721 if (n >= max_count)
722 return -ENOSPC;
723 cpuc->event_list[n] = leader;
724 n++;
725 }
726 if (!dogrp)
727 return n;
728
729 list_for_each_entry(event, &leader->sibling_list, group_entry) {
730 if (!is_x86_event(event) ||
731 event->state <= PERF_EVENT_STATE_OFF)
732 continue;
733
734 if (n >= max_count)
735 return -ENOSPC;
736
737 cpuc->event_list[n] = event;
738 n++;
739 }
740 return n;
741 }
742
743 static inline void x86_assign_hw_event(struct perf_event *event,
744 struct cpu_hw_events *cpuc, int i)
745 {
746 struct hw_perf_event *hwc = &event->hw;
747
748 hwc->idx = cpuc->assign[i];
749 hwc->last_cpu = smp_processor_id();
750 hwc->last_tag = ++cpuc->tags[i];
751
752 if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
753 hwc->config_base = 0;
754 hwc->event_base = 0;
755 } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
756 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
757 /*
758 * We set it so that event_base + idx in wrmsr/rdmsr maps to
759 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
760 */
761 hwc->event_base =
762 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
763 } else {
764 hwc->config_base = x86_pmu.eventsel;
765 hwc->event_base = x86_pmu.perfctr;
766 }
767 }
768
769 static inline int match_prev_assignment(struct hw_perf_event *hwc,
770 struct cpu_hw_events *cpuc,
771 int i)
772 {
773 return hwc->idx == cpuc->assign[i] &&
774 hwc->last_cpu == smp_processor_id() &&
775 hwc->last_tag == cpuc->tags[i];
776 }
777
778 static int x86_pmu_start(struct perf_event *event);
779 static void x86_pmu_stop(struct perf_event *event);
780
781 void hw_perf_enable(void)
782 {
783 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
784 struct perf_event *event;
785 struct hw_perf_event *hwc;
786 int i;
787
788 if (!x86_pmu_initialized())
789 return;
790
791 if (cpuc->enabled)
792 return;
793
794 if (cpuc->n_added) {
795 int n_running = cpuc->n_events - cpuc->n_added;
796 /*
797 * apply assignment obtained either from
798 * hw_perf_group_sched_in() or x86_pmu_enable()
799 *
800 * step1: save events moving to new counters
801 * step2: reprogram moved events into new counters
802 */
803 for (i = 0; i < n_running; i++) {
804 event = cpuc->event_list[i];
805 hwc = &event->hw;
806
807 /*
808 * we can avoid reprogramming counter if:
809 * - assigned same counter as last time
810 * - running on same CPU as last time
811 * - no other event has used the counter since
812 */
813 if (hwc->idx == -1 ||
814 match_prev_assignment(hwc, cpuc, i))
815 continue;
816
817 x86_pmu_stop(event);
818 }
819
820 for (i = 0; i < cpuc->n_events; i++) {
821 event = cpuc->event_list[i];
822 hwc = &event->hw;
823
824 if (!match_prev_assignment(hwc, cpuc, i))
825 x86_assign_hw_event(event, cpuc, i);
826 else if (i < n_running)
827 continue;
828
829 x86_pmu_start(event);
830 }
831 cpuc->n_added = 0;
832 perf_events_lapic_init();
833 }
834
835 cpuc->enabled = 1;
836 barrier();
837
838 x86_pmu.enable_all();
839 }
840
841 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc)
842 {
843 wrmsrl(hwc->config_base + hwc->idx,
844 hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE);
845 }
846
847 static inline void x86_pmu_disable_event(struct perf_event *event)
848 {
849 struct hw_perf_event *hwc = &event->hw;
850
851 wrmsrl(hwc->config_base + hwc->idx, hwc->config);
852 }
853
854 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
855
856 /*
857 * Set the next IRQ period, based on the hwc->period_left value.
858 * To be called with the event disabled in hw:
859 */
860 static int
861 x86_perf_event_set_period(struct perf_event *event)
862 {
863 struct hw_perf_event *hwc = &event->hw;
864 s64 left = atomic64_read(&hwc->period_left);
865 s64 period = hwc->sample_period;
866 int ret = 0, idx = hwc->idx;
867
868 if (idx == X86_PMC_IDX_FIXED_BTS)
869 return 0;
870
871 /*
872 * If we are way outside a reasonable range then just skip forward:
873 */
874 if (unlikely(left <= -period)) {
875 left = period;
876 atomic64_set(&hwc->period_left, left);
877 hwc->last_period = period;
878 ret = 1;
879 }
880
881 if (unlikely(left <= 0)) {
882 left += period;
883 atomic64_set(&hwc->period_left, left);
884 hwc->last_period = period;
885 ret = 1;
886 }
887 /*
888 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
889 */
890 if (unlikely(left < 2))
891 left = 2;
892
893 if (left > x86_pmu.max_period)
894 left = x86_pmu.max_period;
895
896 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
897
898 /*
899 * The hw event starts counting from this event offset,
900 * mark it to be able to extra future deltas:
901 */
902 atomic64_set(&hwc->prev_count, (u64)-left);
903
904 wrmsrl(hwc->event_base + idx,
905 (u64)(-left) & x86_pmu.event_mask);
906
907 perf_event_update_userpage(event);
908
909 return ret;
910 }
911
912 static void x86_pmu_enable_event(struct perf_event *event)
913 {
914 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
915 if (cpuc->enabled)
916 __x86_pmu_enable_event(&event->hw);
917 }
918
919 /*
920 * activate a single event
921 *
922 * The event is added to the group of enabled events
923 * but only if it can be scehduled with existing events.
924 *
925 * Called with PMU disabled. If successful and return value 1,
926 * then guaranteed to call perf_enable() and hw_perf_enable()
927 */
928 static int x86_pmu_enable(struct perf_event *event)
929 {
930 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
931 struct hw_perf_event *hwc;
932 int assign[X86_PMC_IDX_MAX];
933 int n, n0, ret;
934
935 hwc = &event->hw;
936
937 n0 = cpuc->n_events;
938 n = collect_events(cpuc, event, false);
939 if (n < 0)
940 return n;
941
942 ret = x86_pmu.schedule_events(cpuc, n, assign);
943 if (ret)
944 return ret;
945 /*
946 * copy new assignment, now we know it is possible
947 * will be used by hw_perf_enable()
948 */
949 memcpy(cpuc->assign, assign, n*sizeof(int));
950
951 cpuc->n_events = n;
952 cpuc->n_added += n - n0;
953
954 return 0;
955 }
956
957 static int x86_pmu_start(struct perf_event *event)
958 {
959 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
960 int idx = event->hw.idx;
961
962 if (idx == -1)
963 return -EAGAIN;
964
965 x86_perf_event_set_period(event);
966 cpuc->events[idx] = event;
967 __set_bit(idx, cpuc->active_mask);
968 x86_pmu.enable(event);
969 perf_event_update_userpage(event);
970
971 return 0;
972 }
973
974 static void x86_pmu_unthrottle(struct perf_event *event)
975 {
976 int ret = x86_pmu_start(event);
977 WARN_ON_ONCE(ret);
978 }
979
980 void perf_event_print_debug(void)
981 {
982 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
983 u64 pebs;
984 struct cpu_hw_events *cpuc;
985 unsigned long flags;
986 int cpu, idx;
987
988 if (!x86_pmu.num_events)
989 return;
990
991 local_irq_save(flags);
992
993 cpu = smp_processor_id();
994 cpuc = &per_cpu(cpu_hw_events, cpu);
995
996 if (x86_pmu.version >= 2) {
997 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
998 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
999 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1000 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1001 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1002
1003 pr_info("\n");
1004 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1005 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1006 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1007 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1008 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1009 }
1010 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1011
1012 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1013 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1014 rdmsrl(x86_pmu.perfctr + idx, pmc_count);
1015
1016 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1017
1018 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1019 cpu, idx, pmc_ctrl);
1020 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1021 cpu, idx, pmc_count);
1022 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1023 cpu, idx, prev_left);
1024 }
1025 for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
1026 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1027
1028 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1029 cpu, idx, pmc_count);
1030 }
1031 local_irq_restore(flags);
1032 }
1033
1034 static void x86_pmu_stop(struct perf_event *event)
1035 {
1036 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1037 struct hw_perf_event *hwc = &event->hw;
1038 int idx = hwc->idx;
1039
1040 if (!__test_and_clear_bit(idx, cpuc->active_mask))
1041 return;
1042
1043 x86_pmu.disable(event);
1044
1045 /*
1046 * Drain the remaining delta count out of a event
1047 * that we are disabling:
1048 */
1049 x86_perf_event_update(event);
1050
1051 cpuc->events[idx] = NULL;
1052 }
1053
1054 static void x86_pmu_disable(struct perf_event *event)
1055 {
1056 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1057 int i;
1058
1059 x86_pmu_stop(event);
1060
1061 for (i = 0; i < cpuc->n_events; i++) {
1062 if (event == cpuc->event_list[i]) {
1063
1064 if (x86_pmu.put_event_constraints)
1065 x86_pmu.put_event_constraints(cpuc, event);
1066
1067 while (++i < cpuc->n_events)
1068 cpuc->event_list[i-1] = cpuc->event_list[i];
1069
1070 --cpuc->n_events;
1071 break;
1072 }
1073 }
1074 perf_event_update_userpage(event);
1075 }
1076
1077 static int x86_pmu_handle_irq(struct pt_regs *regs)
1078 {
1079 struct perf_sample_data data;
1080 struct cpu_hw_events *cpuc;
1081 struct perf_event *event;
1082 struct hw_perf_event *hwc;
1083 int idx, handled = 0;
1084 u64 val;
1085
1086 perf_sample_data_init(&data, 0);
1087
1088 cpuc = &__get_cpu_var(cpu_hw_events);
1089
1090 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1091 if (!test_bit(idx, cpuc->active_mask))
1092 continue;
1093
1094 event = cpuc->events[idx];
1095 hwc = &event->hw;
1096
1097 val = x86_perf_event_update(event);
1098 if (val & (1ULL << (x86_pmu.event_bits - 1)))
1099 continue;
1100
1101 /*
1102 * event overflow
1103 */
1104 handled = 1;
1105 data.period = event->hw.last_period;
1106
1107 if (!x86_perf_event_set_period(event))
1108 continue;
1109
1110 if (perf_event_overflow(event, 1, &data, regs))
1111 x86_pmu_stop(event);
1112 }
1113
1114 if (handled)
1115 inc_irq_stat(apic_perf_irqs);
1116
1117 return handled;
1118 }
1119
1120 void smp_perf_pending_interrupt(struct pt_regs *regs)
1121 {
1122 irq_enter();
1123 ack_APIC_irq();
1124 inc_irq_stat(apic_pending_irqs);
1125 perf_event_do_pending();
1126 irq_exit();
1127 }
1128
1129 void set_perf_event_pending(void)
1130 {
1131 #ifdef CONFIG_X86_LOCAL_APIC
1132 if (!x86_pmu.apic || !x86_pmu_initialized())
1133 return;
1134
1135 apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1136 #endif
1137 }
1138
1139 void perf_events_lapic_init(void)
1140 {
1141 #ifdef CONFIG_X86_LOCAL_APIC
1142 if (!x86_pmu.apic || !x86_pmu_initialized())
1143 return;
1144
1145 /*
1146 * Always use NMI for PMU
1147 */
1148 apic_write(APIC_LVTPC, APIC_DM_NMI);
1149 #endif
1150 }
1151
1152 static int __kprobes
1153 perf_event_nmi_handler(struct notifier_block *self,
1154 unsigned long cmd, void *__args)
1155 {
1156 struct die_args *args = __args;
1157 struct pt_regs *regs;
1158
1159 if (!atomic_read(&active_events))
1160 return NOTIFY_DONE;
1161
1162 switch (cmd) {
1163 case DIE_NMI:
1164 case DIE_NMI_IPI:
1165 break;
1166
1167 default:
1168 return NOTIFY_DONE;
1169 }
1170
1171 regs = args->regs;
1172
1173 #ifdef CONFIG_X86_LOCAL_APIC
1174 apic_write(APIC_LVTPC, APIC_DM_NMI);
1175 #endif
1176 /*
1177 * Can't rely on the handled return value to say it was our NMI, two
1178 * events could trigger 'simultaneously' raising two back-to-back NMIs.
1179 *
1180 * If the first NMI handles both, the latter will be empty and daze
1181 * the CPU.
1182 */
1183 x86_pmu.handle_irq(regs);
1184
1185 return NOTIFY_STOP;
1186 }
1187
1188 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1189 .notifier_call = perf_event_nmi_handler,
1190 .next = NULL,
1191 .priority = 1
1192 };
1193
1194 static struct event_constraint unconstrained;
1195 static struct event_constraint emptyconstraint;
1196
1197 static struct event_constraint *
1198 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1199 {
1200 struct event_constraint *c;
1201
1202 if (x86_pmu.event_constraints) {
1203 for_each_event_constraint(c, x86_pmu.event_constraints) {
1204 if ((event->hw.config & c->cmask) == c->code)
1205 return c;
1206 }
1207 }
1208
1209 return &unconstrained;
1210 }
1211
1212 static int x86_event_sched_in(struct perf_event *event,
1213 struct perf_cpu_context *cpuctx)
1214 {
1215 int ret = 0;
1216
1217 event->state = PERF_EVENT_STATE_ACTIVE;
1218 event->oncpu = smp_processor_id();
1219 event->tstamp_running += event->ctx->time - event->tstamp_stopped;
1220
1221 if (!is_x86_event(event))
1222 ret = event->pmu->enable(event);
1223
1224 if (!ret && !is_software_event(event))
1225 cpuctx->active_oncpu++;
1226
1227 if (!ret && event->attr.exclusive)
1228 cpuctx->exclusive = 1;
1229
1230 return ret;
1231 }
1232
1233 static void x86_event_sched_out(struct perf_event *event,
1234 struct perf_cpu_context *cpuctx)
1235 {
1236 event->state = PERF_EVENT_STATE_INACTIVE;
1237 event->oncpu = -1;
1238
1239 if (!is_x86_event(event))
1240 event->pmu->disable(event);
1241
1242 event->tstamp_running -= event->ctx->time - event->tstamp_stopped;
1243
1244 if (!is_software_event(event))
1245 cpuctx->active_oncpu--;
1246
1247 if (event->attr.exclusive || !cpuctx->active_oncpu)
1248 cpuctx->exclusive = 0;
1249 }
1250
1251 /*
1252 * Called to enable a whole group of events.
1253 * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
1254 * Assumes the caller has disabled interrupts and has
1255 * frozen the PMU with hw_perf_save_disable.
1256 *
1257 * called with PMU disabled. If successful and return value 1,
1258 * then guaranteed to call perf_enable() and hw_perf_enable()
1259 */
1260 int hw_perf_group_sched_in(struct perf_event *leader,
1261 struct perf_cpu_context *cpuctx,
1262 struct perf_event_context *ctx)
1263 {
1264 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1265 struct perf_event *sub;
1266 int assign[X86_PMC_IDX_MAX];
1267 int n0, n1, ret;
1268
1269 if (!x86_pmu_initialized())
1270 return 0;
1271
1272 /* n0 = total number of events */
1273 n0 = collect_events(cpuc, leader, true);
1274 if (n0 < 0)
1275 return n0;
1276
1277 ret = x86_pmu.schedule_events(cpuc, n0, assign);
1278 if (ret)
1279 return ret;
1280
1281 ret = x86_event_sched_in(leader, cpuctx);
1282 if (ret)
1283 return ret;
1284
1285 n1 = 1;
1286 list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1287 if (sub->state > PERF_EVENT_STATE_OFF) {
1288 ret = x86_event_sched_in(sub, cpuctx);
1289 if (ret)
1290 goto undo;
1291 ++n1;
1292 }
1293 }
1294 /*
1295 * copy new assignment, now we know it is possible
1296 * will be used by hw_perf_enable()
1297 */
1298 memcpy(cpuc->assign, assign, n0*sizeof(int));
1299
1300 cpuc->n_events = n0;
1301 cpuc->n_added += n1;
1302 ctx->nr_active += n1;
1303
1304 /*
1305 * 1 means successful and events are active
1306 * This is not quite true because we defer
1307 * actual activation until hw_perf_enable() but
1308 * this way we* ensure caller won't try to enable
1309 * individual events
1310 */
1311 return 1;
1312 undo:
1313 x86_event_sched_out(leader, cpuctx);
1314 n0 = 1;
1315 list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1316 if (sub->state == PERF_EVENT_STATE_ACTIVE) {
1317 x86_event_sched_out(sub, cpuctx);
1318 if (++n0 == n1)
1319 break;
1320 }
1321 }
1322 return ret;
1323 }
1324
1325 #include "perf_event_amd.c"
1326 #include "perf_event_p6.c"
1327 #include "perf_event_p4.c"
1328 #include "perf_event_intel_lbr.c"
1329 #include "perf_event_intel_ds.c"
1330 #include "perf_event_intel.c"
1331
1332 static int __cpuinit
1333 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1334 {
1335 unsigned int cpu = (long)hcpu;
1336
1337 switch (action & ~CPU_TASKS_FROZEN) {
1338 case CPU_UP_PREPARE:
1339 if (x86_pmu.cpu_prepare)
1340 x86_pmu.cpu_prepare(cpu);
1341 break;
1342
1343 case CPU_STARTING:
1344 if (x86_pmu.cpu_starting)
1345 x86_pmu.cpu_starting(cpu);
1346 break;
1347
1348 case CPU_DYING:
1349 if (x86_pmu.cpu_dying)
1350 x86_pmu.cpu_dying(cpu);
1351 break;
1352
1353 case CPU_DEAD:
1354 if (x86_pmu.cpu_dead)
1355 x86_pmu.cpu_dead(cpu);
1356 break;
1357
1358 default:
1359 break;
1360 }
1361
1362 return NOTIFY_OK;
1363 }
1364
1365 static void __init pmu_check_apic(void)
1366 {
1367 if (cpu_has_apic)
1368 return;
1369
1370 x86_pmu.apic = 0;
1371 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1372 pr_info("no hardware sampling interrupt available.\n");
1373 }
1374
1375 void __init init_hw_perf_events(void)
1376 {
1377 struct event_constraint *c;
1378 int err;
1379
1380 pr_info("Performance Events: ");
1381
1382 switch (boot_cpu_data.x86_vendor) {
1383 case X86_VENDOR_INTEL:
1384 err = intel_pmu_init();
1385 break;
1386 case X86_VENDOR_AMD:
1387 err = amd_pmu_init();
1388 break;
1389 default:
1390 return;
1391 }
1392 if (err != 0) {
1393 pr_cont("no PMU driver, software events only.\n");
1394 return;
1395 }
1396
1397 pmu_check_apic();
1398
1399 pr_cont("%s PMU driver.\n", x86_pmu.name);
1400
1401 if (x86_pmu.quirks)
1402 x86_pmu.quirks();
1403
1404 if (x86_pmu.num_events > X86_PMC_MAX_GENERIC) {
1405 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1406 x86_pmu.num_events, X86_PMC_MAX_GENERIC);
1407 x86_pmu.num_events = X86_PMC_MAX_GENERIC;
1408 }
1409 perf_event_mask = (1 << x86_pmu.num_events) - 1;
1410 perf_max_events = x86_pmu.num_events;
1411
1412 if (x86_pmu.num_events_fixed > X86_PMC_MAX_FIXED) {
1413 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1414 x86_pmu.num_events_fixed, X86_PMC_MAX_FIXED);
1415 x86_pmu.num_events_fixed = X86_PMC_MAX_FIXED;
1416 }
1417
1418 perf_event_mask |=
1419 ((1LL << x86_pmu.num_events_fixed)-1) << X86_PMC_IDX_FIXED;
1420 x86_pmu.intel_ctrl = perf_event_mask;
1421
1422 perf_events_lapic_init();
1423 register_die_notifier(&perf_event_nmi_notifier);
1424
1425 unconstrained = (struct event_constraint)
1426 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_events) - 1,
1427 0, x86_pmu.num_events);
1428
1429 if (x86_pmu.event_constraints) {
1430 for_each_event_constraint(c, x86_pmu.event_constraints) {
1431 if (c->cmask != INTEL_ARCH_FIXED_MASK)
1432 continue;
1433
1434 c->idxmsk64 |= (1ULL << x86_pmu.num_events) - 1;
1435 c->weight += x86_pmu.num_events;
1436 }
1437 }
1438
1439 pr_info("... version: %d\n", x86_pmu.version);
1440 pr_info("... bit width: %d\n", x86_pmu.event_bits);
1441 pr_info("... generic registers: %d\n", x86_pmu.num_events);
1442 pr_info("... value mask: %016Lx\n", x86_pmu.event_mask);
1443 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1444 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_events_fixed);
1445 pr_info("... event mask: %016Lx\n", perf_event_mask);
1446
1447 perf_cpu_notifier(x86_pmu_notifier);
1448 }
1449
1450 static inline void x86_pmu_read(struct perf_event *event)
1451 {
1452 x86_perf_event_update(event);
1453 }
1454
1455 static const struct pmu pmu = {
1456 .enable = x86_pmu_enable,
1457 .disable = x86_pmu_disable,
1458 .start = x86_pmu_start,
1459 .stop = x86_pmu_stop,
1460 .read = x86_pmu_read,
1461 .unthrottle = x86_pmu_unthrottle,
1462 };
1463
1464 /*
1465 * validate that we can schedule this event
1466 */
1467 static int validate_event(struct perf_event *event)
1468 {
1469 struct cpu_hw_events *fake_cpuc;
1470 struct event_constraint *c;
1471 int ret = 0;
1472
1473 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1474 if (!fake_cpuc)
1475 return -ENOMEM;
1476
1477 c = x86_pmu.get_event_constraints(fake_cpuc, event);
1478
1479 if (!c || !c->weight)
1480 ret = -ENOSPC;
1481
1482 if (x86_pmu.put_event_constraints)
1483 x86_pmu.put_event_constraints(fake_cpuc, event);
1484
1485 kfree(fake_cpuc);
1486
1487 return ret;
1488 }
1489
1490 /*
1491 * validate a single event group
1492 *
1493 * validation include:
1494 * - check events are compatible which each other
1495 * - events do not compete for the same counter
1496 * - number of events <= number of counters
1497 *
1498 * validation ensures the group can be loaded onto the
1499 * PMU if it was the only group available.
1500 */
1501 static int validate_group(struct perf_event *event)
1502 {
1503 struct perf_event *leader = event->group_leader;
1504 struct cpu_hw_events *fake_cpuc;
1505 int ret, n;
1506
1507 ret = -ENOMEM;
1508 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1509 if (!fake_cpuc)
1510 goto out;
1511
1512 /*
1513 * the event is not yet connected with its
1514 * siblings therefore we must first collect
1515 * existing siblings, then add the new event
1516 * before we can simulate the scheduling
1517 */
1518 ret = -ENOSPC;
1519 n = collect_events(fake_cpuc, leader, true);
1520 if (n < 0)
1521 goto out_free;
1522
1523 fake_cpuc->n_events = n;
1524 n = collect_events(fake_cpuc, event, false);
1525 if (n < 0)
1526 goto out_free;
1527
1528 fake_cpuc->n_events = n;
1529
1530 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1531
1532 out_free:
1533 kfree(fake_cpuc);
1534 out:
1535 return ret;
1536 }
1537
1538 const struct pmu *hw_perf_event_init(struct perf_event *event)
1539 {
1540 const struct pmu *tmp;
1541 int err;
1542
1543 err = __hw_perf_event_init(event);
1544 if (!err) {
1545 /*
1546 * we temporarily connect event to its pmu
1547 * such that validate_group() can classify
1548 * it as an x86 event using is_x86_event()
1549 */
1550 tmp = event->pmu;
1551 event->pmu = &pmu;
1552
1553 if (event->group_leader != event)
1554 err = validate_group(event);
1555 else
1556 err = validate_event(event);
1557
1558 event->pmu = tmp;
1559 }
1560 if (err) {
1561 if (event->destroy)
1562 event->destroy(event);
1563 return ERR_PTR(err);
1564 }
1565
1566 return &pmu;
1567 }
1568
1569 /*
1570 * callchain support
1571 */
1572
1573 static inline
1574 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
1575 {
1576 if (entry->nr < PERF_MAX_STACK_DEPTH)
1577 entry->ip[entry->nr++] = ip;
1578 }
1579
1580 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
1581 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
1582
1583
1584 static void
1585 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1586 {
1587 /* Ignore warnings */
1588 }
1589
1590 static void backtrace_warning(void *data, char *msg)
1591 {
1592 /* Ignore warnings */
1593 }
1594
1595 static int backtrace_stack(void *data, char *name)
1596 {
1597 return 0;
1598 }
1599
1600 static void backtrace_address(void *data, unsigned long addr, int reliable)
1601 {
1602 struct perf_callchain_entry *entry = data;
1603
1604 if (reliable)
1605 callchain_store(entry, addr);
1606 }
1607
1608 static const struct stacktrace_ops backtrace_ops = {
1609 .warning = backtrace_warning,
1610 .warning_symbol = backtrace_warning_symbol,
1611 .stack = backtrace_stack,
1612 .address = backtrace_address,
1613 .walk_stack = print_context_stack_bp,
1614 };
1615
1616 #include "../dumpstack.h"
1617
1618 static void
1619 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1620 {
1621 callchain_store(entry, PERF_CONTEXT_KERNEL);
1622 callchain_store(entry, regs->ip);
1623
1624 dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1625 }
1626
1627 static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
1628 {
1629 unsigned long bytes;
1630
1631 bytes = copy_from_user_nmi(frame, fp, sizeof(*frame));
1632
1633 return bytes == sizeof(*frame);
1634 }
1635
1636 static void
1637 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1638 {
1639 struct stack_frame frame;
1640 const void __user *fp;
1641
1642 if (!user_mode(regs))
1643 regs = task_pt_regs(current);
1644
1645 fp = (void __user *)regs->bp;
1646
1647 callchain_store(entry, PERF_CONTEXT_USER);
1648 callchain_store(entry, regs->ip);
1649
1650 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1651 frame.next_frame = NULL;
1652 frame.return_address = 0;
1653
1654 if (!copy_stack_frame(fp, &frame))
1655 break;
1656
1657 if ((unsigned long)fp < regs->sp)
1658 break;
1659
1660 callchain_store(entry, frame.return_address);
1661 fp = frame.next_frame;
1662 }
1663 }
1664
1665 static void
1666 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1667 {
1668 int is_user;
1669
1670 if (!regs)
1671 return;
1672
1673 is_user = user_mode(regs);
1674
1675 if (is_user && current->state != TASK_RUNNING)
1676 return;
1677
1678 if (!is_user)
1679 perf_callchain_kernel(regs, entry);
1680
1681 if (current->mm)
1682 perf_callchain_user(regs, entry);
1683 }
1684
1685 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1686 {
1687 struct perf_callchain_entry *entry;
1688
1689 if (in_nmi())
1690 entry = &__get_cpu_var(pmc_nmi_entry);
1691 else
1692 entry = &__get_cpu_var(pmc_irq_entry);
1693
1694 entry->nr = 0;
1695
1696 perf_do_callchain(regs, entry);
1697
1698 return entry;
1699 }
1700
1701 #ifdef CONFIG_EVENT_TRACING
1702 void perf_arch_fetch_caller_regs(struct pt_regs *regs, unsigned long ip, int skip)
1703 {
1704 regs->ip = ip;
1705 /*
1706 * perf_arch_fetch_caller_regs adds another call, we need to increment
1707 * the skip level
1708 */
1709 regs->bp = rewind_frame_pointer(skip + 1);
1710 regs->cs = __KERNEL_CS;
1711 local_save_flags(regs->flags);
1712 }
1713 #endif
x86 "subsystem" repository