drivers/scsi/sata_sis.c

   1 /*
   2  *  sata_sis.c - Silicon Integrated Systems SATA
   3  *
   4  *  Maintained by:  Uwe Koziolek
   5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6  *                  on emails.
   7  *
   8  *  Copyright 2004 Uwe Koziolek
   9  *
  10  *  The contents of this file are subject to the Open
  11  *  Software License version 1.1 that can be found at
  12  *  http://www.opensource.org/licenses/osl-1.1.txt and is included herein
  13  *  by reference.
  14  *
  15  *  Alternatively, the contents of this file may be used under the terms
  16  *  of the GNU General Public License version 2 (the "GPL") as distributed
  17  *  in the kernel source COPYING file, in which case the provisions of
  18  *  the GPL are applicable instead of the above.  If you wish to allow
  19  *  the use of your version of this file only under the terms of the
  20  *  GPL and not to allow others to use your version of this file under
  21  *  the OSL, indicate your decision by deleting the provisions above and
  22  *  replace them with the notice and other provisions required by the GPL.
  23  *  If you do not delete the provisions above, a recipient may use your
  24  *  version of this file under either the OSL or the GPL.
  25  *
  26  */
  27
  28 #include <linux/config.h>
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/pci.h>
  32 #include <linux/init.h>
  33 #include <linux/blkdev.h>
  34 #include <linux/delay.h>
  35 #include <linux/interrupt.h>
  36 #include "scsi.h"
  37 #include <scsi/scsi_host.h>
  38 #include <linux/libata.h>
  39
  40 #define DRV_NAME        "sata_sis"
  41 #define DRV_VERSION     "0.5"
  42
  43 enum {
  44         sis_180                 = 0,
  45         SIS_SCR_PCI_BAR         = 5,
  46
  47         /* PCI configuration registers */
  48         SIS_GENCTL              = 0x54, /* IDE General Control register */
  49         SIS_SCR_BASE            = 0xc0, /* sata0 phy SCR registers */
  50         SIS_SATA1_OFS           = 0x10, /* offset from sata0->sata1 phy regs */
  51
  52         /* random bits */
  53         SIS_FLAG_CFGSCR         = (1 << 30), /* host flag: SCRs via PCI cfg */
  54
  55         GENCTL_IOMAPPED_SCR     = (1 << 26), /* if set, SCRs are in IO space */
  56 };
  57
  58 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
  59 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg);
  60 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
  61
  62 static struct pci_device_id sis_pci_tbl[] = {
  63         { PCI_VENDOR_ID_SI, 0x180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
  64         { PCI_VENDOR_ID_SI, 0x181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
  65         { }     /* terminate list */
  66 };
  67
  68
  69 static struct pci_driver sis_pci_driver = {
  70         .name                   = DRV_NAME,
  71         .id_table               = sis_pci_tbl,
  72         .probe                  = sis_init_one,
  73         .remove                 = ata_pci_remove_one,
  74 };
  75
  76 static Scsi_Host_Template sis_sht = {
  77         .module                 = THIS_MODULE,
  78         .name                   = DRV_NAME,
  79         .ioctl                  = ata_scsi_ioctl,
  80         .queuecommand           = ata_scsi_queuecmd,
  81         .eh_strategy_handler    = ata_scsi_error,
  82         .can_queue              = ATA_DEF_QUEUE,
  83         .this_id                = ATA_SHT_THIS_ID,
  84         .sg_tablesize           = ATA_MAX_PRD,
  85         .max_sectors            = ATA_MAX_SECTORS,
  86         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
  87         .emulated               = ATA_SHT_EMULATED,
  88         .use_clustering         = ATA_SHT_USE_CLUSTERING,
  89         .proc_name              = DRV_NAME,
  90         .dma_boundary           = ATA_DMA_BOUNDARY,
  91         .slave_configure        = ata_scsi_slave_config,
  92         .bios_param             = ata_std_bios_param,
  93         .ordered_flush          = 1,
  94 };
  95
  96 static struct ata_port_operations sis_ops = {
  97         .port_disable           = ata_port_disable,
  98         .tf_load                = ata_tf_load,
  99         .tf_read                = ata_tf_read,
 100         .check_status           = ata_check_status,
 101         .exec_command           = ata_exec_command,
 102         .dev_select             = ata_std_dev_select,
 103         .phy_reset              = sata_phy_reset,
 104         .bmdma_setup            = ata_bmdma_setup,
 105         .bmdma_start            = ata_bmdma_start,
 106         .bmdma_stop             = ata_bmdma_stop,
 107         .bmdma_status           = ata_bmdma_status,
 108         .qc_prep                = ata_qc_prep,
 109         .qc_issue               = ata_qc_issue_prot,
 110         .eng_timeout            = ata_eng_timeout,
 111         .irq_handler            = ata_interrupt,
 112         .irq_clear              = ata_bmdma_irq_clear,
 113         .scr_read               = sis_scr_read,
 114         .scr_write              = sis_scr_write,
 115         .port_start             = ata_port_start,
 116         .port_stop              = ata_port_stop,
 117 };
 118
 119 static struct ata_port_info sis_port_info = {
 120         .sht            = &sis_sht,
 121         .host_flags     = ATA_FLAG_SATA | ATA_FLAG_SATA_RESET |
 122                           ATA_FLAG_NO_LEGACY,
 123         .pio_mask       = 0x1f,
 124         .mwdma_mask     = 0x7,
 125         .udma_mask      = 0x7f,
 126         .port_ops       = &sis_ops,
 127 };
 128
 129
 130 MODULE_AUTHOR("Uwe Koziolek");
 131 MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
 132 MODULE_LICENSE("GPL");
 133 MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
 134 MODULE_VERSION(DRV_VERSION);
 135
 136 static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg)
 137 {
 138         unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
 139
 140         if (port_no)
 141                 addr += SIS_SATA1_OFS;
 142         return addr;
 143 }
 144
 145 static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
 146 {
 147         struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
 148         unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg);
 149         u32 val;
 150
 151         if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
 152                 return 0xffffffff;
 153         pci_read_config_dword(pdev, cfg_addr, &val);
 154         return val;
 155 }
 156
 157 static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val)
 158 {
 159         struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
 160         unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, scr);
 161
 162         if (scr == SCR_ERROR) /* doesn't exist in PCI cfg space */
 163                 return;
 164         pci_write_config_dword(pdev, cfg_addr, val);
 165 }
 166
 167 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
 168 {
 169         if (sc_reg > SCR_CONTROL)
 170                 return 0xffffffffU;
 171
 172         if (ap->flags & SIS_FLAG_CFGSCR)
 173                 return sis_scr_cfg_read(ap, sc_reg);
 174         return inl(ap->ioaddr.scr_addr + (sc_reg * 4));
 175 }
 176
 177 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
 178 {
 179         if (sc_reg > SCR_CONTROL)
 180                 return;
 181
 182         if (ap->flags & SIS_FLAG_CFGSCR)
 183                 sis_scr_cfg_write(ap, sc_reg, val);
 184         else
 185                 outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
 186 }
 187
 188 /* move to PCI layer, integrate w/ MSI stuff */
 189 static void pci_enable_intx(struct pci_dev *pdev)
 190 {
 191         u16 pci_command;
 192
 193         pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
 194         if (pci_command & PCI_COMMAND_INTX_DISABLE) {
 195                 pci_command &= ~PCI_COMMAND_INTX_DISABLE;
 196                 pci_write_config_word(pdev, PCI_COMMAND, pci_command);
 197         }
 198 }
 199
 200 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
 201 {
 202         struct ata_probe_ent *probe_ent = NULL;
 203         int rc;
 204         u32 genctl;
 205         struct ata_port_info *ppi;
 206         int pci_dev_busy = 0;
 207
 208         rc = pci_enable_device(pdev);
 209         if (rc)
 210                 return rc;
 211
 212         rc = pci_request_regions(pdev, DRV_NAME);
 213         if (rc) {
 214                 pci_dev_busy = 1;
 215                 goto err_out;
 216         }
 217
 218         rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
 219         if (rc)
 220                 goto err_out_regions;
 221         rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
 222         if (rc)
 223                 goto err_out_regions;
 224
 225         ppi = &sis_port_info;
 226         probe_ent = ata_pci_init_native_mode(pdev, &ppi);
 227         if (!probe_ent) {
 228                 rc = -ENOMEM;
 229                 goto err_out_regions;
 230         }
 231
 232         /* check and see if the SCRs are in IO space or PCI cfg space */
 233         pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
 234         if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
 235                 probe_ent->host_flags |= SIS_FLAG_CFGSCR;
 236
 237         /* if hardware thinks SCRs are in IO space, but there are
 238          * no IO resources assigned, change to PCI cfg space.
 239          */
 240         if ((!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) &&
 241             ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
 242              (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
 243                 genctl &= ~GENCTL_IOMAPPED_SCR;
 244                 pci_write_config_dword(pdev, SIS_GENCTL, genctl);
 245                 probe_ent->host_flags |= SIS_FLAG_CFGSCR;
 246         }
 247
 248         if (!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) {
 249                 probe_ent->port[0].scr_addr =
 250                         pci_resource_start(pdev, SIS_SCR_PCI_BAR);
 251                 probe_ent->port[1].scr_addr =
 252                         pci_resource_start(pdev, SIS_SCR_PCI_BAR) + 64;
 253         }
 254
 255         pci_set_master(pdev);
 256         pci_enable_intx(pdev);
 257
 258         /* FIXME: check ata_device_add return value */
 259         ata_device_add(probe_ent);
 260         kfree(probe_ent);
 261
 262         return 0;
 263
 264 err_out_regions:
 265         pci_release_regions(pdev);
 266
 267 err_out:
 268         if (!pci_dev_busy)
 269                 pci_disable_device(pdev);
 270         return rc;
 271
 272 }
 273
 274 static int __init sis_init(void)
 275 {
 276         return pci_module_init(&sis_pci_driver);
 277 }
 278
 279 static void __exit sis_exit(void)
 280 {
 281         pci_unregister_driver(&sis_pci_driver);
 282 }
 283
 284 module_init(sis_init);
 285 module_exit(sis_exit);
 286