drivers/char/rocket.c

   1 /*
   2  * RocketPort device driver for Linux
   3  *
   4  * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
   5  *
   6  * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of the
  11  * License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Kernel Synchronization:
  25  *
  26  * This driver has 2 kernel control paths - exception handlers (calls into the driver
  27  * from user mode) and the timer bottom half (tasklet).  This is a polled driver, interrupts
  28  * are not used.
  29  *
  30  * Critical data:
  31  * -  rp_table[], accessed through passed "info" pointers, is a global (static) array of
  32  *    serial port state information and the xmit_buf circular buffer.  Protected by
  33  *    a per port spinlock.
  34  * -  xmit_flags[], an array of ints indexed by line (port) number, indicating that there
  35  *    is data to be transmitted.  Protected by atomic bit operations.
  36  * -  rp_num_ports, int indicating number of open ports, protected by atomic operations.
  37  *
  38  * rp_write() and rp_write_char() functions use a per port semaphore to protect against
  39  * simultaneous access to the same port by more than one process.
  40  */
  41
  42 /****** Defines ******/
  43 #define ROCKET_PARANOIA_CHECK
  44 #define ROCKET_DISABLE_SIMUSAGE
  45
  46 #undef ROCKET_SOFT_FLOW
  47 #undef ROCKET_DEBUG_OPEN
  48 #undef ROCKET_DEBUG_INTR
  49 #undef ROCKET_DEBUG_WRITE
  50 #undef ROCKET_DEBUG_FLOW
  51 #undef ROCKET_DEBUG_THROTTLE
  52 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
  53 #undef ROCKET_DEBUG_RECEIVE
  54 #undef ROCKET_DEBUG_HANGUP
  55 #undef REV_PCI_ORDER
  56 #undef ROCKET_DEBUG_IO
  57
  58 #define POLL_PERIOD HZ/100      /*  Polling period .01 seconds (10ms) */
  59
  60 /****** Kernel includes ******/
  61
  62 #include <linux/module.h>
  63 #include <linux/errno.h>
  64 #include <linux/major.h>
  65 #include <linux/kernel.h>
  66 #include <linux/signal.h>
  67 #include <linux/slab.h>
  68 #include <linux/mm.h>
  69 #include <linux/sched.h>
  70 #include <linux/timer.h>
  71 #include <linux/interrupt.h>
  72 #include <linux/tty.h>
  73 #include <linux/tty_driver.h>
  74 #include <linux/tty_flip.h>
  75 #include <linux/serial.h>
  76 #include <linux/string.h>
  77 #include <linux/fcntl.h>
  78 #include <linux/ptrace.h>
  79 #include <linux/mutex.h>
  80 #include <linux/ioport.h>
  81 #include <linux/delay.h>
  82 #include <linux/completion.h>
  83 #include <linux/wait.h>
  84 #include <linux/pci.h>
  85 #include <linux/uaccess.h>
  86 #include <asm/atomic.h>
  87 #include <asm/unaligned.h>
  88 #include <linux/bitops.h>
  89 #include <linux/spinlock.h>
  90 #include <linux/init.h>
  91
  92 /****** RocketPort includes ******/
  93
  94 #include "rocket_int.h"
  95 #include "rocket.h"
  96
  97 #define ROCKET_VERSION "2.09"
  98 #define ROCKET_DATE "12-June-2003"
  99
 100 /****** RocketPort Local Variables ******/
 101
 102 static void rp_do_poll(unsigned long dummy);
 103
 104 static struct tty_driver *rocket_driver;
 105
 106 static struct rocket_version driver_version = {
 107         ROCKET_VERSION, ROCKET_DATE
 108 };
 109
 110 static struct r_port *rp_table[MAX_RP_PORTS];          /*  The main repository of serial port state information. */
 111 static unsigned int xmit_flags[NUM_BOARDS];            /*  Bit significant, indicates port had data to transmit. */
 112                                                        /*  eg.  Bit 0 indicates port 0 has xmit data, ...        */
 113 static atomic_t rp_num_ports_open;                     /*  Number of serial ports open                           */
 114 static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
 115
 116 static unsigned long board1;                           /* ISA addresses, retrieved from rocketport.conf          */
 117 static unsigned long board2;
 118 static unsigned long board3;
 119 static unsigned long board4;
 120 static unsigned long controller;
 121 static int support_low_speed;
 122 static unsigned long modem1;
 123 static unsigned long modem2;
 124 static unsigned long modem3;
 125 static unsigned long modem4;
 126 static unsigned long pc104_1[8];
 127 static unsigned long pc104_2[8];
 128 static unsigned long pc104_3[8];
 129 static unsigned long pc104_4[8];
 130 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
 131
 132 static int rp_baud_base[NUM_BOARDS];                   /*  Board config info (Someday make a per-board structure)  */
 133 static unsigned long rcktpt_io_addr[NUM_BOARDS];
 134 static int rcktpt_type[NUM_BOARDS];
 135 static int is_PCI[NUM_BOARDS];
 136 static rocketModel_t rocketModel[NUM_BOARDS];
 137 static int max_board;
 138 static const struct tty_port_operations rocket_port_ops;
 139
 140 /*
 141  * The following arrays define the interrupt bits corresponding to each AIOP.
 142  * These bits are different between the ISA and regular PCI boards and the
 143  * Universal PCI boards.
 144  */
 145
 146 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
 147         AIOP_INTR_BIT_0,
 148         AIOP_INTR_BIT_1,
 149         AIOP_INTR_BIT_2,
 150         AIOP_INTR_BIT_3
 151 };
 152
 153 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
 154         UPCI_AIOP_INTR_BIT_0,
 155         UPCI_AIOP_INTR_BIT_1,
 156         UPCI_AIOP_INTR_BIT_2,
 157         UPCI_AIOP_INTR_BIT_3
 158 };
 159
 160 static Byte_t RData[RDATASIZE] = {
 161         0x00, 0x09, 0xf6, 0x82,
 162         0x02, 0x09, 0x86, 0xfb,
 163         0x04, 0x09, 0x00, 0x0a,
 164         0x06, 0x09, 0x01, 0x0a,
 165         0x08, 0x09, 0x8a, 0x13,
 166         0x0a, 0x09, 0xc5, 0x11,
 167         0x0c, 0x09, 0x86, 0x85,
 168         0x0e, 0x09, 0x20, 0x0a,
 169         0x10, 0x09, 0x21, 0x0a,
 170         0x12, 0x09, 0x41, 0xff,
 171         0x14, 0x09, 0x82, 0x00,
 172         0x16, 0x09, 0x82, 0x7b,
 173         0x18, 0x09, 0x8a, 0x7d,
 174         0x1a, 0x09, 0x88, 0x81,
 175         0x1c, 0x09, 0x86, 0x7a,
 176         0x1e, 0x09, 0x84, 0x81,
 177         0x20, 0x09, 0x82, 0x7c,
 178         0x22, 0x09, 0x0a, 0x0a
 179 };
 180
 181 static Byte_t RRegData[RREGDATASIZE] = {
 182         0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
 183         0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
 184         0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
 185         0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
 186         0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
 187         0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
 188         0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
 189         0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
 190         0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
 191         0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
 192         0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
 193         0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
 194         0x22, 0x09, 0x0a, 0x0a  /* 30: Rx FIFO Enable */
 195 };
 196
 197 static CONTROLLER_T sController[CTL_SIZE] = {
 198         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 199          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
 200         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 201          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
 202         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 203          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
 204         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 205          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
 206 };
 207
 208 static Byte_t sBitMapClrTbl[8] = {
 209         0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
 210 };
 211
 212 static Byte_t sBitMapSetTbl[8] = {
 213         0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
 214 };
 215
 216 static int sClockPrescale = 0x14;
 217
 218 /*
 219  *  Line number is the ttySIx number (x), the Minor number.  We
 220  *  assign them sequentially, starting at zero.  The following
 221  *  array keeps track of the line number assigned to a given board/aiop/channel.
 222  */
 223 static unsigned char lineNumbers[MAX_RP_PORTS];
 224 static unsigned long nextLineNumber;
 225
 226 /*****  RocketPort Static Prototypes   *********/
 227 static int __init init_ISA(int i);
 228 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
 229 static void rp_flush_buffer(struct tty_struct *tty);
 230 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
 231 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
 232 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
 233 static void rp_start(struct tty_struct *tty);
 234 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
 235                      int ChanNum);
 236 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
 237 static void sFlushRxFIFO(CHANNEL_T * ChP);
 238 static void sFlushTxFIFO(CHANNEL_T * ChP);
 239 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
 240 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
 241 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
 242 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
 243 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
 244 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
 245                               ByteIO_t * AiopIOList, int AiopIOListSize,
 246                               WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
 247                               int PeriodicOnly, int altChanRingIndicator,
 248                               int UPCIRingInd);
 249 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
 250                            ByteIO_t * AiopIOList, int AiopIOListSize,
 251                            int IRQNum, Byte_t Frequency, int PeriodicOnly);
 252 static int sReadAiopID(ByteIO_t io);
 253 static int sReadAiopNumChan(WordIO_t io);
 254
 255 MODULE_AUTHOR("Theodore Ts'o");
 256 MODULE_DESCRIPTION("Comtrol RocketPort driver");
 257 module_param(board1, ulong, 0);
 258 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
 259 module_param(board2, ulong, 0);
 260 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
 261 module_param(board3, ulong, 0);
 262 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
 263 module_param(board4, ulong, 0);
 264 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
 265 module_param(controller, ulong, 0);
 266 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
 267 module_param(support_low_speed, bool, 0);
 268 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
 269 module_param(modem1, ulong, 0);
 270 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
 271 module_param(modem2, ulong, 0);
 272 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
 273 module_param(modem3, ulong, 0);
 274 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
 275 module_param(modem4, ulong, 0);
 276 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
 277 module_param_array(pc104_1, ulong, NULL, 0);
 278 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
 279 module_param_array(pc104_2, ulong, NULL, 0);
 280 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
 281 module_param_array(pc104_3, ulong, NULL, 0);
 282 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
 283 module_param_array(pc104_4, ulong, NULL, 0);
 284 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
 285
 286 static int rp_init(void);
 287 static void rp_cleanup_module(void);
 288
 289 module_init(rp_init);
 290 module_exit(rp_cleanup_module);
 291
 292
 293 MODULE_LICENSE("Dual BSD/GPL");
 294
 295 /*************************************************************************/
 296 /*                     Module code starts here                           */
 297
 298 static inline int rocket_paranoia_check(struct r_port *info,
 299                                         const char *routine)
 300 {
 301 #ifdef ROCKET_PARANOIA_CHECK
 302         if (!info)
 303                 return 1;
 304         if (info->magic != RPORT_MAGIC) {
 305                 printk(KERN_WARNING "Warning: bad magic number for rocketport "
 306                                 "struct in %s\n", routine);
 307                 return 1;
 308         }
 309 #endif
 310         return 0;
 311 }
 312
 313
 314 /*  Serial port receive data function.  Called (from timer poll) when an AIOPIC signals
 315  *  that receive data is present on a serial port.  Pulls data from FIFO, moves it into the
 316  *  tty layer.
 317  */
 318 static void rp_do_receive(struct r_port *info,
 319                           struct tty_struct *tty,
 320                           CHANNEL_t * cp, unsigned int ChanStatus)
 321 {
 322         unsigned int CharNStat;
 323         int ToRecv, wRecv, space;
 324         unsigned char *cbuf;
 325
 326         ToRecv = sGetRxCnt(cp);
 327 #ifdef ROCKET_DEBUG_INTR
 328         printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
 329 #endif
 330         if (ToRecv == 0)
 331                 return;
 332
 333         /*
 334          * if status indicates there are errored characters in the
 335          * FIFO, then enter status mode (a word in FIFO holds
 336          * character and status).
 337          */
 338         if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
 339                 if (!(ChanStatus & STATMODE)) {
 340 #ifdef ROCKET_DEBUG_RECEIVE
 341                         printk(KERN_INFO "Entering STATMODE...\n");
 342 #endif
 343                         ChanStatus |= STATMODE;
 344                         sEnRxStatusMode(cp);
 345                 }
 346         }
 347
 348         /*
 349          * if we previously entered status mode, then read down the
 350          * FIFO one word at a time, pulling apart the character and
 351          * the status.  Update error counters depending on status
 352          */
 353         if (ChanStatus & STATMODE) {
 354 #ifdef ROCKET_DEBUG_RECEIVE
 355                 printk(KERN_INFO "Ignore %x, read %x...\n",
 356                         info->ignore_status_mask, info->read_status_mask);
 357 #endif
 358                 while (ToRecv) {
 359                         char flag;
 360
 361                         CharNStat = sInW(sGetTxRxDataIO(cp));
 362 #ifdef ROCKET_DEBUG_RECEIVE
 363                         printk(KERN_INFO "%x...\n", CharNStat);
 364 #endif
 365                         if (CharNStat & STMBREAKH)
 366                                 CharNStat &= ~(STMFRAMEH | STMPARITYH);
 367                         if (CharNStat & info->ignore_status_mask) {
 368                                 ToRecv--;
 369                                 continue;
 370                         }
 371                         CharNStat &= info->read_status_mask;
 372                         if (CharNStat & STMBREAKH)
 373                                 flag = TTY_BREAK;
 374                         else if (CharNStat & STMPARITYH)
 375                                 flag = TTY_PARITY;
 376                         else if (CharNStat & STMFRAMEH)
 377                                 flag = TTY_FRAME;
 378                         else if (CharNStat & STMRCVROVRH)
 379                                 flag = TTY_OVERRUN;
 380                         else
 381                                 flag = TTY_NORMAL;
 382                         tty_insert_flip_char(tty, CharNStat & 0xff, flag);
 383                         ToRecv--;
 384                 }
 385
 386                 /*
 387                  * after we've emptied the FIFO in status mode, turn
 388                  * status mode back off
 389                  */
 390                 if (sGetRxCnt(cp) == 0) {
 391 #ifdef ROCKET_DEBUG_RECEIVE
 392                         printk(KERN_INFO "Status mode off.\n");
 393 #endif
 394                         sDisRxStatusMode(cp);
 395                 }
 396         } else {
 397                 /*
 398                  * we aren't in status mode, so read down the FIFO two
 399                  * characters at time by doing repeated word IO
 400                  * transfer.
 401                  */
 402                 space = tty_prepare_flip_string(tty, &cbuf, ToRecv);
 403                 if (space < ToRecv) {
 404 #ifdef ROCKET_DEBUG_RECEIVE
 405                         printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
 406 #endif
 407                         if (space <= 0)
 408                                 return;
 409                         ToRecv = space;
 410                 }
 411                 wRecv = ToRecv >> 1;
 412                 if (wRecv)
 413                         sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
 414                 if (ToRecv & 1)
 415                         cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
 416         }
 417         /*  Push the data up to the tty layer */
 418         tty_flip_buffer_push(tty);
 419 }
 420
 421 /*
 422  *  Serial port transmit data function.  Called from the timer polling loop as a
 423  *  result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
 424  *  to be sent out the serial port.  Data is buffered in rp_table[line].xmit_buf, it is
 425  *  moved to the port's xmit FIFO.  *info is critical data, protected by spinlocks.
 426  */
 427 static void rp_do_transmit(struct r_port *info)
 428 {
 429         int c;
 430         CHANNEL_t *cp = &info->channel;
 431         struct tty_struct *tty;
 432         unsigned long flags;
 433
 434 #ifdef ROCKET_DEBUG_INTR
 435         printk(KERN_DEBUG "%s\n", __func__);
 436 #endif
 437         if (!info)
 438                 return;
 439         tty = tty_port_tty_get(&info->port);
 440
 441         if (tty == NULL) {
 442                 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
 443                 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
 444                 return;
 445         }
 446
 447         spin_lock_irqsave(&info->slock, flags);
 448         info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
 449
 450         /*  Loop sending data to FIFO until done or FIFO full */
 451         while (1) {
 452                 if (tty->stopped || tty->hw_stopped)
 453                         break;
 454                 c = min(info->xmit_fifo_room, info->xmit_cnt);
 455                 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
 456                 if (c <= 0 || info->xmit_fifo_room <= 0)
 457                         break;
 458                 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
 459                 if (c & 1)
 460                         sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
 461                 info->xmit_tail += c;
 462                 info->xmit_tail &= XMIT_BUF_SIZE - 1;
 463                 info->xmit_cnt -= c;
 464                 info->xmit_fifo_room -= c;
 465 #ifdef ROCKET_DEBUG_INTR
 466                 printk(KERN_INFO "tx %d chars...\n", c);
 467 #endif
 468         }
 469
 470         if (info->xmit_cnt == 0)
 471                 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
 472
 473         if (info->xmit_cnt < WAKEUP_CHARS) {
 474                 tty_wakeup(tty);
 475 #ifdef ROCKETPORT_HAVE_POLL_WAIT
 476                 wake_up_interruptible(&tty->poll_wait);
 477 #endif
 478         }
 479
 480         spin_unlock_irqrestore(&info->slock, flags);
 481         tty_kref_put(tty);
 482
 483 #ifdef ROCKET_DEBUG_INTR
 484         printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
 485                info->xmit_tail, info->xmit_fifo_room);
 486 #endif
 487 }
 488
 489 /*
 490  *  Called when a serial port signals it has read data in it's RX FIFO.
 491  *  It checks what interrupts are pending and services them, including
 492  *  receiving serial data.
 493  */
 494 static void rp_handle_port(struct r_port *info)
 495 {
 496         CHANNEL_t *cp;
 497         struct tty_struct *tty;
 498         unsigned int IntMask, ChanStatus;
 499
 500         if (!info)
 501                 return;
 502
 503         if ((info->port.flags & ASYNC_INITIALIZED) == 0) {
 504                 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
 505                                 "info->flags & NOT_INIT\n");
 506                 return;
 507         }
 508         tty = tty_port_tty_get(&info->port);
 509         if (!tty) {
 510                 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
 511                                 "tty==NULL\n");
 512                 return;
 513         }
 514         cp = &info->channel;
 515
 516         IntMask = sGetChanIntID(cp) & info->intmask;
 517 #ifdef ROCKET_DEBUG_INTR
 518         printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
 519 #endif
 520         ChanStatus = sGetChanStatus(cp);
 521         if (IntMask & RXF_TRIG) {       /* Rx FIFO trigger level */
 522                 rp_do_receive(info, tty, cp, ChanStatus);
 523         }
 524         if (IntMask & DELTA_CD) {       /* CD change  */
 525 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
 526                 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
 527                        (ChanStatus & CD_ACT) ? "on" : "off");
 528 #endif
 529                 if (!(ChanStatus & CD_ACT) && info->cd_status) {
 530 #ifdef ROCKET_DEBUG_HANGUP
 531                         printk(KERN_INFO "CD drop, calling hangup.\n");
 532 #endif
 533                         tty_hangup(tty);
 534                 }
 535                 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
 536                 wake_up_interruptible(&info->port.open_wait);
 537         }
 538 #ifdef ROCKET_DEBUG_INTR
 539         if (IntMask & DELTA_CTS) {      /* CTS change */
 540                 printk(KERN_INFO "CTS change...\n");
 541         }
 542         if (IntMask & DELTA_DSR) {      /* DSR change */
 543                 printk(KERN_INFO "DSR change...\n");
 544         }
 545 #endif
 546         tty_kref_put(tty);
 547 }
 548
 549 /*
 550  *  The top level polling routine.  Repeats every 1/100 HZ (10ms).
 551  */
 552 static void rp_do_poll(unsigned long dummy)
 553 {
 554         CONTROLLER_t *ctlp;
 555         int ctrl, aiop, ch, line;
 556         unsigned int xmitmask, i;
 557         unsigned int CtlMask;
 558         unsigned char AiopMask;
 559         Word_t bit;
 560
 561         /*  Walk through all the boards (ctrl's) */
 562         for (ctrl = 0; ctrl < max_board; ctrl++) {
 563                 if (rcktpt_io_addr[ctrl] <= 0)
 564                         continue;
 565
 566                 /*  Get a ptr to the board's control struct */
 567                 ctlp = sCtlNumToCtlPtr(ctrl);
 568
 569                 /*  Get the interrupt status from the board */
 570 #ifdef CONFIG_PCI
 571                 if (ctlp->BusType == isPCI)
 572                         CtlMask = sPCIGetControllerIntStatus(ctlp);
 573                 else
 574 #endif
 575                         CtlMask = sGetControllerIntStatus(ctlp);
 576
 577                 /*  Check if any AIOP read bits are set */
 578                 for (aiop = 0; CtlMask; aiop++) {
 579                         bit = ctlp->AiopIntrBits[aiop];
 580                         if (CtlMask & bit) {
 581                                 CtlMask &= ~bit;
 582                                 AiopMask = sGetAiopIntStatus(ctlp, aiop);
 583
 584                                 /*  Check if any port read bits are set */
 585                                 for (ch = 0; AiopMask;  AiopMask >>= 1, ch++) {
 586                                         if (AiopMask & 1) {
 587
 588                                                 /*  Get the line number (/dev/ttyRx number). */
 589                                                 /*  Read the data from the port. */
 590                                                 line = GetLineNumber(ctrl, aiop, ch);
 591                                                 rp_handle_port(rp_table[line]);
 592                                         }
 593                                 }
 594                         }
 595                 }
 596
 597                 xmitmask = xmit_flags[ctrl];
 598
 599                 /*
 600                  *  xmit_flags contains bit-significant flags, indicating there is data
 601                  *  to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
 602                  *  1, ... (32 total possible).  The variable i has the aiop and ch
 603                  *  numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
 604                  */
 605                 if (xmitmask) {
 606                         for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
 607                                 if (xmitmask & (1 << i)) {
 608                                         aiop = (i & 0x18) >> 3;
 609                                         ch = i & 0x07;
 610                                         line = GetLineNumber(ctrl, aiop, ch);
 611                                         rp_do_transmit(rp_table[line]);
 612                                 }
 613                         }
 614                 }
 615         }
 616
 617         /*
 618          * Reset the timer so we get called at the next clock tick (10ms).
 619          */
 620         if (atomic_read(&rp_num_ports_open))
 621                 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
 622 }
 623
 624 /*
 625  *  Initializes the r_port structure for a port, as well as enabling the port on
 626  *  the board.
 627  *  Inputs:  board, aiop, chan numbers
 628  */
 629 static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
 630 {
 631         unsigned rocketMode;
 632         struct r_port *info;
 633         int line;
 634         CONTROLLER_T *ctlp;
 635
 636         /*  Get the next available line number */
 637         line = SetLineNumber(board, aiop, chan);
 638
 639         ctlp = sCtlNumToCtlPtr(board);
 640
 641         /*  Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
 642         info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
 643         if (!info) {
 644                 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
 645                                 line);
 646                 return;
 647         }
 648
 649         info->magic = RPORT_MAGIC;
 650         info->line = line;
 651         info->ctlp = ctlp;
 652         info->board = board;
 653         info->aiop = aiop;
 654         info->chan = chan;
 655         tty_port_init(&info->port);
 656         info->port.ops = &rocket_port_ops;
 657         init_completion(&info->close_wait);
 658         info->flags &= ~ROCKET_MODE_MASK;
 659         switch (pc104[board][line]) {
 660         case 422:
 661                 info->flags |= ROCKET_MODE_RS422;
 662                 break;
 663         case 485:
 664                 info->flags |= ROCKET_MODE_RS485;
 665                 break;
 666         case 232:
 667         default:
 668                 info->flags |= ROCKET_MODE_RS232;
 669                 break;
 670         }
 671
 672         info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
 673         if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
 674                 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
 675                                 board, aiop, chan);
 676                 kfree(info);
 677                 return;
 678         }
 679
 680         rocketMode = info->flags & ROCKET_MODE_MASK;
 681
 682         if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
 683                 sEnRTSToggle(&info->channel);
 684         else
 685                 sDisRTSToggle(&info->channel);
 686
 687         if (ctlp->boardType == ROCKET_TYPE_PC104) {
 688                 switch (rocketMode) {
 689                 case ROCKET_MODE_RS485:
 690                         sSetInterfaceMode(&info->channel, InterfaceModeRS485);
 691                         break;
 692                 case ROCKET_MODE_RS422:
 693                         sSetInterfaceMode(&info->channel, InterfaceModeRS422);
 694                         break;
 695                 case ROCKET_MODE_RS232:
 696                 default:
 697                         if (info->flags & ROCKET_RTS_TOGGLE)
 698                                 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
 699                         else
 700                                 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
 701                         break;
 702                 }
 703         }
 704         spin_lock_init(&info->slock);
 705         mutex_init(&info->write_mtx);
 706         rp_table[line] = info;
 707         tty_register_device(rocket_driver, line, pci_dev ? &pci_dev->dev :
 708                         NULL);
 709 }
 710
 711 /*
 712  *  Configures a rocketport port according to its termio settings.  Called from
 713  *  user mode into the driver (exception handler).  *info CD manipulation is spinlock protected.
 714  */
 715 static void configure_r_port(struct tty_struct *tty, struct r_port *info,
 716                              struct ktermios *old_termios)
 717 {
 718         unsigned cflag;
 719         unsigned long flags;
 720         unsigned rocketMode;
 721         int bits, baud, divisor;
 722         CHANNEL_t *cp;
 723         struct ktermios *t = tty->termios;
 724
 725         cp = &info->channel;
 726         cflag = t->c_cflag;
 727
 728         /* Byte size and parity */
 729         if ((cflag & CSIZE) == CS8) {
 730                 sSetData8(cp);
 731                 bits = 10;
 732         } else {
 733                 sSetData7(cp);
 734                 bits = 9;
 735         }
 736         if (cflag & CSTOPB) {
 737                 sSetStop2(cp);
 738                 bits++;
 739         } else {
 740                 sSetStop1(cp);
 741         }
 742
 743         if (cflag & PARENB) {
 744                 sEnParity(cp);
 745                 bits++;
 746                 if (cflag & PARODD) {
 747                         sSetOddParity(cp);
 748                 } else {
 749                         sSetEvenParity(cp);
 750                 }
 751         } else {
 752                 sDisParity(cp);
 753         }
 754
 755         /* baud rate */
 756         baud = tty_get_baud_rate(tty);
 757         if (!baud)
 758                 baud = 9600;
 759         divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
 760         if ((divisor >= 8192 || divisor < 0) && old_termios) {
 761                 baud = tty_termios_baud_rate(old_termios);
 762                 if (!baud)
 763                         baud = 9600;
 764                 divisor = (rp_baud_base[info->board] / baud) - 1;
 765         }
 766         if (divisor >= 8192 || divisor < 0) {
 767                 baud = 9600;
 768                 divisor = (rp_baud_base[info->board] / baud) - 1;
 769         }
 770         info->cps = baud / bits;
 771         sSetBaud(cp, divisor);
 772
 773         /* FIXME: Should really back compute a baud rate from the divisor */
 774         tty_encode_baud_rate(tty, baud, baud);
 775
 776         if (cflag & CRTSCTS) {
 777                 info->intmask |= DELTA_CTS;
 778                 sEnCTSFlowCtl(cp);
 779         } else {
 780                 info->intmask &= ~DELTA_CTS;
 781                 sDisCTSFlowCtl(cp);
 782         }
 783         if (cflag & CLOCAL) {
 784                 info->intmask &= ~DELTA_CD;
 785         } else {
 786                 spin_lock_irqsave(&info->slock, flags);
 787                 if (sGetChanStatus(cp) & CD_ACT)
 788                         info->cd_status = 1;
 789                 else
 790                         info->cd_status = 0;
 791                 info->intmask |= DELTA_CD;
 792                 spin_unlock_irqrestore(&info->slock, flags);
 793         }
 794
 795         /*
 796          * Handle software flow control in the board
 797          */
 798 #ifdef ROCKET_SOFT_FLOW
 799         if (I_IXON(tty)) {
 800                 sEnTxSoftFlowCtl(cp);
 801                 if (I_IXANY(tty)) {
 802                         sEnIXANY(cp);
 803                 } else {
 804                         sDisIXANY(cp);
 805                 }
 806                 sSetTxXONChar(cp, START_CHAR(tty));
 807                 sSetTxXOFFChar(cp, STOP_CHAR(tty));
 808         } else {
 809                 sDisTxSoftFlowCtl(cp);
 810                 sDisIXANY(cp);
 811                 sClrTxXOFF(cp);
 812         }
 813 #endif
 814
 815         /*
 816          * Set up ignore/read mask words
 817          */
 818         info->read_status_mask = STMRCVROVRH | 0xFF;
 819         if (I_INPCK(tty))
 820                 info->read_status_mask |= STMFRAMEH | STMPARITYH;
 821         if (I_BRKINT(tty) || I_PARMRK(tty))
 822                 info->read_status_mask |= STMBREAKH;
 823
 824         /*
 825          * Characters to ignore
 826          */
 827         info->ignore_status_mask = 0;
 828         if (I_IGNPAR(tty))
 829                 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
 830         if (I_IGNBRK(tty)) {
 831                 info->ignore_status_mask |= STMBREAKH;
 832                 /*
 833                  * If we're ignoring parity and break indicators,
 834                  * ignore overruns too.  (For real raw support).
 835                  */
 836                 if (I_IGNPAR(tty))
 837                         info->ignore_status_mask |= STMRCVROVRH;
 838         }
 839
 840         rocketMode = info->flags & ROCKET_MODE_MASK;
 841
 842         if ((info->flags & ROCKET_RTS_TOGGLE)
 843             || (rocketMode == ROCKET_MODE_RS485))
 844                 sEnRTSToggle(cp);
 845         else
 846                 sDisRTSToggle(cp);
 847
 848         sSetRTS(&info->channel);
 849
 850         if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
 851                 switch (rocketMode) {
 852                 case ROCKET_MODE_RS485:
 853                         sSetInterfaceMode(cp, InterfaceModeRS485);
 854                         break;
 855                 case ROCKET_MODE_RS422:
 856                         sSetInterfaceMode(cp, InterfaceModeRS422);
 857                         break;
 858                 case ROCKET_MODE_RS232:
 859                 default:
 860                         if (info->flags & ROCKET_RTS_TOGGLE)
 861                                 sSetInterfaceMode(cp, InterfaceModeRS232T);
 862                         else
 863                                 sSetInterfaceMode(cp, InterfaceModeRS232);
 864                         break;
 865                 }
 866         }
 867 }
 868
 869 static int carrier_raised(struct tty_port *port)
 870 {
 871         struct r_port *info = container_of(port, struct r_port, port);
 872         return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
 873 }
 874
 875 static void dtr_rts(struct tty_port *port, int on)
 876 {
 877         struct r_port *info = container_of(port, struct r_port, port);
 878         if (on) {
 879                 sSetDTR(&info->channel);
 880                 sSetRTS(&info->channel);
 881         } else {
 882                 sClrDTR(&info->channel);
 883                 sClrRTS(&info->channel);
 884         }
 885 }
 886
 887 /*
 888  *  Exception handler that opens a serial port.  Creates xmit_buf storage, fills in
 889  *  port's r_port struct.  Initializes the port hardware.
 890  */
 891 static int rp_open(struct tty_struct *tty, struct file *filp)
 892 {
 893         struct r_port *info;
 894         struct tty_port *port;
 895         int line = 0, retval;
 896         CHANNEL_t *cp;
 897         unsigned long page;
 898
 899         line = tty->index;
 900         if (line < 0 || line >= MAX_RP_PORTS || ((info = rp_table[line]) == NULL))
 901                 return -ENXIO;
 902         port = &info->port;
 903
 904         page = __get_free_page(GFP_KERNEL);
 905         if (!page)
 906                 return -ENOMEM;
 907
 908         if (port->flags & ASYNC_CLOSING) {
 909                 retval = wait_for_completion_interruptible(&info->close_wait);
 910                 free_page(page);
 911                 if (retval)
 912                         return retval;
 913                 return ((port->flags & ASYNC_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
 914         }
 915
 916         /*
 917          * We must not sleep from here until the port is marked fully in use.
 918          */
 919         if (info->xmit_buf)
 920                 free_page(page);
 921         else
 922                 info->xmit_buf = (unsigned char *) page;
 923
 924         tty->driver_data = info;
 925         tty_port_tty_set(port, tty);
 926
 927         if (port->count++ == 0) {
 928                 atomic_inc(&rp_num_ports_open);
 929
 930 #ifdef ROCKET_DEBUG_OPEN
 931                 printk(KERN_INFO "rocket mod++ = %d...\n",
 932                                 atomic_read(&rp_num_ports_open));
 933 #endif
 934         }
 935 #ifdef ROCKET_DEBUG_OPEN
 936         printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
 937 #endif
 938
 939         /*
 940          * Info->count is now 1; so it's safe to sleep now.
 941          */
 942         if (!test_bit(ASYNCB_INITIALIZED, &port->flags)) {
 943                 cp = &info->channel;
 944                 sSetRxTrigger(cp, TRIG_1);
 945                 if (sGetChanStatus(cp) & CD_ACT)
 946                         info->cd_status = 1;
 947                 else
 948                         info->cd_status = 0;
 949                 sDisRxStatusMode(cp);
 950                 sFlushRxFIFO(cp);
 951                 sFlushTxFIFO(cp);
 952
 953                 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
 954                 sSetRxTrigger(cp, TRIG_1);
 955
 956                 sGetChanStatus(cp);
 957                 sDisRxStatusMode(cp);
 958                 sClrTxXOFF(cp);
 959
 960                 sDisCTSFlowCtl(cp);
 961                 sDisTxSoftFlowCtl(cp);
 962
 963                 sEnRxFIFO(cp);
 964                 sEnTransmit(cp);
 965
 966                 set_bit(ASYNCB_INITIALIZED, &info->port.flags);
 967
 968                 /*
 969                  * Set up the tty->alt_speed kludge
 970                  */
 971                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
 972                         tty->alt_speed = 57600;
 973                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
 974                         tty->alt_speed = 115200;
 975                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
 976                         tty->alt_speed = 230400;
 977                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
 978                         tty->alt_speed = 460800;
 979
 980                 configure_r_port(tty, info, NULL);
 981                 if (tty->termios->c_cflag & CBAUD) {
 982                         sSetDTR(cp);
 983                         sSetRTS(cp);
 984                 }
 985         }
 986         /*  Starts (or resets) the maint polling loop */
 987         mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
 988
 989         retval = tty_port_block_til_ready(port, tty, filp);
 990         if (retval) {
 991 #ifdef ROCKET_DEBUG_OPEN
 992                 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
 993 #endif
 994                 return retval;
 995         }
 996         return 0;
 997 }
 998
 999 /*
1000  *  Exception handler that closes a serial port. info->port.count is considered critical.
1001  */
1002 static void rp_close(struct tty_struct *tty, struct file *filp)
1003 {
1004         struct r_port *info = tty->driver_data;
1005         struct tty_port *port = &info->port;
1006         int timeout;
1007         CHANNEL_t *cp;
1008
1009         if (rocket_paranoia_check(info, "rp_close"))
1010                 return;
1011
1012 #ifdef ROCKET_DEBUG_OPEN
1013         printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
1014 #endif
1015
1016         if (tty_port_close_start(port, tty, filp) == 0)
1017                 return;
1018
1019         mutex_lock(&port->mutex);
1020         cp = &info->channel;
1021         /*
1022          * Before we drop DTR, make sure the UART transmitter
1023          * has completely drained; this is especially
1024          * important if there is a transmit FIFO!
1025          */
1026         timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1027         if (timeout == 0)
1028                 timeout = 1;
1029         rp_wait_until_sent(tty, timeout);
1030         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1031
1032         sDisTransmit(cp);
1033         sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1034         sDisCTSFlowCtl(cp);
1035         sDisTxSoftFlowCtl(cp);
1036         sClrTxXOFF(cp);
1037         sFlushRxFIFO(cp);
1038         sFlushTxFIFO(cp);
1039         sClrRTS(cp);
1040         if (C_HUPCL(tty))
1041                 sClrDTR(cp);
1042
1043         rp_flush_buffer(tty);
1044
1045         tty_ldisc_flush(tty);
1046
1047         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1048
1049         /* We can't yet use tty_port_close_end as the buffer handling in this
1050            driver is a bit different to the usual */
1051
1052         if (port->blocked_open) {
1053                 if (port->close_delay) {
1054                         msleep_interruptible(jiffies_to_msecs(port->close_delay));
1055                 }
1056                 wake_up_interruptible(&port->open_wait);
1057         } else {
1058                 if (info->xmit_buf) {
1059                         free_page((unsigned long) info->xmit_buf);
1060                         info->xmit_buf = NULL;
1061                 }
1062         }
1063         spin_lock_irq(&port->lock);
1064         info->port.flags &= ~(ASYNC_INITIALIZED | ASYNC_CLOSING | ASYNC_NORMAL_ACTIVE);
1065         tty->closing = 0;
1066         spin_unlock_irq(&port->lock);
1067         mutex_unlock(&port->mutex);
1068         tty_port_tty_set(port, NULL);
1069
1070         wake_up_interruptible(&port->close_wait);
1071         complete_all(&info->close_wait);
1072         atomic_dec(&rp_num_ports_open);
1073
1074 #ifdef ROCKET_DEBUG_OPEN
1075         printk(KERN_INFO "rocket mod-- = %d...\n",
1076                         atomic_read(&rp_num_ports_open));
1077         printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1078 #endif
1079
1080 }
1081
1082 static void rp_set_termios(struct tty_struct *tty,
1083                            struct ktermios *old_termios)
1084 {
1085         struct r_port *info = tty->driver_data;
1086         CHANNEL_t *cp;
1087         unsigned cflag;
1088
1089         if (rocket_paranoia_check(info, "rp_set_termios"))
1090                 return;
1091
1092         cflag = tty->termios->c_cflag;
1093
1094         /*
1095          * This driver doesn't support CS5 or CS6
1096          */
1097         if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1098                 tty->termios->c_cflag =
1099                     ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1100         /* Or CMSPAR */
1101         tty->termios->c_cflag &= ~CMSPAR;
1102
1103         configure_r_port(tty, info, old_termios);
1104
1105         cp = &info->channel;
1106
1107         /* Handle transition to B0 status */
1108         if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) {
1109                 sClrDTR(cp);
1110                 sClrRTS(cp);
1111         }
1112
1113         /* Handle transition away from B0 status */
1114         if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) {
1115                 if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS))
1116                         sSetRTS(cp);
1117                 sSetDTR(cp);
1118         }
1119
1120         if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) {
1121                 tty->hw_stopped = 0;
1122                 rp_start(tty);
1123         }
1124 }
1125
1126 static int rp_break(struct tty_struct *tty, int break_state)
1127 {
1128         struct r_port *info = tty->driver_data;
1129         unsigned long flags;
1130
1131         if (rocket_paranoia_check(info, "rp_break"))
1132                 return -EINVAL;
1133
1134         spin_lock_irqsave(&info->slock, flags);
1135         if (break_state == -1)
1136                 sSendBreak(&info->channel);
1137         else
1138                 sClrBreak(&info->channel);
1139         spin_unlock_irqrestore(&info->slock, flags);
1140         return 0;
1141 }
1142
1143 /*
1144  * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1145  * the UPCI boards was added, it was decided to make this a function because
1146  * the macro was getting too complicated. All cases except the first one
1147  * (UPCIRingInd) are taken directly from the original macro.
1148  */
1149 static int sGetChanRI(CHANNEL_T * ChP)
1150 {
1151         CONTROLLER_t *CtlP = ChP->CtlP;
1152         int ChanNum = ChP->ChanNum;
1153         int RingInd = 0;
1154
1155         if (CtlP->UPCIRingInd)
1156                 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1157         else if (CtlP->AltChanRingIndicator)
1158                 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1159         else if (CtlP->boardType == ROCKET_TYPE_PC104)
1160                 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1161
1162         return RingInd;
1163 }
1164
1165 /********************************************************************************************/
1166 /*  Here are the routines used by rp_ioctl.  These are all called from exception handlers.  */
1167
1168 /*
1169  *  Returns the state of the serial modem control lines.  These next 2 functions
1170  *  are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1171  */
1172 static int rp_tiocmget(struct tty_struct *tty, struct file *file)
1173 {
1174         struct r_port *info = tty->driver_data;
1175         unsigned int control, result, ChanStatus;
1176
1177         ChanStatus = sGetChanStatusLo(&info->channel);
1178         control = info->channel.TxControl[3];
1179         result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1180                 ((control & SET_DTR) ?  TIOCM_DTR : 0) |
1181                 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1182                 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1183                 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1184                 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1185
1186         return result;
1187 }
1188
1189 /*
1190  *  Sets the modem control lines
1191  */
1192 static int rp_tiocmset(struct tty_struct *tty, struct file *file,
1193                     unsigned int set, unsigned int clear)
1194 {
1195         struct r_port *info = tty->driver_data;
1196
1197         if (set & TIOCM_RTS)
1198                 info->channel.TxControl[3] |= SET_RTS;
1199         if (set & TIOCM_DTR)
1200                 info->channel.TxControl[3] |= SET_DTR;
1201         if (clear & TIOCM_RTS)
1202                 info->channel.TxControl[3] &= ~SET_RTS;
1203         if (clear & TIOCM_DTR)
1204                 info->channel.TxControl[3] &= ~SET_DTR;
1205
1206         out32(info->channel.IndexAddr, info->channel.TxControl);
1207         return 0;
1208 }
1209
1210 static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1211 {
1212         struct rocket_config tmp;
1213
1214         if (!retinfo)
1215                 return -EFAULT;
1216         memset(&tmp, 0, sizeof (tmp));
1217         mutex_lock(&info->port.mutex);
1218         tmp.line = info->line;
1219         tmp.flags = info->flags;
1220         tmp.close_delay = info->port.close_delay;
1221         tmp.closing_wait = info->port.closing_wait;
1222         tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1223         mutex_unlock(&info->port.mutex);
1224
1225         if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1226                 return -EFAULT;
1227         return 0;
1228 }
1229
1230 static int set_config(struct tty_struct *tty, struct r_port *info,
1231                                         struct rocket_config __user *new_info)
1232 {
1233         struct rocket_config new_serial;
1234
1235         if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1236                 return -EFAULT;
1237
1238         mutex_lock(&info->port.mutex);
1239         if (!capable(CAP_SYS_ADMIN))
1240         {
1241                 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) {
1242                         mutex_unlock(&info->port.mutex);
1243                         return -EPERM;
1244                 }
1245                 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1246                 configure_r_port(tty, info, NULL);
1247                 return 0;
1248         }
1249
1250         info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1251         info->port.close_delay = new_serial.close_delay;
1252         info->port.closing_wait = new_serial.closing_wait;
1253
1254         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1255                 tty->alt_speed = 57600;
1256         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1257                 tty->alt_speed = 115200;
1258         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1259                 tty->alt_speed = 230400;
1260         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1261                 tty->alt_speed = 460800;
1262         mutex_unlock(&info->port.mutex);
1263
1264         configure_r_port(tty, info, NULL);
1265         return 0;
1266 }
1267
1268 /*
1269  *  This function fills in a rocket_ports struct with information
1270  *  about what boards/ports are in the system.  This info is passed
1271  *  to user space.  See setrocket.c where the info is used to create
1272  *  the /dev/ttyRx ports.
1273  */
1274 static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1275 {
1276         struct rocket_ports tmp;
1277         int board;
1278
1279         if (!retports)
1280                 return -EFAULT;
1281         memset(&tmp, 0, sizeof (tmp));
1282         tmp.tty_major = rocket_driver->major;
1283
1284         for (board = 0; board < 4; board++) {
1285                 tmp.rocketModel[board].model = rocketModel[board].model;
1286                 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1287                 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1288                 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1289                 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1290         }
1291         if (copy_to_user(retports, &tmp, sizeof (*retports)))
1292                 return -EFAULT;
1293         return 0;
1294 }
1295
1296 static int reset_rm2(struct r_port *info, void __user *arg)
1297 {
1298         int reset;
1299
1300         if (!capable(CAP_SYS_ADMIN))
1301                 return -EPERM;
1302
1303         if (copy_from_user(&reset, arg, sizeof (int)))
1304                 return -EFAULT;
1305         if (reset)
1306                 reset = 1;
1307
1308         if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1309             rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1310                 return -EINVAL;
1311
1312         if (info->ctlp->BusType == isISA)
1313                 sModemReset(info->ctlp, info->chan, reset);
1314         else
1315                 sPCIModemReset(info->ctlp, info->chan, reset);
1316
1317         return 0;
1318 }
1319
1320 static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1321 {
1322         if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1323                 return -EFAULT;
1324         return 0;
1325 }
1326
1327 /*  IOCTL call handler into the driver */
1328 static int rp_ioctl(struct tty_struct *tty, struct file *file,
1329                     unsigned int cmd, unsigned long arg)
1330 {
1331         struct r_port *info = tty->driver_data;
1332         void __user *argp = (void __user *)arg;
1333         int ret = 0;
1334
1335         if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1336                 return -ENXIO;
1337
1338         switch (cmd) {
1339         case RCKP_GET_STRUCT:
1340                 if (copy_to_user(argp, info, sizeof (struct r_port)))
1341                         ret = -EFAULT;
1342                 break;
1343         case RCKP_GET_CONFIG:
1344                 ret = get_config(info, argp);
1345                 break;
1346         case RCKP_SET_CONFIG:
1347                 ret = set_config(tty, info, argp);
1348                 break;
1349         case RCKP_GET_PORTS:
1350                 ret = get_ports(info, argp);
1351                 break;
1352         case RCKP_RESET_RM2:
1353                 ret = reset_rm2(info, argp);
1354                 break;
1355         case RCKP_GET_VERSION:
1356                 ret = get_version(info, argp);
1357                 break;
1358         default:
1359                 ret = -ENOIOCTLCMD;
1360         }
1361         return ret;
1362 }
1363
1364 static void rp_send_xchar(struct tty_struct *tty, char ch)
1365 {
1366         struct r_port *info = tty->driver_data;
1367         CHANNEL_t *cp;
1368
1369         if (rocket_paranoia_check(info, "rp_send_xchar"))
1370                 return;
1371
1372         cp = &info->channel;
1373         if (sGetTxCnt(cp))
1374                 sWriteTxPrioByte(cp, ch);
1375         else
1376                 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1377 }
1378
1379 static void rp_throttle(struct tty_struct *tty)
1380 {
1381         struct r_port *info = tty->driver_data;
1382         CHANNEL_t *cp;
1383
1384 #ifdef ROCKET_DEBUG_THROTTLE
1385         printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1386                tty->ldisc.chars_in_buffer(tty));
1387 #endif
1388
1389         if (rocket_paranoia_check(info, "rp_throttle"))
1390                 return;
1391
1392         cp = &info->channel;
1393         if (I_IXOFF(tty))
1394                 rp_send_xchar(tty, STOP_CHAR(tty));
1395
1396         sClrRTS(&info->channel);
1397 }
1398
1399 static void rp_unthrottle(struct tty_struct *tty)
1400 {
1401         struct r_port *info = tty->driver_data;
1402         CHANNEL_t *cp;
1403 #ifdef ROCKET_DEBUG_THROTTLE
1404         printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1405                tty->ldisc.chars_in_buffer(tty));
1406 #endif
1407
1408         if (rocket_paranoia_check(info, "rp_throttle"))
1409                 return;
1410
1411         cp = &info->channel;
1412         if (I_IXOFF(tty))
1413                 rp_send_xchar(tty, START_CHAR(tty));
1414
1415         sSetRTS(&info->channel);
1416 }
1417
1418 /*
1419  * ------------------------------------------------------------
1420  * rp_stop() and rp_start()
1421  *
1422  * This routines are called before setting or resetting tty->stopped.
1423  * They enable or disable transmitter interrupts, as necessary.
1424  * ------------------------------------------------------------
1425  */
1426 static void rp_stop(struct tty_struct *tty)
1427 {
1428         struct r_port *info = tty->driver_data;
1429
1430 #ifdef ROCKET_DEBUG_FLOW
1431         printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1432                info->xmit_cnt, info->xmit_fifo_room);
1433 #endif
1434
1435         if (rocket_paranoia_check(info, "rp_stop"))
1436                 return;
1437
1438         if (sGetTxCnt(&info->channel))
1439                 sDisTransmit(&info->channel);
1440 }
1441
1442 static void rp_start(struct tty_struct *tty)
1443 {
1444         struct r_port *info = tty->driver_data;
1445
1446 #ifdef ROCKET_DEBUG_FLOW
1447         printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1448                info->xmit_cnt, info->xmit_fifo_room);
1449 #endif
1450
1451         if (rocket_paranoia_check(info, "rp_stop"))
1452                 return;
1453
1454         sEnTransmit(&info->channel);
1455         set_bit((info->aiop * 8) + info->chan,
1456                 (void *) &xmit_flags[info->board]);
1457 }
1458
1459 /*
1460  * rp_wait_until_sent() --- wait until the transmitter is empty
1461  */
1462 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1463 {
1464         struct r_port *info = tty->driver_data;
1465         CHANNEL_t *cp;
1466         unsigned long orig_jiffies;
1467         int check_time, exit_time;
1468         int txcnt;
1469
1470         if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1471                 return;
1472
1473         cp = &info->channel;
1474
1475         orig_jiffies = jiffies;
1476 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1477         printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...\n", timeout,
1478                jiffies);
1479         printk(KERN_INFO "cps=%d...\n", info->cps);
1480 #endif
1481         while (1) {
1482                 txcnt = sGetTxCnt(cp);
1483                 if (!txcnt) {
1484                         if (sGetChanStatusLo(cp) & TXSHRMT)
1485                                 break;
1486                         check_time = (HZ / info->cps) / 5;
1487                 } else {
1488                         check_time = HZ * txcnt / info->cps;
1489                 }
1490                 if (timeout) {
1491                         exit_time = orig_jiffies + timeout - jiffies;
1492                         if (exit_time <= 0)
1493                                 break;
1494                         if (exit_time < check_time)
1495                                 check_time = exit_time;
1496                 }
1497                 if (check_time == 0)
1498                         check_time = 1;
1499 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1500                 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1501                                 jiffies, check_time);
1502 #endif
1503                 msleep_interruptible(jiffies_to_msecs(check_time));
1504                 if (signal_pending(current))
1505                         break;
1506         }
1507         __set_current_state(TASK_RUNNING);
1508 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1509         printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1510 #endif
1511 }
1512
1513 /*
1514  * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1515  */
1516 static void rp_hangup(struct tty_struct *tty)
1517 {
1518         CHANNEL_t *cp;
1519         struct r_port *info = tty->driver_data;
1520         unsigned long flags;
1521
1522         if (rocket_paranoia_check(info, "rp_hangup"))
1523                 return;
1524
1525 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1526         printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1527 #endif
1528         rp_flush_buffer(tty);
1529         spin_lock_irqsave(&info->port.lock, flags);
1530         if (info->port.flags & ASYNC_CLOSING) {
1531                 spin_unlock_irqrestore(&info->port.lock, flags);
1532                 return;
1533         }
1534         if (info->port.count)
1535                 atomic_dec(&rp_num_ports_open);
1536         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1537         spin_unlock_irqrestore(&info->port.lock, flags);
1538
1539         tty_port_hangup(&info->port);
1540
1541         cp = &info->channel;
1542         sDisRxFIFO(cp);
1543         sDisTransmit(cp);
1544         sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1545         sDisCTSFlowCtl(cp);
1546         sDisTxSoftFlowCtl(cp);
1547         sClrTxXOFF(cp);
1548         clear_bit(ASYNCB_INITIALIZED, &info->port.flags);
1549
1550         wake_up_interruptible(&info->port.open_wait);
1551 }
1552
1553 /*
1554  *  Exception handler - write char routine.  The RocketPort driver uses a
1555  *  double-buffering strategy, with the twist that if the in-memory CPU
1556  *  buffer is empty, and there's space in the transmit FIFO, the
1557  *  writing routines will write directly to transmit FIFO.
1558  *  Write buffer and counters protected by spinlocks
1559  */
1560 static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1561 {
1562         struct r_port *info = tty->driver_data;
1563         CHANNEL_t *cp;
1564         unsigned long flags;
1565
1566         if (rocket_paranoia_check(info, "rp_put_char"))
1567                 return 0;
1568
1569         /*
1570          * Grab the port write mutex, locking out other processes that try to
1571          * write to this port
1572          */
1573         mutex_lock(&info->write_mtx);
1574
1575 #ifdef ROCKET_DEBUG_WRITE
1576         printk(KERN_INFO "rp_put_char %c...\n", ch);
1577 #endif
1578
1579         spin_lock_irqsave(&info->slock, flags);
1580         cp = &info->channel;
1581
1582         if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
1583                 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1584
1585         if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1586                 info->xmit_buf[info->xmit_head++] = ch;
1587                 info->xmit_head &= XMIT_BUF_SIZE - 1;
1588                 info->xmit_cnt++;
1589                 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1590         } else {
1591                 sOutB(sGetTxRxDataIO(cp), ch);
1592                 info->xmit_fifo_room--;
1593         }
1594         spin_unlock_irqrestore(&info->slock, flags);
1595         mutex_unlock(&info->write_mtx);
1596         return 1;
1597 }
1598
1599 /*
1600  *  Exception handler - write routine, called when user app writes to the device.
1601  *  A per port write mutex is used to protect from another process writing to
1602  *  this port at the same time.  This other process could be running on the other CPU
1603  *  or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1604  *  Spinlocks protect the info xmit members.
1605  */
1606 static int rp_write(struct tty_struct *tty,
1607                     const unsigned char *buf, int count)
1608 {
1609         struct r_port *info = tty->driver_data;
1610         CHANNEL_t *cp;
1611         const unsigned char *b;
1612         int c, retval = 0;
1613         unsigned long flags;
1614
1615         if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1616                 return 0;
1617
1618         if (mutex_lock_interruptible(&info->write_mtx))
1619                 return -ERESTARTSYS;
1620
1621 #ifdef ROCKET_DEBUG_WRITE
1622         printk(KERN_INFO "rp_write %d chars...\n", count);
1623 #endif
1624         cp = &info->channel;
1625
1626         if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
1627                 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1628
1629         /*
1630          *  If the write queue for the port is empty, and there is FIFO space, stuff bytes
1631          *  into FIFO.  Use the write queue for temp storage.
1632          */
1633         if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1634                 c = min(count, info->xmit_fifo_room);
1635                 b = buf;
1636
1637                 /*  Push data into FIFO, 2 bytes at a time */
1638                 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1639
1640                 /*  If there is a byte remaining, write it */
1641                 if (c & 1)
1642                         sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1643
1644                 retval += c;
1645                 buf += c;
1646                 count -= c;
1647
1648                 spin_lock_irqsave(&info->slock, flags);
1649                 info->xmit_fifo_room -= c;
1650                 spin_unlock_irqrestore(&info->slock, flags);
1651         }
1652
1653         /* If count is zero, we wrote it all and are done */
1654         if (!count)
1655                 goto end;
1656
1657         /*  Write remaining data into the port's xmit_buf */
1658         while (1) {
1659                 /* Hung up ? */
1660                 if (!test_bit(ASYNCB_NORMAL_ACTIVE, &info->port.flags))
1661                         goto end;
1662                 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1663                 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1664                 if (c <= 0)
1665                         break;
1666
1667                 b = buf;
1668                 memcpy(info->xmit_buf + info->xmit_head, b, c);
1669
1670                 spin_lock_irqsave(&info->slock, flags);
1671                 info->xmit_head =
1672                     (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1673                 info->xmit_cnt += c;
1674                 spin_unlock_irqrestore(&info->slock, flags);
1675
1676                 buf += c;
1677                 count -= c;
1678                 retval += c;
1679         }
1680
1681         if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
1682                 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1683
1684 end:
1685         if (info->xmit_cnt < WAKEUP_CHARS) {
1686                 tty_wakeup(tty);
1687 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1688                 wake_up_interruptible(&tty->poll_wait);
1689 #endif
1690         }
1691         mutex_unlock(&info->write_mtx);
1692         return retval;
1693 }
1694
1695 /*
1696  * Return the number of characters that can be sent.  We estimate
1697  * only using the in-memory transmit buffer only, and ignore the
1698  * potential space in the transmit FIFO.
1699  */
1700 static int rp_write_room(struct tty_struct *tty)
1701 {
1702         struct r_port *info = tty->driver_data;
1703         int ret;
1704
1705         if (rocket_paranoia_check(info, "rp_write_room"))
1706                 return 0;
1707
1708         ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1709         if (ret < 0)
1710                 ret = 0;
1711 #ifdef ROCKET_DEBUG_WRITE
1712         printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1713 #endif
1714         return ret;
1715 }
1716
1717 /*
1718  * Return the number of characters in the buffer.  Again, this only
1719  * counts those characters in the in-memory transmit buffer.
1720  */
1721 static int rp_chars_in_buffer(struct tty_struct *tty)
1722 {
1723         struct r_port *info = tty->driver_data;
1724         CHANNEL_t *cp;
1725
1726         if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1727                 return 0;
1728
1729         cp = &info->channel;
1730
1731 #ifdef ROCKET_DEBUG_WRITE
1732         printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1733 #endif
1734         return info->xmit_cnt;
1735 }
1736
1737 /*
1738  *  Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1739  *  r_port struct for the port.  Note that spinlock are used to protect info members,
1740  *  do not call this function if the spinlock is already held.
1741  */
1742 static void rp_flush_buffer(struct tty_struct *tty)
1743 {
1744         struct r_port *info = tty->driver_data;
1745         CHANNEL_t *cp;
1746         unsigned long flags;
1747
1748         if (rocket_paranoia_check(info, "rp_flush_buffer"))
1749                 return;
1750
1751         spin_lock_irqsave(&info->slock, flags);
1752         info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1753         spin_unlock_irqrestore(&info->slock, flags);
1754
1755 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1756         wake_up_interruptible(&tty->poll_wait);
1757 #endif
1758         tty_wakeup(tty);
1759
1760         cp = &info->channel;
1761         sFlushTxFIFO(cp);
1762 }
1763
1764 #ifdef CONFIG_PCI
1765
1766 static struct pci_device_id __devinitdata rocket_pci_ids[] = {
1767         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_ANY_ID) },
1768         { }
1769 };
1770 MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1771
1772 /*
1773  *  Called when a PCI card is found.  Retrieves and stores model information,
1774  *  init's aiopic and serial port hardware.
1775  *  Inputs:  i is the board number (0-n)
1776  */
1777 static __init int register_PCI(int i, struct pci_dev *dev)
1778 {
1779         int num_aiops, aiop, max_num_aiops, num_chan, chan;
1780         unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1781         char *str, *board_type;
1782         CONTROLLER_t *ctlp;
1783
1784         int fast_clock = 0;
1785         int altChanRingIndicator = 0;
1786         int ports_per_aiop = 8;
1787         WordIO_t ConfigIO = 0;
1788         ByteIO_t UPCIRingInd = 0;
1789
1790         if (!dev || pci_enable_device(dev))
1791                 return 0;
1792
1793         rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1794
1795         rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1796         rocketModel[i].loadrm2 = 0;
1797         rocketModel[i].startingPortNumber = nextLineNumber;
1798
1799         /*  Depending on the model, set up some config variables */
1800         switch (dev->device) {
1801         case PCI_DEVICE_ID_RP4QUAD:
1802                 str = "Quadcable";
1803                 max_num_aiops = 1;
1804                 ports_per_aiop = 4;
1805                 rocketModel[i].model = MODEL_RP4QUAD;
1806                 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1807                 rocketModel[i].numPorts = 4;
1808                 break;
1809         case PCI_DEVICE_ID_RP8OCTA:
1810                 str = "Octacable";
1811                 max_num_aiops = 1;
1812                 rocketModel[i].model = MODEL_RP8OCTA;
1813                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1814                 rocketModel[i].numPorts = 8;
1815                 break;
1816         case PCI_DEVICE_ID_URP8OCTA:
1817                 str = "Octacable";
1818                 max_num_aiops = 1;
1819                 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1820                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1821                 rocketModel[i].numPorts = 8;
1822                 break;
1823         case PCI_DEVICE_ID_RP8INTF:
1824                 str = "8";
1825                 max_num_aiops = 1;
1826                 rocketModel[i].model = MODEL_RP8INTF;
1827                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1828                 rocketModel[i].numPorts = 8;
1829                 break;
1830         case PCI_DEVICE_ID_URP8INTF:
1831                 str = "8";
1832                 max_num_aiops = 1;
1833                 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1834                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1835                 rocketModel[i].numPorts = 8;
1836                 break;
1837         case PCI_DEVICE_ID_RP8J:
1838                 str = "8J";
1839                 max_num_aiops = 1;
1840                 rocketModel[i].model = MODEL_RP8J;
1841                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1842                 rocketModel[i].numPorts = 8;
1843                 break;
1844         case PCI_DEVICE_ID_RP4J:
1845                 str = "4J";
1846                 max_num_aiops = 1;
1847                 ports_per_aiop = 4;
1848                 rocketModel[i].model = MODEL_RP4J;
1849                 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1850                 rocketModel[i].numPorts = 4;
1851                 break;
1852         case PCI_DEVICE_ID_RP8SNI:
1853                 str = "8 (DB78 Custom)";
1854                 max_num_aiops = 1;
1855                 rocketModel[i].model = MODEL_RP8SNI;
1856                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1857                 rocketModel[i].numPorts = 8;
1858                 break;
1859         case PCI_DEVICE_ID_RP16SNI:
1860                 str = "16 (DB78 Custom)";
1861                 max_num_aiops = 2;
1862                 rocketModel[i].model = MODEL_RP16SNI;
1863                 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1864                 rocketModel[i].numPorts = 16;
1865                 break;
1866         case PCI_DEVICE_ID_RP16INTF:
1867                 str = "16";
1868                 max_num_aiops = 2;
1869                 rocketModel[i].model = MODEL_RP16INTF;
1870                 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1871                 rocketModel[i].numPorts = 16;
1872                 break;
1873         case PCI_DEVICE_ID_URP16INTF:
1874                 str = "16";
1875                 max_num_aiops = 2;
1876                 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1877                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1878                 rocketModel[i].numPorts = 16;
1879                 break;
1880         case PCI_DEVICE_ID_CRP16INTF:
1881                 str = "16";
1882                 max_num_aiops = 2;
1883                 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1884                 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1885                 rocketModel[i].numPorts = 16;
1886                 break;
1887         case PCI_DEVICE_ID_RP32INTF:
1888                 str = "32";
1889                 max_num_aiops = 4;
1890                 rocketModel[i].model = MODEL_RP32INTF;
1891                 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1892                 rocketModel[i].numPorts = 32;
1893                 break;
1894         case PCI_DEVICE_ID_URP32INTF:
1895                 str = "32";
1896                 max_num_aiops = 4;
1897                 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1898                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1899                 rocketModel[i].numPorts = 32;
1900                 break;
1901         case PCI_DEVICE_ID_RPP4:
1902                 str = "Plus Quadcable";
1903                 max_num_aiops = 1;
1904                 ports_per_aiop = 4;
1905                 altChanRingIndicator++;
1906                 fast_clock++;
1907                 rocketModel[i].model = MODEL_RPP4;
1908                 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
1909                 rocketModel[i].numPorts = 4;
1910                 break;
1911         case PCI_DEVICE_ID_RPP8:
1912                 str = "Plus Octacable";
1913                 max_num_aiops = 2;
1914                 ports_per_aiop = 4;
1915                 altChanRingIndicator++;
1916                 fast_clock++;
1917                 rocketModel[i].model = MODEL_RPP8;
1918                 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
1919                 rocketModel[i].numPorts = 8;
1920                 break;
1921         case PCI_DEVICE_ID_RP2_232:
1922                 str = "Plus 2 (RS-232)";
1923                 max_num_aiops = 1;
1924                 ports_per_aiop = 2;
1925                 altChanRingIndicator++;
1926                 fast_clock++;
1927                 rocketModel[i].model = MODEL_RP2_232;
1928                 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
1929                 rocketModel[i].numPorts = 2;
1930                 break;
1931         case PCI_DEVICE_ID_RP2_422:
1932                 str = "Plus 2 (RS-422)";
1933                 max_num_aiops = 1;
1934                 ports_per_aiop = 2;
1935                 altChanRingIndicator++;
1936                 fast_clock++;
1937                 rocketModel[i].model = MODEL_RP2_422;
1938                 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
1939                 rocketModel[i].numPorts = 2;
1940                 break;
1941         case PCI_DEVICE_ID_RP6M:
1942
1943                 max_num_aiops = 1;
1944                 ports_per_aiop = 6;
1945                 str = "6-port";
1946
1947                 /*  If revision is 1, the rocketmodem flash must be loaded.
1948                  *  If it is 2 it is a "socketed" version. */
1949                 if (dev->revision == 1) {
1950                         rcktpt_type[i] = ROCKET_TYPE_MODEMII;
1951                         rocketModel[i].loadrm2 = 1;
1952                 } else {
1953                         rcktpt_type[i] = ROCKET_TYPE_MODEM;
1954                 }
1955
1956                 rocketModel[i].model = MODEL_RP6M;
1957                 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
1958                 rocketModel[i].numPorts = 6;
1959                 break;
1960         case PCI_DEVICE_ID_RP4M:
1961                 max_num_aiops = 1;
1962                 ports_per_aiop = 4;
1963                 str = "4-port";
1964                 if (dev->revision == 1) {
1965                         rcktpt_type[i] = ROCKET_TYPE_MODEMII;
1966                         rocketModel[i].loadrm2 = 1;
1967                 } else {
1968                         rcktpt_type[i] = ROCKET_TYPE_MODEM;
1969                 }
1970
1971                 rocketModel[i].model = MODEL_RP4M;
1972                 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
1973                 rocketModel[i].numPorts = 4;
1974                 break;
1975         default:
1976                 str = "(unknown/unsupported)";
1977                 max_num_aiops = 0;
1978                 break;
1979         }
1980
1981         /*
1982          * Check for UPCI boards.
1983          */
1984
1985         switch (dev->device) {
1986         case PCI_DEVICE_ID_URP32INTF:
1987         case PCI_DEVICE_ID_URP8INTF:
1988         case PCI_DEVICE_ID_URP16INTF:
1989         case PCI_DEVICE_ID_CRP16INTF:
1990         case PCI_DEVICE_ID_URP8OCTA:
1991                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
1992                 ConfigIO = pci_resource_start(dev, 1);
1993                 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
1994                         UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
1995
1996                         /*
1997                          * Check for octa or quad cable.
1998                          */
1999                         if (!
2000                             (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2001                              PCI_GPIO_CTRL_8PORT)) {
2002                                 str = "Quadcable";
2003                                 ports_per_aiop = 4;
2004                                 rocketModel[i].numPorts = 4;
2005                         }
2006                 }
2007                 break;
2008         case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2009                 str = "8 ports";
2010                 max_num_aiops = 1;
2011                 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2012                 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2013                 rocketModel[i].numPorts = 8;
2014                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2015                 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2016                 ConfigIO = pci_resource_start(dev, 1);
2017                 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2018                 break;
2019         case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2020                 str = "4 ports";
2021                 max_num_aiops = 1;
2022                 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2023                 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2024                 rocketModel[i].numPorts = 4;
2025                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2026                 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2027                 ConfigIO = pci_resource_start(dev, 1);
2028                 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2029                 break;
2030         default:
2031                 break;
2032         }
2033
2034         switch (rcktpt_type[i]) {
2035         case ROCKET_TYPE_MODEM:
2036                 board_type = "RocketModem";
2037                 break;
2038         case ROCKET_TYPE_MODEMII:
2039                 board_type = "RocketModem II";
2040                 break;
2041         case ROCKET_TYPE_MODEMIII:
2042                 board_type = "RocketModem III";
2043                 break;
2044         default:
2045                 board_type = "RocketPort";
2046                 break;
2047         }
2048
2049         if (fast_clock) {
2050                 sClockPrescale = 0x12;  /* mod 2 (divide by 3) */
2051                 rp_baud_base[i] = 921600;
2052         } else {
2053                 /*
2054                  * If support_low_speed is set, use the slow clock
2055                  * prescale, which supports 50 bps
2056                  */
2057                 if (support_low_speed) {
2058                         /* mod 9 (divide by 10) prescale */
2059                         sClockPrescale = 0x19;
2060                         rp_baud_base[i] = 230400;
2061                 } else {
2062                         /* mod 4 (devide by 5) prescale */
2063                         sClockPrescale = 0x14;
2064                         rp_baud_base[i] = 460800;
2065                 }
2066         }
2067
2068         for (aiop = 0; aiop < max_num_aiops; aiop++)
2069                 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2070         ctlp = sCtlNumToCtlPtr(i);
2071         num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2072         for (aiop = 0; aiop < max_num_aiops; aiop++)
2073                 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2074
2075         dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2076                 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2077                 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2078                 rocketModel[i].startingPortNumber,
2079                 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
2080
2081         if (num_aiops <= 0) {
2082                 rcktpt_io_addr[i] = 0;
2083                 return (0);
2084         }
2085         is_PCI[i] = 1;
2086
2087         /*  Reset the AIOPIC, init the serial ports */
2088         for (aiop = 0; aiop < num_aiops; aiop++) {
2089                 sResetAiopByNum(ctlp, aiop);
2090                 num_chan = ports_per_aiop;
2091                 for (chan = 0; chan < num_chan; chan++)
2092                         init_r_port(i, aiop, chan, dev);
2093         }
2094
2095         /*  Rocket modems must be reset */
2096         if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2097             (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2098             (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2099                 num_chan = ports_per_aiop;
2100                 for (chan = 0; chan < num_chan; chan++)
2101                         sPCIModemReset(ctlp, chan, 1);
2102                 msleep(500);
2103                 for (chan = 0; chan < num_chan; chan++)
2104                         sPCIModemReset(ctlp, chan, 0);
2105                 msleep(500);
2106                 rmSpeakerReset(ctlp, rocketModel[i].model);
2107         }
2108         return (1);
2109 }
2110
2111 /*
2112  *  Probes for PCI cards, inits them if found
2113  *  Input:   board_found = number of ISA boards already found, or the
2114  *           starting board number
2115  *  Returns: Number of PCI boards found
2116  */
2117 static int __init init_PCI(int boards_found)
2118 {
2119         struct pci_dev *dev = NULL;
2120         int count = 0;
2121
2122         /*  Work through the PCI device list, pulling out ours */
2123         while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2124                 if (register_PCI(count + boards_found, dev))
2125                         count++;
2126         }
2127         return (count);
2128 }
2129
2130 #endif                          /* CONFIG_PCI */
2131
2132 /*
2133  *  Probes for ISA cards
2134  *  Input:   i = the board number to look for
2135  *  Returns: 1 if board found, 0 else
2136  */
2137 static int __init init_ISA(int i)
2138 {
2139         int num_aiops, num_chan = 0, total_num_chan = 0;
2140         int aiop, chan;
2141         unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2142         CONTROLLER_t *ctlp;
2143         char *type_string;
2144
2145         /*  If io_addr is zero, no board configured */
2146         if (rcktpt_io_addr[i] == 0)
2147                 return (0);
2148
2149         /*  Reserve the IO region */
2150         if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2151                 printk(KERN_ERR "Unable to reserve IO region for configured "
2152                                 "ISA RocketPort at address 0x%lx, board not "
2153                                 "installed...\n", rcktpt_io_addr[i]);
2154                 rcktpt_io_addr[i] = 0;
2155                 return (0);
2156         }
2157
2158         ctlp = sCtlNumToCtlPtr(i);
2159
2160         ctlp->boardType = rcktpt_type[i];
2161
2162         switch (rcktpt_type[i]) {
2163         case ROCKET_TYPE_PC104:
2164                 type_string = "(PC104)";
2165                 break;
2166         case ROCKET_TYPE_MODEM:
2167                 type_string = "(RocketModem)";
2168                 break;
2169         case ROCKET_TYPE_MODEMII:
2170                 type_string = "(RocketModem II)";
2171                 break;
2172         default:
2173                 type_string = "";
2174                 break;
2175         }
2176
2177         /*
2178          * If support_low_speed is set, use the slow clock prescale,
2179          * which supports 50 bps
2180          */
2181         if (support_low_speed) {
2182                 sClockPrescale = 0x19;  /* mod 9 (divide by 10) prescale */
2183                 rp_baud_base[i] = 230400;
2184         } else {
2185                 sClockPrescale = 0x14;  /* mod 4 (devide by 5) prescale */
2186                 rp_baud_base[i] = 460800;
2187         }
2188
2189         for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2190                 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2191
2192         num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio,  MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2193
2194         if (ctlp->boardType == ROCKET_TYPE_PC104) {
2195                 sEnAiop(ctlp, 2);       /* only one AIOPIC, but these */
2196                 sEnAiop(ctlp, 3);       /* CSels used for other stuff */
2197         }
2198
2199         /*  If something went wrong initing the AIOP's release the ISA IO memory */
2200         if (num_aiops <= 0) {
2201                 release_region(rcktpt_io_addr[i], 64);
2202                 rcktpt_io_addr[i] = 0;
2203                 return (0);
2204         }
2205
2206         rocketModel[i].startingPortNumber = nextLineNumber;
2207
2208         for (aiop = 0; aiop < num_aiops; aiop++) {
2209                 sResetAiopByNum(ctlp, aiop);
2210                 sEnAiop(ctlp, aiop);
2211                 num_chan = sGetAiopNumChan(ctlp, aiop);
2212                 total_num_chan += num_chan;
2213                 for (chan = 0; chan < num_chan; chan++)
2214                         init_r_port(i, aiop, chan, NULL);
2215         }
2216         is_PCI[i] = 0;
2217         if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2218                 num_chan = sGetAiopNumChan(ctlp, 0);
2219                 total_num_chan = num_chan;
2220                 for (chan = 0; chan < num_chan; chan++)
2221                         sModemReset(ctlp, chan, 1);
2222                 msleep(500);
2223                 for (chan = 0; chan < num_chan; chan++)
2224                         sModemReset(ctlp, chan, 0);
2225                 msleep(500);
2226                 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2227         } else {
2228                 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2229         }
2230         rocketModel[i].numPorts = total_num_chan;
2231         rocketModel[i].model = MODEL_ISA;
2232
2233         printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2234                i, rcktpt_io_addr[i], num_aiops, type_string);
2235
2236         printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2237                rocketModel[i].modelString,
2238                rocketModel[i].startingPortNumber,
2239                rocketModel[i].startingPortNumber +
2240                rocketModel[i].numPorts - 1);
2241
2242         return (1);
2243 }
2244
2245 static const struct tty_operations rocket_ops = {
2246         .open = rp_open,
2247         .close = rp_close,
2248         .write = rp_write,
2249         .put_char = rp_put_char,
2250         .write_room = rp_write_room,
2251         .chars_in_buffer = rp_chars_in_buffer,
2252         .flush_buffer = rp_flush_buffer,
2253         .ioctl = rp_ioctl,
2254         .throttle = rp_throttle,
2255         .unthrottle = rp_unthrottle,
2256         .set_termios = rp_set_termios,
2257         .stop = rp_stop,
2258         .start = rp_start,
2259         .hangup = rp_hangup,
2260         .break_ctl = rp_break,
2261         .send_xchar = rp_send_xchar,
2262         .wait_until_sent = rp_wait_until_sent,
2263         .tiocmget = rp_tiocmget,
2264         .tiocmset = rp_tiocmset,
2265 };
2266
2267 static const struct tty_port_operations rocket_port_ops = {
2268         .carrier_raised = carrier_raised,
2269         .dtr_rts = dtr_rts,
2270 };
2271
2272 /*
2273  * The module "startup" routine; it's run when the module is loaded.
2274  */
2275 static int __init rp_init(void)
2276 {
2277         int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
2278
2279         printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2280                ROCKET_VERSION, ROCKET_DATE);
2281
2282         rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2283         if (!rocket_driver)
2284                 goto err;
2285
2286         /*
2287          *  If board 1 is non-zero, there is at least one ISA configured.  If controller is
2288          *  zero, use the default controller IO address of board1 + 0x40.
2289          */
2290         if (board1) {
2291                 if (controller == 0)
2292                         controller = board1 + 0x40;
2293         } else {
2294                 controller = 0;  /*  Used as a flag, meaning no ISA boards */
2295         }
2296
2297         /*  If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2298         if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2299                 printk(KERN_ERR "Unable to reserve IO region for first "
2300                         "configured ISA RocketPort controller 0x%lx.  "
2301                         "Driver exiting\n", controller);
2302                 ret = -EBUSY;
2303                 goto err_tty;
2304         }
2305
2306         /*  Store ISA variable retrieved from command line or .conf file. */
2307         rcktpt_io_addr[0] = board1;
2308         rcktpt_io_addr[1] = board2;
2309         rcktpt_io_addr[2] = board3;
2310         rcktpt_io_addr[3] = board4;
2311
2312         rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2313         rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2314         rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2315         rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2316         rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2317         rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2318         rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2319         rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2320
2321         /*
2322          * Set up the tty driver structure and then register this
2323          * driver with the tty layer.
2324          */
2325
2326         rocket_driver->owner = THIS_MODULE;
2327         rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2328         rocket_driver->name = "ttyR";
2329         rocket_driver->driver_name = "Comtrol RocketPort";
2330         rocket_driver->major = TTY_ROCKET_MAJOR;
2331         rocket_driver->minor_start = 0;
2332         rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2333         rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2334         rocket_driver->init_termios = tty_std_termios;
2335         rocket_driver->init_termios.c_cflag =
2336             B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2337         rocket_driver->init_termios.c_ispeed = 9600;
2338         rocket_driver->init_termios.c_ospeed = 9600;
2339 #ifdef ROCKET_SOFT_FLOW
2340         rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
2341 #endif
2342         tty_set_operations(rocket_driver, &rocket_ops);
2343
2344         ret = tty_register_driver(rocket_driver);
2345         if (ret < 0) {
2346                 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2347                 goto err_tty;
2348         }
2349
2350 #ifdef ROCKET_DEBUG_OPEN
2351         printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2352 #endif
2353
2354         /*
2355          *  OK, let's probe each of the controllers looking for boards.  Any boards found
2356          *  will be initialized here.
2357          */
2358         isa_boards_found = 0;
2359         pci_boards_found = 0;
2360
2361         for (i = 0; i < NUM_BOARDS; i++) {
2362                 if (init_ISA(i))
2363                         isa_boards_found++;
2364         }
2365
2366 #ifdef CONFIG_PCI
2367         if (isa_boards_found < NUM_BOARDS)
2368                 pci_boards_found = init_PCI(isa_boards_found);
2369 #endif
2370
2371         max_board = pci_boards_found + isa_boards_found;
2372
2373         if (max_board == 0) {
2374                 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2375                 ret = -ENXIO;
2376                 goto err_ttyu;
2377         }
2378
2379         return 0;
2380 err_ttyu:
2381         tty_unregister_driver(rocket_driver);
2382 err_tty:
2383         put_tty_driver(rocket_driver);
2384 err:
2385         return ret;
2386 }
2387
2388
2389 static void rp_cleanup_module(void)
2390 {
2391         int retval;
2392         int i;
2393
2394         del_timer_sync(&rocket_timer);
2395
2396         retval = tty_unregister_driver(rocket_driver);
2397         if (retval)
2398                 printk(KERN_ERR "Error %d while trying to unregister "
2399                        "rocketport driver\n", -retval);
2400
2401         for (i = 0; i < MAX_RP_PORTS; i++)
2402                 if (rp_table[i]) {
2403                         tty_unregister_device(rocket_driver, i);
2404                         kfree(rp_table[i]);
2405                 }
2406
2407         put_tty_driver(rocket_driver);
2408
2409         for (i = 0; i < NUM_BOARDS; i++) {
2410                 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2411                         continue;
2412                 release_region(rcktpt_io_addr[i], 64);
2413         }
2414         if (controller)
2415                 release_region(controller, 4);
2416 }
2417
2418 /***************************************************************************
2419 Function: sInitController
2420 Purpose:  Initialization of controller global registers and controller
2421           structure.
2422 Call:     sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2423                           IRQNum,Frequency,PeriodicOnly)
2424           CONTROLLER_T *CtlP; Ptr to controller structure
2425           int CtlNum; Controller number
2426           ByteIO_t MudbacIO; Mudbac base I/O address.
2427           ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2428              This list must be in the order the AIOPs will be found on the
2429              controller.  Once an AIOP in the list is not found, it is
2430              assumed that there are no more AIOPs on the controller.
2431           int AiopIOListSize; Number of addresses in AiopIOList
2432           int IRQNum; Interrupt Request number.  Can be any of the following:
2433                          0: Disable global interrupts
2434                          3: IRQ 3
2435                          4: IRQ 4
2436                          5: IRQ 5
2437                          9: IRQ 9
2438                          10: IRQ 10
2439                          11: IRQ 11
2440                          12: IRQ 12
2441                          15: IRQ 15
2442           Byte_t Frequency: A flag identifying the frequency
2443                    of the periodic interrupt, can be any one of the following:
2444                       FREQ_DIS - periodic interrupt disabled
2445                       FREQ_137HZ - 137 Hertz
2446                       FREQ_69HZ - 69 Hertz
2447                       FREQ_34HZ - 34 Hertz
2448                       FREQ_17HZ - 17 Hertz
2449                       FREQ_9HZ - 9 Hertz
2450                       FREQ_4HZ - 4 Hertz
2451                    If IRQNum is set to 0 the Frequency parameter is
2452                    overidden, it is forced to a value of FREQ_DIS.
2453           int PeriodicOnly: 1 if all interrupts except the periodic
2454                                interrupt are to be blocked.
2455                             0 is both the periodic interrupt and
2456                                other channel interrupts are allowed.
2457                             If IRQNum is set to 0 the PeriodicOnly parameter is
2458                                overidden, it is forced to a value of 0.
2459 Return:   int: Number of AIOPs on the controller, or CTLID_NULL if controller
2460                initialization failed.
2461
2462 Comments:
2463           If periodic interrupts are to be disabled but AIOP interrupts
2464           are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2465
2466           If interrupts are to be completely disabled set IRQNum to 0.
2467
2468           Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2469           invalid combination.
2470
2471           This function performs initialization of global interrupt modes,
2472           but it does not actually enable global interrupts.  To enable
2473           and disable global interrupts use functions sEnGlobalInt() and
2474           sDisGlobalInt().  Enabling of global interrupts is normally not
2475           done until all other initializations are complete.
2476
2477           Even if interrupts are globally enabled, they must also be
2478           individually enabled for each channel that is to generate
2479           interrupts.
2480
2481 Warnings: No range checking on any of the parameters is done.
2482
2483           No context switches are allowed while executing this function.
2484
2485           After this function all AIOPs on the controller are disabled,
2486           they can be enabled with sEnAiop().
2487 */
2488 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2489                            ByteIO_t * AiopIOList, int AiopIOListSize,
2490                            int IRQNum, Byte_t Frequency, int PeriodicOnly)
2491 {
2492         int i;
2493         ByteIO_t io;
2494         int done;
2495
2496         CtlP->AiopIntrBits = aiop_intr_bits;
2497         CtlP->AltChanRingIndicator = 0;
2498         CtlP->CtlNum = CtlNum;
2499         CtlP->CtlID = CTLID_0001;       /* controller release 1 */
2500         CtlP->BusType = isISA;
2501         CtlP->MBaseIO = MudbacIO;
2502         CtlP->MReg1IO = MudbacIO + 1;
2503         CtlP->MReg2IO = MudbacIO + 2;
2504         CtlP->MReg3IO = MudbacIO + 3;
2505 #if 1
2506         CtlP->MReg2 = 0;        /* interrupt disable */
2507         CtlP->MReg3 = 0;        /* no periodic interrupts */
2508 #else
2509         if (sIRQMap[IRQNum] == 0) {     /* interrupts globally disabled */
2510                 CtlP->MReg2 = 0;        /* interrupt disable */
2511                 CtlP->MReg3 = 0;        /* no periodic interrupts */
2512         } else {
2513                 CtlP->MReg2 = sIRQMap[IRQNum];  /* set IRQ number */
2514                 CtlP->MReg3 = Frequency;        /* set frequency */
2515                 if (PeriodicOnly) {     /* periodic interrupt only */
2516                         CtlP->MReg3 |= PERIODIC_ONLY;
2517                 }
2518         }
2519 #endif
2520         sOutB(CtlP->MReg2IO, CtlP->MReg2);
2521         sOutB(CtlP->MReg3IO, CtlP->MReg3);
2522         sControllerEOI(CtlP);   /* clear EOI if warm init */
2523         /* Init AIOPs */
2524         CtlP->NumAiop = 0;
2525         for (i = done = 0; i < AiopIOListSize; i++) {
2526                 io = AiopIOList[i];
2527                 CtlP->AiopIO[i] = (WordIO_t) io;
2528                 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2529                 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2530                 sOutB(MudbacIO, (Byte_t) (io >> 6));    /* set up AIOP I/O in MUDBAC */
2531                 if (done)
2532                         continue;
2533                 sEnAiop(CtlP, i);       /* enable the AIOP */
2534                 CtlP->AiopID[i] = sReadAiopID(io);      /* read AIOP ID */
2535                 if (CtlP->AiopID[i] == AIOPID_NULL)     /* if AIOP does not exist */
2536                         done = 1;       /* done looking for AIOPs */
2537                 else {
2538                         CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2539                         sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE);    /* clock prescaler */
2540                         sOutB(io + _INDX_DATA, sClockPrescale);
2541                         CtlP->NumAiop++;        /* bump count of AIOPs */
2542                 }
2543                 sDisAiop(CtlP, i);      /* disable AIOP */
2544         }
2545
2546         if (CtlP->NumAiop == 0)
2547                 return (-1);
2548         else
2549                 return (CtlP->NumAiop);
2550 }
2551
2552 /***************************************************************************
2553 Function: sPCIInitController
2554 Purpose:  Initialization of controller global registers and controller
2555           structure.
2556 Call:     sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2557                           IRQNum,Frequency,PeriodicOnly)
2558           CONTROLLER_T *CtlP; Ptr to controller structure
2559           int CtlNum; Controller number
2560           ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2561              This list must be in the order the AIOPs will be found on the
2562              controller.  Once an AIOP in the list is not found, it is
2563              assumed that there are no more AIOPs on the controller.
2564           int AiopIOListSize; Number of addresses in AiopIOList
2565           int IRQNum; Interrupt Request number.  Can be any of the following:
2566                          0: Disable global interrupts
2567                          3: IRQ 3
2568                          4: IRQ 4
2569                          5: IRQ 5
2570                          9: IRQ 9
2571                          10: IRQ 10
2572                          11: IRQ 11
2573                          12: IRQ 12
2574                          15: IRQ 15
2575           Byte_t Frequency: A flag identifying the frequency
2576                    of the periodic interrupt, can be any one of the following:
2577                       FREQ_DIS - periodic interrupt disabled
2578                       FREQ_137HZ - 137 Hertz
2579                       FREQ_69HZ - 69 Hertz
2580                       FREQ_34HZ - 34 Hertz
2581                       FREQ_17HZ - 17 Hertz
2582                       FREQ_9HZ - 9 Hertz
2583                       FREQ_4HZ - 4 Hertz
2584                    If IRQNum is set to 0 the Frequency parameter is
2585                    overidden, it is forced to a value of FREQ_DIS.
2586           int PeriodicOnly: 1 if all interrupts except the periodic
2587                                interrupt are to be blocked.
2588                             0 is both the periodic interrupt and
2589                                other channel interrupts are allowed.
2590                             If IRQNum is set to 0 the PeriodicOnly parameter is
2591                                overidden, it is forced to a value of 0.
2592 Return:   int: Number of AIOPs on the controller, or CTLID_NULL if controller
2593                initialization failed.
2594
2595 Comments:
2596           If periodic interrupts are to be disabled but AIOP interrupts
2597           are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2598
2599           If interrupts are to be completely disabled set IRQNum to 0.
2600
2601           Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2602           invalid combination.
2603
2604           This function performs initialization of global interrupt modes,
2605           but it does not actually enable global interrupts.  To enable
2606           and disable global interrupts use functions sEnGlobalInt() and
2607           sDisGlobalInt().  Enabling of global interrupts is normally not
2608           done until all other initializations are complete.
2609
2610           Even if interrupts are globally enabled, they must also be
2611           individually enabled for each channel that is to generate
2612           interrupts.
2613
2614 Warnings: No range checking on any of the parameters is done.
2615
2616           No context switches are allowed while executing this function.
2617
2618           After this function all AIOPs on the controller are disabled,
2619           they can be enabled with sEnAiop().
2620 */
2621 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2622                               ByteIO_t * AiopIOList, int AiopIOListSize,
2623                               WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2624                               int PeriodicOnly, int altChanRingIndicator,
2625                               int UPCIRingInd)
2626 {
2627         int i;
2628         ByteIO_t io;
2629
2630         CtlP->AltChanRingIndicator = altChanRingIndicator;
2631         CtlP->UPCIRingInd = UPCIRingInd;
2632         CtlP->CtlNum = CtlNum;
2633         CtlP->CtlID = CTLID_0001;       /* controller release 1 */
2634         CtlP->BusType = isPCI;  /* controller release 1 */
2635
2636         if (ConfigIO) {
2637                 CtlP->isUPCI = 1;
2638                 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2639                 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2640                 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2641         } else {
2642                 CtlP->isUPCI = 0;
2643                 CtlP->PCIIO =
2644                     (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2645                 CtlP->AiopIntrBits = aiop_intr_bits;
2646         }
2647
2648         sPCIControllerEOI(CtlP);        /* clear EOI if warm init */
2649         /* Init AIOPs */
2650         CtlP->NumAiop = 0;
2651         for (i = 0; i < AiopIOListSize; i++) {
2652                 io = AiopIOList[i];
2653                 CtlP->AiopIO[i] = (WordIO_t) io;
2654                 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2655
2656                 CtlP->AiopID[i] = sReadAiopID(io);      /* read AIOP ID */
2657                 if (CtlP->AiopID[i] == AIOPID_NULL)     /* if AIOP does not exist */
2658                         break;  /* done looking for AIOPs */
2659
2660                 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2661                 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE);    /* clock prescaler */
2662                 sOutB(io + _INDX_DATA, sClockPrescale);
2663                 CtlP->NumAiop++;        /* bump count of AIOPs */
2664         }
2665
2666         if (CtlP->NumAiop == 0)
2667                 return (-1);
2668         else
2669                 return (CtlP->NumAiop);
2670 }
2671
2672 /***************************************************************************
2673 Function: sReadAiopID
2674 Purpose:  Read the AIOP idenfication number directly from an AIOP.
2675 Call:     sReadAiopID(io)
2676           ByteIO_t io: AIOP base I/O address
2677 Return:   int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2678                  is replace by an identifying number.
2679           Flag AIOPID_NULL if no valid AIOP is found
2680 Warnings: No context switches are allowed while executing this function.
2681
2682 */
2683 static int sReadAiopID(ByteIO_t io)
2684 {
2685         Byte_t AiopID;          /* ID byte from AIOP */
2686
2687         sOutB(io + _CMD_REG, RESET_ALL);        /* reset AIOP */
2688         sOutB(io + _CMD_REG, 0x0);
2689         AiopID = sInW(io + _CHN_STAT0) & 0x07;
2690         if (AiopID == 0x06)
2691                 return (1);
2692         else                    /* AIOP does not exist */
2693                 return (-1);
2694 }
2695
2696 /***************************************************************************
2697 Function: sReadAiopNumChan
2698 Purpose:  Read the number of channels available in an AIOP directly from
2699           an AIOP.
2700 Call:     sReadAiopNumChan(io)
2701           WordIO_t io: AIOP base I/O address
2702 Return:   int: The number of channels available
2703 Comments: The number of channels is determined by write/reads from identical
2704           offsets within the SRAM address spaces for channels 0 and 4.
2705           If the channel 4 space is mirrored to channel 0 it is a 4 channel
2706           AIOP, otherwise it is an 8 channel.
2707 Warnings: No context switches are allowed while executing this function.
2708 */
2709 static int sReadAiopNumChan(WordIO_t io)
2710 {
2711         Word_t x;
2712         static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2713
2714         /* write to chan 0 SRAM */
2715         out32((DWordIO_t) io + _INDX_ADDR, R);
2716         sOutW(io + _INDX_ADDR, 0);      /* read from SRAM, chan 0 */
2717         x = sInW(io + _INDX_DATA);
2718         sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2719         if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2720                 return (8);
2721         else
2722                 return (4);
2723 }
2724
2725 /***************************************************************************
2726 Function: sInitChan
2727 Purpose:  Initialization of a channel and channel structure
2728 Call:     sInitChan(CtlP,ChP,AiopNum,ChanNum)
2729           CONTROLLER_T *CtlP; Ptr to controller structure
2730           CHANNEL_T *ChP; Ptr to channel structure
2731           int AiopNum; AIOP number within controller
2732           int ChanNum; Channel number within AIOP
2733 Return:   int: 1 if initialization succeeded, 0 if it fails because channel
2734                number exceeds number of channels available in AIOP.
2735 Comments: This function must be called before a channel can be used.
2736 Warnings: No range checking on any of the parameters is done.
2737
2738           No context switches are allowed while executing this function.
2739 */
2740 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2741                      int ChanNum)
2742 {
2743         int i;
2744         WordIO_t AiopIO;
2745         WordIO_t ChIOOff;
2746         Byte_t *ChR;
2747         Word_t ChOff;
2748         static Byte_t R[4];
2749         int brd9600;
2750
2751         if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2752                 return 0;       /* exceeds num chans in AIOP */
2753
2754         /* Channel, AIOP, and controller identifiers */
2755         ChP->CtlP = CtlP;
2756         ChP->ChanID = CtlP->AiopID[AiopNum];
2757         ChP->AiopNum = AiopNum;
2758         ChP->ChanNum = ChanNum;
2759
2760         /* Global direct addresses */
2761         AiopIO = CtlP->AiopIO[AiopNum];
2762         ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2763         ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2764         ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2765         ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2766         ChP->IndexData = AiopIO + _INDX_DATA;
2767
2768         /* Channel direct addresses */
2769         ChIOOff = AiopIO + ChP->ChanNum * 2;
2770         ChP->TxRxData = ChIOOff + _TD0;
2771         ChP->ChanStat = ChIOOff + _CHN_STAT0;
2772         ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2773         ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2774
2775         /* Initialize the channel from the RData array */
2776         for (i = 0; i < RDATASIZE; i += 4) {
2777                 R[0] = RData[i];
2778                 R[1] = RData[i + 1] + 0x10 * ChanNum;
2779                 R[2] = RData[i + 2];
2780                 R[3] = RData[i + 3];
2781                 out32(ChP->IndexAddr, R);
2782         }
2783
2784         ChR = ChP->R;
2785         for (i = 0; i < RREGDATASIZE; i += 4) {
2786                 ChR[i] = RRegData[i];
2787                 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2788                 ChR[i + 2] = RRegData[i + 2];
2789                 ChR[i + 3] = RRegData[i + 3];
2790         }
2791
2792         /* Indexed registers */
2793         ChOff = (Word_t) ChanNum *0x1000;
2794
2795         if (sClockPrescale == 0x14)
2796                 brd9600 = 47;
2797         else
2798                 brd9600 = 23;
2799
2800         ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2801         ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2802         ChP->BaudDiv[2] = (Byte_t) brd9600;
2803         ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2804         out32(ChP->IndexAddr, ChP->BaudDiv);
2805
2806         ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2807         ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2808         ChP->TxControl[2] = 0;
2809         ChP->TxControl[3] = 0;
2810         out32(ChP->IndexAddr, ChP->TxControl);
2811
2812         ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2813         ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2814         ChP->RxControl[2] = 0;
2815         ChP->RxControl[3] = 0;
2816         out32(ChP->IndexAddr, ChP->RxControl);
2817
2818         ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2819         ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2820         ChP->TxEnables[2] = 0;
2821         ChP->TxEnables[3] = 0;
2822         out32(ChP->IndexAddr, ChP->TxEnables);
2823
2824         ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2825         ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2826         ChP->TxCompare[2] = 0;
2827         ChP->TxCompare[3] = 0;
2828         out32(ChP->IndexAddr, ChP->TxCompare);
2829
2830         ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2831         ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2832         ChP->TxReplace1[2] = 0;
2833         ChP->TxReplace1[3] = 0;
2834         out32(ChP->IndexAddr, ChP->TxReplace1);
2835
2836         ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2837         ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2838         ChP->TxReplace2[2] = 0;
2839         ChP->TxReplace2[3] = 0;
2840         out32(ChP->IndexAddr, ChP->TxReplace2);
2841
2842         ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2843         ChP->TxFIFO = ChOff + _TX_FIFO;
2844
2845         sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT);  /* apply reset Tx FIFO count */
2846         sOutB(ChP->Cmd, (Byte_t) ChanNum);      /* remove reset Tx FIFO count */
2847         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs);      /* clear Tx in/out ptrs */
2848         sOutW(ChP->IndexData, 0);
2849         ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2850         ChP->RxFIFO = ChOff + _RX_FIFO;
2851
2852         sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT);  /* apply reset Rx FIFO count */
2853         sOutB(ChP->Cmd, (Byte_t) ChanNum);      /* remove reset Rx FIFO count */
2854         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs);      /* clear Rx out ptr */
2855         sOutW(ChP->IndexData, 0);
2856         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2);  /* clear Rx in ptr */
2857         sOutW(ChP->IndexData, 0);
2858         ChP->TxPrioCnt = ChOff + _TXP_CNT;
2859         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2860         sOutB(ChP->IndexData, 0);
2861         ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2862         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2863         sOutB(ChP->IndexData, 0);
2864         ChP->TxPrioBuf = ChOff + _TXP_BUF;
2865         sEnRxProcessor(ChP);    /* start the Rx processor */
2866
2867         return 1;
2868 }
2869
2870 /***************************************************************************
2871 Function: sStopRxProcessor
2872 Purpose:  Stop the receive processor from processing a channel.
2873 Call:     sStopRxProcessor(ChP)
2874           CHANNEL_T *ChP; Ptr to channel structure
2875
2876 Comments: The receive processor can be started again with sStartRxProcessor().
2877           This function causes the receive processor to skip over the
2878           stopped channel.  It does not stop it from processing other channels.
2879
2880 Warnings: No context switches are allowed while executing this function.
2881
2882           Do not leave the receive processor stopped for more than one
2883           character time.
2884
2885           After calling this function a delay of 4 uS is required to ensure
2886           that the receive processor is no longer processing this channel.
2887 */
2888 static void sStopRxProcessor(CHANNEL_T * ChP)
2889 {
2890         Byte_t R[4];
2891
2892         R[0] = ChP->R[0];
2893         R[1] = ChP->R[1];
2894         R[2] = 0x0a;
2895         R[3] = ChP->R[3];
2896         out32(ChP->IndexAddr, R);
2897 }
2898
2899 /***************************************************************************
2900 Function: sFlushRxFIFO
2901 Purpose:  Flush the Rx FIFO
2902 Call:     sFlushRxFIFO(ChP)
2903           CHANNEL_T *ChP; Ptr to channel structure
2904 Return:   void
2905 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2906           while it is being flushed the receive processor is stopped
2907           and the transmitter is disabled.  After these operations a
2908           4 uS delay is done before clearing the pointers to allow
2909           the receive processor to stop.  These items are handled inside
2910           this function.
2911 Warnings: No context switches are allowed while executing this function.
2912 */
2913 static void sFlushRxFIFO(CHANNEL_T * ChP)
2914 {
2915         int i;
2916         Byte_t Ch;              /* channel number within AIOP */
2917         int RxFIFOEnabled;      /* 1 if Rx FIFO enabled */
2918
2919         if (sGetRxCnt(ChP) == 0)        /* Rx FIFO empty */
2920                 return;         /* don't need to flush */
2921
2922         RxFIFOEnabled = 0;
2923         if (ChP->R[0x32] == 0x08) {     /* Rx FIFO is enabled */
2924                 RxFIFOEnabled = 1;
2925                 sDisRxFIFO(ChP);        /* disable it */
2926                 for (i = 0; i < 2000 / 200; i++)        /* delay 2 uS to allow proc to disable FIFO */
2927                         sInB(ChP->IntChan);     /* depends on bus i/o timing */
2928         }
2929         sGetChanStatus(ChP);    /* clear any pending Rx errors in chan stat */
2930         Ch = (Byte_t) sGetChanNum(ChP);
2931         sOutB(ChP->Cmd, Ch | RESRXFCNT);        /* apply reset Rx FIFO count */
2932         sOutB(ChP->Cmd, Ch);    /* remove reset Rx FIFO count */
2933         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs);      /* clear Rx out ptr */
2934         sOutW(ChP->IndexData, 0);
2935         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2);  /* clear Rx in ptr */
2936         sOutW(ChP->IndexData, 0);
2937         if (RxFIFOEnabled)
2938                 sEnRxFIFO(ChP); /* enable Rx FIFO */
2939 }
2940
2941 /***************************************************************************
2942 Function: sFlushTxFIFO
2943 Purpose:  Flush the Tx FIFO
2944 Call:     sFlushTxFIFO(ChP)
2945           CHANNEL_T *ChP; Ptr to channel structure
2946 Return:   void
2947 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2948           while it is being flushed the receive processor is stopped
2949           and the transmitter is disabled.  After these operations a
2950           4 uS delay is done before clearing the pointers to allow
2951           the receive processor to stop.  These items are handled inside
2952           this function.
2953 Warnings: No context switches are allowed while executing this function.
2954 */
2955 static void sFlushTxFIFO(CHANNEL_T * ChP)
2956 {
2957         int i;
2958         Byte_t Ch;              /* channel number within AIOP */
2959         int TxEnabled;          /* 1 if transmitter enabled */
2960
2961         if (sGetTxCnt(ChP) == 0)        /* Tx FIFO empty */
2962                 return;         /* don't need to flush */
2963
2964         TxEnabled = 0;
2965         if (ChP->TxControl[3] & TX_ENABLE) {
2966                 TxEnabled = 1;
2967                 sDisTransmit(ChP);      /* disable transmitter */
2968         }
2969         sStopRxProcessor(ChP);  /* stop Rx processor */
2970         for (i = 0; i < 4000 / 200; i++)        /* delay 4 uS to allow proc to stop */
2971                 sInB(ChP->IntChan);     /* depends on bus i/o timing */
2972         Ch = (Byte_t) sGetChanNum(ChP);
2973         sOutB(ChP->Cmd, Ch | RESTXFCNT);        /* apply reset Tx FIFO count */
2974         sOutB(ChP->Cmd, Ch);    /* remove reset Tx FIFO count */
2975         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs);      /* clear Tx in/out ptrs */
2976         sOutW(ChP->IndexData, 0);
2977         if (TxEnabled)
2978                 sEnTransmit(ChP);       /* enable transmitter */
2979         sStartRxProcessor(ChP); /* restart Rx processor */
2980 }
2981
2982 /***************************************************************************
2983 Function: sWriteTxPrioByte
2984 Purpose:  Write a byte of priority transmit data to a channel
2985 Call:     sWriteTxPrioByte(ChP,Data)
2986           CHANNEL_T *ChP; Ptr to channel structure
2987           Byte_t Data; The transmit data byte
2988
2989 Return:   int: 1 if the bytes is successfully written, otherwise 0.
2990
2991 Comments: The priority byte is transmitted before any data in the Tx FIFO.
2992
2993 Warnings: No context switches are allowed while executing this function.
2994 */
2995 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
2996 {
2997         Byte_t DWBuf[4];        /* buffer for double word writes */
2998         Word_t *WordPtr;        /* must be far because Win SS != DS */
2999         register DWordIO_t IndexAddr;
3000
3001         if (sGetTxCnt(ChP) > 1) {       /* write it to Tx priority buffer */
3002                 IndexAddr = ChP->IndexAddr;
3003                 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt);    /* get priority buffer status */
3004                 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
3005                         return (0);     /* nothing sent */
3006
3007                 WordPtr = (Word_t *) (&DWBuf[0]);
3008                 *WordPtr = ChP->TxPrioBuf;      /* data byte address */
3009
3010                 DWBuf[2] = Data;        /* data byte value */
3011                 out32(IndexAddr, DWBuf);        /* write it out */
3012
3013                 *WordPtr = ChP->TxPrioCnt;      /* Tx priority count address */
3014
3015                 DWBuf[2] = PRI_PEND + 1;        /* indicate 1 byte pending */
3016                 DWBuf[3] = 0;   /* priority buffer pointer */
3017                 out32(IndexAddr, DWBuf);        /* write it out */
3018         } else {                /* write it to Tx FIFO */
3019
3020                 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3021         }
3022         return (1);             /* 1 byte sent */
3023 }
3024
3025 /***************************************************************************
3026 Function: sEnInterrupts
3027 Purpose:  Enable one or more interrupts for a channel
3028 Call:     sEnInterrupts(ChP,Flags)
3029           CHANNEL_T *ChP; Ptr to channel structure
3030           Word_t Flags: Interrupt enable flags, can be any combination
3031              of the following flags:
3032                 TXINT_EN:   Interrupt on Tx FIFO empty
3033                 RXINT_EN:   Interrupt on Rx FIFO at trigger level (see
3034                             sSetRxTrigger())
3035                 SRCINT_EN:  Interrupt on SRC (Special Rx Condition)
3036                 MCINT_EN:   Interrupt on modem input change
3037                 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3038                             Interrupt Channel Register.
3039 Return:   void
3040 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3041           enabled.  If an interrupt enable flag is not set in Flags, that
3042           interrupt will not be changed.  Interrupts can be disabled with
3043           function sDisInterrupts().
3044
3045           This function sets the appropriate bit for the channel in the AIOP's
3046           Interrupt Mask Register if the CHANINT_EN flag is set.  This allows
3047           this channel's bit to be set in the AIOP's Interrupt Channel Register.
3048
3049           Interrupts must also be globally enabled before channel interrupts
3050           will be passed on to the host.  This is done with function
3051           sEnGlobalInt().
3052
3053           In some cases it may be desirable to disable interrupts globally but
3054           enable channel interrupts.  This would allow the global interrupt
3055           status register to be used to determine which AIOPs need service.
3056 */
3057 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3058 {
3059         Byte_t Mask;            /* Interrupt Mask Register */
3060
3061         ChP->RxControl[2] |=
3062             ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3063
3064         out32(ChP->IndexAddr, ChP->RxControl);
3065
3066         ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3067
3068         out32(ChP->IndexAddr, ChP->TxControl);
3069
3070         if (Flags & CHANINT_EN) {
3071                 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3072                 sOutB(ChP->IntMask, Mask);
3073         }
3074 }
3075
3076 /***************************************************************************
3077 Function: sDisInterrupts
3078 Purpose:  Disable one or more interrupts for a channel
3079 Call:     sDisInterrupts(ChP,Flags)
3080           CHANNEL_T *ChP; Ptr to channel structure
3081           Word_t Flags: Interrupt flags, can be any combination
3082              of the following flags:
3083                 TXINT_EN:   Interrupt on Tx FIFO empty
3084                 RXINT_EN:   Interrupt on Rx FIFO at trigger level (see
3085                             sSetRxTrigger())
3086                 SRCINT_EN:  Interrupt on SRC (Special Rx Condition)
3087                 MCINT_EN:   Interrupt on modem input change
3088                 CHANINT_EN: Disable channel interrupt signal to the
3089                             AIOP's Interrupt Channel Register.
3090 Return:   void
3091 Comments: If an interrupt flag is set in Flags, that interrupt will be
3092           disabled.  If an interrupt flag is not set in Flags, that
3093           interrupt will not be changed.  Interrupts can be enabled with
3094           function sEnInterrupts().
3095
3096           This function clears the appropriate bit for the channel in the AIOP's
3097           Interrupt Mask Register if the CHANINT_EN flag is set.  This blocks
3098           this channel's bit from being set in the AIOP's Interrupt Channel
3099           Register.
3100 */
3101 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3102 {
3103         Byte_t Mask;            /* Interrupt Mask Register */
3104
3105         ChP->RxControl[2] &=
3106             ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3107         out32(ChP->IndexAddr, ChP->RxControl);
3108         ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3109         out32(ChP->IndexAddr, ChP->TxControl);
3110
3111         if (Flags & CHANINT_EN) {
3112                 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3113                 sOutB(ChP->IntMask, Mask);
3114         }
3115 }
3116
3117 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3118 {
3119         sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3120 }
3121
3122 /*
3123  *  Not an official SSCI function, but how to reset RocketModems.
3124  *  ISA bus version
3125  */
3126 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3127 {
3128         ByteIO_t addr;
3129         Byte_t val;
3130
3131         addr = CtlP->AiopIO[0] + 0x400;
3132         val = sInB(CtlP->MReg3IO);
3133         /* if AIOP[1] is not enabled, enable it */
3134         if ((val & 2) == 0) {
3135                 val = sInB(CtlP->MReg2IO);
3136                 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3137                 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3138         }
3139
3140         sEnAiop(CtlP, 1);
3141         if (!on)
3142                 addr += 8;
3143         sOutB(addr + chan, 0);  /* apply or remove reset */
3144         sDisAiop(CtlP, 1);
3145 }
3146
3147 /*
3148  *  Not an official SSCI function, but how to reset RocketModems.
3149  *  PCI bus version
3150  */
3151 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3152 {
3153         ByteIO_t addr;
3154
3155         addr = CtlP->AiopIO[0] + 0x40;  /* 2nd AIOP */
3156         if (!on)
3157                 addr += 8;
3158         sOutB(addr + chan, 0);  /* apply or remove reset */
3159 }
3160
3161 /*  Resets the speaker controller on RocketModem II and III devices */
3162 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3163 {
3164         ByteIO_t addr;
3165
3166         /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3167         if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3168                 addr = CtlP->AiopIO[0] + 0x4F;
3169                 sOutB(addr, 0);
3170         }
3171
3172         /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3173         if ((model == MODEL_UPCI_RM3_8PORT)
3174             || (model == MODEL_UPCI_RM3_4PORT)) {
3175                 addr = CtlP->AiopIO[0] + 0x88;
3176                 sOutB(addr, 0);
3177         }
3178 }
3179
3180 /*  Returns the line number given the controller (board), aiop and channel number */
3181 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3182 {
3183         return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3184 }
3185
3186 /*
3187  *  Stores the line number associated with a given controller (board), aiop
3188  *  and channel number.
3189  *  Returns:  The line number assigned
3190  */
3191 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3192 {
3193         lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3194         return (nextLineNumber - 1);
3195 }