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gma500: nuke the last bits of TTM code
[linux-2.6/x86.git] / drivers / staging / gma500 / psb_drv.c
blobab1da30e094c9b91d0a9e8411ff5c4c9ff2c2208
1 /**************************************************************************
2 * Copyright (c) 2007-2011, Intel Corporation.
3 * All Rights Reserved.
4 * Copyright (c) 2008, Tungsten Graphics, Inc. Cedar Park, TX., USA.
5 * All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 **************************************************************************/
21
22 #include <drm/drmP.h>
23 #include <drm/drm.h>
24 #include "psb_drm.h"
25 #include "psb_drv.h"
26 #include "psb_fb.h"
27 #include "psb_reg.h"
28 #include "psb_intel_reg.h"
29 #include "psb_intel_bios.h"
30 #include <drm/drm_pciids.h>
31 #include "psb_powermgmt.h"
32 #include <linux/cpu.h>
33 #include <linux/notifier.h>
34 #include <linux/spinlock.h>
35 #include <linux/pm_runtime.h>
36 #include <acpi/video.h>
37
38 int drm_psb_debug;
39 static int drm_psb_trap_pagefaults;
40
41 int drm_psb_no_fb;
42
43 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
44
45 MODULE_PARM_DESC(debug, "Enable debug output");
46 MODULE_PARM_DESC(no_fb, "Disable FBdev");
47 MODULE_PARM_DESC(trap_pagefaults, "Error and reset on MMU pagefaults");
48 module_param_named(debug, drm_psb_debug, int, 0600);
49 module_param_named(no_fb, drm_psb_no_fb, int, 0600);
50 module_param_named(trap_pagefaults, drm_psb_trap_pagefaults, int, 0600);
51
52
53 static struct pci_device_id pciidlist[] = {
54 { 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8108 },
55 { 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8109 },
56 { 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
57 { 0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
58 { 0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
59 { 0x8086, 0x4103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
60 { 0x8086, 0x4104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
61 { 0x8086, 0x4105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
62 { 0x8086, 0x4106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
63 { 0x8086, 0x4107, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
64 { 0, 0, 0}
65 };
66 MODULE_DEVICE_TABLE(pci, pciidlist);
67
68 /*
69 * Standard IOCTLs.
70 */
71
72 #define DRM_IOCTL_PSB_KMS_OFF \
73 DRM_IO(DRM_PSB_KMS_OFF + DRM_COMMAND_BASE)
74 #define DRM_IOCTL_PSB_KMS_ON \
75 DRM_IO(DRM_PSB_KMS_ON + DRM_COMMAND_BASE)
76 #define DRM_IOCTL_PSB_SIZES \
77 DRM_IOR(DRM_PSB_SIZES + DRM_COMMAND_BASE, \
78 struct drm_psb_sizes_arg)
79 #define DRM_IOCTL_PSB_FUSE_REG \
80 DRM_IOWR(DRM_PSB_FUSE_REG + DRM_COMMAND_BASE, uint32_t)
81 #define DRM_IOCTL_PSB_DC_STATE \
82 DRM_IOW(DRM_PSB_DC_STATE + DRM_COMMAND_BASE, \
83 struct drm_psb_dc_state_arg)
84 #define DRM_IOCTL_PSB_ADB \
85 DRM_IOWR(DRM_PSB_ADB + DRM_COMMAND_BASE, uint32_t)
86 #define DRM_IOCTL_PSB_MODE_OPERATION \
87 DRM_IOWR(DRM_PSB_MODE_OPERATION + DRM_COMMAND_BASE, \
88 struct drm_psb_mode_operation_arg)
89 #define DRM_IOCTL_PSB_STOLEN_MEMORY \
90 DRM_IOWR(DRM_PSB_STOLEN_MEMORY + DRM_COMMAND_BASE, \
91 struct drm_psb_stolen_memory_arg)
92 #define DRM_IOCTL_PSB_REGISTER_RW \
93 DRM_IOWR(DRM_PSB_REGISTER_RW + DRM_COMMAND_BASE, \
94 struct drm_psb_register_rw_arg)
95 #define DRM_IOCTL_PSB_DPST \
96 DRM_IOWR(DRM_PSB_DPST + DRM_COMMAND_BASE, \
97 uint32_t)
98 #define DRM_IOCTL_PSB_GAMMA \
99 DRM_IOWR(DRM_PSB_GAMMA + DRM_COMMAND_BASE, \
100 struct drm_psb_dpst_lut_arg)
101 #define DRM_IOCTL_PSB_DPST_BL \
102 DRM_IOWR(DRM_PSB_DPST_BL + DRM_COMMAND_BASE, \
103 uint32_t)
104 #define DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID \
105 DRM_IOWR(DRM_PSB_GET_PIPE_FROM_CRTC_ID + DRM_COMMAND_BASE, \
106 struct drm_psb_get_pipe_from_crtc_id_arg)
107
108 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
109 struct drm_file *file_priv);
110 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
111 struct drm_file *file_priv);
112 static int psb_adb_ioctl(struct drm_device *dev, void *data,
113 struct drm_file *file_priv);
114 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
115 struct drm_file *file_priv);
116 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
117 struct drm_file *file_priv);
118 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
119 struct drm_file *file_priv);
120 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
121 struct drm_file *file_priv);
122 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
123 struct drm_file *file_priv);
124 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
125 struct drm_file *file_priv);
126
127 #define PSB_IOCTL_DEF(ioctl, func, flags) \
128 [DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, flags, func}
129
130 static struct drm_ioctl_desc psb_ioctls[] = {
131 PSB_IOCTL_DEF(DRM_IOCTL_PSB_KMS_OFF, psbfb_kms_off_ioctl,
132 DRM_ROOT_ONLY),
133 PSB_IOCTL_DEF(DRM_IOCTL_PSB_KMS_ON,
134 psbfb_kms_on_ioctl,
135 DRM_ROOT_ONLY),
136 PSB_IOCTL_DEF(DRM_IOCTL_PSB_SIZES, psb_sizes_ioctl, DRM_AUTH),
137 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DC_STATE, psb_dc_state_ioctl, DRM_AUTH),
138 PSB_IOCTL_DEF(DRM_IOCTL_PSB_ADB, psb_adb_ioctl, DRM_AUTH),
139 PSB_IOCTL_DEF(DRM_IOCTL_PSB_MODE_OPERATION, psb_mode_operation_ioctl,
140 DRM_AUTH),
141 PSB_IOCTL_DEF(DRM_IOCTL_PSB_STOLEN_MEMORY, psb_stolen_memory_ioctl,
142 DRM_AUTH),
143 PSB_IOCTL_DEF(DRM_IOCTL_PSB_REGISTER_RW, psb_register_rw_ioctl,
144 DRM_AUTH),
145 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST, psb_dpst_ioctl, DRM_AUTH),
146 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GAMMA, psb_gamma_ioctl, DRM_AUTH),
147 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST_BL, psb_dpst_bl_ioctl, DRM_AUTH),
148 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID,
149 psb_intel_get_pipe_from_crtc_id, 0),
150
151 };
152
153 static void psb_lastclose(struct drm_device *dev)
154 {
155 return;
156 }
157
158 static void psb_do_takedown(struct drm_device *dev)
159 {
160 /* FIXME: do we need to clean up the gtt here ? */
161 }
162
163 void mrst_get_fuse_settings(struct drm_device *dev)
164 {
165 struct drm_psb_private *dev_priv = dev->dev_private;
166 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
167 uint32_t fuse_value = 0;
168 uint32_t fuse_value_tmp = 0;
169
170 #define FB_REG06 0xD0810600
171 #define FB_MIPI_DISABLE (1 << 11)
172 #define FB_REG09 0xD0810900
173 #define FB_REG09 0xD0810900
174 #define FB_SKU_MASK 0x7000
175 #define FB_SKU_SHIFT 12
176 #define FB_SKU_100 0
177 #define FB_SKU_100L 1
178 #define FB_SKU_83 2
179 pci_write_config_dword(pci_root, 0xD0, FB_REG06);
180 pci_read_config_dword(pci_root, 0xD4, &fuse_value);
181
182 dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
183
184 DRM_INFO("internal display is %s\n",
185 dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
186
187 /*prevent Runtime suspend at start*/
188 if (dev_priv->iLVDS_enable) {
189 dev_priv->is_lvds_on = true;
190 dev_priv->is_mipi_on = false;
191 }
192 else {
193 dev_priv->is_mipi_on = true;
194 dev_priv->is_lvds_on = false;
195 }
196
197 dev_priv->video_device_fuse = fuse_value;
198
199 pci_write_config_dword(pci_root, 0xD0, FB_REG09);
200 pci_read_config_dword(pci_root, 0xD4, &fuse_value);
201
202 DRM_INFO("SKU values is 0x%x. \n", fuse_value);
203 fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
204
205 dev_priv->fuse_reg_value = fuse_value;
206
207 switch (fuse_value_tmp) {
208 case FB_SKU_100:
209 dev_priv->core_freq = 200;
210 break;
211 case FB_SKU_100L:
212 dev_priv->core_freq = 100;
213 break;
214 case FB_SKU_83:
215 dev_priv->core_freq = 166;
216 break;
217 default:
218 DRM_ERROR("Invalid SKU values, SKU value = 0x%08x\n", fuse_value_tmp);
219 dev_priv->core_freq = 0;
220 }
221 DRM_INFO("LNC core clk is %dMHz.\n", dev_priv->core_freq);
222 pci_dev_put(pci_root);
223 }
224
225 void mid_get_pci_revID (struct drm_psb_private *dev_priv)
226 {
227 uint32_t platform_rev_id = 0;
228 struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
229
230 /*get the revison ID, B0:D2:F0;0x08 */
231 pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
232 dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
233 pci_dev_put(pci_gfx_root);
234 PSB_DEBUG_ENTRY("platform_rev_id is %x\n", dev_priv->platform_rev_id);
235 }
236
237 void mrst_get_vbt_data(struct drm_psb_private *dev_priv)
238 {
239 struct mrst_vbt *vbt = &dev_priv->vbt_data;
240 u32 platform_config_address;
241 u16 new_size;
242 u8 *vbt_virtual;
243 u8 bpi;
244 u8 number_desc = 0;
245 struct mrst_timing_info *dp_ti = &dev_priv->gct_data.DTD;
246 struct gct_r10_timing_info ti;
247 void *pGCT;
248 struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
249
250 /*get the address of the platform config vbt, B0:D2:F0;0xFC */
251 pci_read_config_dword(pci_gfx_root, 0xFC, &platform_config_address);
252 pci_dev_put(pci_gfx_root);
253 DRM_INFO("drm platform config address is %x\n",
254 platform_config_address);
255
256 /* check for platform config address == 0. */
257 /* this means fw doesn't support vbt */
258
259 if (platform_config_address == 0) {
260 vbt->size = 0;
261 return;
262 }
263
264 /* get the virtual address of the vbt */
265 vbt_virtual = ioremap(platform_config_address, sizeof(*vbt));
266
267 memcpy(vbt, vbt_virtual, sizeof(*vbt));
268 iounmap(vbt_virtual); /* Free virtual address space */
269
270 printk(KERN_ALERT "GCT revision is %x\n", vbt->revision);
271
272 switch (vbt->revision) {
273 case 0:
274 vbt->mrst_gct = NULL;
275 vbt->mrst_gct = \
276 ioremap(platform_config_address + sizeof(*vbt) - 4,
277 vbt->size - sizeof(*vbt) + 4);
278 pGCT = vbt->mrst_gct;
279 bpi = ((struct mrst_gct_v1 *)pGCT)->PD.BootPanelIndex;
280 dev_priv->gct_data.bpi = bpi;
281 dev_priv->gct_data.pt =
282 ((struct mrst_gct_v1 *)pGCT)->PD.PanelType;
283 memcpy(&dev_priv->gct_data.DTD,
284 &((struct mrst_gct_v1 *)pGCT)->panel[bpi].DTD,
285 sizeof(struct mrst_timing_info));
286 dev_priv->gct_data.Panel_Port_Control =
287 ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_Port_Control;
288 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
289 ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
290 break;
291 case 1:
292 vbt->mrst_gct = NULL;
293 vbt->mrst_gct = \
294 ioremap(platform_config_address + sizeof(*vbt) - 4,
295 vbt->size - sizeof(*vbt) + 4);
296 pGCT = vbt->mrst_gct;
297 bpi = ((struct mrst_gct_v2 *)pGCT)->PD.BootPanelIndex;
298 dev_priv->gct_data.bpi = bpi;
299 dev_priv->gct_data.pt =
300 ((struct mrst_gct_v2 *)pGCT)->PD.PanelType;
301 memcpy(&dev_priv->gct_data.DTD,
302 &((struct mrst_gct_v2 *)pGCT)->panel[bpi].DTD,
303 sizeof(struct mrst_timing_info));
304 dev_priv->gct_data.Panel_Port_Control =
305 ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_Port_Control;
306 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
307 ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
308 break;
309 case 0x10:
310 /*header definition changed from rev 01 (v2) to rev 10h. */
311 /*so, some values have changed location*/
312 new_size = vbt->checksum; /*checksum contains lo size byte*/
313 /*LSB of mrst_gct contains hi size byte*/
314 new_size |= ((0xff & (unsigned int)vbt->mrst_gct)) << 8;
315
316 vbt->checksum = vbt->size; /*size contains the checksum*/
317 if (new_size > 0xff)
318 vbt->size = 0xff; /*restrict size to 255*/
319 else
320 vbt->size = new_size;
321
322 /* number of descriptors defined in the GCT */
323 number_desc = ((0xff00 & (unsigned int)vbt->mrst_gct)) >> 8;
324 bpi = ((0xff0000 & (unsigned int)vbt->mrst_gct)) >> 16;
325 vbt->mrst_gct = NULL;
326 vbt->mrst_gct = \
327 ioremap(platform_config_address + GCT_R10_HEADER_SIZE,
328 GCT_R10_DISPLAY_DESC_SIZE * number_desc);
329 pGCT = vbt->mrst_gct;
330 pGCT = (u8 *)pGCT + (bpi*GCT_R10_DISPLAY_DESC_SIZE);
331 dev_priv->gct_data.bpi = bpi; /*save boot panel id*/
332
333 /*copy the GCT display timings into a temp structure*/
334 memcpy(&ti, pGCT, sizeof(struct gct_r10_timing_info));
335
336 /*now copy the temp struct into the dev_priv->gct_data*/
337 dp_ti->pixel_clock = ti.pixel_clock;
338 dp_ti->hactive_hi = ti.hactive_hi;
339 dp_ti->hactive_lo = ti.hactive_lo;
340 dp_ti->hblank_hi = ti.hblank_hi;
341 dp_ti->hblank_lo = ti.hblank_lo;
342 dp_ti->hsync_offset_hi = ti.hsync_offset_hi;
343 dp_ti->hsync_offset_lo = ti.hsync_offset_lo;
344 dp_ti->hsync_pulse_width_hi = ti.hsync_pulse_width_hi;
345 dp_ti->hsync_pulse_width_lo = ti.hsync_pulse_width_lo;
346 dp_ti->vactive_hi = ti.vactive_hi;
347 dp_ti->vactive_lo = ti.vactive_lo;
348 dp_ti->vblank_hi = ti.vblank_hi;
349 dp_ti->vblank_lo = ti.vblank_lo;
350 dp_ti->vsync_offset_hi = ti.vsync_offset_hi;
351 dp_ti->vsync_offset_lo = ti.vsync_offset_lo;
352 dp_ti->vsync_pulse_width_hi = ti.vsync_pulse_width_hi;
353 dp_ti->vsync_pulse_width_lo = ti.vsync_pulse_width_lo;
354
355 /*mov the MIPI_Display_Descriptor data from GCT to dev priv*/
356 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
357 *((u8 *)pGCT + 0x0d);
358 dev_priv->gct_data.Panel_MIPI_Display_Descriptor |=
359 (*((u8 *)pGCT + 0x0e)) << 8;
360 break;
361 default:
362 printk(KERN_ERR "Unknown revision of GCT!\n");
363 vbt->size = 0;
364 }
365 }
366
367 static void psb_get_core_freq(struct drm_device *dev)
368 {
369 uint32_t clock;
370 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
371 struct drm_psb_private *dev_priv = dev->dev_private;
372
373 /*pci_write_config_dword(pci_root, 0xD4, 0x00C32004);*/
374 /*pci_write_config_dword(pci_root, 0xD0, 0xE0033000);*/
375
376 pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
377 pci_read_config_dword(pci_root, 0xD4, &clock);
378 pci_dev_put(pci_root);
379
380 switch (clock & 0x07) {
381 case 0:
382 dev_priv->core_freq = 100;
383 break;
384 case 1:
385 dev_priv->core_freq = 133;
386 break;
387 case 2:
388 dev_priv->core_freq = 150;
389 break;
390 case 3:
391 dev_priv->core_freq = 178;
392 break;
393 case 4:
394 dev_priv->core_freq = 200;
395 break;
396 case 5:
397 case 6:
398 case 7:
399 dev_priv->core_freq = 266;
400 default:
401 dev_priv->core_freq = 0;
402 }
403 }
404
405 static int psb_do_init(struct drm_device *dev)
406 {
407 struct drm_psb_private *dev_priv =
408 (struct drm_psb_private *) dev->dev_private;
409 struct psb_gtt *pg = dev_priv->pg;
410
411 uint32_t stolen_gtt;
412
413 int ret = -ENOMEM;
414
415 if (pg->mmu_gatt_start & 0x0FFFFFFF) {
416 DRM_ERROR("Gatt must be 256M aligned. This is a bug.\n");
417 ret = -EINVAL;
418 goto out_err;
419 }
420
421
422 stolen_gtt = (pg->stolen_size >> PAGE_SHIFT) * 4;
423 stolen_gtt = (stolen_gtt + PAGE_SIZE - 1) >> PAGE_SHIFT;
424 stolen_gtt =
425 (stolen_gtt < pg->gtt_pages) ? stolen_gtt : pg->gtt_pages;
426
427 dev_priv->gatt_free_offset = pg->mmu_gatt_start +
428 (stolen_gtt << PAGE_SHIFT) * 1024;
429
430 if (1 || drm_debug) {
431 uint32_t core_id = PSB_RSGX32(PSB_CR_CORE_ID);
432 uint32_t core_rev = PSB_RSGX32(PSB_CR_CORE_REVISION);
433 DRM_INFO("SGX core id = 0x%08x\n", core_id);
434 DRM_INFO("SGX core rev major = 0x%02x, minor = 0x%02x\n",
435 (core_rev & _PSB_CC_REVISION_MAJOR_MASK) >>
436 _PSB_CC_REVISION_MAJOR_SHIFT,
437 (core_rev & _PSB_CC_REVISION_MINOR_MASK) >>
438 _PSB_CC_REVISION_MINOR_SHIFT);
439 DRM_INFO
440 ("SGX core rev maintenance = 0x%02x, designer = 0x%02x\n",
441 (core_rev & _PSB_CC_REVISION_MAINTENANCE_MASK) >>
442 _PSB_CC_REVISION_MAINTENANCE_SHIFT,
443 (core_rev & _PSB_CC_REVISION_DESIGNER_MASK) >>
444 _PSB_CC_REVISION_DESIGNER_SHIFT);
445 }
446
447
448 spin_lock_init(&dev_priv->irqmask_lock);
449
450 /* FIXME: can we kill ta_mem_size ? */
451 dev_priv->sizes.ta_mem_size = 0;
452
453 PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0);
454 PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1);
455 PSB_RSGX32(PSB_CR_BIF_BANK1);
456 PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) | _PSB_MMU_ER_MASK,
457 PSB_CR_BIF_CTRL);
458 psb_spank(dev_priv);
459
460 /* mmu_gatt ?? */
461 PSB_WSGX32(pg->gatt_start, PSB_CR_BIF_TWOD_REQ_BASE);
462
463 return 0;
464 out_err:
465 psb_do_takedown(dev);
466 return ret;
467 }
468
469 static int psb_driver_unload(struct drm_device *dev)
470 {
471 struct drm_psb_private *dev_priv =
472 (struct drm_psb_private *) dev->dev_private;
473
474 /* Kill vblank etc here */
475
476 psb_backlight_exit(); /*writes minimum value to backlight HW reg */
477
478 if (drm_psb_no_fb == 0)
479 psb_modeset_cleanup(dev);
480
481 if (dev_priv) {
482 psb_lid_timer_takedown(dev_priv);
483
484 psb_do_takedown(dev);
485
486
487 if (dev_priv->pf_pd) {
488 psb_mmu_free_pagedir(dev_priv->pf_pd);
489 dev_priv->pf_pd = NULL;
490 }
491 if (dev_priv->mmu) {
492 struct psb_gtt *pg = dev_priv->pg;
493
494 down_read(&pg->sem);
495 psb_mmu_remove_pfn_sequence(
496 psb_mmu_get_default_pd
497 (dev_priv->mmu),
498 pg->mmu_gatt_start,
499 dev_priv->vram_stolen_size >> PAGE_SHIFT);
500 up_read(&pg->sem);
501 psb_mmu_driver_takedown(dev_priv->mmu);
502 dev_priv->mmu = NULL;
503 }
504 psb_gtt_takedown(dev);
505 if (dev_priv->scratch_page) {
506 __free_page(dev_priv->scratch_page);
507 dev_priv->scratch_page = NULL;
508 }
509 if (dev_priv->vdc_reg) {
510 iounmap(dev_priv->vdc_reg);
511 dev_priv->vdc_reg = NULL;
512 }
513 if (dev_priv->sgx_reg) {
514 iounmap(dev_priv->sgx_reg);
515 dev_priv->sgx_reg = NULL;
516 }
517
518 kfree(dev_priv);
519 dev->dev_private = NULL;
520
521 /*destroy VBT data*/
522 psb_intel_destroy_bios(dev);
523 }
524
525 gma_power_uninit(dev);
526
527 return 0;
528 }
529
530
531 static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
532 {
533 struct drm_psb_private *dev_priv;
534 unsigned long resource_start;
535 struct psb_gtt *pg;
536 unsigned long irqflags;
537 int ret = -ENOMEM;
538 uint32_t tt_pages;
539 struct drm_connector *connector;
540 struct psb_intel_output *psb_intel_output;
541
542 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
543 if (dev_priv == NULL)
544 return -ENOMEM;
545
546 if (IS_MRST(dev))
547 dev_priv->num_pipe = 1;
548 else
549 dev_priv->num_pipe = 2;
550
551 dev_priv->dev = dev;
552
553 dev->dev_private = (void *) dev_priv;
554 dev_priv->chipset = chipset;
555
556 PSB_DEBUG_INIT("Mapping MMIO\n");
557 resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE);
558
559 dev_priv->vdc_reg =
560 ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE);
561 if (!dev_priv->vdc_reg)
562 goto out_err;
563
564 if (IS_MRST(dev))
565 dev_priv->sgx_reg = ioremap(resource_start + MRST_SGX_OFFSET,
566 PSB_SGX_SIZE);
567 else
568 dev_priv->sgx_reg = ioremap(resource_start + PSB_SGX_OFFSET,
569 PSB_SGX_SIZE);
570
571 if (!dev_priv->sgx_reg)
572 goto out_err;
573
574 if (IS_MRST(dev)) {
575 mrst_get_fuse_settings(dev);
576 mrst_get_vbt_data(dev_priv);
577 mid_get_pci_revID(dev_priv);
578 } else {
579 psb_get_core_freq(dev);
580 psb_intel_opregion_init(dev);
581 psb_intel_init_bios(dev);
582 }
583
584 /* Init OSPM support */
585 gma_power_init(dev);
586
587 ret = -ENOMEM;
588
589 dev_priv->scratch_page = alloc_page(GFP_DMA32 | __GFP_ZERO);
590 if (!dev_priv->scratch_page)
591 goto out_err;
592
593 set_pages_uc(dev_priv->scratch_page, 1);
594
595 ret = psb_gtt_init(dev, 0);
596 if (ret)
597 goto out_err;
598
599 dev_priv->mmu = psb_mmu_driver_init((void *)0,
600 drm_psb_trap_pagefaults, 0,
601 dev_priv);
602 if (!dev_priv->mmu)
603 goto out_err;
604
605 pg = dev_priv->pg;
606
607 tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
608 (pg->gatt_pages) : PSB_TT_PRIV0_PLIMIT;
609
610
611 dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0);
612 if (!dev_priv->pf_pd)
613 goto out_err;
614
615 psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0);
616 psb_mmu_set_pd_context(dev_priv->pf_pd, 1);
617
618 ret = psb_do_init(dev);
619 if (ret)
620 return ret;
621
622 PSB_WSGX32(0x20000000, PSB_CR_PDS_EXEC_BASE);
623 PSB_WSGX32(0x30000000, PSB_CR_BIF_3D_REQ_BASE);
624
625 /* igd_opregion_init(&dev_priv->opregion_dev); */
626 acpi_video_register();
627 if (dev_priv->lid_state)
628 psb_lid_timer_init(dev_priv);
629
630 ret = drm_vblank_init(dev, dev_priv->num_pipe);
631 if (ret)
632 goto out_err;
633
634 /*
635 * Install interrupt handlers prior to powering off SGX or else we will
636 * crash.
637 */
638 dev_priv->vdc_irq_mask = 0;
639 dev_priv->pipestat[0] = 0;
640 dev_priv->pipestat[1] = 0;
641 dev_priv->pipestat[2] = 0;
642 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
643 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
644 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
645 PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R);
646 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
647 if (drm_core_check_feature(dev, DRIVER_MODESET))
648 drm_irq_install(dev);
649
650 dev->vblank_disable_allowed = 1;
651
652 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
653
654 dev->driver->get_vblank_counter = psb_get_vblank_counter;
655
656 if (drm_psb_no_fb == 0) {
657 psb_modeset_init(dev);
658 psb_fbdev_init(dev);
659 drm_kms_helper_poll_init(dev);
660 }
661
662 /* Only add backlight support if we have LVDS output */
663 list_for_each_entry(connector, &dev->mode_config.connector_list,
664 head) {
665 psb_intel_output = to_psb_intel_output(connector);
666
667 switch (psb_intel_output->type) {
668 case INTEL_OUTPUT_LVDS:
669 ret = psb_backlight_init(dev);
670 break;
671 }
672 }
673
674 if (ret)
675 return ret;
676 #if 0
677 /*enable runtime pm at last*/
678 pm_runtime_enable(&dev->pdev->dev);
679 pm_runtime_set_active(&dev->pdev->dev);
680 #endif
681 /*Intel drm driver load is done, continue doing pvr load*/
682 DRM_DEBUG("Pvr driver load\n");
683 return 0;
684 out_err:
685 psb_driver_unload(dev);
686 return ret;
687 }
688
689 int psb_driver_device_is_agp(struct drm_device *dev)
690 {
691 return 0;
692 }
693
694
695 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
696 struct drm_file *file_priv)
697 {
698 struct drm_psb_private *dev_priv = psb_priv(dev);
699 struct drm_psb_sizes_arg *arg =
700 (struct drm_psb_sizes_arg *) data;
701
702 *arg = dev_priv->sizes;
703 return 0;
704 }
705
706 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
707 struct drm_file *file_priv)
708 {
709 uint32_t flags;
710 uint32_t obj_id;
711 struct drm_mode_object *obj;
712 struct drm_connector *connector;
713 struct drm_crtc *crtc;
714 struct drm_psb_dc_state_arg *arg =
715 (struct drm_psb_dc_state_arg *)data;
716
717 flags = arg->flags;
718 obj_id = arg->obj_id;
719
720 if (flags & PSB_DC_CRTC_MASK) {
721 obj = drm_mode_object_find(dev, obj_id,
722 DRM_MODE_OBJECT_CRTC);
723 if (!obj) {
724 DRM_DEBUG("Invalid CRTC object.\n");
725 return -EINVAL;
726 }
727
728 crtc = obj_to_crtc(obj);
729
730 mutex_lock(&dev->mode_config.mutex);
731 if (drm_helper_crtc_in_use(crtc)) {
732 if (flags & PSB_DC_CRTC_SAVE)
733 crtc->funcs->save(crtc);
734 else
735 crtc->funcs->restore(crtc);
736 }
737 mutex_unlock(&dev->mode_config.mutex);
738
739 return 0;
740 } else if (flags & PSB_DC_OUTPUT_MASK) {
741 obj = drm_mode_object_find(dev, obj_id,
742 DRM_MODE_OBJECT_CONNECTOR);
743 if (!obj) {
744 DRM_DEBUG("Invalid connector id.\n");
745 return -EINVAL;
746 }
747
748 connector = obj_to_connector(obj);
749 if (flags & PSB_DC_OUTPUT_SAVE)
750 connector->funcs->save(connector);
751 else
752 connector->funcs->restore(connector);
753
754 return 0;
755 }
756
757 DRM_DEBUG("Bad flags 0x%x\n", flags);
758 return -EINVAL;
759 }
760
761 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
762 struct drm_file *file_priv)
763 {
764 struct drm_psb_private *dev_priv = psb_priv(dev);
765 uint32_t *arg = data;
766 struct backlight_device bd;
767 dev_priv->blc_adj2 = *arg;
768
769 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
770 bd.props.brightness = psb_get_brightness(&bd);
771 psb_set_brightness(&bd);
772 #endif
773 return 0;
774 }
775
776 static int psb_adb_ioctl(struct drm_device *dev, void *data,
777 struct drm_file *file_priv)
778 {
779 struct drm_psb_private *dev_priv = psb_priv(dev);
780 uint32_t *arg = data;
781 struct backlight_device bd;
782 dev_priv->blc_adj1 = *arg;
783
784 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
785 bd.props.brightness = psb_get_brightness(&bd);
786 psb_set_brightness(&bd);
787 #endif
788 return 0;
789 }
790
791 /* return the current mode to the dpst module */
792 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
793 struct drm_file *file_priv)
794 {
795 struct drm_psb_private *dev_priv = psb_priv(dev);
796 uint32_t *arg = data;
797 uint32_t x;
798 uint32_t y;
799 uint32_t reg;
800
801 if (!gma_power_begin(dev, 0))
802 return -EIO;
803
804 reg = PSB_RVDC32(PIPEASRC);
805
806 gma_power_end(dev);
807
808 /* horizontal is the left 16 bits */
809 x = reg >> 16;
810 /* vertical is the right 16 bits */
811 y = reg & 0x0000ffff;
812
813 /* the values are the image size minus one */
814 x++;
815 y++;
816
817 *arg = (x << 16) | y;
818
819 return 0;
820 }
821 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
822 struct drm_file *file_priv)
823 {
824 struct drm_psb_dpst_lut_arg *lut_arg = data;
825 struct drm_mode_object *obj;
826 struct drm_crtc *crtc;
827 struct drm_connector *connector;
828 struct psb_intel_crtc *psb_intel_crtc;
829 int i = 0;
830 int32_t obj_id;
831
832 obj_id = lut_arg->output_id;
833 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_CONNECTOR);
834 if (!obj) {
835 DRM_DEBUG("Invalid Connector object.\n");
836 return -EINVAL;
837 }
838
839 connector = obj_to_connector(obj);
840 crtc = connector->encoder->crtc;
841 psb_intel_crtc = to_psb_intel_crtc(crtc);
842
843 for (i = 0; i < 256; i++)
844 psb_intel_crtc->lut_adj[i] = lut_arg->lut[i];
845
846 psb_intel_crtc_load_lut(crtc);
847
848 return 0;
849 }
850
851 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
852 struct drm_file *file_priv)
853 {
854 uint32_t obj_id;
855 uint16_t op;
856 struct drm_mode_modeinfo *umode;
857 struct drm_display_mode *mode = NULL;
858 struct drm_psb_mode_operation_arg *arg;
859 struct drm_mode_object *obj;
860 struct drm_connector *connector;
861 struct drm_framebuffer *drm_fb;
862 struct psb_framebuffer *psb_fb;
863 struct drm_connector_helper_funcs *connector_funcs;
864 int ret = 0;
865 int resp = MODE_OK;
866 struct drm_psb_private *dev_priv = psb_priv(dev);
867
868 arg = (struct drm_psb_mode_operation_arg *)data;
869 obj_id = arg->obj_id;
870 op = arg->operation;
871
872 switch (op) {
873 case PSB_MODE_OPERATION_SET_DC_BASE:
874 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_FB);
875 if (!obj) {
876 DRM_ERROR("Invalid FB id %d\n", obj_id);
877 return -EINVAL;
878 }
879
880 drm_fb = obj_to_fb(obj);
881 psb_fb = to_psb_fb(drm_fb);
882
883 if (gma_power_begin(dev, 0)) {
884 REG_WRITE(DSPASURF, psb_fb->gtt->offset);
885 REG_READ(DSPASURF);
886 gma_power_end(dev);
887 } else {
888 dev_priv->saveDSPASURF = psb_fb->gtt->offset;
889 }
890
891 return 0;
892 case PSB_MODE_OPERATION_MODE_VALID:
893 umode = &arg->mode;
894
895 mutex_lock(&dev->mode_config.mutex);
896
897 obj = drm_mode_object_find(dev, obj_id,
898 DRM_MODE_OBJECT_CONNECTOR);
899 if (!obj) {
900 ret = -EINVAL;
901 goto mode_op_out;
902 }
903
904 connector = obj_to_connector(obj);
905
906 mode = drm_mode_create(dev);
907 if (!mode) {
908 ret = -ENOMEM;
909 goto mode_op_out;
910 }
911
912 /* drm_crtc_convert_umode(mode, umode); */
913 {
914 mode->clock = umode->clock;
915 mode->hdisplay = umode->hdisplay;
916 mode->hsync_start = umode->hsync_start;
917 mode->hsync_end = umode->hsync_end;
918 mode->htotal = umode->htotal;
919 mode->hskew = umode->hskew;
920 mode->vdisplay = umode->vdisplay;
921 mode->vsync_start = umode->vsync_start;
922 mode->vsync_end = umode->vsync_end;
923 mode->vtotal = umode->vtotal;
924 mode->vscan = umode->vscan;
925 mode->vrefresh = umode->vrefresh;
926 mode->flags = umode->flags;
927 mode->type = umode->type;
928 strncpy(mode->name, umode->name, DRM_DISPLAY_MODE_LEN);
929 mode->name[DRM_DISPLAY_MODE_LEN-1] = 0;
930 }
931
932 connector_funcs = (struct drm_connector_helper_funcs *)
933 connector->helper_private;
934
935 if (connector_funcs->mode_valid) {
936 resp = connector_funcs->mode_valid(connector, mode);
937 arg->data = (void *)resp;
938 }
939
940 /*do some clean up work*/
941 if (mode)
942 drm_mode_destroy(dev, mode);
943 mode_op_out:
944 mutex_unlock(&dev->mode_config.mutex);
945 return ret;
946
947 default:
948 DRM_DEBUG("Unsupported psb mode operation");
949 return -EOPNOTSUPP;
950 }
951
952 return 0;
953 }
954
955 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
956 struct drm_file *file_priv)
957 {
958 struct drm_psb_private *dev_priv = psb_priv(dev);
959 struct drm_psb_stolen_memory_arg *arg = data;
960
961 arg->base = dev_priv->stolen_base;
962 arg->size = dev_priv->vram_stolen_size;
963
964 return 0;
965 }
966
967 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
968 struct drm_file *file_priv)
969 {
970 struct drm_psb_private *dev_priv = psb_priv(dev);
971 struct drm_psb_register_rw_arg *arg = data;
972 bool usage = arg->b_force_hw_on ? true : false;
973
974 if (arg->display_write_mask != 0) {
975 if (gma_power_begin(dev, usage)) {
976 if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
977 PSB_WVDC32(arg->display.pfit_controls,
978 PFIT_CONTROL);
979 if (arg->display_write_mask &
980 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
981 PSB_WVDC32(arg->display.pfit_autoscale_ratios,
982 PFIT_AUTO_RATIOS);
983 if (arg->display_write_mask &
984 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
985 PSB_WVDC32(
986 arg->display.pfit_programmed_scale_ratios,
987 PFIT_PGM_RATIOS);
988 if (arg->display_write_mask & REGRWBITS_PIPEASRC)
989 PSB_WVDC32(arg->display.pipeasrc,
990 PIPEASRC);
991 if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
992 PSB_WVDC32(arg->display.pipebsrc,
993 PIPEBSRC);
994 if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
995 PSB_WVDC32(arg->display.vtotal_a,
996 VTOTAL_A);
997 if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
998 PSB_WVDC32(arg->display.vtotal_b,
999 VTOTAL_B);
1000 gma_power_end(dev);
1001 } else {
1002 if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
1003 dev_priv->savePFIT_CONTROL =
1004 arg->display.pfit_controls;
1005 if (arg->display_write_mask &
1006 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1007 dev_priv->savePFIT_AUTO_RATIOS =
1008 arg->display.pfit_autoscale_ratios;
1009 if (arg->display_write_mask &
1010 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1011 dev_priv->savePFIT_PGM_RATIOS =
1012 arg->display.pfit_programmed_scale_ratios;
1013 if (arg->display_write_mask & REGRWBITS_PIPEASRC)
1014 dev_priv->savePIPEASRC = arg->display.pipeasrc;
1015 if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
1016 dev_priv->savePIPEBSRC = arg->display.pipebsrc;
1017 if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
1018 dev_priv->saveVTOTAL_A = arg->display.vtotal_a;
1019 if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
1020 dev_priv->saveVTOTAL_B = arg->display.vtotal_b;
1021 }
1022 }
1023
1024 if (arg->display_read_mask != 0) {
1025 if (gma_power_begin(dev, usage)) {
1026 if (arg->display_read_mask &
1027 REGRWBITS_PFIT_CONTROLS)
1028 arg->display.pfit_controls =
1029 PSB_RVDC32(PFIT_CONTROL);
1030 if (arg->display_read_mask &
1031 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1032 arg->display.pfit_autoscale_ratios =
1033 PSB_RVDC32(PFIT_AUTO_RATIOS);
1034 if (arg->display_read_mask &
1035 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1036 arg->display.pfit_programmed_scale_ratios =
1037 PSB_RVDC32(PFIT_PGM_RATIOS);
1038 if (arg->display_read_mask & REGRWBITS_PIPEASRC)
1039 arg->display.pipeasrc = PSB_RVDC32(PIPEASRC);
1040 if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
1041 arg->display.pipebsrc = PSB_RVDC32(PIPEBSRC);
1042 if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
1043 arg->display.vtotal_a = PSB_RVDC32(VTOTAL_A);
1044 if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
1045 arg->display.vtotal_b = PSB_RVDC32(VTOTAL_B);
1046 gma_power_end(dev);
1047 } else {
1048 if (arg->display_read_mask &
1049 REGRWBITS_PFIT_CONTROLS)
1050 arg->display.pfit_controls =
1051 dev_priv->savePFIT_CONTROL;
1052 if (arg->display_read_mask &
1053 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1054 arg->display.pfit_autoscale_ratios =
1055 dev_priv->savePFIT_AUTO_RATIOS;
1056 if (arg->display_read_mask &
1057 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1058 arg->display.pfit_programmed_scale_ratios =
1059 dev_priv->savePFIT_PGM_RATIOS;
1060 if (arg->display_read_mask & REGRWBITS_PIPEASRC)
1061 arg->display.pipeasrc = dev_priv->savePIPEASRC;
1062 if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
1063 arg->display.pipebsrc = dev_priv->savePIPEBSRC;
1064 if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
1065 arg->display.vtotal_a = dev_priv->saveVTOTAL_A;
1066 if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
1067 arg->display.vtotal_b = dev_priv->saveVTOTAL_B;
1068 }
1069 }
1070
1071 if (arg->overlay_write_mask != 0) {
1072 if (gma_power_begin(dev, usage)) {
1073 if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
1074 PSB_WVDC32(arg->overlay.OGAMC5, OV_OGAMC5);
1075 PSB_WVDC32(arg->overlay.OGAMC4, OV_OGAMC4);
1076 PSB_WVDC32(arg->overlay.OGAMC3, OV_OGAMC3);
1077 PSB_WVDC32(arg->overlay.OGAMC2, OV_OGAMC2);
1078 PSB_WVDC32(arg->overlay.OGAMC1, OV_OGAMC1);
1079 PSB_WVDC32(arg->overlay.OGAMC0, OV_OGAMC0);
1080 }
1081 if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
1082 PSB_WVDC32(arg->overlay.OGAMC5, OVC_OGAMC5);
1083 PSB_WVDC32(arg->overlay.OGAMC4, OVC_OGAMC4);
1084 PSB_WVDC32(arg->overlay.OGAMC3, OVC_OGAMC3);
1085 PSB_WVDC32(arg->overlay.OGAMC2, OVC_OGAMC2);
1086 PSB_WVDC32(arg->overlay.OGAMC1, OVC_OGAMC1);
1087 PSB_WVDC32(arg->overlay.OGAMC0, OVC_OGAMC0);
1088 }
1089
1090 if (arg->overlay_write_mask & OV_REGRWBITS_OVADD) {
1091 PSB_WVDC32(arg->overlay.OVADD, OV_OVADD);
1092
1093 if (arg->overlay.b_wait_vblank) {
1094 /* Wait for 20ms.*/
1095 unsigned long vblank_timeout = jiffies
1096 + HZ/50;
1097 uint32_t temp;
1098 while (time_before_eq(jiffies,
1099 vblank_timeout)) {
1100 temp = PSB_RVDC32(OV_DOVASTA);
1101 if ((temp & (0x1 << 31)) != 0)
1102 break;
1103 cpu_relax();
1104 }
1105 }
1106 }
1107 if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD) {
1108 PSB_WVDC32(arg->overlay.OVADD, OVC_OVADD);
1109 if (arg->overlay.b_wait_vblank) {
1110 /* Wait for 20ms.*/
1111 unsigned long vblank_timeout =
1112 jiffies + HZ/50;
1113 uint32_t temp;
1114 while (time_before_eq(jiffies,
1115 vblank_timeout)) {
1116 temp = PSB_RVDC32(OVC_DOVCSTA);
1117 if ((temp & (0x1 << 31)) != 0)
1118 break;
1119 cpu_relax();
1120 }
1121 }
1122 }
1123 gma_power_end(dev);
1124 } else {
1125 if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
1126 dev_priv->saveOV_OGAMC5 = arg->overlay.OGAMC5;
1127 dev_priv->saveOV_OGAMC4 = arg->overlay.OGAMC4;
1128 dev_priv->saveOV_OGAMC3 = arg->overlay.OGAMC3;
1129 dev_priv->saveOV_OGAMC2 = arg->overlay.OGAMC2;
1130 dev_priv->saveOV_OGAMC1 = arg->overlay.OGAMC1;
1131 dev_priv->saveOV_OGAMC0 = arg->overlay.OGAMC0;
1132 }
1133 if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
1134 dev_priv->saveOVC_OGAMC5 = arg->overlay.OGAMC5;
1135 dev_priv->saveOVC_OGAMC4 = arg->overlay.OGAMC4;
1136 dev_priv->saveOVC_OGAMC3 = arg->overlay.OGAMC3;
1137 dev_priv->saveOVC_OGAMC2 = arg->overlay.OGAMC2;
1138 dev_priv->saveOVC_OGAMC1 = arg->overlay.OGAMC1;
1139 dev_priv->saveOVC_OGAMC0 = arg->overlay.OGAMC0;
1140 }
1141 if (arg->overlay_write_mask & OV_REGRWBITS_OVADD)
1142 dev_priv->saveOV_OVADD = arg->overlay.OVADD;
1143 if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD)
1144 dev_priv->saveOVC_OVADD = arg->overlay.OVADD;
1145 }
1146 }
1147
1148 if (arg->overlay_read_mask != 0) {
1149 if (gma_power_begin(dev, usage)) {
1150 if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
1151 arg->overlay.OGAMC5 = PSB_RVDC32(OV_OGAMC5);
1152 arg->overlay.OGAMC4 = PSB_RVDC32(OV_OGAMC4);
1153 arg->overlay.OGAMC3 = PSB_RVDC32(OV_OGAMC3);
1154 arg->overlay.OGAMC2 = PSB_RVDC32(OV_OGAMC2);
1155 arg->overlay.OGAMC1 = PSB_RVDC32(OV_OGAMC1);
1156 arg->overlay.OGAMC0 = PSB_RVDC32(OV_OGAMC0);
1157 }
1158 if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
1159 arg->overlay.OGAMC5 = PSB_RVDC32(OVC_OGAMC5);
1160 arg->overlay.OGAMC4 = PSB_RVDC32(OVC_OGAMC4);
1161 arg->overlay.OGAMC3 = PSB_RVDC32(OVC_OGAMC3);
1162 arg->overlay.OGAMC2 = PSB_RVDC32(OVC_OGAMC2);
1163 arg->overlay.OGAMC1 = PSB_RVDC32(OVC_OGAMC1);
1164 arg->overlay.OGAMC0 = PSB_RVDC32(OVC_OGAMC0);
1165 }
1166 if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
1167 arg->overlay.OVADD = PSB_RVDC32(OV_OVADD);
1168 if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
1169 arg->overlay.OVADD = PSB_RVDC32(OVC_OVADD);
1170 gma_power_end(dev);
1171 } else {
1172 if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
1173 arg->overlay.OGAMC5 = dev_priv->saveOV_OGAMC5;
1174 arg->overlay.OGAMC4 = dev_priv->saveOV_OGAMC4;
1175 arg->overlay.OGAMC3 = dev_priv->saveOV_OGAMC3;
1176 arg->overlay.OGAMC2 = dev_priv->saveOV_OGAMC2;
1177 arg->overlay.OGAMC1 = dev_priv->saveOV_OGAMC1;
1178 arg->overlay.OGAMC0 = dev_priv->saveOV_OGAMC0;
1179 }
1180 if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
1181 arg->overlay.OGAMC5 = dev_priv->saveOVC_OGAMC5;
1182 arg->overlay.OGAMC4 = dev_priv->saveOVC_OGAMC4;
1183 arg->overlay.OGAMC3 = dev_priv->saveOVC_OGAMC3;
1184 arg->overlay.OGAMC2 = dev_priv->saveOVC_OGAMC2;
1185 arg->overlay.OGAMC1 = dev_priv->saveOVC_OGAMC1;
1186 arg->overlay.OGAMC0 = dev_priv->saveOVC_OGAMC0;
1187 }
1188 if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
1189 arg->overlay.OVADD = dev_priv->saveOV_OVADD;
1190 if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
1191 arg->overlay.OVADD = dev_priv->saveOVC_OVADD;
1192 }
1193 }
1194
1195 if (arg->sprite_enable_mask != 0) {
1196 if (gma_power_begin(dev, usage)) {
1197 PSB_WVDC32(0x1F3E, DSPARB);
1198 PSB_WVDC32(arg->sprite.dspa_control
1199 | PSB_RVDC32(DSPACNTR), DSPACNTR);
1200 PSB_WVDC32(arg->sprite.dspa_key_value, DSPAKEYVAL);
1201 PSB_WVDC32(arg->sprite.dspa_key_mask, DSPAKEYMASK);
1202 PSB_WVDC32(PSB_RVDC32(DSPASURF), DSPASURF);
1203 PSB_RVDC32(DSPASURF);
1204 PSB_WVDC32(arg->sprite.dspc_control, DSPCCNTR);
1205 PSB_WVDC32(arg->sprite.dspc_stride, DSPCSTRIDE);
1206 PSB_WVDC32(arg->sprite.dspc_position, DSPCPOS);
1207 PSB_WVDC32(arg->sprite.dspc_linear_offset, DSPCLINOFF);
1208 PSB_WVDC32(arg->sprite.dspc_size, DSPCSIZE);
1209 PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
1210 PSB_RVDC32(DSPCSURF);
1211 gma_power_end(dev);
1212 }
1213 }
1214
1215 if (arg->sprite_disable_mask != 0) {
1216 if (gma_power_begin(dev, usage)) {
1217 PSB_WVDC32(0x3F3E, DSPARB);
1218 PSB_WVDC32(0x0, DSPCCNTR);
1219 PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
1220 PSB_RVDC32(DSPCSURF);
1221 gma_power_end(dev);
1222 }
1223 }
1224
1225 if (arg->subpicture_enable_mask != 0) {
1226 if (gma_power_begin(dev, usage)) {
1227 uint32_t temp;
1228 if (arg->subpicture_enable_mask & REGRWBITS_DSPACNTR) {
1229 temp = PSB_RVDC32(DSPACNTR);
1230 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1231 temp &= ~DISPPLANE_BOTTOM;
1232 temp |= DISPPLANE_32BPP;
1233 PSB_WVDC32(temp, DSPACNTR);
1234
1235 temp = PSB_RVDC32(DSPABASE);
1236 PSB_WVDC32(temp, DSPABASE);
1237 PSB_RVDC32(DSPABASE);
1238 temp = PSB_RVDC32(DSPASURF);
1239 PSB_WVDC32(temp, DSPASURF);
1240 PSB_RVDC32(DSPASURF);
1241 }
1242 if (arg->subpicture_enable_mask & REGRWBITS_DSPBCNTR) {
1243 temp = PSB_RVDC32(DSPBCNTR);
1244 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1245 temp &= ~DISPPLANE_BOTTOM;
1246 temp |= DISPPLANE_32BPP;
1247 PSB_WVDC32(temp, DSPBCNTR);
1248
1249 temp = PSB_RVDC32(DSPBBASE);
1250 PSB_WVDC32(temp, DSPBBASE);
1251 PSB_RVDC32(DSPBBASE);
1252 temp = PSB_RVDC32(DSPBSURF);
1253 PSB_WVDC32(temp, DSPBSURF);
1254 PSB_RVDC32(DSPBSURF);
1255 }
1256 if (arg->subpicture_enable_mask & REGRWBITS_DSPCCNTR) {
1257 temp = PSB_RVDC32(DSPCCNTR);
1258 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1259 temp &= ~DISPPLANE_BOTTOM;
1260 temp |= DISPPLANE_32BPP;
1261 PSB_WVDC32(temp, DSPCCNTR);
1262
1263 temp = PSB_RVDC32(DSPCBASE);
1264 PSB_WVDC32(temp, DSPCBASE);
1265 PSB_RVDC32(DSPCBASE);
1266 temp = PSB_RVDC32(DSPCSURF);
1267 PSB_WVDC32(temp, DSPCSURF);
1268 PSB_RVDC32(DSPCSURF);
1269 }
1270 gma_power_end(dev);
1271 }
1272 }
1273
1274 if (arg->subpicture_disable_mask != 0) {
1275 if (gma_power_begin(dev, usage)) {
1276 uint32_t temp;
1277 if (arg->subpicture_disable_mask & REGRWBITS_DSPACNTR) {
1278 temp = PSB_RVDC32(DSPACNTR);
1279 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1280 temp |= DISPPLANE_32BPP_NO_ALPHA;
1281 PSB_WVDC32(temp, DSPACNTR);
1282
1283 temp = PSB_RVDC32(DSPABASE);
1284 PSB_WVDC32(temp, DSPABASE);
1285 PSB_RVDC32(DSPABASE);
1286 temp = PSB_RVDC32(DSPASURF);
1287 PSB_WVDC32(temp, DSPASURF);
1288 PSB_RVDC32(DSPASURF);
1289 }
1290 if (arg->subpicture_disable_mask & REGRWBITS_DSPBCNTR) {
1291 temp = PSB_RVDC32(DSPBCNTR);
1292 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1293 temp |= DISPPLANE_32BPP_NO_ALPHA;
1294 PSB_WVDC32(temp, DSPBCNTR);
1295
1296 temp = PSB_RVDC32(DSPBBASE);
1297 PSB_WVDC32(temp, DSPBBASE);
1298 PSB_RVDC32(DSPBBASE);
1299 temp = PSB_RVDC32(DSPBSURF);
1300 PSB_WVDC32(temp, DSPBSURF);
1301 PSB_RVDC32(DSPBSURF);
1302 }
1303 if (arg->subpicture_disable_mask & REGRWBITS_DSPCCNTR) {
1304 temp = PSB_RVDC32(DSPCCNTR);
1305 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1306 temp |= DISPPLANE_32BPP_NO_ALPHA;
1307 PSB_WVDC32(temp, DSPCCNTR);
1308
1309 temp = PSB_RVDC32(DSPCBASE);
1310 PSB_WVDC32(temp, DSPCBASE);
1311 PSB_RVDC32(DSPCBASE);
1312 temp = PSB_RVDC32(DSPCSURF);
1313 PSB_WVDC32(temp, DSPCSURF);
1314 PSB_RVDC32(DSPCSURF);
1315 }
1316 gma_power_end(dev);
1317 }
1318 }
1319
1320 return 0;
1321 }
1322
1323 static int psb_driver_open(struct drm_device *dev, struct drm_file *priv)
1324 {
1325 return 0;
1326 }
1327
1328 static void psb_driver_close(struct drm_device *dev, struct drm_file *priv)
1329 {
1330 }
1331
1332 static long psb_unlocked_ioctl(struct file *filp, unsigned int cmd,
1333 unsigned long arg)
1334 {
1335 struct drm_file *file_priv = filp->private_data;
1336 struct drm_device *dev = file_priv->minor->dev;
1337 struct drm_psb_private *dev_priv = dev->dev_private;
1338 static unsigned int runtime_allowed;
1339 unsigned int nr = DRM_IOCTL_NR(cmd);
1340
1341 DRM_DEBUG("cmd = %x, nr = %x\n", cmd, nr);
1342
1343 if (runtime_allowed == 1 && dev_priv->is_lvds_on) {
1344 runtime_allowed++;
1345 pm_runtime_allow(&dev->pdev->dev);
1346 dev_priv->rpm_enabled = 1;
1347 }
1348 return drm_ioctl(filp, cmd, arg);
1349
1350 /* FIXME: do we need to wrap the other side of this */
1351 }
1352
1353
1354 /* When a client dies:
1355 * - Check for and clean up flipped page state
1356 */
1357 void psb_driver_preclose(struct drm_device *dev, struct drm_file *priv)
1358 {
1359 }
1360
1361 static void psb_remove(struct pci_dev *pdev)
1362 {
1363 struct drm_device *dev = pci_get_drvdata(pdev);
1364 drm_put_dev(dev);
1365 }
1366
1367 static const struct dev_pm_ops psb_pm_ops = {
1368 .runtime_suspend = psb_runtime_suspend,
1369 .runtime_resume = psb_runtime_resume,
1370 .runtime_idle = psb_runtime_idle,
1371 };
1372
1373 static struct vm_operations_struct psb_gem_vm_ops = {
1374 .fault = psb_gem_fault,
1375 .open = drm_gem_vm_open,
1376 .close = drm_gem_vm_close,
1377 };
1378
1379 static struct drm_driver driver = {
1380 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | \
1381 DRIVER_IRQ_VBL | DRIVER_MODESET| DRIVER_GEM ,
1382 .load = psb_driver_load,
1383 .unload = psb_driver_unload,
1384
1385 .ioctls = psb_ioctls,
1386 .num_ioctls = DRM_ARRAY_SIZE(psb_ioctls),
1387 .device_is_agp = psb_driver_device_is_agp,
1388 .irq_preinstall = psb_irq_preinstall,
1389 .irq_postinstall = psb_irq_postinstall,
1390 .irq_uninstall = psb_irq_uninstall,
1391 .irq_handler = psb_irq_handler,
1392 .enable_vblank = psb_enable_vblank,
1393 .disable_vblank = psb_disable_vblank,
1394 .get_vblank_counter = psb_get_vblank_counter,
1395 .lastclose = psb_lastclose,
1396 .open = psb_driver_open,
1397 .preclose = psb_driver_preclose,
1398 .postclose = psb_driver_close,
1399 .reclaim_buffers = drm_core_reclaim_buffers,
1400
1401 .gem_init_object = psb_gem_init_object,
1402 .gem_free_object = psb_gem_free_object,
1403 .gem_vm_ops = &psb_gem_vm_ops,
1404 .dumb_create = psb_gem_dumb_create,
1405 .dumb_map_offset = psb_gem_dumb_map_gtt,
1406 .dumb_destroy = psb_gem_dumb_destroy,
1407
1408 .fops = {
1409 .owner = THIS_MODULE,
1410 .open = drm_open,
1411 .release = drm_release,
1412 .unlocked_ioctl = psb_unlocked_ioctl,
1413 .mmap = drm_gem_mmap,
1414 .poll = drm_poll,
1415 .fasync = drm_fasync,
1416 .read = drm_read,
1417 },
1418 .name = DRIVER_NAME,
1419 .desc = DRIVER_DESC,
1420 .date = PSB_DRM_DRIVER_DATE,
1421 .major = PSB_DRM_DRIVER_MAJOR,
1422 .minor = PSB_DRM_DRIVER_MINOR,
1423 .patchlevel = PSB_DRM_DRIVER_PATCHLEVEL
1424 };
1425
1426 static struct pci_driver psb_pci_driver = {
1427 .name = DRIVER_NAME,
1428 .id_table = pciidlist,
1429 .resume = gma_power_resume,
1430 .suspend = gma_power_suspend,
1431 .probe = psb_probe,
1432 .remove = psb_remove,
1433 #ifdef CONFIG_PM
1434 .driver.pm = &psb_pm_ops,
1435 #endif
1436 };
1437
1438 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1439 {
1440 /* MLD Added this from Inaky's patch */
1441 if (pci_enable_msi(pdev))
1442 DRM_ERROR("Enable MSI failed!\n");
1443 return drm_get_pci_dev(pdev, ent, &driver);
1444 }
1445
1446 static int __init psb_init(void)
1447 {
1448 return drm_pci_init(&driver, &psb_pci_driver);
1449 }
1450
1451 static void __exit psb_exit(void)
1452 {
1453 drm_pci_exit(&driver, &psb_pci_driver);
1454 }
1455
1456 late_initcall(psb_init);
1457 module_exit(psb_exit);
1458
1459 MODULE_AUTHOR("Alan Cox <alan@linux.intel.com> and others");
1460 MODULE_DESCRIPTION(DRIVER_DESC);
1461 MODULE_LICENSE("GPL");
x86 "subsystem" repository