drivers/pci/msi.h

   1 /*
   2  * Copyright (C) 2003-2004 Intel
   3  * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
   4  */
   5
   6 #ifndef MSI_H
   7 #define MSI_H
   8
   9 #include <asm/msi.h>
  10
  11 /*
  12  * Assume the maximum number of hot plug slots supported by the system is about
  13  * ten. The worstcase is that each of these slots is hot-added with a device,
  14  * which has two MSI/MSI-X capable functions. To avoid any MSI-X driver, which
  15  * attempts to request all available vectors, NR_HP_RESERVED_VECTORS is defined
  16  * as below to ensure at least one message is assigned to each detected MSI/
  17  * MSI-X device function.
  18  */
  19 #define NR_HP_RESERVED_VECTORS  20
  20
  21 extern int vector_irq[NR_VECTORS];
  22 extern void (*interrupt[NR_IRQS])(void);
  23 extern int pci_vector_resources(int last, int nr_released);
  24
  25 #ifdef CONFIG_SMP
  26 #define set_msi_irq_affinity    set_msi_affinity
  27 #else
  28 #define set_msi_irq_affinity    NULL
  29 #endif
  30
  31 /*
  32  * MSI-X Address Register
  33  */
  34 #define PCI_MSIX_FLAGS_QSIZE            0x7FF
  35 #define PCI_MSIX_FLAGS_ENABLE           (1 << 15)
  36 #define PCI_MSIX_FLAGS_BIRMASK          (7 << 0)
  37 #define PCI_MSIX_FLAGS_BITMASK          (1 << 0)
  38
  39 #define PCI_MSIX_ENTRY_SIZE                     16
  40 #define  PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET       0
  41 #define  PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET       4
  42 #define  PCI_MSIX_ENTRY_DATA_OFFSET             8
  43 #define  PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET      12
  44
  45 #define msi_control_reg(base)           (base + PCI_MSI_FLAGS)
  46 #define msi_lower_address_reg(base)     (base + PCI_MSI_ADDRESS_LO)
  47 #define msi_upper_address_reg(base)     (base + PCI_MSI_ADDRESS_HI)
  48 #define msi_data_reg(base, is64bit)     \
  49         ( (is64bit == 1) ? base+PCI_MSI_DATA_64 : base+PCI_MSI_DATA_32 )
  50 #define msi_mask_bits_reg(base, is64bit) \
  51         ( (is64bit == 1) ? base+PCI_MSI_MASK_BIT : base+PCI_MSI_MASK_BIT-4)
  52 #define msi_disable(control)            control &= ~PCI_MSI_FLAGS_ENABLE
  53 #define multi_msi_capable(control) \
  54         (1 << ((control & PCI_MSI_FLAGS_QMASK) >> 1))
  55 #define multi_msi_enable(control, num) \
  56         control |= (((num >> 1) << 4) & PCI_MSI_FLAGS_QSIZE);
  57 #define is_64bit_address(control)       (control & PCI_MSI_FLAGS_64BIT)
  58 #define is_mask_bit_support(control)    (control & PCI_MSI_FLAGS_MASKBIT)
  59 #define msi_enable(control, num) multi_msi_enable(control, num); \
  60         control |= PCI_MSI_FLAGS_ENABLE
  61
  62 #define msix_table_offset_reg(base)     (base + 0x04)
  63 #define msix_pba_offset_reg(base)       (base + 0x08)
  64 #define msix_enable(control)            control |= PCI_MSIX_FLAGS_ENABLE
  65 #define msix_disable(control)           control &= ~PCI_MSIX_FLAGS_ENABLE
  66 #define msix_table_size(control)        ((control & PCI_MSIX_FLAGS_QSIZE)+1)
  67 #define multi_msix_capable              msix_table_size
  68 #define msix_unmask(address)            (address & ~PCI_MSIX_FLAGS_BITMASK)
  69 #define msix_mask(address)              (address | PCI_MSIX_FLAGS_BITMASK)
  70 #define msix_is_pending(address)        (address & PCI_MSIX_FLAGS_PENDMASK)
  71
  72 /*
  73  * MSI Defined Data Structures
  74  */
  75 #define MSI_ADDRESS_HEADER              0xfee
  76 #define MSI_ADDRESS_HEADER_SHIFT        12
  77 #define MSI_ADDRESS_HEADER_MASK         0xfff000
  78 #define MSI_ADDRESS_DEST_ID_MASK        0xfff0000f
  79 #define MSI_TARGET_CPU_MASK             0xff
  80 #define MSI_DELIVERY_MODE               0
  81 #define MSI_LEVEL_MODE                  1       /* Edge always assert */
  82 #define MSI_TRIGGER_MODE                0       /* MSI is edge sensitive */
  83 #define MSI_PHYSICAL_MODE               0
  84 #define MSI_LOGICAL_MODE                1
  85 #define MSI_REDIRECTION_HINT_MODE       0
  86
  87 struct msg_data {
  88 #if defined(__LITTLE_ENDIAN_BITFIELD)
  89         __u32   vector          :  8;
  90         __u32   delivery_mode   :  3;   /* 000b: FIXED | 001b: lowest prior */
  91         __u32   reserved_1      :  3;
  92         __u32   level           :  1;   /* 0: deassert | 1: assert */
  93         __u32   trigger         :  1;   /* 0: edge | 1: level */
  94         __u32   reserved_2      : 16;
  95 #elif defined(__BIG_ENDIAN_BITFIELD)
  96         __u32   reserved_2      : 16;
  97         __u32   trigger         :  1;   /* 0: edge | 1: level */
  98         __u32   level           :  1;   /* 0: deassert | 1: assert */
  99         __u32   reserved_1      :  3;
 100         __u32   delivery_mode   :  3;   /* 000b: FIXED | 001b: lowest prior */
 101         __u32   vector          :  8;
 102 #else
 103 #error "Bitfield endianness not defined! Check your byteorder.h"
 104 #endif
 105 } __attribute__ ((packed));
 106
 107 struct msg_address {
 108         union {
 109                 struct {
 110 #if defined(__LITTLE_ENDIAN_BITFIELD)
 111                         __u32   reserved_1      :  2;
 112                         __u32   dest_mode       :  1;   /*0:physic | 1:logic */
 113                         __u32   redirection_hint:  1;   /*0: dedicated CPU
 114                                                           1: lowest priority */
 115                         __u32   reserved_2      :  4;
 116                         __u32   dest_id         : 24;   /* Destination ID */
 117 #elif defined(__BIG_ENDIAN_BITFIELD)
 118                         __u32   dest_id         : 24;   /* Destination ID */
 119                         __u32   reserved_2      :  4;
 120                         __u32   redirection_hint:  1;   /*0: dedicated CPU
 121                                                           1: lowest priority */
 122                         __u32   dest_mode       :  1;   /*0:physic | 1:logic */
 123                         __u32   reserved_1      :  2;
 124 #else
 125 #error "Bitfield endianness not defined! Check your byteorder.h"
 126 #endif
 127                 }u;
 128                 __u32  value;
 129         }lo_address;
 130         __u32   hi_address;
 131 } __attribute__ ((packed));
 132
 133 struct msi_desc {
 134         struct {
 135                 __u8    type    : 5;    /* {0: unused, 5h:MSI, 11h:MSI-X} */
 136                 __u8    maskbit : 1;    /* mask-pending bit supported ?   */
 137                 __u8    state   : 1;    /* {0: free, 1: busy}             */
 138                 __u8    reserved: 1;    /* reserved                       */
 139                 __u8    entry_nr;       /* specific enabled entry         */
 140                 __u8    default_vector; /* default pre-assigned vector    */
 141                 __u8    current_cpu;    /* current destination cpu        */
 142         }msi_attrib;
 143
 144         struct {
 145                 __u16   head;
 146                 __u16   tail;
 147         }link;
 148
 149         void __iomem *mask_base;
 150         struct pci_dev *dev;
 151 };
 152
 153 #endif /* MSI_H */