?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
libata: implement and use ops inheritance
[linux-2.6/x86.git] / drivers / ata / sata_promise.c
blobe09b975c973df0a6370d188d4880616264d9398b
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Mikael Pettersson <mikpe@it.uu.se>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2003-2004 Red Hat, Inc.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware information only available under NDA.
31 *
32 */
33
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/device.h>
42 #include <scsi/scsi.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
46 #include "sata_promise.h"
47
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "2.12"
50
51 enum {
52 PDC_MAX_PORTS = 4,
53 PDC_MMIO_BAR = 3,
54 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */
55
56 /* register offsets */
57 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
58 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
59 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
60 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
61 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
62 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
63 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
64 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
65 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
66 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
67 PDC_FLASH_CTL = 0x44, /* Flash control register */
68 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
69 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
70 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
71 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
72 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
73 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
74
75 /* PDC_GLOBAL_CTL bit definitions */
76 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
77 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
78 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
79 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
80 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
81 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
82 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
83 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
84 PDC_DRIVE_ERR = (1 << 21), /* drive error */
85 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
86 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
87 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
88 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
89 PDC2_ATA_DMA_CNT_ERR,
90 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
91 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
92 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
93 PDC1_ERR_MASK | PDC2_ERR_MASK,
94
95 board_2037x = 0, /* FastTrak S150 TX2plus */
96 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */
97 board_20319 = 2, /* FastTrak S150 TX4 */
98 board_20619 = 3, /* FastTrak TX4000 */
99 board_2057x = 4, /* SATAII150 Tx2plus */
100 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */
101 board_40518 = 6, /* SATAII150 Tx4 */
102
103 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
104
105 /* Sequence counter control registers bit definitions */
106 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
107
108 /* Feature register values */
109 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
110 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
111
112 /* Device/Head register values */
113 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
114
115 /* PDC_CTLSTAT bit definitions */
116 PDC_DMA_ENABLE = (1 << 7),
117 PDC_IRQ_DISABLE = (1 << 10),
118 PDC_RESET = (1 << 11), /* HDMA reset */
119
120 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
121 ATA_FLAG_MMIO |
122 ATA_FLAG_PIO_POLLING,
123
124 /* ap->flags bits */
125 PDC_FLAG_GEN_II = (1 << 24),
126 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */
127 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */
128 };
129
130 struct pdc_port_priv {
131 u8 *pkt;
132 dma_addr_t pkt_dma;
133 };
134
135 static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
136 static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
137 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
138 static int pdc_common_port_start(struct ata_port *ap);
139 static int pdc_sata_port_start(struct ata_port *ap);
140 static void pdc_qc_prep(struct ata_queued_cmd *qc);
141 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
142 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
143 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
144 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
145 static void pdc_irq_clear(struct ata_port *ap);
146 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
147 static void pdc_freeze(struct ata_port *ap);
148 static void pdc_sata_freeze(struct ata_port *ap);
149 static void pdc_thaw(struct ata_port *ap);
150 static void pdc_sata_thaw(struct ata_port *ap);
151 static void pdc_pata_error_handler(struct ata_port *ap);
152 static void pdc_sata_error_handler(struct ata_port *ap);
153 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
154 static int pdc_pata_cable_detect(struct ata_port *ap);
155 static int pdc_sata_cable_detect(struct ata_port *ap);
156
157 static struct scsi_host_template pdc_ata_sht = {
158 ATA_BASE_SHT(DRV_NAME),
159 .sg_tablesize = PDC_MAX_PRD,
160 .dma_boundary = ATA_DMA_BOUNDARY,
161 };
162
163 static const struct ata_port_operations pdc_common_ops = {
164 .inherits = &ata_sff_port_ops,
165
166 .tf_load = pdc_tf_load_mmio,
167 .exec_command = pdc_exec_command_mmio,
168 .check_atapi_dma = pdc_check_atapi_dma,
169 .qc_prep = pdc_qc_prep,
170 .qc_issue = pdc_qc_issue_prot,
171 .irq_clear = pdc_irq_clear,
172
173 .post_internal_cmd = pdc_post_internal_cmd,
174 };
175
176 static struct ata_port_operations pdc_sata_ops = {
177 .inherits = &pdc_common_ops,
178 .cable_detect = pdc_sata_cable_detect,
179 .freeze = pdc_sata_freeze,
180 .thaw = pdc_sata_thaw,
181 .error_handler = pdc_sata_error_handler,
182 .scr_read = pdc_sata_scr_read,
183 .scr_write = pdc_sata_scr_write,
184 .port_start = pdc_sata_port_start,
185 };
186
187 /* First-generation chips need a more restrictive ->check_atapi_dma op */
188 static struct ata_port_operations pdc_old_sata_ops = {
189 .inherits = &pdc_sata_ops,
190 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
191 };
192
193 static struct ata_port_operations pdc_pata_ops = {
194 .inherits = &pdc_common_ops,
195 .cable_detect = pdc_pata_cable_detect,
196 .freeze = pdc_freeze,
197 .thaw = pdc_thaw,
198 .error_handler = pdc_pata_error_handler,
199 .port_start = pdc_common_port_start,
200 };
201
202 static const struct ata_port_info pdc_port_info[] = {
203 [board_2037x] =
204 {
205 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
206 PDC_FLAG_SATA_PATA,
207 .pio_mask = 0x1f, /* pio0-4 */
208 .mwdma_mask = 0x07, /* mwdma0-2 */
209 .udma_mask = ATA_UDMA6,
210 .port_ops = &pdc_old_sata_ops,
211 },
212
213 [board_2037x_pata] =
214 {
215 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
216 .pio_mask = 0x1f, /* pio0-4 */
217 .mwdma_mask = 0x07, /* mwdma0-2 */
218 .udma_mask = ATA_UDMA6,
219 .port_ops = &pdc_pata_ops,
220 },
221
222 [board_20319] =
223 {
224 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
225 PDC_FLAG_4_PORTS,
226 .pio_mask = 0x1f, /* pio0-4 */
227 .mwdma_mask = 0x07, /* mwdma0-2 */
228 .udma_mask = ATA_UDMA6,
229 .port_ops = &pdc_old_sata_ops,
230 },
231
232 [board_20619] =
233 {
234 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
235 PDC_FLAG_4_PORTS,
236 .pio_mask = 0x1f, /* pio0-4 */
237 .mwdma_mask = 0x07, /* mwdma0-2 */
238 .udma_mask = ATA_UDMA6,
239 .port_ops = &pdc_pata_ops,
240 },
241
242 [board_2057x] =
243 {
244 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
245 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
246 .pio_mask = 0x1f, /* pio0-4 */
247 .mwdma_mask = 0x07, /* mwdma0-2 */
248 .udma_mask = ATA_UDMA6,
249 .port_ops = &pdc_sata_ops,
250 },
251
252 [board_2057x_pata] =
253 {
254 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
255 PDC_FLAG_GEN_II,
256 .pio_mask = 0x1f, /* pio0-4 */
257 .mwdma_mask = 0x07, /* mwdma0-2 */
258 .udma_mask = ATA_UDMA6,
259 .port_ops = &pdc_pata_ops,
260 },
261
262 [board_40518] =
263 {
264 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
265 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
266 .pio_mask = 0x1f, /* pio0-4 */
267 .mwdma_mask = 0x07, /* mwdma0-2 */
268 .udma_mask = ATA_UDMA6,
269 .port_ops = &pdc_sata_ops,
270 },
271 };
272
273 static const struct pci_device_id pdc_ata_pci_tbl[] = {
274 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
275 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
276 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
277 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
278 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
279 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
280 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
281 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
282 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
283 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
284
285 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
286 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
287 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
288 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
289 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
290 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
291
292 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
293
294 { } /* terminate list */
295 };
296
297 static struct pci_driver pdc_ata_pci_driver = {
298 .name = DRV_NAME,
299 .id_table = pdc_ata_pci_tbl,
300 .probe = pdc_ata_init_one,
301 .remove = ata_pci_remove_one,
302 };
303
304 static int pdc_common_port_start(struct ata_port *ap)
305 {
306 struct device *dev = ap->host->dev;
307 struct pdc_port_priv *pp;
308 int rc;
309
310 rc = ata_port_start(ap);
311 if (rc)
312 return rc;
313
314 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
315 if (!pp)
316 return -ENOMEM;
317
318 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
319 if (!pp->pkt)
320 return -ENOMEM;
321
322 ap->private_data = pp;
323
324 return 0;
325 }
326
327 static int pdc_sata_port_start(struct ata_port *ap)
328 {
329 int rc;
330
331 rc = pdc_common_port_start(ap);
332 if (rc)
333 return rc;
334
335 /* fix up PHYMODE4 align timing */
336 if (ap->flags & PDC_FLAG_GEN_II) {
337 void __iomem *mmio = ap->ioaddr.scr_addr;
338 unsigned int tmp;
339
340 tmp = readl(mmio + 0x014);
341 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
342 writel(tmp, mmio + 0x014);
343 }
344
345 return 0;
346 }
347
348 static void pdc_reset_port(struct ata_port *ap)
349 {
350 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
351 unsigned int i;
352 u32 tmp;
353
354 for (i = 11; i > 0; i--) {
355 tmp = readl(mmio);
356 if (tmp & PDC_RESET)
357 break;
358
359 udelay(100);
360
361 tmp |= PDC_RESET;
362 writel(tmp, mmio);
363 }
364
365 tmp &= ~PDC_RESET;
366 writel(tmp, mmio);
367 readl(mmio); /* flush */
368 }
369
370 static int pdc_pata_cable_detect(struct ata_port *ap)
371 {
372 u8 tmp;
373 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
374
375 tmp = readb(mmio);
376 if (tmp & 0x01)
377 return ATA_CBL_PATA40;
378 return ATA_CBL_PATA80;
379 }
380
381 static int pdc_sata_cable_detect(struct ata_port *ap)
382 {
383 return ATA_CBL_SATA;
384 }
385
386 static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
387 {
388 if (sc_reg > SCR_CONTROL)
389 return -EINVAL;
390 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4));
391 return 0;
392 }
393
394 static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
395 {
396 if (sc_reg > SCR_CONTROL)
397 return -EINVAL;
398 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
399 return 0;
400 }
401
402 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
403 {
404 struct ata_port *ap = qc->ap;
405 dma_addr_t sg_table = ap->prd_dma;
406 unsigned int cdb_len = qc->dev->cdb_len;
407 u8 *cdb = qc->cdb;
408 struct pdc_port_priv *pp = ap->private_data;
409 u8 *buf = pp->pkt;
410 u32 *buf32 = (u32 *) buf;
411 unsigned int dev_sel, feature;
412
413 /* set control bits (byte 0), zero delay seq id (byte 3),
414 * and seq id (byte 2)
415 */
416 switch (qc->tf.protocol) {
417 case ATAPI_PROT_DMA:
418 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
419 buf32[0] = cpu_to_le32(PDC_PKT_READ);
420 else
421 buf32[0] = 0;
422 break;
423 case ATAPI_PROT_NODATA:
424 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
425 break;
426 default:
427 BUG();
428 break;
429 }
430 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
431 buf32[2] = 0; /* no next-packet */
432
433 /* select drive */
434 if (sata_scr_valid(&ap->link))
435 dev_sel = PDC_DEVICE_SATA;
436 else
437 dev_sel = qc->tf.device;
438
439 buf[12] = (1 << 5) | ATA_REG_DEVICE;
440 buf[13] = dev_sel;
441 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
442 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
443
444 buf[16] = (1 << 5) | ATA_REG_NSECT;
445 buf[17] = qc->tf.nsect;
446 buf[18] = (1 << 5) | ATA_REG_LBAL;
447 buf[19] = qc->tf.lbal;
448
449 /* set feature and byte counter registers */
450 if (qc->tf.protocol != ATAPI_PROT_DMA)
451 feature = PDC_FEATURE_ATAPI_PIO;
452 else
453 feature = PDC_FEATURE_ATAPI_DMA;
454
455 buf[20] = (1 << 5) | ATA_REG_FEATURE;
456 buf[21] = feature;
457 buf[22] = (1 << 5) | ATA_REG_BYTEL;
458 buf[23] = qc->tf.lbam;
459 buf[24] = (1 << 5) | ATA_REG_BYTEH;
460 buf[25] = qc->tf.lbah;
461
462 /* send ATAPI packet command 0xA0 */
463 buf[26] = (1 << 5) | ATA_REG_CMD;
464 buf[27] = qc->tf.command;
465
466 /* select drive and check DRQ */
467 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
468 buf[29] = dev_sel;
469
470 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
471 BUG_ON(cdb_len & ~0x1E);
472
473 /* append the CDB as the final part */
474 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
475 memcpy(buf+31, cdb, cdb_len);
476 }
477
478 /**
479 * pdc_fill_sg - Fill PCI IDE PRD table
480 * @qc: Metadata associated with taskfile to be transferred
481 *
482 * Fill PCI IDE PRD (scatter-gather) table with segments
483 * associated with the current disk command.
484 * Make sure hardware does not choke on it.
485 *
486 * LOCKING:
487 * spin_lock_irqsave(host lock)
488 *
489 */
490 static void pdc_fill_sg(struct ata_queued_cmd *qc)
491 {
492 struct ata_port *ap = qc->ap;
493 struct scatterlist *sg;
494 const u32 SG_COUNT_ASIC_BUG = 41*4;
495 unsigned int si, idx;
496 u32 len;
497
498 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
499 return;
500
501 idx = 0;
502 for_each_sg(qc->sg, sg, qc->n_elem, si) {
503 u32 addr, offset;
504 u32 sg_len;
505
506 /* determine if physical DMA addr spans 64K boundary.
507 * Note h/w doesn't support 64-bit, so we unconditionally
508 * truncate dma_addr_t to u32.
509 */
510 addr = (u32) sg_dma_address(sg);
511 sg_len = sg_dma_len(sg);
512
513 while (sg_len) {
514 offset = addr & 0xffff;
515 len = sg_len;
516 if ((offset + sg_len) > 0x10000)
517 len = 0x10000 - offset;
518
519 ap->prd[idx].addr = cpu_to_le32(addr);
520 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
521 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
522
523 idx++;
524 sg_len -= len;
525 addr += len;
526 }
527 }
528
529 len = le32_to_cpu(ap->prd[idx - 1].flags_len);
530
531 if (len > SG_COUNT_ASIC_BUG) {
532 u32 addr;
533
534 VPRINTK("Splitting last PRD.\n");
535
536 addr = le32_to_cpu(ap->prd[idx - 1].addr);
537 ap->prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
538 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
539
540 addr = addr + len - SG_COUNT_ASIC_BUG;
541 len = SG_COUNT_ASIC_BUG;
542 ap->prd[idx].addr = cpu_to_le32(addr);
543 ap->prd[idx].flags_len = cpu_to_le32(len);
544 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
545
546 idx++;
547 }
548
549 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
550 }
551
552 static void pdc_qc_prep(struct ata_queued_cmd *qc)
553 {
554 struct pdc_port_priv *pp = qc->ap->private_data;
555 unsigned int i;
556
557 VPRINTK("ENTER\n");
558
559 switch (qc->tf.protocol) {
560 case ATA_PROT_DMA:
561 pdc_fill_sg(qc);
562 /* fall through */
563
564 case ATA_PROT_NODATA:
565 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
566 qc->dev->devno, pp->pkt);
567
568 if (qc->tf.flags & ATA_TFLAG_LBA48)
569 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
570 else
571 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
572
573 pdc_pkt_footer(&qc->tf, pp->pkt, i);
574 break;
575
576 case ATAPI_PROT_PIO:
577 pdc_fill_sg(qc);
578 break;
579
580 case ATAPI_PROT_DMA:
581 pdc_fill_sg(qc);
582 /*FALLTHROUGH*/
583 case ATAPI_PROT_NODATA:
584 pdc_atapi_pkt(qc);
585 break;
586
587 default:
588 break;
589 }
590 }
591
592 static int pdc_is_sataii_tx4(unsigned long flags)
593 {
594 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
595 return (flags & mask) == mask;
596 }
597
598 static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
599 int is_sataii_tx4)
600 {
601 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
602 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
603 }
604
605 static unsigned int pdc_sata_nr_ports(const struct ata_port *ap)
606 {
607 return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2;
608 }
609
610 static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap)
611 {
612 const struct ata_host *host = ap->host;
613 unsigned int nr_ports = pdc_sata_nr_ports(ap);
614 unsigned int i;
615
616 for(i = 0; i < nr_ports && host->ports[i] != ap; ++i)
617 ;
618 BUG_ON(i >= nr_ports);
619 return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags));
620 }
621
622 static unsigned int pdc_sata_hotplug_offset(const struct ata_port *ap)
623 {
624 return (ap->flags & PDC_FLAG_GEN_II) ? PDC2_SATA_PLUG_CSR : PDC_SATA_PLUG_CSR;
625 }
626
627 static void pdc_freeze(struct ata_port *ap)
628 {
629 void __iomem *mmio = ap->ioaddr.cmd_addr;
630 u32 tmp;
631
632 tmp = readl(mmio + PDC_CTLSTAT);
633 tmp |= PDC_IRQ_DISABLE;
634 tmp &= ~PDC_DMA_ENABLE;
635 writel(tmp, mmio + PDC_CTLSTAT);
636 readl(mmio + PDC_CTLSTAT); /* flush */
637 }
638
639 static void pdc_sata_freeze(struct ata_port *ap)
640 {
641 struct ata_host *host = ap->host;
642 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
643 unsigned int hotplug_offset = pdc_sata_hotplug_offset(ap);
644 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
645 u32 hotplug_status;
646
647 /* Disable hotplug events on this port.
648 *
649 * Locking:
650 * 1) hotplug register accesses must be serialised via host->lock
651 * 2) ap->lock == &ap->host->lock
652 * 3) ->freeze() and ->thaw() are called with ap->lock held
653 */
654 hotplug_status = readl(host_mmio + hotplug_offset);
655 hotplug_status |= 0x11 << (ata_no + 16);
656 writel(hotplug_status, host_mmio + hotplug_offset);
657 readl(host_mmio + hotplug_offset); /* flush */
658
659 pdc_freeze(ap);
660 }
661
662 static void pdc_thaw(struct ata_port *ap)
663 {
664 void __iomem *mmio = ap->ioaddr.cmd_addr;
665 u32 tmp;
666
667 /* clear IRQ */
668 readl(mmio + PDC_INT_SEQMASK);
669
670 /* turn IRQ back on */
671 tmp = readl(mmio + PDC_CTLSTAT);
672 tmp &= ~PDC_IRQ_DISABLE;
673 writel(tmp, mmio + PDC_CTLSTAT);
674 readl(mmio + PDC_CTLSTAT); /* flush */
675 }
676
677 static void pdc_sata_thaw(struct ata_port *ap)
678 {
679 struct ata_host *host = ap->host;
680 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
681 unsigned int hotplug_offset = pdc_sata_hotplug_offset(ap);
682 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
683 u32 hotplug_status;
684
685 pdc_thaw(ap);
686
687 /* Enable hotplug events on this port.
688 * Locking: see pdc_sata_freeze().
689 */
690 hotplug_status = readl(host_mmio + hotplug_offset);
691 hotplug_status |= 0x11 << ata_no;
692 hotplug_status &= ~(0x11 << (ata_no + 16));
693 writel(hotplug_status, host_mmio + hotplug_offset);
694 readl(host_mmio + hotplug_offset); /* flush */
695 }
696
697 static void pdc_common_error_handler(struct ata_port *ap, ata_reset_fn_t hardreset)
698 {
699 if (!(ap->pflags & ATA_PFLAG_FROZEN))
700 pdc_reset_port(ap);
701
702 /* perform recovery */
703 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
704 ata_std_postreset);
705 }
706
707 static void pdc_pata_error_handler(struct ata_port *ap)
708 {
709 pdc_common_error_handler(ap, NULL);
710 }
711
712 static void pdc_sata_error_handler(struct ata_port *ap)
713 {
714 pdc_common_error_handler(ap, sata_std_hardreset);
715 }
716
717 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
718 {
719 struct ata_port *ap = qc->ap;
720
721 /* make DMA engine forget about the failed command */
722 if (qc->flags & ATA_QCFLAG_FAILED)
723 pdc_reset_port(ap);
724 }
725
726 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
727 u32 port_status, u32 err_mask)
728 {
729 struct ata_eh_info *ehi = &ap->link.eh_info;
730 unsigned int ac_err_mask = 0;
731
732 ata_ehi_clear_desc(ehi);
733 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
734 port_status &= err_mask;
735
736 if (port_status & PDC_DRIVE_ERR)
737 ac_err_mask |= AC_ERR_DEV;
738 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
739 ac_err_mask |= AC_ERR_HSM;
740 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
741 ac_err_mask |= AC_ERR_ATA_BUS;
742 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
743 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
744 ac_err_mask |= AC_ERR_HOST_BUS;
745
746 if (sata_scr_valid(&ap->link)) {
747 u32 serror;
748
749 pdc_sata_scr_read(ap, SCR_ERROR, &serror);
750 ehi->serror |= serror;
751 }
752
753 qc->err_mask |= ac_err_mask;
754
755 pdc_reset_port(ap);
756
757 ata_port_abort(ap);
758 }
759
760 static inline unsigned int pdc_host_intr(struct ata_port *ap,
761 struct ata_queued_cmd *qc)
762 {
763 unsigned int handled = 0;
764 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
765 u32 port_status, err_mask;
766
767 err_mask = PDC_ERR_MASK;
768 if (ap->flags & PDC_FLAG_GEN_II)
769 err_mask &= ~PDC1_ERR_MASK;
770 else
771 err_mask &= ~PDC2_ERR_MASK;
772 port_status = readl(port_mmio + PDC_GLOBAL_CTL);
773 if (unlikely(port_status & err_mask)) {
774 pdc_error_intr(ap, qc, port_status, err_mask);
775 return 1;
776 }
777
778 switch (qc->tf.protocol) {
779 case ATA_PROT_DMA:
780 case ATA_PROT_NODATA:
781 case ATAPI_PROT_DMA:
782 case ATAPI_PROT_NODATA:
783 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
784 ata_qc_complete(qc);
785 handled = 1;
786 break;
787
788 default:
789 ap->stats.idle_irq++;
790 break;
791 }
792
793 return handled;
794 }
795
796 static void pdc_irq_clear(struct ata_port *ap)
797 {
798 struct ata_host *host = ap->host;
799 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
800
801 readl(mmio + PDC_INT_SEQMASK);
802 }
803
804 static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
805 {
806 struct ata_host *host = dev_instance;
807 struct ata_port *ap;
808 u32 mask = 0;
809 unsigned int i, tmp;
810 unsigned int handled = 0;
811 void __iomem *mmio_base;
812 unsigned int hotplug_offset, ata_no;
813 u32 hotplug_status;
814 int is_sataii_tx4;
815
816 VPRINTK("ENTER\n");
817
818 if (!host || !host->iomap[PDC_MMIO_BAR]) {
819 VPRINTK("QUICK EXIT\n");
820 return IRQ_NONE;
821 }
822
823 mmio_base = host->iomap[PDC_MMIO_BAR];
824
825 spin_lock(&host->lock);
826
827 /* read and clear hotplug flags for all ports */
828 if (host->ports[0]->flags & PDC_FLAG_GEN_II)
829 hotplug_offset = PDC2_SATA_PLUG_CSR;
830 else
831 hotplug_offset = PDC_SATA_PLUG_CSR;
832 hotplug_status = readl(mmio_base + hotplug_offset);
833 if (hotplug_status & 0xff)
834 writel(hotplug_status | 0xff, mmio_base + hotplug_offset);
835 hotplug_status &= 0xff; /* clear uninteresting bits */
836
837 /* reading should also clear interrupts */
838 mask = readl(mmio_base + PDC_INT_SEQMASK);
839
840 if (mask == 0xffffffff && hotplug_status == 0) {
841 VPRINTK("QUICK EXIT 2\n");
842 goto done_irq;
843 }
844
845 mask &= 0xffff; /* only 16 tags possible */
846 if (mask == 0 && hotplug_status == 0) {
847 VPRINTK("QUICK EXIT 3\n");
848 goto done_irq;
849 }
850
851 writel(mask, mmio_base + PDC_INT_SEQMASK);
852
853 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
854
855 for (i = 0; i < host->n_ports; i++) {
856 VPRINTK("port %u\n", i);
857 ap = host->ports[i];
858
859 /* check for a plug or unplug event */
860 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
861 tmp = hotplug_status & (0x11 << ata_no);
862 if (tmp && ap &&
863 !(ap->flags & ATA_FLAG_DISABLED)) {
864 struct ata_eh_info *ehi = &ap->link.eh_info;
865 ata_ehi_clear_desc(ehi);
866 ata_ehi_hotplugged(ehi);
867 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
868 ata_port_freeze(ap);
869 ++handled;
870 continue;
871 }
872
873 /* check for a packet interrupt */
874 tmp = mask & (1 << (i + 1));
875 if (tmp && ap &&
876 !(ap->flags & ATA_FLAG_DISABLED)) {
877 struct ata_queued_cmd *qc;
878
879 qc = ata_qc_from_tag(ap, ap->link.active_tag);
880 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
881 handled += pdc_host_intr(ap, qc);
882 }
883 }
884
885 VPRINTK("EXIT\n");
886
887 done_irq:
888 spin_unlock(&host->lock);
889 return IRQ_RETVAL(handled);
890 }
891
892 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
893 {
894 struct ata_port *ap = qc->ap;
895 struct pdc_port_priv *pp = ap->private_data;
896 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
897 unsigned int port_no = ap->port_no;
898 u8 seq = (u8) (port_no + 1);
899
900 VPRINTK("ENTER, ap %p\n", ap);
901
902 writel(0x00000001, mmio + (seq * 4));
903 readl(mmio + (seq * 4)); /* flush */
904
905 pp->pkt[2] = seq;
906 wmb(); /* flush PRD, pkt writes */
907 writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
908 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
909 }
910
911 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
912 {
913 switch (qc->tf.protocol) {
914 case ATAPI_PROT_NODATA:
915 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
916 break;
917 /*FALLTHROUGH*/
918 case ATA_PROT_NODATA:
919 if (qc->tf.flags & ATA_TFLAG_POLLING)
920 break;
921 /*FALLTHROUGH*/
922 case ATAPI_PROT_DMA:
923 case ATA_PROT_DMA:
924 pdc_packet_start(qc);
925 return 0;
926
927 default:
928 break;
929 }
930
931 return ata_qc_issue_prot(qc);
932 }
933
934 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
935 {
936 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
937 ata_tf_load(ap, tf);
938 }
939
940 static void pdc_exec_command_mmio(struct ata_port *ap,
941 const struct ata_taskfile *tf)
942 {
943 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
944 ata_exec_command(ap, tf);
945 }
946
947 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
948 {
949 u8 *scsicmd = qc->scsicmd->cmnd;
950 int pio = 1; /* atapi dma off by default */
951
952 /* Whitelist commands that may use DMA. */
953 switch (scsicmd[0]) {
954 case WRITE_12:
955 case WRITE_10:
956 case WRITE_6:
957 case READ_12:
958 case READ_10:
959 case READ_6:
960 case 0xad: /* READ_DVD_STRUCTURE */
961 case 0xbe: /* READ_CD */
962 pio = 0;
963 }
964 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
965 if (scsicmd[0] == WRITE_10) {
966 unsigned int lba =
967 (scsicmd[2] << 24) |
968 (scsicmd[3] << 16) |
969 (scsicmd[4] << 8) |
970 scsicmd[5];
971 if (lba >= 0xFFFF4FA2)
972 pio = 1;
973 }
974 return pio;
975 }
976
977 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
978 {
979 /* First generation chips cannot use ATAPI DMA on SATA ports */
980 return 1;
981 }
982
983 static void pdc_ata_setup_port(struct ata_port *ap,
984 void __iomem *base, void __iomem *scr_addr)
985 {
986 ap->ioaddr.cmd_addr = base;
987 ap->ioaddr.data_addr = base;
988 ap->ioaddr.feature_addr =
989 ap->ioaddr.error_addr = base + 0x4;
990 ap->ioaddr.nsect_addr = base + 0x8;
991 ap->ioaddr.lbal_addr = base + 0xc;
992 ap->ioaddr.lbam_addr = base + 0x10;
993 ap->ioaddr.lbah_addr = base + 0x14;
994 ap->ioaddr.device_addr = base + 0x18;
995 ap->ioaddr.command_addr =
996 ap->ioaddr.status_addr = base + 0x1c;
997 ap->ioaddr.altstatus_addr =
998 ap->ioaddr.ctl_addr = base + 0x38;
999 ap->ioaddr.scr_addr = scr_addr;
1000 }
1001
1002 static void pdc_host_init(struct ata_host *host)
1003 {
1004 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1005 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
1006 int hotplug_offset;
1007 u32 tmp;
1008
1009 if (is_gen2)
1010 hotplug_offset = PDC2_SATA_PLUG_CSR;
1011 else
1012 hotplug_offset = PDC_SATA_PLUG_CSR;
1013
1014 /*
1015 * Except for the hotplug stuff, this is voodoo from the
1016 * Promise driver. Label this entire section
1017 * "TODO: figure out why we do this"
1018 */
1019
1020 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
1021 tmp = readl(mmio + PDC_FLASH_CTL);
1022 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
1023 if (!is_gen2)
1024 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
1025 writel(tmp, mmio + PDC_FLASH_CTL);
1026
1027 /* clear plug/unplug flags for all ports */
1028 tmp = readl(mmio + hotplug_offset);
1029 writel(tmp | 0xff, mmio + hotplug_offset);
1030
1031 /* unmask plug/unplug ints */
1032 tmp = readl(mmio + hotplug_offset);
1033 writel(tmp & ~0xff0000, mmio + hotplug_offset);
1034
1035 /* don't initialise TBG or SLEW on 2nd generation chips */
1036 if (is_gen2)
1037 return;
1038
1039 /* reduce TBG clock to 133 Mhz. */
1040 tmp = readl(mmio + PDC_TBG_MODE);
1041 tmp &= ~0x30000; /* clear bit 17, 16*/
1042 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
1043 writel(tmp, mmio + PDC_TBG_MODE);
1044
1045 readl(mmio + PDC_TBG_MODE); /* flush */
1046 msleep(10);
1047
1048 /* adjust slew rate control register. */
1049 tmp = readl(mmio + PDC_SLEW_CTL);
1050 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
1051 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
1052 writel(tmp, mmio + PDC_SLEW_CTL);
1053 }
1054
1055 static int pdc_ata_init_one(struct pci_dev *pdev,
1056 const struct pci_device_id *ent)
1057 {
1058 static int printed_version;
1059 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
1060 const struct ata_port_info *ppi[PDC_MAX_PORTS];
1061 struct ata_host *host;
1062 void __iomem *base;
1063 int n_ports, i, rc;
1064 int is_sataii_tx4;
1065
1066 if (!printed_version++)
1067 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1068
1069 /* enable and acquire resources */
1070 rc = pcim_enable_device(pdev);
1071 if (rc)
1072 return rc;
1073
1074 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
1075 if (rc == -EBUSY)
1076 pcim_pin_device(pdev);
1077 if (rc)
1078 return rc;
1079 base = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
1080
1081 /* determine port configuration and setup host */
1082 n_ports = 2;
1083 if (pi->flags & PDC_FLAG_4_PORTS)
1084 n_ports = 4;
1085 for (i = 0; i < n_ports; i++)
1086 ppi[i] = pi;
1087
1088 if (pi->flags & PDC_FLAG_SATA_PATA) {
1089 u8 tmp = readb(base + PDC_FLASH_CTL+1);
1090 if (!(tmp & 0x80))
1091 ppi[n_ports++] = pi + 1;
1092 }
1093
1094 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1095 if (!host) {
1096 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
1097 return -ENOMEM;
1098 }
1099 host->iomap = pcim_iomap_table(pdev);
1100
1101 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
1102 for (i = 0; i < host->n_ports; i++) {
1103 struct ata_port *ap = host->ports[i];
1104 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
1105 unsigned int port_offset = 0x200 + ata_no * 0x80;
1106 unsigned int scr_offset = 0x400 + ata_no * 0x100;
1107
1108 pdc_ata_setup_port(ap, base + port_offset, base + scr_offset);
1109
1110 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1111 ata_port_pbar_desc(ap, PDC_MMIO_BAR, port_offset, "port");
1112 }
1113
1114 /* initialize adapter */
1115 pdc_host_init(host);
1116
1117 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1118 if (rc)
1119 return rc;
1120 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1121 if (rc)
1122 return rc;
1123
1124 /* start host, request IRQ and attach */
1125 pci_set_master(pdev);
1126 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
1127 &pdc_ata_sht);
1128 }
1129
1130 static int __init pdc_ata_init(void)
1131 {
1132 return pci_register_driver(&pdc_ata_pci_driver);
1133 }
1134
1135 static void __exit pdc_ata_exit(void)
1136 {
1137 pci_unregister_driver(&pdc_ata_pci_driver);
1138 }
1139
1140 MODULE_AUTHOR("Jeff Garzik");
1141 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1142 MODULE_LICENSE("GPL");
1143 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1144 MODULE_VERSION(DRV_VERSION);
1145
1146 module_init(pdc_ata_init);
1147 module_exit(pdc_ata_exit);
x86 "subsystem" repository