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libata: implement and use ops inheritance
[linux-2.6/x86.git] / drivers / ata / pdc_adma.c
bloba5706149af6b82733406329725d9c0c92387ec64
1 /*
2 * pdc_adma.c - Pacific Digital Corporation ADMA
3 *
4 * Maintained by: Mark Lord <mlord@pobox.com>
5 *
6 * Copyright 2005 Mark Lord
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 *
27 * Supports ATA disks in single-packet ADMA mode.
28 * Uses PIO for everything else.
29 *
30 * TODO: Use ADMA transfers for ATAPI devices, when possible.
31 * This requires careful attention to a number of quirks of the chip.
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <linux/libata.h>
45
46 #define DRV_NAME "pdc_adma"
47 #define DRV_VERSION "1.0"
48
49 /* macro to calculate base address for ATA regs */
50 #define ADMA_ATA_REGS(base, port_no) ((base) + ((port_no) * 0x40))
51
52 /* macro to calculate base address for ADMA regs */
53 #define ADMA_REGS(base, port_no) ((base) + 0x80 + ((port_no) * 0x20))
54
55 /* macro to obtain addresses from ata_port */
56 #define ADMA_PORT_REGS(ap) \
57 ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
58
59 enum {
60 ADMA_MMIO_BAR = 4,
61
62 ADMA_PORTS = 2,
63 ADMA_CPB_BYTES = 40,
64 ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16,
65 ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
66
67 ADMA_DMA_BOUNDARY = 0xffffffff,
68
69 /* global register offsets */
70 ADMA_MODE_LOCK = 0x00c7,
71
72 /* per-channel register offsets */
73 ADMA_CONTROL = 0x0000, /* ADMA control */
74 ADMA_STATUS = 0x0002, /* ADMA status */
75 ADMA_CPB_COUNT = 0x0004, /* CPB count */
76 ADMA_CPB_CURRENT = 0x000c, /* current CPB address */
77 ADMA_CPB_NEXT = 0x000c, /* next CPB address */
78 ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */
79 ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */
80 ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */
81
82 /* ADMA_CONTROL register bits */
83 aNIEN = (1 << 8), /* irq mask: 1==masked */
84 aGO = (1 << 7), /* packet trigger ("Go!") */
85 aRSTADM = (1 << 5), /* ADMA logic reset */
86 aPIOMD4 = 0x0003, /* PIO mode 4 */
87
88 /* ADMA_STATUS register bits */
89 aPSD = (1 << 6),
90 aUIRQ = (1 << 4),
91 aPERR = (1 << 0),
92
93 /* CPB bits */
94 cDONE = (1 << 0),
95 cATERR = (1 << 3),
96
97 cVLD = (1 << 0),
98 cDAT = (1 << 2),
99 cIEN = (1 << 3),
100
101 /* PRD bits */
102 pORD = (1 << 4),
103 pDIRO = (1 << 5),
104 pEND = (1 << 7),
105
106 /* ATA register flags */
107 rIGN = (1 << 5),
108 rEND = (1 << 7),
109
110 /* ATA register addresses */
111 ADMA_REGS_CONTROL = 0x0e,
112 ADMA_REGS_SECTOR_COUNT = 0x12,
113 ADMA_REGS_LBA_LOW = 0x13,
114 ADMA_REGS_LBA_MID = 0x14,
115 ADMA_REGS_LBA_HIGH = 0x15,
116 ADMA_REGS_DEVICE = 0x16,
117 ADMA_REGS_COMMAND = 0x17,
118
119 /* PCI device IDs */
120 board_1841_idx = 0, /* ADMA 2-port controller */
121 };
122
123 typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
124
125 struct adma_port_priv {
126 u8 *pkt;
127 dma_addr_t pkt_dma;
128 adma_state_t state;
129 };
130
131 static int adma_ata_init_one(struct pci_dev *pdev,
132 const struct pci_device_id *ent);
133 static int adma_port_start(struct ata_port *ap);
134 static void adma_host_stop(struct ata_host *host);
135 static void adma_port_stop(struct ata_port *ap);
136 static void adma_qc_prep(struct ata_queued_cmd *qc);
137 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
138 static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
139 static void adma_bmdma_stop(struct ata_queued_cmd *qc);
140 static u8 adma_bmdma_status(struct ata_port *ap);
141 static void adma_freeze(struct ata_port *ap);
142 static void adma_thaw(struct ata_port *ap);
143 static void adma_error_handler(struct ata_port *ap);
144
145 static struct scsi_host_template adma_ata_sht = {
146 ATA_BASE_SHT(DRV_NAME),
147 .sg_tablesize = LIBATA_MAX_PRD,
148 .dma_boundary = ADMA_DMA_BOUNDARY,
149 };
150
151 static struct ata_port_operations adma_ata_ops = {
152 .inherits = &ata_base_port_ops,
153
154 .dev_select = ata_std_dev_select,
155 .tf_load = ata_tf_load,
156 .tf_read = ata_tf_read,
157 .check_status = ata_check_status,
158 .exec_command = ata_exec_command,
159 .data_xfer = ata_data_xfer,
160 .check_atapi_dma = adma_check_atapi_dma,
161 .bmdma_stop = adma_bmdma_stop,
162 .bmdma_status = adma_bmdma_status,
163 .qc_prep = adma_qc_prep,
164 .qc_issue = adma_qc_issue,
165 .irq_on = ata_irq_on,
166
167 .freeze = adma_freeze,
168 .thaw = adma_thaw,
169 .error_handler = adma_error_handler,
170
171 .port_start = adma_port_start,
172 .port_stop = adma_port_stop,
173 .host_stop = adma_host_stop,
174 };
175
176 static struct ata_port_info adma_port_info[] = {
177 /* board_1841_idx */
178 {
179 .flags = ATA_FLAG_SLAVE_POSS |
180 ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO |
181 ATA_FLAG_PIO_POLLING,
182 .pio_mask = 0x10, /* pio4 */
183 .udma_mask = ATA_UDMA4,
184 .port_ops = &adma_ata_ops,
185 },
186 };
187
188 static const struct pci_device_id adma_ata_pci_tbl[] = {
189 { PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
190
191 { } /* terminate list */
192 };
193
194 static struct pci_driver adma_ata_pci_driver = {
195 .name = DRV_NAME,
196 .id_table = adma_ata_pci_tbl,
197 .probe = adma_ata_init_one,
198 .remove = ata_pci_remove_one,
199 };
200
201 static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
202 {
203 return 1; /* ATAPI DMA not yet supported */
204 }
205
206 static void adma_bmdma_stop(struct ata_queued_cmd *qc)
207 {
208 /* nothing */
209 }
210
211 static u8 adma_bmdma_status(struct ata_port *ap)
212 {
213 return 0;
214 }
215
216 static void adma_reset_engine(struct ata_port *ap)
217 {
218 void __iomem *chan = ADMA_PORT_REGS(ap);
219
220 /* reset ADMA to idle state */
221 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
222 udelay(2);
223 writew(aPIOMD4, chan + ADMA_CONTROL);
224 udelay(2);
225 }
226
227 static void adma_reinit_engine(struct ata_port *ap)
228 {
229 struct adma_port_priv *pp = ap->private_data;
230 void __iomem *chan = ADMA_PORT_REGS(ap);
231
232 /* mask/clear ATA interrupts */
233 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
234 ata_check_status(ap);
235
236 /* reset the ADMA engine */
237 adma_reset_engine(ap);
238
239 /* set in-FIFO threshold to 0x100 */
240 writew(0x100, chan + ADMA_FIFO_IN);
241
242 /* set CPB pointer */
243 writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
244
245 /* set out-FIFO threshold to 0x100 */
246 writew(0x100, chan + ADMA_FIFO_OUT);
247
248 /* set CPB count */
249 writew(1, chan + ADMA_CPB_COUNT);
250
251 /* read/discard ADMA status */
252 readb(chan + ADMA_STATUS);
253 }
254
255 static inline void adma_enter_reg_mode(struct ata_port *ap)
256 {
257 void __iomem *chan = ADMA_PORT_REGS(ap);
258
259 writew(aPIOMD4, chan + ADMA_CONTROL);
260 readb(chan + ADMA_STATUS); /* flush */
261 }
262
263 static void adma_freeze(struct ata_port *ap)
264 {
265 void __iomem *chan = ADMA_PORT_REGS(ap);
266
267 /* mask/clear ATA interrupts */
268 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
269 ata_check_status(ap);
270
271 /* reset ADMA to idle state */
272 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
273 udelay(2);
274 writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL);
275 udelay(2);
276 }
277
278 static void adma_thaw(struct ata_port *ap)
279 {
280 adma_reinit_engine(ap);
281 }
282
283 static int adma_prereset(struct ata_link *link, unsigned long deadline)
284 {
285 struct ata_port *ap = link->ap;
286 struct adma_port_priv *pp = ap->private_data;
287
288 if (pp->state != adma_state_idle) /* healthy paranoia */
289 pp->state = adma_state_mmio;
290 adma_reinit_engine(ap);
291
292 return ata_std_prereset(link, deadline);
293 }
294
295 static void adma_error_handler(struct ata_port *ap)
296 {
297 ata_do_eh(ap, adma_prereset, ata_std_softreset, NULL,
298 ata_std_postreset);
299 }
300
301 static int adma_fill_sg(struct ata_queued_cmd *qc)
302 {
303 struct scatterlist *sg;
304 struct ata_port *ap = qc->ap;
305 struct adma_port_priv *pp = ap->private_data;
306 u8 *buf = pp->pkt, *last_buf = NULL;
307 int i = (2 + buf[3]) * 8;
308 u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
309 unsigned int si;
310
311 for_each_sg(qc->sg, sg, qc->n_elem, si) {
312 u32 addr;
313 u32 len;
314
315 addr = (u32)sg_dma_address(sg);
316 *(__le32 *)(buf + i) = cpu_to_le32(addr);
317 i += 4;
318
319 len = sg_dma_len(sg) >> 3;
320 *(__le32 *)(buf + i) = cpu_to_le32(len);
321 i += 4;
322
323 last_buf = &buf[i];
324 buf[i++] = pFLAGS;
325 buf[i++] = qc->dev->dma_mode & 0xf;
326 buf[i++] = 0; /* pPKLW */
327 buf[i++] = 0; /* reserved */
328
329 *(__le32 *)(buf + i) =
330 (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
331 i += 4;
332
333 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
334 (unsigned long)addr, len);
335 }
336
337 if (likely(last_buf))
338 *last_buf |= pEND;
339
340 return i;
341 }
342
343 static void adma_qc_prep(struct ata_queued_cmd *qc)
344 {
345 struct adma_port_priv *pp = qc->ap->private_data;
346 u8 *buf = pp->pkt;
347 u32 pkt_dma = (u32)pp->pkt_dma;
348 int i = 0;
349
350 VPRINTK("ENTER\n");
351
352 adma_enter_reg_mode(qc->ap);
353 if (qc->tf.protocol != ATA_PROT_DMA) {
354 ata_qc_prep(qc);
355 return;
356 }
357
358 buf[i++] = 0; /* Response flags */
359 buf[i++] = 0; /* reserved */
360 buf[i++] = cVLD | cDAT | cIEN;
361 i++; /* cLEN, gets filled in below */
362
363 *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */
364 i += 4; /* cNCPB */
365 i += 4; /* cPRD, gets filled in below */
366
367 buf[i++] = 0; /* reserved */
368 buf[i++] = 0; /* reserved */
369 buf[i++] = 0; /* reserved */
370 buf[i++] = 0; /* reserved */
371
372 /* ATA registers; must be a multiple of 4 */
373 buf[i++] = qc->tf.device;
374 buf[i++] = ADMA_REGS_DEVICE;
375 if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
376 buf[i++] = qc->tf.hob_nsect;
377 buf[i++] = ADMA_REGS_SECTOR_COUNT;
378 buf[i++] = qc->tf.hob_lbal;
379 buf[i++] = ADMA_REGS_LBA_LOW;
380 buf[i++] = qc->tf.hob_lbam;
381 buf[i++] = ADMA_REGS_LBA_MID;
382 buf[i++] = qc->tf.hob_lbah;
383 buf[i++] = ADMA_REGS_LBA_HIGH;
384 }
385 buf[i++] = qc->tf.nsect;
386 buf[i++] = ADMA_REGS_SECTOR_COUNT;
387 buf[i++] = qc->tf.lbal;
388 buf[i++] = ADMA_REGS_LBA_LOW;
389 buf[i++] = qc->tf.lbam;
390 buf[i++] = ADMA_REGS_LBA_MID;
391 buf[i++] = qc->tf.lbah;
392 buf[i++] = ADMA_REGS_LBA_HIGH;
393 buf[i++] = 0;
394 buf[i++] = ADMA_REGS_CONTROL;
395 buf[i++] = rIGN;
396 buf[i++] = 0;
397 buf[i++] = qc->tf.command;
398 buf[i++] = ADMA_REGS_COMMAND | rEND;
399
400 buf[3] = (i >> 3) - 2; /* cLEN */
401 *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */
402
403 i = adma_fill_sg(qc);
404 wmb(); /* flush PRDs and pkt to memory */
405 #if 0
406 /* dump out CPB + PRDs for debug */
407 {
408 int j, len = 0;
409 static char obuf[2048];
410 for (j = 0; j < i; ++j) {
411 len += sprintf(obuf+len, "%02x ", buf[j]);
412 if ((j & 7) == 7) {
413 printk("%s\n", obuf);
414 len = 0;
415 }
416 }
417 if (len)
418 printk("%s\n", obuf);
419 }
420 #endif
421 }
422
423 static inline void adma_packet_start(struct ata_queued_cmd *qc)
424 {
425 struct ata_port *ap = qc->ap;
426 void __iomem *chan = ADMA_PORT_REGS(ap);
427
428 VPRINTK("ENTER, ap %p\n", ap);
429
430 /* fire up the ADMA engine */
431 writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
432 }
433
434 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
435 {
436 struct adma_port_priv *pp = qc->ap->private_data;
437
438 switch (qc->tf.protocol) {
439 case ATA_PROT_DMA:
440 pp->state = adma_state_pkt;
441 adma_packet_start(qc);
442 return 0;
443
444 case ATAPI_PROT_DMA:
445 BUG();
446 break;
447
448 default:
449 break;
450 }
451
452 pp->state = adma_state_mmio;
453 return ata_qc_issue_prot(qc);
454 }
455
456 static inline unsigned int adma_intr_pkt(struct ata_host *host)
457 {
458 unsigned int handled = 0, port_no;
459
460 for (port_no = 0; port_no < host->n_ports; ++port_no) {
461 struct ata_port *ap = host->ports[port_no];
462 struct adma_port_priv *pp;
463 struct ata_queued_cmd *qc;
464 void __iomem *chan = ADMA_PORT_REGS(ap);
465 u8 status = readb(chan + ADMA_STATUS);
466
467 if (status == 0)
468 continue;
469 handled = 1;
470 adma_enter_reg_mode(ap);
471 if (ap->flags & ATA_FLAG_DISABLED)
472 continue;
473 pp = ap->private_data;
474 if (!pp || pp->state != adma_state_pkt)
475 continue;
476 qc = ata_qc_from_tag(ap, ap->link.active_tag);
477 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
478 if (status & aPERR)
479 qc->err_mask |= AC_ERR_HOST_BUS;
480 else if ((status & (aPSD | aUIRQ)))
481 qc->err_mask |= AC_ERR_OTHER;
482
483 if (pp->pkt[0] & cATERR)
484 qc->err_mask |= AC_ERR_DEV;
485 else if (pp->pkt[0] != cDONE)
486 qc->err_mask |= AC_ERR_OTHER;
487
488 if (!qc->err_mask)
489 ata_qc_complete(qc);
490 else {
491 struct ata_eh_info *ehi = &ap->link.eh_info;
492 ata_ehi_clear_desc(ehi);
493 ata_ehi_push_desc(ehi,
494 "ADMA-status 0x%02X", status);
495 ata_ehi_push_desc(ehi,
496 "pkt[0] 0x%02X", pp->pkt[0]);
497
498 if (qc->err_mask == AC_ERR_DEV)
499 ata_port_abort(ap);
500 else
501 ata_port_freeze(ap);
502 }
503 }
504 }
505 return handled;
506 }
507
508 static inline unsigned int adma_intr_mmio(struct ata_host *host)
509 {
510 unsigned int handled = 0, port_no;
511
512 for (port_no = 0; port_no < host->n_ports; ++port_no) {
513 struct ata_port *ap;
514 ap = host->ports[port_no];
515 if (ap && (!(ap->flags & ATA_FLAG_DISABLED))) {
516 struct ata_queued_cmd *qc;
517 struct adma_port_priv *pp = ap->private_data;
518 if (!pp || pp->state != adma_state_mmio)
519 continue;
520 qc = ata_qc_from_tag(ap, ap->link.active_tag);
521 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
522
523 /* check main status, clearing INTRQ */
524 u8 status = ata_check_status(ap);
525 if ((status & ATA_BUSY))
526 continue;
527 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
528 ap->print_id, qc->tf.protocol, status);
529
530 /* complete taskfile transaction */
531 pp->state = adma_state_idle;
532 qc->err_mask |= ac_err_mask(status);
533 if (!qc->err_mask)
534 ata_qc_complete(qc);
535 else {
536 struct ata_eh_info *ehi =
537 &ap->link.eh_info;
538 ata_ehi_clear_desc(ehi);
539 ata_ehi_push_desc(ehi,
540 "status 0x%02X", status);
541
542 if (qc->err_mask == AC_ERR_DEV)
543 ata_port_abort(ap);
544 else
545 ata_port_freeze(ap);
546 }
547 handled = 1;
548 }
549 }
550 }
551 return handled;
552 }
553
554 static irqreturn_t adma_intr(int irq, void *dev_instance)
555 {
556 struct ata_host *host = dev_instance;
557 unsigned int handled = 0;
558
559 VPRINTK("ENTER\n");
560
561 spin_lock(&host->lock);
562 handled = adma_intr_pkt(host) | adma_intr_mmio(host);
563 spin_unlock(&host->lock);
564
565 VPRINTK("EXIT\n");
566
567 return IRQ_RETVAL(handled);
568 }
569
570 static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
571 {
572 port->cmd_addr =
573 port->data_addr = base + 0x000;
574 port->error_addr =
575 port->feature_addr = base + 0x004;
576 port->nsect_addr = base + 0x008;
577 port->lbal_addr = base + 0x00c;
578 port->lbam_addr = base + 0x010;
579 port->lbah_addr = base + 0x014;
580 port->device_addr = base + 0x018;
581 port->status_addr =
582 port->command_addr = base + 0x01c;
583 port->altstatus_addr =
584 port->ctl_addr = base + 0x038;
585 }
586
587 static int adma_port_start(struct ata_port *ap)
588 {
589 struct device *dev = ap->host->dev;
590 struct adma_port_priv *pp;
591 int rc;
592
593 rc = ata_port_start(ap);
594 if (rc)
595 return rc;
596 adma_enter_reg_mode(ap);
597 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
598 if (!pp)
599 return -ENOMEM;
600 pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
601 GFP_KERNEL);
602 if (!pp->pkt)
603 return -ENOMEM;
604 /* paranoia? */
605 if ((pp->pkt_dma & 7) != 0) {
606 printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n",
607 (u32)pp->pkt_dma);
608 return -ENOMEM;
609 }
610 memset(pp->pkt, 0, ADMA_PKT_BYTES);
611 ap->private_data = pp;
612 adma_reinit_engine(ap);
613 return 0;
614 }
615
616 static void adma_port_stop(struct ata_port *ap)
617 {
618 adma_reset_engine(ap);
619 }
620
621 static void adma_host_stop(struct ata_host *host)
622 {
623 unsigned int port_no;
624
625 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
626 adma_reset_engine(host->ports[port_no]);
627 }
628
629 static void adma_host_init(struct ata_host *host, unsigned int chip_id)
630 {
631 unsigned int port_no;
632
633 /* enable/lock aGO operation */
634 writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);
635
636 /* reset the ADMA logic */
637 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
638 adma_reset_engine(host->ports[port_no]);
639 }
640
641 static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
642 {
643 int rc;
644
645 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
646 if (rc) {
647 dev_printk(KERN_ERR, &pdev->dev,
648 "32-bit DMA enable failed\n");
649 return rc;
650 }
651 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
652 if (rc) {
653 dev_printk(KERN_ERR, &pdev->dev,
654 "32-bit consistent DMA enable failed\n");
655 return rc;
656 }
657 return 0;
658 }
659
660 static int adma_ata_init_one(struct pci_dev *pdev,
661 const struct pci_device_id *ent)
662 {
663 static int printed_version;
664 unsigned int board_idx = (unsigned int) ent->driver_data;
665 const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
666 struct ata_host *host;
667 void __iomem *mmio_base;
668 int rc, port_no;
669
670 if (!printed_version++)
671 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
672
673 /* alloc host */
674 host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
675 if (!host)
676 return -ENOMEM;
677
678 /* acquire resources and fill host */
679 rc = pcim_enable_device(pdev);
680 if (rc)
681 return rc;
682
683 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
684 return -ENODEV;
685
686 rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
687 if (rc)
688 return rc;
689 host->iomap = pcim_iomap_table(pdev);
690 mmio_base = host->iomap[ADMA_MMIO_BAR];
691
692 rc = adma_set_dma_masks(pdev, mmio_base);
693 if (rc)
694 return rc;
695
696 for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
697 struct ata_port *ap = host->ports[port_no];
698 void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
699 unsigned int offset = port_base - mmio_base;
700
701 adma_ata_setup_port(&ap->ioaddr, port_base);
702
703 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
704 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
705 }
706
707 /* initialize adapter */
708 adma_host_init(host, board_idx);
709
710 pci_set_master(pdev);
711 return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
712 &adma_ata_sht);
713 }
714
715 static int __init adma_ata_init(void)
716 {
717 return pci_register_driver(&adma_ata_pci_driver);
718 }
719
720 static void __exit adma_ata_exit(void)
721 {
722 pci_unregister_driver(&adma_ata_pci_driver);
723 }
724
725 MODULE_AUTHOR("Mark Lord");
726 MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
727 MODULE_LICENSE("GPL");
728 MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
729 MODULE_VERSION(DRV_VERSION);
730
731 module_init(adma_ata_init);
732 module_exit(adma_ata_exit);
x86 "subsystem" repository