2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #define BITS_PER_BYTE 8
20 #define OFDM_PLCP_BITS 22
21 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
34 #define OFDM_SIFS_TIME 16
36 static u32 bits_per_symbol
[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 { 52, 108 }, /* 8: BPSK */
47 { 104, 216 }, /* 9: QPSK 1/2 */
48 { 156, 324 }, /* 10: QPSK 3/4 */
49 { 208, 432 }, /* 11: 16-QAM 1/2 */
50 { 312, 648 }, /* 12: 16-QAM 3/4 */
51 { 416, 864 }, /* 13: 64-QAM 2/3 */
52 { 468, 972 }, /* 14: 64-QAM 3/4 */
53 { 520, 1080 }, /* 15: 64-QAM 5/6 */
56 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
59 * Insert a chain of ath_buf (descriptors) on a txq and
60 * assume the descriptors are already chained together by caller.
61 * NB: must be called with txq lock held
64 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
65 struct list_head
*head
)
67 struct ath_hal
*ah
= sc
->sc_ah
;
71 * Insert the frame on the outbound list and
72 * pass it on to the hardware.
78 bf
= list_first_entry(head
, struct ath_buf
, list
);
80 list_splice_tail_init(head
, &txq
->axq_q
);
82 txq
->axq_totalqueued
++;
83 txq
->axq_linkbuf
= list_entry(txq
->axq_q
.prev
, struct ath_buf
, list
);
85 DPRINTF(sc
, ATH_DBG_QUEUE
,
86 "%s: txq depth = %d\n", __func__
, txq
->axq_depth
);
88 if (txq
->axq_link
== NULL
) {
89 ath9k_hw_puttxbuf(ah
, txq
->axq_qnum
, bf
->bf_daddr
);
90 DPRINTF(sc
, ATH_DBG_XMIT
,
91 "%s: TXDP[%u] = %llx (%p)\n",
92 __func__
, txq
->axq_qnum
,
93 ito64(bf
->bf_daddr
), bf
->bf_desc
);
95 *txq
->axq_link
= bf
->bf_daddr
;
96 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: link[%u] (%p)=%llx (%p)\n",
98 txq
->axq_qnum
, txq
->axq_link
,
99 ito64(bf
->bf_daddr
), bf
->bf_desc
);
101 txq
->axq_link
= &(bf
->bf_lastbf
->bf_desc
->ds_link
);
102 ath9k_hw_txstart(ah
, txq
->axq_qnum
);
105 /* Get transmit rate index using rate in Kbps */
107 static int ath_tx_findindex(const struct ath9k_rate_table
*rt
, int rate
)
112 for (i
= 0; i
< rt
->rateCount
; i
++) {
113 if (rt
->info
[i
].rateKbps
== rate
) {
122 /* Check if it's okay to send out aggregates */
124 static int ath_aggr_query(struct ath_softc
*sc
, struct ath_node
*an
, u8 tidno
)
126 struct ath_atx_tid
*tid
;
127 tid
= ATH_AN_2_TID(an
, tidno
);
129 if (tid
->state
& AGGR_ADDBA_COMPLETE
||
130 tid
->state
& AGGR_ADDBA_PROGRESS
)
136 /* Calculate Atheros packet type from IEEE80211 packet header */
138 static enum ath9k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
140 struct ieee80211_hdr
*hdr
;
141 enum ath9k_pkt_type htype
;
144 hdr
= (struct ieee80211_hdr
*)skb
->data
;
145 fc
= hdr
->frame_control
;
147 if (ieee80211_is_beacon(fc
))
148 htype
= ATH9K_PKT_TYPE_BEACON
;
149 else if (ieee80211_is_probe_resp(fc
))
150 htype
= ATH9K_PKT_TYPE_PROBE_RESP
;
151 else if (ieee80211_is_atim(fc
))
152 htype
= ATH9K_PKT_TYPE_ATIM
;
153 else if (ieee80211_is_pspoll(fc
))
154 htype
= ATH9K_PKT_TYPE_PSPOLL
;
156 htype
= ATH9K_PKT_TYPE_NORMAL
;
161 static bool check_min_rate(struct sk_buff
*skb
)
163 struct ieee80211_hdr
*hdr
;
164 bool use_minrate
= false;
167 hdr
= (struct ieee80211_hdr
*)skb
->data
;
168 fc
= hdr
->frame_control
;
170 if (ieee80211_is_mgmt(fc
) || ieee80211_is_ctl(fc
)) {
172 } else if (ieee80211_is_data(fc
)) {
173 if (ieee80211_is_nullfunc(fc
) ||
174 /* Port Access Entity (IEEE 802.1X) */
175 (skb
->protocol
== cpu_to_be16(ETH_P_PAE
))) {
183 static int get_hw_crypto_keytype(struct sk_buff
*skb
)
185 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
187 if (tx_info
->control
.hw_key
) {
188 if (tx_info
->control
.hw_key
->alg
== ALG_WEP
)
189 return ATH9K_KEY_TYPE_WEP
;
190 else if (tx_info
->control
.hw_key
->alg
== ALG_TKIP
)
191 return ATH9K_KEY_TYPE_TKIP
;
192 else if (tx_info
->control
.hw_key
->alg
== ALG_CCMP
)
193 return ATH9K_KEY_TYPE_AES
;
196 return ATH9K_KEY_TYPE_CLEAR
;
199 static void setup_rate_retries(struct ath_softc
*sc
, struct sk_buff
*skb
)
201 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
202 struct ath_tx_info_priv
*tx_info_priv
;
203 struct ath_rc_series
*rcs
;
204 struct ieee80211_hdr
*hdr
;
205 const struct ath9k_rate_table
*rt
;
210 rt
= sc
->sc_currates
;
213 hdr
= (struct ieee80211_hdr
*)skb
->data
;
214 fc
= hdr
->frame_control
;
215 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->control
.vif
; /* HACK */
216 rcs
= tx_info_priv
->rcs
;
218 /* Check if min rates have to be used */
219 use_minrate
= check_min_rate(skb
);
221 if (ieee80211_is_data(fc
) && !use_minrate
) {
222 if (is_multicast_ether_addr(hdr
->addr1
)) {
224 ath_tx_findindex(rt
, tx_info_priv
->min_rate
);
225 /* mcast packets are not re-tried */
229 /* for management and control frames,
230 or for NULL and EAPOL frames */
232 rcs
[0].rix
= ath_rate_findrateix(sc
, tx_info_priv
->min_rate
);
235 rcs
[0].tries
= ATH_MGT_TXMAXTRY
;
240 if (ieee80211_has_morefrags(fc
) ||
241 (le16_to_cpu(hdr
->seq_ctrl
) & IEEE80211_SCTL_FRAG
)) {
242 rcs
[1].tries
= rcs
[2].tries
= rcs
[3].tries
= 0;
243 rcs
[1].rix
= rcs
[2].rix
= rcs
[3].rix
= 0;
244 /* reset tries but keep rate index */
245 rcs
[0].tries
= ATH_TXMAXTRY
;
249 /* Called only when tx aggregation is enabled and HT is supported */
251 static void assign_aggr_tid_seqno(struct sk_buff
*skb
,
254 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
255 struct ieee80211_hdr
*hdr
;
257 struct ath_atx_tid
*tid
;
261 if (!tx_info
->control
.sta
)
264 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
265 hdr
= (struct ieee80211_hdr
*)skb
->data
;
266 fc
= hdr
->frame_control
;
270 if (ieee80211_is_data_qos(fc
)) {
271 qc
= ieee80211_get_qos_ctl(hdr
);
272 bf
->bf_tidno
= qc
[0] & 0xf;
277 if (ieee80211_is_data(fc
) && !check_min_rate(skb
)) {
278 /* For HT capable stations, we save tidno for later use.
279 * We also override seqno set by upper layer with the one
280 * in tx aggregation state.
282 * If fragmentation is on, the sequence number is
283 * not overridden, since it has been
284 * incremented by the fragmentation routine.
286 * FIXME: check if the fragmentation threshold exceeds
289 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
290 hdr
->seq_ctrl
= cpu_to_le16(tid
->seq_next
<<
291 IEEE80211_SEQ_SEQ_SHIFT
);
292 bf
->bf_seqno
= tid
->seq_next
;
293 INCR(tid
->seq_next
, IEEE80211_SEQ_MAX
);
297 static int setup_tx_flags(struct ath_softc
*sc
, struct sk_buff
*skb
,
300 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
303 flags
|= ATH9K_TXDESC_CLRDMASK
; /* needed for crypto errors */
304 flags
|= ATH9K_TXDESC_INTREQ
;
306 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
307 flags
|= ATH9K_TXDESC_NOACK
;
308 if (tx_info
->control
.rates
[0].flags
& IEEE80211_TX_RC_USE_RTS_CTS
)
309 flags
|= ATH9K_TXDESC_RTSENA
;
314 static struct ath_buf
*ath_tx_get_buffer(struct ath_softc
*sc
)
316 struct ath_buf
*bf
= NULL
;
318 spin_lock_bh(&sc
->sc_txbuflock
);
320 if (unlikely(list_empty(&sc
->sc_txbuf
))) {
321 spin_unlock_bh(&sc
->sc_txbuflock
);
325 bf
= list_first_entry(&sc
->sc_txbuf
, struct ath_buf
, list
);
328 spin_unlock_bh(&sc
->sc_txbuflock
);
333 /* To complete a chain of buffers associated a frame */
335 static void ath_tx_complete_buf(struct ath_softc
*sc
,
337 struct list_head
*bf_q
,
338 int txok
, int sendbar
)
340 struct sk_buff
*skb
= bf
->bf_mpdu
;
341 struct ath_xmit_status tx_status
;
344 * Set retry information.
345 * NB: Don't use the information in the descriptor, because the frame
346 * could be software retried.
348 tx_status
.retries
= bf
->bf_retries
;
352 tx_status
.flags
= ATH_TX_BAR
;
355 tx_status
.flags
|= ATH_TX_ERROR
;
357 if (bf_isxretried(bf
))
358 tx_status
.flags
|= ATH_TX_XRETRY
;
361 /* Unmap this frame */
362 pci_unmap_single(sc
->pdev
,
366 /* complete this frame */
367 ath_tx_complete(sc
, skb
, &tx_status
);
370 * Return the list of ath_buf of this mpdu to free queue
372 spin_lock_bh(&sc
->sc_txbuflock
);
373 list_splice_tail_init(bf_q
, &sc
->sc_txbuf
);
374 spin_unlock_bh(&sc
->sc_txbuflock
);
378 * queue up a dest/ac pair for tx scheduling
379 * NB: must be called with txq lock held
382 static void ath_tx_queue_tid(struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
384 struct ath_atx_ac
*ac
= tid
->ac
;
387 * if tid is paused, hold off
393 * add tid to ac atmost once
399 list_add_tail(&tid
->list
, &ac
->tid_q
);
402 * add node ac to txq atmost once
408 list_add_tail(&ac
->list
, &txq
->axq_acq
);
413 static void ath_tx_pause_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
415 struct ath_txq
*txq
= &sc
->sc_txq
[tid
->ac
->qnum
];
417 spin_lock_bh(&txq
->axq_lock
);
421 spin_unlock_bh(&txq
->axq_lock
);
424 /* resume a tid and schedule aggregate */
426 void ath_tx_resume_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
428 struct ath_txq
*txq
= &sc
->sc_txq
[tid
->ac
->qnum
];
430 ASSERT(tid
->paused
> 0);
431 spin_lock_bh(&txq
->axq_lock
);
438 if (list_empty(&tid
->buf_q
))
442 * Add this TID to scheduler and try to send out aggregates
444 ath_tx_queue_tid(txq
, tid
);
445 ath_txq_schedule(sc
, txq
);
447 spin_unlock_bh(&txq
->axq_lock
);
450 /* Compute the number of bad frames */
452 static int ath_tx_num_badfrms(struct ath_softc
*sc
, struct ath_buf
*bf
,
455 struct ath_buf
*bf_last
= bf
->bf_lastbf
;
456 struct ath_desc
*ds
= bf_last
->bf_desc
;
458 u32 ba
[WME_BA_BMP_SIZE
>> 5];
463 if (ds
->ds_txstat
.ts_flags
== ATH9K_TX_SW_ABORTED
)
466 isaggr
= bf_isaggr(bf
);
468 seq_st
= ATH_DS_BA_SEQ(ds
);
469 memcpy(ba
, ATH_DS_BA_BITMAP(ds
), WME_BA_BMP_SIZE
>> 3);
473 ba_index
= ATH_BA_INDEX(seq_st
, bf
->bf_seqno
);
474 if (!txok
|| (isaggr
&& !ATH_BA_ISSET(ba
, ba_index
)))
483 static void ath_tx_set_retry(struct ath_softc
*sc
, struct ath_buf
*bf
)
486 struct ieee80211_hdr
*hdr
;
488 bf
->bf_state
.bf_type
|= BUF_RETRY
;
492 hdr
= (struct ieee80211_hdr
*)skb
->data
;
493 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_RETRY
);
496 /* Update block ack window */
498 static void ath_tx_update_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
503 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
504 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
506 tid
->tx_buf
[cindex
] = NULL
;
508 while (tid
->baw_head
!= tid
->baw_tail
&& !tid
->tx_buf
[tid
->baw_head
]) {
509 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
510 INCR(tid
->baw_head
, ATH_TID_MAX_BUFS
);
515 * ath_pkt_dur - compute packet duration (NB: not NAV)
518 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
519 * width - 0 for 20 MHz, 1 for 40 MHz
520 * half_gi - to use 4us v/s 3.6 us for symbol time
523 static u32
ath_pkt_duration(struct ath_softc
*sc
, u8 rix
, struct ath_buf
*bf
,
524 int width
, int half_gi
, bool shortPreamble
)
526 const struct ath9k_rate_table
*rt
= sc
->sc_currates
;
527 u32 nbits
, nsymbits
, duration
, nsymbols
;
531 pktlen
= bf_isaggr(bf
) ? bf
->bf_al
: bf
->bf_frmlen
;
532 rc
= rt
->info
[rix
].rateCode
;
535 * for legacy rates, use old function to compute packet duration
538 return ath9k_hw_computetxtime(sc
->sc_ah
, rt
, pktlen
, rix
,
541 * find number of symbols: PLCP + data
543 nbits
= (pktlen
<< 3) + OFDM_PLCP_BITS
;
544 nsymbits
= bits_per_symbol
[HT_RC_2_MCS(rc
)][width
];
545 nsymbols
= (nbits
+ nsymbits
- 1) / nsymbits
;
548 duration
= SYMBOL_TIME(nsymbols
);
550 duration
= SYMBOL_TIME_HALFGI(nsymbols
);
553 * addup duration for legacy/ht training and signal fields
555 streams
= HT_RC_2_STREAMS(rc
);
556 duration
+= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
561 /* Rate module function to set rate related fields in tx descriptor */
563 static void ath_buf_set_rate(struct ath_softc
*sc
, struct ath_buf
*bf
)
565 struct ath_hal
*ah
= sc
->sc_ah
;
566 const struct ath9k_rate_table
*rt
;
567 struct ath_desc
*ds
= bf
->bf_desc
;
568 struct ath_desc
*lastds
= bf
->bf_lastbf
->bf_desc
;
569 struct ath9k_11n_rate_series series
[4];
570 int i
, flags
, rtsctsena
= 0;
572 u8 rix
= 0, cix
, ctsrate
= 0;
573 struct ath_node
*an
= NULL
;
575 struct ieee80211_tx_info
*tx_info
;
577 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
578 tx_info
= IEEE80211_SKB_CB(skb
);
580 if (tx_info
->control
.sta
)
581 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
584 * get the cix for the lowest valid rix.
586 rt
= sc
->sc_currates
;
588 if (bf
->bf_rcs
[i
].tries
) {
589 rix
= bf
->bf_rcs
[i
].rix
;
593 flags
= (bf
->bf_flags
& (ATH9K_TXDESC_RTSENA
| ATH9K_TXDESC_CTSENA
));
594 cix
= rt
->info
[rix
].controlRate
;
597 * If 802.11g protection is enabled, determine whether
598 * to use RTS/CTS or just CTS. Note that this is only
599 * done for OFDM/HT unicast frames.
601 if (sc
->sc_protmode
!= PROT_M_NONE
&&
602 (rt
->info
[rix
].phy
== PHY_OFDM
||
603 rt
->info
[rix
].phy
== PHY_HT
) &&
604 (bf
->bf_flags
& ATH9K_TXDESC_NOACK
) == 0) {
605 if (sc
->sc_protmode
== PROT_M_RTSCTS
)
606 flags
= ATH9K_TXDESC_RTSENA
;
607 else if (sc
->sc_protmode
== PROT_M_CTSONLY
)
608 flags
= ATH9K_TXDESC_CTSENA
;
610 cix
= rt
->info
[sc
->sc_protrix
].controlRate
;
614 /* For 11n, the default behavior is to enable RTS for
615 * hw retried frames. We enable the global flag here and
616 * let rate series flags determine which rates will actually
619 if ((ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_HT
) && bf_isdata(bf
)) {
621 * 802.11g protection not needed, use our default behavior
624 flags
= ATH9K_TXDESC_RTSENA
;
628 * Set protection if aggregate protection on
630 if (sc
->sc_config
.ath_aggr_prot
&&
631 (!bf_isaggr(bf
) || (bf_isaggr(bf
) && bf
->bf_al
< 8192))) {
632 flags
= ATH9K_TXDESC_RTSENA
;
633 cix
= rt
->info
[sc
->sc_protrix
].controlRate
;
638 * For AR5416 - RTS cannot be followed by a frame larger than 8K.
640 if (bf_isaggr(bf
) && (bf
->bf_al
> ah
->ah_caps
.rts_aggr_limit
)) {
642 * Ensure that in the case of SM Dynamic power save
643 * while we are bursting the second aggregate the
646 flags
&= ~(ATH9K_TXDESC_RTSENA
);
650 * CTS transmit rate is derived from the transmit rate
651 * by looking in the h/w rate table. We must also factor
652 * in whether or not a short preamble is to be used.
653 * NB: cix is set above where RTS/CTS is enabled
656 ctsrate
= rt
->info
[cix
].rateCode
|
657 (bf_isshpreamble(bf
) ? rt
->info
[cix
].shortPreamble
: 0);
660 * Setup HAL rate series
662 memset(series
, 0, sizeof(struct ath9k_11n_rate_series
) * 4);
664 for (i
= 0; i
< 4; i
++) {
665 if (!bf
->bf_rcs
[i
].tries
)
668 rix
= bf
->bf_rcs
[i
].rix
;
670 series
[i
].Rate
= rt
->info
[rix
].rateCode
|
671 (bf_isshpreamble(bf
) ? rt
->info
[rix
].shortPreamble
: 0);
673 series
[i
].Tries
= bf
->bf_rcs
[i
].tries
;
675 series
[i
].RateFlags
= (
676 (bf
->bf_rcs
[i
].flags
& ATH_RC_RTSCTS_FLAG
) ?
677 ATH9K_RATESERIES_RTS_CTS
: 0) |
678 ((bf
->bf_rcs
[i
].flags
& ATH_RC_CW40_FLAG
) ?
679 ATH9K_RATESERIES_2040
: 0) |
680 ((bf
->bf_rcs
[i
].flags
& ATH_RC_SGI_FLAG
) ?
681 ATH9K_RATESERIES_HALFGI
: 0);
683 series
[i
].PktDuration
= ath_pkt_duration(sc
, rix
, bf
,
684 (bf
->bf_rcs
[i
].flags
& ATH_RC_CW40_FLAG
) != 0,
685 (bf
->bf_rcs
[i
].flags
& ATH_RC_SGI_FLAG
),
686 bf_isshpreamble(bf
));
688 if (bf_isht(bf
) && an
)
689 series
[i
].ChSel
= ath_chainmask_sel_logic(sc
, an
);
691 series
[i
].ChSel
= sc
->sc_tx_chainmask
;
694 series
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
698 * set dur_update_en for l-sig computation except for PS-Poll frames
700 ath9k_hw_set11n_ratescenario(ah
, ds
, lastds
,
706 if (sc
->sc_config
.ath_aggr_prot
&& flags
)
707 ath9k_hw_set11n_burstduration(ah
, ds
, 8192);
711 * Function to send a normal HT (non-AMPDU) frame
712 * NB: must be called with txq lock held
715 static int ath_tx_send_normal(struct ath_softc
*sc
,
717 struct ath_atx_tid
*tid
,
718 struct list_head
*bf_head
)
722 struct ieee80211_tx_info
*tx_info
;
723 struct ath_tx_info_priv
*tx_info_priv
;
725 BUG_ON(list_empty(bf_head
));
727 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
728 bf
->bf_state
.bf_type
&= ~BUF_AMPDU
; /* regular HT frame */
730 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
731 tx_info
= IEEE80211_SKB_CB(skb
);
734 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->control
.vif
;
735 memcpy(bf
->bf_rcs
, tx_info_priv
->rcs
, 4 * sizeof(tx_info_priv
->rcs
[0]));
737 /* update starting sequence number for subsequent ADDBA request */
738 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
740 /* Queue to h/w without aggregation */
742 bf
->bf_lastbf
= bf
->bf_lastfrm
; /* one single frame */
743 ath_buf_set_rate(sc
, bf
);
744 ath_tx_txqaddbuf(sc
, txq
, bf_head
);
749 /* flush tid's software queue and send frames as non-ampdu's */
751 static void ath_tx_flush_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
753 struct ath_txq
*txq
= &sc
->sc_txq
[tid
->ac
->qnum
];
755 struct list_head bf_head
;
756 INIT_LIST_HEAD(&bf_head
);
758 ASSERT(tid
->paused
> 0);
759 spin_lock_bh(&txq
->axq_lock
);
763 if (tid
->paused
> 0) {
764 spin_unlock_bh(&txq
->axq_lock
);
768 while (!list_empty(&tid
->buf_q
)) {
769 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
770 ASSERT(!bf_isretried(bf
));
771 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
772 ath_tx_send_normal(sc
, txq
, tid
, &bf_head
);
775 spin_unlock_bh(&txq
->axq_lock
);
778 /* Completion routine of an aggregate */
780 static void ath_tx_complete_aggr_rifs(struct ath_softc
*sc
,
783 struct list_head
*bf_q
,
786 struct ath_node
*an
= NULL
;
788 struct ieee80211_tx_info
*tx_info
;
789 struct ath_atx_tid
*tid
= NULL
;
790 struct ath_buf
*bf_last
= bf
->bf_lastbf
;
791 struct ath_desc
*ds
= bf_last
->bf_desc
;
792 struct ath_buf
*bf_next
, *bf_lastq
= NULL
;
793 struct list_head bf_head
, bf_pending
;
795 u32 ba
[WME_BA_BMP_SIZE
>> 5];
796 int isaggr
, txfail
, txpending
, sendbar
= 0, needreset
= 0;
798 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
799 tx_info
= IEEE80211_SKB_CB(skb
);
801 if (tx_info
->control
.sta
) {
802 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
803 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
806 isaggr
= bf_isaggr(bf
);
809 if (ATH_DS_TX_BA(ds
)) {
811 * extract starting sequence and
814 seq_st
= ATH_DS_BA_SEQ(ds
);
816 ATH_DS_BA_BITMAP(ds
),
817 WME_BA_BMP_SIZE
>> 3);
819 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
822 * AR5416 can become deaf/mute when BA
823 * issue happens. Chip needs to be reset.
824 * But AP code may have sychronization issues
825 * when perform internal reset in this routine.
826 * Only enable reset in STA mode for now.
828 if (sc
->sc_ah
->ah_opmode
== ATH9K_M_STA
)
832 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
836 INIT_LIST_HEAD(&bf_pending
);
837 INIT_LIST_HEAD(&bf_head
);
840 txfail
= txpending
= 0;
841 bf_next
= bf
->bf_next
;
843 if (ATH_BA_ISSET(ba
, ATH_BA_INDEX(seq_st
, bf
->bf_seqno
))) {
844 /* transmit completion, subframe is
845 * acked by block ack */
846 } else if (!isaggr
&& txok
) {
847 /* transmit completion */
850 if (!(tid
->state
& AGGR_CLEANUP
) &&
851 ds
->ds_txstat
.ts_flags
!= ATH9K_TX_SW_ABORTED
) {
852 if (bf
->bf_retries
< ATH_MAX_SW_RETRIES
) {
853 ath_tx_set_retry(sc
, bf
);
856 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
862 * cleanup in progress, just fail
863 * the un-acked sub-frames
869 * Remove ath_buf's of this sub-frame from aggregate queue.
871 if (bf_next
== NULL
) { /* last subframe in the aggregate */
872 ASSERT(bf
->bf_lastfrm
== bf_last
);
875 * The last descriptor of the last sub frame could be
876 * a holding descriptor for h/w. If that's the case,
877 * bf->bf_lastfrm won't be in the bf_q.
878 * Make sure we handle bf_q properly here.
881 if (!list_empty(bf_q
)) {
882 bf_lastq
= list_entry(bf_q
->prev
,
883 struct ath_buf
, list
);
884 list_cut_position(&bf_head
,
885 bf_q
, &bf_lastq
->list
);
888 * XXX: if the last subframe only has one
889 * descriptor which is also being used as
890 * a holding descriptor. Then the ath_buf
891 * is not in the bf_q at all.
893 INIT_LIST_HEAD(&bf_head
);
896 ASSERT(!list_empty(bf_q
));
897 list_cut_position(&bf_head
,
898 bf_q
, &bf
->bf_lastfrm
->list
);
903 * complete the acked-ones/xretried ones; update
906 spin_lock_bh(&txq
->axq_lock
);
907 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
908 spin_unlock_bh(&txq
->axq_lock
);
910 /* complete this sub-frame */
911 ath_tx_complete_buf(sc
, bf
, &bf_head
, !txfail
, sendbar
);
914 * retry the un-acked ones
917 * XXX: if the last descriptor is holding descriptor,
918 * in order to requeue the frame to software queue, we
919 * need to allocate a new descriptor and
920 * copy the content of holding descriptor to it.
922 if (bf
->bf_next
== NULL
&&
923 bf_last
->bf_status
& ATH_BUFSTATUS_STALE
) {
926 /* allocate new descriptor */
927 spin_lock_bh(&sc
->sc_txbuflock
);
928 ASSERT(!list_empty((&sc
->sc_txbuf
)));
929 tbf
= list_first_entry(&sc
->sc_txbuf
,
930 struct ath_buf
, list
);
931 list_del(&tbf
->list
);
932 spin_unlock_bh(&sc
->sc_txbuflock
);
934 ATH_TXBUF_RESET(tbf
);
936 /* copy descriptor content */
937 tbf
->bf_mpdu
= bf_last
->bf_mpdu
;
938 tbf
->bf_buf_addr
= bf_last
->bf_buf_addr
;
939 *(tbf
->bf_desc
) = *(bf_last
->bf_desc
);
941 /* link it to the frame */
943 bf_lastq
->bf_desc
->ds_link
=
945 bf
->bf_lastfrm
= tbf
;
946 ath9k_hw_cleartxdesc(sc
->sc_ah
,
947 bf
->bf_lastfrm
->bf_desc
);
949 tbf
->bf_state
= bf_last
->bf_state
;
950 tbf
->bf_lastfrm
= tbf
;
951 ath9k_hw_cleartxdesc(sc
->sc_ah
,
952 tbf
->bf_lastfrm
->bf_desc
);
954 /* copy the DMA context */
956 bf_last
->bf_dmacontext
;
958 list_add_tail(&tbf
->list
, &bf_head
);
961 * Clear descriptor status words for
964 ath9k_hw_cleartxdesc(sc
->sc_ah
,
965 bf
->bf_lastfrm
->bf_desc
);
969 * Put this buffer to the temporary pending
970 * queue to retain ordering
972 list_splice_tail_init(&bf_head
, &bf_pending
);
978 if (tid
->state
& AGGR_CLEANUP
) {
979 /* check to see if we're done with cleaning the h/w queue */
980 spin_lock_bh(&txq
->axq_lock
);
982 if (tid
->baw_head
== tid
->baw_tail
) {
983 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
984 tid
->addba_exchangeattempts
= 0;
985 spin_unlock_bh(&txq
->axq_lock
);
987 tid
->state
&= ~AGGR_CLEANUP
;
989 /* send buffered frames as singles */
990 ath_tx_flush_tid(sc
, tid
);
992 spin_unlock_bh(&txq
->axq_lock
);
998 * prepend un-acked frames to the beginning of the pending frame queue
1000 if (!list_empty(&bf_pending
)) {
1001 spin_lock_bh(&txq
->axq_lock
);
1002 /* Note: we _prepend_, we _do_not_ at to
1003 * the end of the queue ! */
1004 list_splice(&bf_pending
, &tid
->buf_q
);
1005 ath_tx_queue_tid(txq
, tid
);
1006 spin_unlock_bh(&txq
->axq_lock
);
1010 ath_reset(sc
, false);
1015 /* Process completed xmit descriptors from the specified queue */
1017 static int ath_tx_processq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1019 struct ath_hal
*ah
= sc
->sc_ah
;
1020 struct ath_buf
*bf
, *lastbf
, *bf_held
= NULL
;
1021 struct list_head bf_head
;
1022 struct ath_desc
*ds
, *tmp_ds
;
1023 struct sk_buff
*skb
;
1024 struct ieee80211_tx_info
*tx_info
;
1025 struct ath_tx_info_priv
*tx_info_priv
;
1026 int nacked
, txok
, nbad
= 0, isrifs
= 0;
1029 DPRINTF(sc
, ATH_DBG_QUEUE
,
1030 "%s: tx queue %d (%x), link %p\n", __func__
,
1031 txq
->axq_qnum
, ath9k_hw_gettxbuf(sc
->sc_ah
, txq
->axq_qnum
),
1036 spin_lock_bh(&txq
->axq_lock
);
1037 if (list_empty(&txq
->axq_q
)) {
1038 txq
->axq_link
= NULL
;
1039 txq
->axq_linkbuf
= NULL
;
1040 spin_unlock_bh(&txq
->axq_lock
);
1043 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
1046 * There is a race condition that a BH gets scheduled
1047 * after sw writes TxE and before hw re-load the last
1048 * descriptor to get the newly chained one.
1049 * Software must keep the last DONE descriptor as a
1050 * holding descriptor - software does so by marking
1051 * it with the STALE flag.
1054 if (bf
->bf_status
& ATH_BUFSTATUS_STALE
) {
1056 if (list_is_last(&bf_held
->list
, &txq
->axq_q
)) {
1058 * The holding descriptor is the last
1059 * descriptor in queue. It's safe to remove
1060 * the last holding descriptor in BH context.
1062 spin_unlock_bh(&txq
->axq_lock
);
1065 /* Lets work with the next buffer now */
1066 bf
= list_entry(bf_held
->list
.next
,
1067 struct ath_buf
, list
);
1071 lastbf
= bf
->bf_lastbf
;
1072 ds
= lastbf
->bf_desc
; /* NB: last decriptor */
1074 status
= ath9k_hw_txprocdesc(ah
, ds
);
1075 if (status
== -EINPROGRESS
) {
1076 spin_unlock_bh(&txq
->axq_lock
);
1079 if (bf
->bf_desc
== txq
->axq_lastdsWithCTS
)
1080 txq
->axq_lastdsWithCTS
= NULL
;
1081 if (ds
== txq
->axq_gatingds
)
1082 txq
->axq_gatingds
= NULL
;
1085 * Remove ath_buf's of the same transmit unit from txq,
1086 * however leave the last descriptor back as the holding
1087 * descriptor for hw.
1089 lastbf
->bf_status
|= ATH_BUFSTATUS_STALE
;
1090 INIT_LIST_HEAD(&bf_head
);
1092 if (!list_is_singular(&lastbf
->list
))
1093 list_cut_position(&bf_head
,
1094 &txq
->axq_q
, lastbf
->list
.prev
);
1099 txq
->axq_aggr_depth
--;
1101 txok
= (ds
->ds_txstat
.ts_status
== 0);
1103 spin_unlock_bh(&txq
->axq_lock
);
1106 list_del(&bf_held
->list
);
1107 spin_lock_bh(&sc
->sc_txbuflock
);
1108 list_add_tail(&bf_held
->list
, &sc
->sc_txbuf
);
1109 spin_unlock_bh(&sc
->sc_txbuflock
);
1112 if (!bf_isampdu(bf
)) {
1114 * This frame is sent out as a single frame.
1115 * Use hardware retry status for this frame.
1117 bf
->bf_retries
= ds
->ds_txstat
.ts_longretry
;
1118 if (ds
->ds_txstat
.ts_status
& ATH9K_TXERR_XRETRY
)
1119 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
1122 nbad
= ath_tx_num_badfrms(sc
, bf
, txok
);
1125 tx_info
= IEEE80211_SKB_CB(skb
);
1128 tx_info_priv
= (struct ath_tx_info_priv
*) tx_info
->control
.vif
;
1129 if (ds
->ds_txstat
.ts_status
& ATH9K_TXERR_FILT
)
1130 tx_info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1131 if ((ds
->ds_txstat
.ts_status
& ATH9K_TXERR_FILT
) == 0 &&
1132 (bf
->bf_flags
& ATH9K_TXDESC_NOACK
) == 0) {
1133 if (ds
->ds_txstat
.ts_status
== 0)
1136 if (bf_isdata(bf
)) {
1138 tmp_ds
= bf
->bf_rifslast
->bf_desc
;
1141 memcpy(&tx_info_priv
->tx
,
1143 sizeof(tx_info_priv
->tx
));
1144 tx_info_priv
->n_frames
= bf
->bf_nframes
;
1145 tx_info_priv
->n_bad_frames
= nbad
;
1150 * Complete this transmit unit
1153 ath_tx_complete_aggr_rifs(sc
, txq
, bf
, &bf_head
, txok
);
1155 ath_tx_complete_buf(sc
, bf
, &bf_head
, txok
, 0);
1157 /* Wake up mac80211 queue */
1159 spin_lock_bh(&txq
->axq_lock
);
1160 if (txq
->stopped
&& ath_txq_depth(sc
, txq
->axq_qnum
) <=
1163 qnum
= ath_get_mac80211_qnum(txq
->axq_qnum
, sc
);
1165 ieee80211_wake_queue(sc
->hw
, qnum
);
1172 * schedule any pending packets if aggregation is enabled
1174 if (sc
->sc_flags
& SC_OP_TXAGGR
)
1175 ath_txq_schedule(sc
, txq
);
1176 spin_unlock_bh(&txq
->axq_lock
);
1181 static void ath_tx_stopdma(struct ath_softc
*sc
, struct ath_txq
*txq
)
1183 struct ath_hal
*ah
= sc
->sc_ah
;
1185 (void) ath9k_hw_stoptxdma(ah
, txq
->axq_qnum
);
1186 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: tx queue [%u] %x, link %p\n",
1187 __func__
, txq
->axq_qnum
,
1188 ath9k_hw_gettxbuf(ah
, txq
->axq_qnum
), txq
->axq_link
);
1191 /* Drain only the data queues */
1193 static void ath_drain_txdataq(struct ath_softc
*sc
, bool retry_tx
)
1195 struct ath_hal
*ah
= sc
->sc_ah
;
1196 int i
, status
, npend
= 0;
1198 if (!(sc
->sc_flags
& SC_OP_INVALID
)) {
1199 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1200 if (ATH_TXQ_SETUP(sc
, i
)) {
1201 ath_tx_stopdma(sc
, &sc
->sc_txq
[i
]);
1202 /* The TxDMA may not really be stopped.
1203 * Double check the hal tx pending count */
1204 npend
+= ath9k_hw_numtxpending(ah
,
1205 sc
->sc_txq
[i
].axq_qnum
);
1211 /* TxDMA not stopped, reset the hal */
1212 DPRINTF(sc
, ATH_DBG_XMIT
,
1213 "%s: Unable to stop TxDMA. Reset HAL!\n", __func__
);
1215 spin_lock_bh(&sc
->sc_resetlock
);
1216 if (!ath9k_hw_reset(ah
,
1217 sc
->sc_ah
->ah_curchan
,
1218 sc
->sc_ht_info
.tx_chan_width
,
1219 sc
->sc_tx_chainmask
, sc
->sc_rx_chainmask
,
1220 sc
->sc_ht_extprotspacing
, true, &status
)) {
1222 DPRINTF(sc
, ATH_DBG_FATAL
,
1223 "%s: unable to reset hardware; hal status %u\n",
1227 spin_unlock_bh(&sc
->sc_resetlock
);
1230 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1231 if (ATH_TXQ_SETUP(sc
, i
))
1232 ath_tx_draintxq(sc
, &sc
->sc_txq
[i
], retry_tx
);
1236 /* Add a sub-frame to block ack window */
1238 static void ath_tx_addto_baw(struct ath_softc
*sc
,
1239 struct ath_atx_tid
*tid
,
1244 if (bf_isretried(bf
))
1247 index
= ATH_BA_INDEX(tid
->seq_start
, bf
->bf_seqno
);
1248 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
1250 ASSERT(tid
->tx_buf
[cindex
] == NULL
);
1251 tid
->tx_buf
[cindex
] = bf
;
1253 if (index
>= ((tid
->baw_tail
- tid
->baw_head
) &
1254 (ATH_TID_MAX_BUFS
- 1))) {
1255 tid
->baw_tail
= cindex
;
1256 INCR(tid
->baw_tail
, ATH_TID_MAX_BUFS
);
1261 * Function to send an A-MPDU
1262 * NB: must be called with txq lock held
1265 static int ath_tx_send_ampdu(struct ath_softc
*sc
,
1266 struct ath_atx_tid
*tid
,
1267 struct list_head
*bf_head
,
1268 struct ath_tx_control
*txctl
)
1271 struct sk_buff
*skb
;
1272 struct ieee80211_tx_info
*tx_info
;
1273 struct ath_tx_info_priv
*tx_info_priv
;
1275 BUG_ON(list_empty(bf_head
));
1277 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
1278 bf
->bf_state
.bf_type
|= BUF_AMPDU
;
1281 * Do not queue to h/w when any of the following conditions is true:
1282 * - there are pending frames in software queue
1283 * - the TID is currently paused for ADDBA/BAR request
1284 * - seqno is not within block-ack window
1285 * - h/w queue depth exceeds low water mark
1287 if (!list_empty(&tid
->buf_q
) || tid
->paused
||
1288 !BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
) ||
1289 txctl
->txq
->axq_depth
>= ATH_AGGR_MIN_QDEPTH
) {
1291 * Add this frame to software queue for scheduling later
1294 list_splice_tail_init(bf_head
, &tid
->buf_q
);
1295 ath_tx_queue_tid(txctl
->txq
, tid
);
1299 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
1300 tx_info
= IEEE80211_SKB_CB(skb
);
1302 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->control
.vif
;
1303 memcpy(bf
->bf_rcs
, tx_info_priv
->rcs
, 4 * sizeof(tx_info_priv
->rcs
[0]));
1305 /* Add sub-frame to BAW */
1306 ath_tx_addto_baw(sc
, tid
, bf
);
1308 /* Queue to h/w without aggregation */
1310 bf
->bf_lastbf
= bf
->bf_lastfrm
; /* one single frame */
1311 ath_buf_set_rate(sc
, bf
);
1312 ath_tx_txqaddbuf(sc
, txctl
->txq
, bf_head
);
1319 * returns aggr limit based on lowest of the rates
1322 static u32
ath_lookup_rate(struct ath_softc
*sc
,
1324 struct ath_atx_tid
*tid
)
1326 const struct ath9k_rate_table
*rt
= sc
->sc_currates
;
1327 struct sk_buff
*skb
;
1328 struct ieee80211_tx_info
*tx_info
;
1329 struct ath_tx_info_priv
*tx_info_priv
;
1330 u32 max_4ms_framelen
, frame_length
;
1331 u16 aggr_limit
, legacy
= 0, maxampdu
;
1334 skb
= (struct sk_buff
*)bf
->bf_mpdu
;
1335 tx_info
= IEEE80211_SKB_CB(skb
);
1336 tx_info_priv
= (struct ath_tx_info_priv
*)
1337 tx_info
->control
.vif
; /* XXX: HACK! */
1339 tx_info_priv
->rcs
, 4 * sizeof(tx_info_priv
->rcs
[0]));
1342 * Find the lowest frame length among the rate series that will have a
1343 * 4ms transmit duration.
1344 * TODO - TXOP limit needs to be considered.
1346 max_4ms_framelen
= ATH_AMPDU_LIMIT_MAX
;
1348 for (i
= 0; i
< 4; i
++) {
1349 if (bf
->bf_rcs
[i
].tries
) {
1350 frame_length
= bf
->bf_rcs
[i
].max_4ms_framelen
;
1352 if (rt
->info
[bf
->bf_rcs
[i
].rix
].phy
!= PHY_HT
) {
1357 max_4ms_framelen
= min(max_4ms_framelen
, frame_length
);
1362 * limit aggregate size by the minimum rate if rate selected is
1363 * not a probe rate, if rate selected is a probe rate then
1364 * avoid aggregation of this packet.
1366 if (tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
|| legacy
)
1369 aggr_limit
= min(max_4ms_framelen
,
1370 (u32
)ATH_AMPDU_LIMIT_DEFAULT
);
1373 * h/w can accept aggregates upto 16 bit lengths (65535).
1374 * The IE, however can hold upto 65536, which shows up here
1375 * as zero. Ignore 65536 since we are constrained by hw.
1377 maxampdu
= tid
->an
->maxampdu
;
1379 aggr_limit
= min(aggr_limit
, maxampdu
);
1385 * returns the number of delimiters to be added to
1386 * meet the minimum required mpdudensity.
1387 * caller should make sure that the rate is HT rate .
1390 static int ath_compute_num_delims(struct ath_softc
*sc
,
1391 struct ath_atx_tid
*tid
,
1395 const struct ath9k_rate_table
*rt
= sc
->sc_currates
;
1396 u32 nsymbits
, nsymbols
, mpdudensity
;
1399 int width
, half_gi
, ndelim
, mindelim
;
1401 /* Select standard number of delimiters based on frame length alone */
1402 ndelim
= ATH_AGGR_GET_NDELIM(frmlen
);
1405 * If encryption enabled, hardware requires some more padding between
1407 * TODO - this could be improved to be dependent on the rate.
1408 * The hardware can keep up at lower rates, but not higher rates
1410 if (bf
->bf_keytype
!= ATH9K_KEY_TYPE_CLEAR
)
1411 ndelim
+= ATH_AGGR_ENCRYPTDELIM
;
1414 * Convert desired mpdu density from microeconds to bytes based
1415 * on highest rate in rate series (i.e. first rate) to determine
1416 * required minimum length for subframe. Take into account
1417 * whether high rate is 20 or 40Mhz and half or full GI.
1419 mpdudensity
= tid
->an
->mpdudensity
;
1422 * If there is no mpdu density restriction, no further calculation
1425 if (mpdudensity
== 0)
1428 rix
= bf
->bf_rcs
[0].rix
;
1429 flags
= bf
->bf_rcs
[0].flags
;
1430 rc
= rt
->info
[rix
].rateCode
;
1431 width
= (flags
& ATH_RC_CW40_FLAG
) ? 1 : 0;
1432 half_gi
= (flags
& ATH_RC_SGI_FLAG
) ? 1 : 0;
1435 nsymbols
= NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity
);
1437 nsymbols
= NUM_SYMBOLS_PER_USEC(mpdudensity
);
1442 nsymbits
= bits_per_symbol
[HT_RC_2_MCS(rc
)][width
];
1443 minlen
= (nsymbols
* nsymbits
) / BITS_PER_BYTE
;
1445 /* Is frame shorter than required minimum length? */
1446 if (frmlen
< minlen
) {
1447 /* Get the minimum number of delimiters required. */
1448 mindelim
= (minlen
- frmlen
) / ATH_AGGR_DELIM_SZ
;
1449 ndelim
= max(mindelim
, ndelim
);
1456 * For aggregation from software buffer queue.
1457 * NB: must be called with txq lock held
1460 static enum ATH_AGGR_STATUS
ath_tx_form_aggr(struct ath_softc
*sc
,
1461 struct ath_atx_tid
*tid
,
1462 struct list_head
*bf_q
,
1463 struct ath_buf
**bf_last
,
1464 struct aggr_rifs_param
*param
,
1467 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1468 struct ath_buf
*bf
, *tbf
, *bf_first
, *bf_prev
= NULL
;
1469 struct list_head bf_head
;
1470 int rl
= 0, nframes
= 0, ndelim
;
1471 u16 aggr_limit
= 0, al
= 0, bpad
= 0,
1472 al_delta
, h_baw
= tid
->baw_size
/ 2;
1473 enum ATH_AGGR_STATUS status
= ATH_AGGR_DONE
;
1474 int prev_al
= 0, is_ds_rate
= 0;
1475 INIT_LIST_HEAD(&bf_head
);
1477 BUG_ON(list_empty(&tid
->buf_q
));
1479 bf_first
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1482 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1485 * do not step over block-ack window
1487 if (!BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
)) {
1488 status
= ATH_AGGR_BAW_CLOSED
;
1493 aggr_limit
= ath_lookup_rate(sc
, bf
, tid
);
1496 * Is rate dual stream
1499 (bf
->bf_rcs
[0].flags
& ATH_RC_DS_FLAG
) ? 1 : 0;
1503 * do not exceed aggregation limit
1505 al_delta
= ATH_AGGR_DELIM_SZ
+ bf
->bf_frmlen
;
1507 if (nframes
&& (aggr_limit
<
1508 (al
+ bpad
+ al_delta
+ prev_al
))) {
1509 status
= ATH_AGGR_LIMITED
;
1514 * do not exceed subframe limit
1516 if ((nframes
+ *prev_frames
) >=
1517 min((int)h_baw
, ATH_AMPDU_SUBFRAME_DEFAULT
)) {
1518 status
= ATH_AGGR_LIMITED
;
1523 * add padding for previous frame to aggregation length
1525 al
+= bpad
+ al_delta
;
1528 * Get the delimiters needed to meet the MPDU
1529 * density for this node.
1531 ndelim
= ath_compute_num_delims(sc
, tid
, bf_first
, bf
->bf_frmlen
);
1533 bpad
= PADBYTES(al_delta
) + (ndelim
<< 2);
1536 bf
->bf_lastfrm
->bf_desc
->ds_link
= 0;
1539 * this packet is part of an aggregate
1540 * - remove all descriptors belonging to this frame from
1542 * - add it to block ack window
1543 * - set up descriptors for aggregation
1545 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
1546 ath_tx_addto_baw(sc
, tid
, bf
);
1548 list_for_each_entry(tbf
, &bf_head
, list
) {
1549 ath9k_hw_set11n_aggr_middle(sc
->sc_ah
,
1550 tbf
->bf_desc
, ndelim
);
1554 * link buffers of this frame to the aggregate
1556 list_splice_tail_init(&bf_head
, bf_q
);
1560 bf_prev
->bf_next
= bf
;
1561 bf_prev
->bf_lastfrm
->bf_desc
->ds_link
= bf
->bf_daddr
;
1567 * terminate aggregation on a small packet boundary
1569 if (bf
->bf_frmlen
< ATH_AGGR_MINPLEN
) {
1570 status
= ATH_AGGR_SHORTPKT
;
1574 } while (!list_empty(&tid
->buf_q
));
1576 bf_first
->bf_al
= al
;
1577 bf_first
->bf_nframes
= nframes
;
1584 * process pending frames possibly doing a-mpdu aggregation
1585 * NB: must be called with txq lock held
1588 static void ath_tx_sched_aggr(struct ath_softc
*sc
,
1589 struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
1591 struct ath_buf
*bf
, *tbf
, *bf_last
, *bf_lastaggr
= NULL
;
1592 enum ATH_AGGR_STATUS status
;
1593 struct list_head bf_q
;
1594 struct aggr_rifs_param param
= {0, 0, 0, 0, NULL
};
1595 int prev_frames
= 0;
1598 if (list_empty(&tid
->buf_q
))
1601 INIT_LIST_HEAD(&bf_q
);
1603 status
= ath_tx_form_aggr(sc
, tid
, &bf_q
, &bf_lastaggr
, ¶m
,
1607 * no frames picked up to be aggregated; block-ack
1608 * window is not open
1610 if (list_empty(&bf_q
))
1613 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
1614 bf_last
= list_entry(bf_q
.prev
, struct ath_buf
, list
);
1615 bf
->bf_lastbf
= bf_last
;
1618 * if only one frame, send as non-aggregate
1620 if (bf
->bf_nframes
== 1) {
1621 ASSERT(bf
->bf_lastfrm
== bf_last
);
1623 bf
->bf_state
.bf_type
&= ~BUF_AGGR
;
1625 * clear aggr bits for every descriptor
1626 * XXX TODO: is there a way to optimize it?
1628 list_for_each_entry(tbf
, &bf_q
, list
) {
1629 ath9k_hw_clr11n_aggr(sc
->sc_ah
, tbf
->bf_desc
);
1632 ath_buf_set_rate(sc
, bf
);
1633 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
1638 * setup first desc with rate and aggr info
1640 bf
->bf_state
.bf_type
|= BUF_AGGR
;
1641 ath_buf_set_rate(sc
, bf
);
1642 ath9k_hw_set11n_aggr_first(sc
->sc_ah
, bf
->bf_desc
, bf
->bf_al
);
1645 * anchor last frame of aggregate correctly
1647 ASSERT(bf_lastaggr
);
1648 ASSERT(bf_lastaggr
->bf_lastfrm
== bf_last
);
1650 ath9k_hw_set11n_aggr_last(sc
->sc_ah
, tbf
->bf_desc
);
1652 /* XXX: We don't enter into this loop, consider removing this */
1653 while (!list_empty(&bf_q
) && !list_is_last(&tbf
->list
, &bf_q
)) {
1654 tbf
= list_entry(tbf
->list
.next
, struct ath_buf
, list
);
1655 ath9k_hw_set11n_aggr_last(sc
->sc_ah
, tbf
->bf_desc
);
1658 txq
->axq_aggr_depth
++;
1661 * Normal aggregate, queue to hardware
1663 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
1665 } while (txq
->axq_depth
< ATH_AGGR_MIN_QDEPTH
&&
1666 status
!= ATH_AGGR_BAW_CLOSED
);
1669 /* Called with txq lock held */
1671 static void ath_tid_drain(struct ath_softc
*sc
,
1672 struct ath_txq
*txq
,
1673 struct ath_atx_tid
*tid
)
1677 struct list_head bf_head
;
1678 INIT_LIST_HEAD(&bf_head
);
1681 if (list_empty(&tid
->buf_q
))
1683 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
1685 list_cut_position(&bf_head
, &tid
->buf_q
, &bf
->bf_lastfrm
->list
);
1687 /* update baw for software retried frame */
1688 if (bf_isretried(bf
))
1689 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
1692 * do not indicate packets while holding txq spinlock.
1693 * unlock is intentional here
1695 spin_unlock(&txq
->axq_lock
);
1697 /* complete this sub-frame */
1698 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
1700 spin_lock(&txq
->axq_lock
);
1704 * TODO: For frame(s) that are in the retry state, we will reuse the
1705 * sequence number(s) without setting the retry bit. The
1706 * alternative is to give up on these and BAR the receiver's window
1709 tid
->seq_next
= tid
->seq_start
;
1710 tid
->baw_tail
= tid
->baw_head
;
1714 * Drain all pending buffers
1715 * NB: must be called with txq lock held
1718 static void ath_txq_drain_pending_buffers(struct ath_softc
*sc
,
1719 struct ath_txq
*txq
)
1721 struct ath_atx_ac
*ac
, *ac_tmp
;
1722 struct ath_atx_tid
*tid
, *tid_tmp
;
1724 list_for_each_entry_safe(ac
, ac_tmp
, &txq
->axq_acq
, list
) {
1725 list_del(&ac
->list
);
1727 list_for_each_entry_safe(tid
, tid_tmp
, &ac
->tid_q
, list
) {
1728 list_del(&tid
->list
);
1730 ath_tid_drain(sc
, txq
, tid
);
1735 static void ath_tx_setup_buffer(struct ath_softc
*sc
, struct ath_buf
*bf
,
1736 struct sk_buff
*skb
, struct scatterlist
*sg
,
1737 struct ath_tx_control
*txctl
)
1739 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1740 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1741 struct ath_tx_info_priv
*tx_info_priv
;
1742 struct ath_rc_series
*rcs
;
1746 tx_info_priv
= (struct ath_tx_info_priv
*)tx_info
->control
.vif
;
1747 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1748 fc
= hdr
->frame_control
;
1749 rcs
= tx_info_priv
->rcs
;
1751 ATH_TXBUF_RESET(bf
);
1755 bf
->bf_frmlen
= skb
->len
+ FCS_LEN
- (hdrlen
& 3);
1757 ieee80211_is_data(fc
) ?
1758 (bf
->bf_state
.bf_type
|= BUF_DATA
) :
1759 (bf
->bf_state
.bf_type
&= ~BUF_DATA
);
1760 ieee80211_is_back_req(fc
) ?
1761 (bf
->bf_state
.bf_type
|= BUF_BAR
) :
1762 (bf
->bf_state
.bf_type
&= ~BUF_BAR
);
1763 ieee80211_is_pspoll(fc
) ?
1764 (bf
->bf_state
.bf_type
|= BUF_PSPOLL
) :
1765 (bf
->bf_state
.bf_type
&= ~BUF_PSPOLL
);
1766 (sc
->sc_flags
& SC_OP_PREAMBLE_SHORT
) ?
1767 (bf
->bf_state
.bf_type
|= BUF_SHORT_PREAMBLE
) :
1768 (bf
->bf_state
.bf_type
&= ~BUF_SHORT_PREAMBLE
);
1769 (sc
->hw
->conf
.ht
.enabled
&&
1770 (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
)) ?
1771 (bf
->bf_state
.bf_type
|= BUF_HT
) :
1772 (bf
->bf_state
.bf_type
&= ~BUF_HT
);
1774 bf
->bf_flags
= setup_tx_flags(sc
, skb
, txctl
->txq
);
1778 bf
->bf_keytype
= get_hw_crypto_keytype(skb
);
1780 if (bf
->bf_keytype
!= ATH9K_KEY_TYPE_CLEAR
) {
1781 bf
->bf_frmlen
+= tx_info
->control
.hw_key
->icv_len
;
1782 bf
->bf_keyix
= tx_info
->control
.hw_key
->hw_key_idx
;
1784 bf
->bf_keyix
= ATH9K_TXKEYIX_INVALID
;
1789 setup_rate_retries(sc
, skb
);
1791 bf
->bf_rcs
[0] = rcs
[0];
1792 bf
->bf_rcs
[1] = rcs
[1];
1793 bf
->bf_rcs
[2] = rcs
[2];
1794 bf
->bf_rcs
[3] = rcs
[3];
1796 /* Assign seqno, tidno */
1798 if (bf_isht(bf
) && (sc
->sc_flags
& SC_OP_TXAGGR
))
1799 assign_aggr_tid_seqno(skb
, bf
);
1804 bf
->bf_dmacontext
= pci_map_single(sc
->pdev
, skb
->data
,
1805 skb
->len
, PCI_DMA_TODEVICE
);
1806 bf
->bf_buf_addr
= bf
->bf_dmacontext
;
1809 /* FIXME: tx power */
1810 static void ath_tx_start_dma(struct ath_softc
*sc
, struct ath_buf
*bf
,
1811 struct scatterlist
*sg
, u32 n_sg
,
1812 struct ath_tx_control
*txctl
)
1814 struct sk_buff
*skb
= (struct sk_buff
*)bf
->bf_mpdu
;
1815 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1816 struct ath_node
*an
= NULL
;
1817 struct list_head bf_head
;
1818 struct ath_desc
*ds
;
1819 struct ath_atx_tid
*tid
;
1820 struct ath_hal
*ah
= sc
->sc_ah
;
1823 frm_type
= get_hw_packet_type(skb
);
1825 INIT_LIST_HEAD(&bf_head
);
1826 list_add_tail(&bf
->list
, &bf_head
);
1828 /* setup descriptor */
1832 ds
->ds_data
= bf
->bf_buf_addr
;
1834 /* Formulate first tx descriptor with tx controls */
1836 ath9k_hw_set11n_txdesc(ah
, ds
, bf
->bf_frmlen
, frm_type
, MAX_RATE_POWER
,
1837 bf
->bf_keyix
, bf
->bf_keytype
, bf
->bf_flags
);
1839 ath9k_hw_filltxdesc(ah
, ds
,
1840 sg_dma_len(sg
), /* segment length */
1841 true, /* first segment */
1842 (n_sg
== 1) ? true : false, /* last segment */
1843 ds
); /* first descriptor */
1845 bf
->bf_lastfrm
= bf
;
1847 spin_lock_bh(&txctl
->txq
->axq_lock
);
1849 if (bf_isht(bf
) && (sc
->sc_flags
& SC_OP_TXAGGR
) &&
1850 tx_info
->control
.sta
) {
1851 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
1852 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
1854 if (ath_aggr_query(sc
, an
, bf
->bf_tidno
)) {
1856 * Try aggregation if it's a unicast data frame
1857 * and the destination is HT capable.
1859 ath_tx_send_ampdu(sc
, tid
, &bf_head
, txctl
);
1862 * Send this frame as regular when ADDBA
1863 * exchange is neither complete nor pending.
1865 ath_tx_send_normal(sc
, txctl
->txq
,
1872 ath_buf_set_rate(sc
, bf
);
1873 ath_tx_txqaddbuf(sc
, txctl
->txq
, &bf_head
);
1876 spin_unlock_bh(&txctl
->txq
->axq_lock
);
1879 int ath_tx_start(struct ath_softc
*sc
, struct sk_buff
*skb
,
1880 struct ath_tx_control
*txctl
)
1883 struct scatterlist sg
;
1885 /* Check if a tx buffer is available */
1887 bf
= ath_tx_get_buffer(sc
);
1889 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: TX buffers are full\n",
1894 ath_tx_setup_buffer(sc
, bf
, skb
, &sg
, txctl
);
1898 memset(&sg
, 0, sizeof(struct scatterlist
));
1899 sg_dma_address(&sg
) = bf
->bf_dmacontext
;
1900 sg_dma_len(&sg
) = skb
->len
;
1902 ath_tx_start_dma(sc
, bf
, &sg
, 1, txctl
);
1907 /* Initialize TX queue and h/w */
1909 int ath_tx_init(struct ath_softc
*sc
, int nbufs
)
1914 spin_lock_init(&sc
->sc_txbuflock
);
1916 /* Setup tx descriptors */
1917 error
= ath_descdma_setup(sc
, &sc
->sc_txdma
, &sc
->sc_txbuf
,
1920 DPRINTF(sc
, ATH_DBG_FATAL
,
1921 "%s: failed to allocate tx descriptors: %d\n",
1926 /* XXX allocate beacon state together with vap */
1927 error
= ath_descdma_setup(sc
, &sc
->sc_bdma
, &sc
->sc_bbuf
,
1928 "beacon", ATH_BCBUF
, 1);
1930 DPRINTF(sc
, ATH_DBG_FATAL
,
1931 "%s: failed to allocate "
1932 "beacon descripotrs: %d\n",
1945 /* Reclaim all tx queue resources */
1947 int ath_tx_cleanup(struct ath_softc
*sc
)
1949 /* cleanup beacon descriptors */
1950 if (sc
->sc_bdma
.dd_desc_len
!= 0)
1951 ath_descdma_cleanup(sc
, &sc
->sc_bdma
, &sc
->sc_bbuf
);
1953 /* cleanup tx descriptors */
1954 if (sc
->sc_txdma
.dd_desc_len
!= 0)
1955 ath_descdma_cleanup(sc
, &sc
->sc_txdma
, &sc
->sc_txbuf
);
1960 /* Setup a h/w transmit queue */
1962 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
)
1964 struct ath_hal
*ah
= sc
->sc_ah
;
1965 struct ath9k_tx_queue_info qi
;
1968 memset(&qi
, 0, sizeof(qi
));
1969 qi
.tqi_subtype
= subtype
;
1970 qi
.tqi_aifs
= ATH9K_TXQ_USEDEFAULT
;
1971 qi
.tqi_cwmin
= ATH9K_TXQ_USEDEFAULT
;
1972 qi
.tqi_cwmax
= ATH9K_TXQ_USEDEFAULT
;
1973 qi
.tqi_physCompBuf
= 0;
1976 * Enable interrupts only for EOL and DESC conditions.
1977 * We mark tx descriptors to receive a DESC interrupt
1978 * when a tx queue gets deep; otherwise waiting for the
1979 * EOL to reap descriptors. Note that this is done to
1980 * reduce interrupt load and this only defers reaping
1981 * descriptors, never transmitting frames. Aside from
1982 * reducing interrupts this also permits more concurrency.
1983 * The only potential downside is if the tx queue backs
1984 * up in which case the top half of the kernel may backup
1985 * due to a lack of tx descriptors.
1987 * The UAPSD queue is an exception, since we take a desc-
1988 * based intr on the EOSP frames.
1990 if (qtype
== ATH9K_TX_QUEUE_UAPSD
)
1991 qi
.tqi_qflags
= TXQ_FLAG_TXDESCINT_ENABLE
;
1993 qi
.tqi_qflags
= TXQ_FLAG_TXEOLINT_ENABLE
|
1994 TXQ_FLAG_TXDESCINT_ENABLE
;
1995 qnum
= ath9k_hw_setuptxqueue(ah
, qtype
, &qi
);
1998 * NB: don't print a message, this happens
1999 * normally on parts with too few tx queues
2003 if (qnum
>= ARRAY_SIZE(sc
->sc_txq
)) {
2004 DPRINTF(sc
, ATH_DBG_FATAL
,
2005 "%s: hal qnum %u out of range, max %u!\n",
2006 __func__
, qnum
, (unsigned int)ARRAY_SIZE(sc
->sc_txq
));
2007 ath9k_hw_releasetxqueue(ah
, qnum
);
2010 if (!ATH_TXQ_SETUP(sc
, qnum
)) {
2011 struct ath_txq
*txq
= &sc
->sc_txq
[qnum
];
2013 txq
->axq_qnum
= qnum
;
2014 txq
->axq_link
= NULL
;
2015 INIT_LIST_HEAD(&txq
->axq_q
);
2016 INIT_LIST_HEAD(&txq
->axq_acq
);
2017 spin_lock_init(&txq
->axq_lock
);
2019 txq
->axq_aggr_depth
= 0;
2020 txq
->axq_totalqueued
= 0;
2021 txq
->axq_linkbuf
= NULL
;
2022 sc
->sc_txqsetup
|= 1<<qnum
;
2024 return &sc
->sc_txq
[qnum
];
2027 /* Reclaim resources for a setup queue */
2029 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
)
2031 ath9k_hw_releasetxqueue(sc
->sc_ah
, txq
->axq_qnum
);
2032 sc
->sc_txqsetup
&= ~(1<<txq
->axq_qnum
);
2036 * Setup a hardware data transmit queue for the specified
2037 * access control. The hal may not support all requested
2038 * queues in which case it will return a reference to a
2039 * previously setup queue. We record the mapping from ac's
2040 * to h/w queues for use by ath_tx_start and also track
2041 * the set of h/w queues being used to optimize work in the
2042 * transmit interrupt handler and related routines.
2045 int ath_tx_setup(struct ath_softc
*sc
, int haltype
)
2047 struct ath_txq
*txq
;
2049 if (haltype
>= ARRAY_SIZE(sc
->sc_haltype2q
)) {
2050 DPRINTF(sc
, ATH_DBG_FATAL
,
2051 "%s: HAL AC %u out of range, max %zu!\n",
2052 __func__
, haltype
, ARRAY_SIZE(sc
->sc_haltype2q
));
2055 txq
= ath_txq_setup(sc
, ATH9K_TX_QUEUE_DATA
, haltype
);
2057 sc
->sc_haltype2q
[haltype
] = txq
->axq_qnum
;
2063 int ath_tx_get_qnum(struct ath_softc
*sc
, int qtype
, int haltype
)
2068 case ATH9K_TX_QUEUE_DATA
:
2069 if (haltype
>= ARRAY_SIZE(sc
->sc_haltype2q
)) {
2070 DPRINTF(sc
, ATH_DBG_FATAL
,
2071 "%s: HAL AC %u out of range, max %zu!\n",
2073 haltype
, ARRAY_SIZE(sc
->sc_haltype2q
));
2076 qnum
= sc
->sc_haltype2q
[haltype
];
2078 case ATH9K_TX_QUEUE_BEACON
:
2079 qnum
= sc
->sc_bhalq
;
2081 case ATH9K_TX_QUEUE_CAB
:
2082 qnum
= sc
->sc_cabq
->axq_qnum
;
2090 /* Get a transmit queue, if available */
2092 struct ath_txq
*ath_test_get_txq(struct ath_softc
*sc
, struct sk_buff
*skb
)
2094 struct ath_txq
*txq
= NULL
;
2097 qnum
= ath_get_hal_qnum(skb_get_queue_mapping(skb
), sc
);
2098 txq
= &sc
->sc_txq
[qnum
];
2100 spin_lock_bh(&txq
->axq_lock
);
2102 /* Try to avoid running out of descriptors */
2103 if (txq
->axq_depth
>= (ATH_TXBUF
- 20)) {
2104 DPRINTF(sc
, ATH_DBG_FATAL
,
2105 "%s: TX queue: %d is full, depth: %d\n",
2106 __func__
, qnum
, txq
->axq_depth
);
2107 ieee80211_stop_queue(sc
->hw
, skb_get_queue_mapping(skb
));
2109 spin_unlock_bh(&txq
->axq_lock
);
2113 spin_unlock_bh(&txq
->axq_lock
);
2118 /* Update parameters for a transmit queue */
2120 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
2121 struct ath9k_tx_queue_info
*qinfo
)
2123 struct ath_hal
*ah
= sc
->sc_ah
;
2125 struct ath9k_tx_queue_info qi
;
2127 if (qnum
== sc
->sc_bhalq
) {
2129 * XXX: for beacon queue, we just save the parameter.
2130 * It will be picked up by ath_beaconq_config when
2133 sc
->sc_beacon_qi
= *qinfo
;
2137 ASSERT(sc
->sc_txq
[qnum
].axq_qnum
== qnum
);
2139 ath9k_hw_get_txq_props(ah
, qnum
, &qi
);
2140 qi
.tqi_aifs
= qinfo
->tqi_aifs
;
2141 qi
.tqi_cwmin
= qinfo
->tqi_cwmin
;
2142 qi
.tqi_cwmax
= qinfo
->tqi_cwmax
;
2143 qi
.tqi_burstTime
= qinfo
->tqi_burstTime
;
2144 qi
.tqi_readyTime
= qinfo
->tqi_readyTime
;
2146 if (!ath9k_hw_set_txq_props(ah
, qnum
, &qi
)) {
2147 DPRINTF(sc
, ATH_DBG_FATAL
,
2148 "%s: unable to update hardware queue %u!\n",
2152 ath9k_hw_resettxqueue(ah
, qnum
); /* push to h/w */
2158 int ath_cabq_update(struct ath_softc
*sc
)
2160 struct ath9k_tx_queue_info qi
;
2161 int qnum
= sc
->sc_cabq
->axq_qnum
;
2162 struct ath_beacon_config conf
;
2164 ath9k_hw_get_txq_props(sc
->sc_ah
, qnum
, &qi
);
2166 * Ensure the readytime % is within the bounds.
2168 if (sc
->sc_config
.cabqReadytime
< ATH9K_READY_TIME_LO_BOUND
)
2169 sc
->sc_config
.cabqReadytime
= ATH9K_READY_TIME_LO_BOUND
;
2170 else if (sc
->sc_config
.cabqReadytime
> ATH9K_READY_TIME_HI_BOUND
)
2171 sc
->sc_config
.cabqReadytime
= ATH9K_READY_TIME_HI_BOUND
;
2173 ath_get_beaconconfig(sc
, ATH_IF_ID_ANY
, &conf
);
2175 (conf
.beacon_interval
* sc
->sc_config
.cabqReadytime
) / 100;
2176 ath_txq_update(sc
, qnum
, &qi
);
2181 /* Deferred processing of transmit interrupt */
2183 void ath_tx_tasklet(struct ath_softc
*sc
)
2186 u32 qcumask
= ((1 << ATH9K_NUM_TX_QUEUES
) - 1);
2188 ath9k_hw_gettxintrtxqs(sc
->sc_ah
, &qcumask
);
2191 * Process each active queue.
2193 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2194 if (ATH_TXQ_SETUP(sc
, i
) && (qcumask
& (1 << i
)))
2195 ath_tx_processq(sc
, &sc
->sc_txq
[i
]);
2199 void ath_tx_draintxq(struct ath_softc
*sc
,
2200 struct ath_txq
*txq
, bool retry_tx
)
2202 struct ath_buf
*bf
, *lastbf
;
2203 struct list_head bf_head
;
2205 INIT_LIST_HEAD(&bf_head
);
2208 * NB: this assumes output has been stopped and
2209 * we do not need to block ath_tx_tasklet
2212 spin_lock_bh(&txq
->axq_lock
);
2214 if (list_empty(&txq
->axq_q
)) {
2215 txq
->axq_link
= NULL
;
2216 txq
->axq_linkbuf
= NULL
;
2217 spin_unlock_bh(&txq
->axq_lock
);
2221 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
2223 if (bf
->bf_status
& ATH_BUFSTATUS_STALE
) {
2224 list_del(&bf
->list
);
2225 spin_unlock_bh(&txq
->axq_lock
);
2227 spin_lock_bh(&sc
->sc_txbuflock
);
2228 list_add_tail(&bf
->list
, &sc
->sc_txbuf
);
2229 spin_unlock_bh(&sc
->sc_txbuflock
);
2233 lastbf
= bf
->bf_lastbf
;
2235 lastbf
->bf_desc
->ds_txstat
.ts_flags
=
2236 ATH9K_TX_SW_ABORTED
;
2238 /* remove ath_buf's of the same mpdu from txq */
2239 list_cut_position(&bf_head
, &txq
->axq_q
, &lastbf
->list
);
2242 spin_unlock_bh(&txq
->axq_lock
);
2245 ath_tx_complete_aggr_rifs(sc
, txq
, bf
, &bf_head
, 0);
2247 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
2250 /* flush any pending frames if aggregation is enabled */
2251 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2253 spin_lock_bh(&txq
->axq_lock
);
2254 ath_txq_drain_pending_buffers(sc
, txq
);
2255 spin_unlock_bh(&txq
->axq_lock
);
2260 /* Drain the transmit queues and reclaim resources */
2262 void ath_draintxq(struct ath_softc
*sc
, bool retry_tx
)
2264 /* stop beacon queue. The beacon will be freed when
2265 * we go to INIT state */
2266 if (!(sc
->sc_flags
& SC_OP_INVALID
)) {
2267 (void) ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->sc_bhalq
);
2268 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: beacon queue %x\n", __func__
,
2269 ath9k_hw_gettxbuf(sc
->sc_ah
, sc
->sc_bhalq
));
2272 ath_drain_txdataq(sc
, retry_tx
);
2275 u32
ath_txq_depth(struct ath_softc
*sc
, int qnum
)
2277 return sc
->sc_txq
[qnum
].axq_depth
;
2280 u32
ath_txq_aggr_depth(struct ath_softc
*sc
, int qnum
)
2282 return sc
->sc_txq
[qnum
].axq_aggr_depth
;
2285 bool ath_tx_aggr_check(struct ath_softc
*sc
, struct ath_node
*an
, u8 tidno
)
2287 struct ath_atx_tid
*txtid
;
2289 if (!(sc
->sc_flags
& SC_OP_TXAGGR
))
2292 txtid
= ATH_AN_2_TID(an
, tidno
);
2294 if (!(txtid
->state
& AGGR_ADDBA_COMPLETE
)) {
2295 if (!(txtid
->state
& AGGR_ADDBA_PROGRESS
) &&
2296 (txtid
->addba_exchangeattempts
< ADDBA_EXCHANGE_ATTEMPTS
)) {
2297 txtid
->addba_exchangeattempts
++;
2305 /* Start TX aggregation */
2307 int ath_tx_aggr_start(struct ath_softc
*sc
, struct ieee80211_sta
*sta
,
2310 struct ath_atx_tid
*txtid
;
2311 struct ath_node
*an
;
2313 an
= (struct ath_node
*)sta
->drv_priv
;
2315 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2316 txtid
= ATH_AN_2_TID(an
, tid
);
2317 txtid
->state
|= AGGR_ADDBA_PROGRESS
;
2318 ath_tx_pause_tid(sc
, txtid
);
2324 /* Stop tx aggregation */
2326 int ath_tx_aggr_stop(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
2328 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
2330 ath_tx_aggr_teardown(sc
, an
, tid
);
2334 /* Resume tx aggregation */
2336 void ath_tx_aggr_resume(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
2338 struct ath_atx_tid
*txtid
;
2339 struct ath_node
*an
;
2341 an
= (struct ath_node
*)sta
->drv_priv
;
2343 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
2344 txtid
= ATH_AN_2_TID(an
, tid
);
2346 IEEE80211_MIN_AMPDU_BUF
<< sta
->ht_cap
.ampdu_factor
;
2347 txtid
->state
|= AGGR_ADDBA_COMPLETE
;
2348 txtid
->state
&= ~AGGR_ADDBA_PROGRESS
;
2349 ath_tx_resume_tid(sc
, txtid
);
2354 * Performs transmit side cleanup when TID changes from aggregated to
2356 * - Pause the TID and mark cleanup in progress
2357 * - Discard all retry frames from the s/w queue.
2360 void ath_tx_aggr_teardown(struct ath_softc
*sc
, struct ath_node
*an
, u8 tid
)
2362 struct ath_atx_tid
*txtid
= ATH_AN_2_TID(an
, tid
);
2363 struct ath_txq
*txq
= &sc
->sc_txq
[txtid
->ac
->qnum
];
2365 struct list_head bf_head
;
2366 INIT_LIST_HEAD(&bf_head
);
2368 DPRINTF(sc
, ATH_DBG_AGGR
, "%s: teardown TX aggregation\n", __func__
);
2370 if (txtid
->state
& AGGR_CLEANUP
) /* cleanup is in progress */
2373 if (!(txtid
->state
& AGGR_ADDBA_COMPLETE
)) {
2374 txtid
->addba_exchangeattempts
= 0;
2378 /* TID must be paused first */
2379 ath_tx_pause_tid(sc
, txtid
);
2381 /* drop all software retried frames and mark this TID */
2382 spin_lock_bh(&txq
->axq_lock
);
2383 while (!list_empty(&txtid
->buf_q
)) {
2384 bf
= list_first_entry(&txtid
->buf_q
, struct ath_buf
, list
);
2385 if (!bf_isretried(bf
)) {
2387 * NB: it's based on the assumption that
2388 * software retried frame will always stay
2389 * at the head of software queue.
2393 list_cut_position(&bf_head
,
2394 &txtid
->buf_q
, &bf
->bf_lastfrm
->list
);
2395 ath_tx_update_baw(sc
, txtid
, bf
->bf_seqno
);
2397 /* complete this sub-frame */
2398 ath_tx_complete_buf(sc
, bf
, &bf_head
, 0, 0);
2401 if (txtid
->baw_head
!= txtid
->baw_tail
) {
2402 spin_unlock_bh(&txq
->axq_lock
);
2403 txtid
->state
|= AGGR_CLEANUP
;
2405 txtid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2406 txtid
->addba_exchangeattempts
= 0;
2407 spin_unlock_bh(&txq
->axq_lock
);
2408 ath_tx_flush_tid(sc
, txtid
);
2413 * Tx scheduling logic
2414 * NB: must be called with txq lock held
2417 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
)
2419 struct ath_atx_ac
*ac
;
2420 struct ath_atx_tid
*tid
;
2422 /* nothing to schedule */
2423 if (list_empty(&txq
->axq_acq
))
2426 * get the first node/ac pair on the queue
2428 ac
= list_first_entry(&txq
->axq_acq
, struct ath_atx_ac
, list
);
2429 list_del(&ac
->list
);
2433 * process a single tid per destination
2436 /* nothing to schedule */
2437 if (list_empty(&ac
->tid_q
))
2440 tid
= list_first_entry(&ac
->tid_q
, struct ath_atx_tid
, list
);
2441 list_del(&tid
->list
);
2444 if (tid
->paused
) /* check next tid to keep h/w busy */
2447 if ((txq
->axq_depth
% 2) == 0)
2448 ath_tx_sched_aggr(sc
, txq
, tid
);
2451 * add tid to round-robin queue if more frames
2452 * are pending for the tid
2454 if (!list_empty(&tid
->buf_q
))
2455 ath_tx_queue_tid(txq
, tid
);
2457 /* only schedule one TID at a time */
2459 } while (!list_empty(&ac
->tid_q
));
2462 * schedule AC if more TIDs need processing
2464 if (!list_empty(&ac
->tid_q
)) {
2466 * add dest ac to txq if not already added
2470 list_add_tail(&ac
->list
, &txq
->axq_acq
);
2475 /* Initialize per-node transmit state */
2477 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
)
2479 struct ath_atx_tid
*tid
;
2480 struct ath_atx_ac
*ac
;
2484 * Init per tid tx state
2486 for (tidno
= 0, tid
= &an
->an_aggr
.tx
.tid
[tidno
];
2487 tidno
< WME_NUM_TID
;
2491 tid
->seq_start
= tid
->seq_next
= 0;
2492 tid
->baw_size
= WME_MAX_BA
;
2493 tid
->baw_head
= tid
->baw_tail
= 0;
2495 tid
->paused
= false;
2496 tid
->state
&= ~AGGR_CLEANUP
;
2497 INIT_LIST_HEAD(&tid
->buf_q
);
2499 acno
= TID_TO_WME_AC(tidno
);
2500 tid
->ac
= &an
->an_aggr
.tx
.ac
[acno
];
2503 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2504 tid
->state
&= ~AGGR_ADDBA_PROGRESS
;
2505 tid
->addba_exchangeattempts
= 0;
2509 * Init per ac tx state
2511 for (acno
= 0, ac
= &an
->an_aggr
.tx
.ac
[acno
];
2512 acno
< WME_NUM_AC
; acno
++, ac
++) {
2514 INIT_LIST_HEAD(&ac
->tid_q
);
2518 ac
->qnum
= ath_tx_get_qnum(sc
,
2519 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_BE
);
2522 ac
->qnum
= ath_tx_get_qnum(sc
,
2523 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_BK
);
2526 ac
->qnum
= ath_tx_get_qnum(sc
,
2527 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_VI
);
2530 ac
->qnum
= ath_tx_get_qnum(sc
,
2531 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_VO
);
2537 /* Cleanupthe pending buffers for the node. */
2539 void ath_tx_node_cleanup(struct ath_softc
*sc
, struct ath_node
*an
)
2542 struct ath_atx_ac
*ac
, *ac_tmp
;
2543 struct ath_atx_tid
*tid
, *tid_tmp
;
2544 struct ath_txq
*txq
;
2545 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2546 if (ATH_TXQ_SETUP(sc
, i
)) {
2547 txq
= &sc
->sc_txq
[i
];
2549 spin_lock(&txq
->axq_lock
);
2551 list_for_each_entry_safe(ac
,
2552 ac_tmp
, &txq
->axq_acq
, list
) {
2553 tid
= list_first_entry(&ac
->tid_q
,
2554 struct ath_atx_tid
, list
);
2555 if (tid
&& tid
->an
!= an
)
2557 list_del(&ac
->list
);
2560 list_for_each_entry_safe(tid
,
2561 tid_tmp
, &ac
->tid_q
, list
) {
2562 list_del(&tid
->list
);
2564 ath_tid_drain(sc
, txq
, tid
);
2565 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2566 tid
->addba_exchangeattempts
= 0;
2567 tid
->state
&= ~AGGR_CLEANUP
;
2571 spin_unlock(&txq
->axq_lock
);
2576 void ath_tx_cabq(struct ath_softc
*sc
, struct sk_buff
*skb
)
2578 int hdrlen
, padsize
;
2579 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2580 struct ath_tx_control txctl
;
2582 memset(&txctl
, 0, sizeof(struct ath_tx_control
));
2585 * As a temporary workaround, assign seq# here; this will likely need
2586 * to be cleaned up to work better with Beacon transmission and virtual
2589 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
2590 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
2591 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
2593 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
2594 hdr
->seq_ctrl
|= cpu_to_le16(sc
->seq_no
);
2597 /* Add the padding after the header if this is not already done */
2598 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
2600 padsize
= hdrlen
% 4;
2601 if (skb_headroom(skb
) < padsize
) {
2602 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: TX CABQ padding "
2603 "failed\n", __func__
);
2604 dev_kfree_skb_any(skb
);
2607 skb_push(skb
, padsize
);
2608 memmove(skb
->data
, skb
->data
+ padsize
, hdrlen
);
2611 txctl
.txq
= sc
->sc_cabq
;
2613 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: transmitting CABQ packet, skb: %p\n",
2617 if (ath_tx_start(sc
, skb
, &txctl
) != 0) {
2618 DPRINTF(sc
, ATH_DBG_XMIT
, "%s: TX failed\n", __func__
);
2624 dev_kfree_skb_any(skb
);