Sparseify MIPS.
[linux-2.6/verdex.git] / arch / mips / mm / cache.c
blobc0ac4f97e1ae9ee79e3c1bd12c227dbcd3b8e9b6
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
6 * Copyright (C) 1994 - 2003 by Ralf Baechle
7 */
8 #include <linux/config.h>
9 #include <linux/init.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/sched.h>
13 #include <linux/mm.h>
15 #include <asm/cacheflush.h>
16 #include <asm/processor.h>
17 #include <asm/cpu.h>
18 #include <asm/cpu-features.h>
20 /* Cache operations. */
21 void (*flush_cache_all)(void);
22 void (*__flush_cache_all)(void);
23 void (*flush_cache_mm)(struct mm_struct *mm);
24 void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start,
25 unsigned long end);
26 void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
27 void (*flush_icache_range)(unsigned long __user start,
28 unsigned long __user end);
29 void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page);
31 /* MIPS specific cache operations */
32 void (*flush_cache_sigtramp)(unsigned long addr);
33 void (*flush_data_cache_page)(unsigned long addr);
34 void (*flush_icache_all)(void);
36 #ifdef CONFIG_DMA_NONCOHERENT
38 /* DMA cache operations. */
39 void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
40 void (*_dma_cache_wback)(unsigned long start, unsigned long size);
41 void (*_dma_cache_inv)(unsigned long start, unsigned long size);
43 EXPORT_SYMBOL(_dma_cache_wback_inv);
44 EXPORT_SYMBOL(_dma_cache_wback);
45 EXPORT_SYMBOL(_dma_cache_inv);
47 #endif /* CONFIG_DMA_NONCOHERENT */
50 * We could optimize the case where the cache argument is not BCACHE but
51 * that seems very atypical use ...
53 asmlinkage int sys_cacheflush(unsigned long __user addr,
54 unsigned long bytes, unsigned int cache)
56 if (!access_ok(VERIFY_WRITE, (void __user *) addr, bytes))
57 return -EFAULT;
59 flush_icache_range(addr, addr + bytes);
61 return 0;
64 void __flush_dcache_page(struct page *page)
66 struct address_space *mapping = page_mapping(page);
67 unsigned long addr;
69 if (mapping && !mapping_mapped(mapping)) {
70 SetPageDcacheDirty(page);
71 return;
75 * We could delay the flush for the !page_mapping case too. But that
76 * case is for exec env/arg pages and those are %99 certainly going to
77 * get faulted into the tlb (and thus flushed) anyways.
79 addr = (unsigned long) page_address(page);
80 flush_data_cache_page(addr);
83 EXPORT_SYMBOL(__flush_dcache_page);
85 void __update_cache(struct vm_area_struct *vma, unsigned long address,
86 pte_t pte)
88 struct page *page;
89 unsigned long pfn, addr;
91 pfn = pte_pfn(pte);
92 if (pfn_valid(pfn) && (page = pfn_to_page(pfn), page_mapping(page)) &&
93 Page_dcache_dirty(page)) {
94 if (pages_do_alias((unsigned long)page_address(page),
95 address & PAGE_MASK)) {
96 addr = (unsigned long) page_address(page);
97 flush_data_cache_page(addr);
100 ClearPageDcacheDirty(page);
104 extern void ld_mmu_r23000(void);
105 extern void ld_mmu_r4xx0(void);
106 extern void ld_mmu_tx39(void);
107 extern void ld_mmu_r6000(void);
108 extern void ld_mmu_tfp(void);
109 extern void ld_mmu_andes(void);
110 extern void ld_mmu_sb1(void);
112 void __init cpu_cache_init(void)
114 if (cpu_has_4ktlb) {
115 #if defined(CONFIG_CPU_R4X00) || defined(CONFIG_CPU_VR41XX) || \
116 defined(CONFIG_CPU_R4300) || defined(CONFIG_CPU_R5000) || \
117 defined(CONFIG_CPU_NEVADA) || defined(CONFIG_CPU_R5432) || \
118 defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_MIPS32) || \
119 defined(CONFIG_CPU_MIPS64) || defined(CONFIG_CPU_TX49XX) || \
120 defined(CONFIG_CPU_RM7000) || defined(CONFIG_CPU_RM9000)
121 ld_mmu_r4xx0();
122 #endif
123 } else switch (current_cpu_data.cputype) {
124 #ifdef CONFIG_CPU_R3000
125 case CPU_R2000:
126 case CPU_R3000:
127 case CPU_R3000A:
128 case CPU_R3081E:
129 ld_mmu_r23000();
130 break;
131 #endif
132 #ifdef CONFIG_CPU_TX39XX
133 case CPU_TX3912:
134 case CPU_TX3922:
135 case CPU_TX3927:
136 ld_mmu_tx39();
137 break;
138 #endif
139 #ifdef CONFIG_CPU_R10000
140 case CPU_R10000:
141 case CPU_R12000:
142 ld_mmu_r4xx0();
143 break;
144 #endif
145 #ifdef CONFIG_CPU_SB1
146 case CPU_SB1:
147 ld_mmu_sb1();
148 break;
149 #endif
151 case CPU_R8000:
152 panic("R8000 is unsupported");
153 break;
155 default:
156 panic("Yeee, unsupported cache architecture.");