include/asm-x86_64/io_apic.h

   1 #ifndef __ASM_IO_APIC_H
   2 #define __ASM_IO_APIC_H
   3
   4 #include <asm/types.h>
   5 #include <asm/mpspec.h>
   6
   7 /*
   8  * Intel IO-APIC support for SMP and UP systems.
   9  *
  10  * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
  11  */
  12
  13 #define APIC_MISMATCH_DEBUG
  14
  15 #define IO_APIC_BASE(idx) \
  16                 ((volatile int *)(__fix_to_virt(FIX_IO_APIC_BASE_0 + idx) \
  17                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK)))
  18
  19 /*
  20  * The structure of the IO-APIC:
  21  */
  22 union IO_APIC_reg_00 {
  23         u32     raw;
  24         struct {
  25                 u32     __reserved_2    : 14,
  26                         LTS             :  1,
  27                         delivery_type   :  1,
  28                         __reserved_1    :  8,
  29                         ID              :  8;
  30         } __attribute__ ((packed)) bits;
  31 };
  32
  33 union IO_APIC_reg_01 {
  34         u32     raw;
  35         struct {
  36                 u32     version         :  8,
  37                 __reserved_2    :  7,
  38                 PRQ             :  1,
  39                 entries         :  8,
  40                 __reserved_1    :  8;
  41         } __attribute__ ((packed)) bits;
  42 };
  43
  44 union IO_APIC_reg_02 {
  45         u32     raw;
  46         struct {
  47                 u32     __reserved_2    : 24,
  48                 arbitration     :  4,
  49                 __reserved_1    :  4;
  50         } __attribute__ ((packed)) bits;
  51 };
  52
  53 union IO_APIC_reg_03 {
  54         u32     raw;
  55         struct {
  56                 u32     boot_DT         :  1,
  57                         __reserved_1    : 31;
  58         } __attribute__ ((packed)) bits;
  59 };
  60
  61 /*
  62  * # of IO-APICs and # of IRQ routing registers
  63  */
  64 extern int nr_ioapics;
  65 extern int nr_ioapic_registers[MAX_IO_APICS];
  66
  67 enum ioapic_irq_destination_types {
  68         dest_Fixed = 0,
  69         dest_LowestPrio = 1,
  70         dest_SMI = 2,
  71         dest__reserved_1 = 3,
  72         dest_NMI = 4,
  73         dest_INIT = 5,
  74         dest__reserved_2 = 6,
  75         dest_ExtINT = 7
  76 };
  77
  78 struct IO_APIC_route_entry {
  79         __u32   vector          :  8,
  80                 delivery_mode   :  3,   /* 000: FIXED
  81                                          * 001: lowest prio
  82                                          * 111: ExtINT
  83                                          */
  84                 dest_mode       :  1,   /* 0: physical, 1: logical */
  85                 delivery_status :  1,
  86                 polarity        :  1,
  87                 irr             :  1,
  88                 trigger         :  1,   /* 0: edge, 1: level */
  89                 mask            :  1,   /* 0: enabled, 1: disabled */
  90                 __reserved_2    : 15;
  91
  92         union {         struct { __u32
  93                                         __reserved_1    : 24,
  94                                         physical_dest   :  4,
  95                                         __reserved_2    :  4;
  96                         } physical;
  97
  98                         struct { __u32
  99                                         __reserved_1    : 24,
 100                                         logical_dest    :  8;
 101                         } logical;
 102         } dest;
 103
 104 } __attribute__ ((packed));
 105
 106 /*
 107  * MP-BIOS irq configuration table structures:
 108  */
 109
 110 /* I/O APIC entries */
 111 extern struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
 112
 113 /* # of MP IRQ source entries */
 114 extern int mp_irq_entries;
 115
 116 /* MP IRQ source entries */
 117 extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
 118
 119 /* non-0 if default (table-less) MP configuration */
 120 extern int mpc_default_type;
 121
 122 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 123 {
 124         *IO_APIC_BASE(apic) = reg;
 125         return *(IO_APIC_BASE(apic)+4);
 126 }
 127
 128 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 129 {
 130         *IO_APIC_BASE(apic) = reg;
 131         *(IO_APIC_BASE(apic)+4) = value;
 132 }
 133
 134 /*
 135  * Re-write a value: to be used for read-modify-write
 136  * cycles where the read already set up the index register.
 137  */
 138 static inline void io_apic_modify(unsigned int apic, unsigned int value)
 139 {
 140         *(IO_APIC_BASE(apic)+4) = value;
 141 }
 142
 143 /*
 144  * Synchronize the IO-APIC and the CPU by doing
 145  * a dummy read from the IO-APIC
 146  */
 147 static inline void io_apic_sync(unsigned int apic)
 148 {
 149         (void) *(IO_APIC_BASE(apic)+4);
 150 }
 151
 152 /* 1 if "noapic" boot option passed */
 153 extern int skip_ioapic_setup;
 154
 155 /*
 156  * If we use the IO-APIC for IRQ routing, disable automatic
 157  * assignment of PCI IRQ's.
 158  */
 159 #define io_apic_assign_pci_irqs (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
 160
 161 #ifdef CONFIG_ACPI
 162 extern int io_apic_get_version (int ioapic);
 163 extern int io_apic_get_redir_entries (int ioapic);
 164 extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int, int);
 165 #endif
 166
 167 extern int sis_apic_bug; /* dummy */
 168
 169 void enable_NMI_through_LVT0 (void * dummy);
 170
 171 extern spinlock_t i8259A_lock;
 172
 173 #endif