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local_t: alpha extension
[linux-2.6/verdex.git] / drivers / serial / mpsc.c
blobd09f2097d5b0ce6abc9cd25f849e19d37a3b0064
1 /*
2 * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240,
3 * GT64260, MV64340, MV64360, GT96100, ... ).
4 *
5 * Author: Mark A. Greer <mgreer@mvista.com>
6 *
7 * Based on an old MPSC driver that was in the linuxppc tree. It appears to
8 * have been created by Chris Zankel (formerly of MontaVista) but there
9 * is no proper Copyright so I'm not sure. Apparently, parts were also
10 * taken from PPCBoot (now U-Boot). Also based on drivers/serial/8250.c
11 * by Russell King.
12 *
13 * 2004 (c) MontaVista, Software, Inc. This file is licensed under
14 * the terms of the GNU General Public License version 2. This program
15 * is licensed "as is" without any warranty of any kind, whether express
16 * or implied.
17 */
18 /*
19 * The MPSC interface is much like a typical network controller's interface.
20 * That is, you set up separate rings of descriptors for transmitting and
21 * receiving data. There is also a pool of buffers with (one buffer per
22 * descriptor) that incoming data are dma'd into or outgoing data are dma'd
23 * out of.
24 *
25 * The MPSC requires two other controllers to be able to work. The Baud Rate
26 * Generator (BRG) provides a clock at programmable frequencies which determines
27 * the baud rate. The Serial DMA Controller (SDMA) takes incoming data from the
28 * MPSC and DMA's it into memory or DMA's outgoing data and passes it to the
29 * MPSC. It is actually the SDMA interrupt that the driver uses to keep the
30 * transmit and receive "engines" going (i.e., indicate data has been
31 * transmitted or received).
32 *
33 * NOTES:
34 *
35 * 1) Some chips have an erratum where several regs cannot be
36 * read. To work around that, we keep a local copy of those regs in
37 * 'mpsc_port_info'.
38 *
39 * 2) Some chips have an erratum where the ctlr will hang when the SDMA ctlr
40 * accesses system mem with coherency enabled. For that reason, the driver
41 * assumes that coherency for that ctlr has been disabled. This means
42 * that when in a cache coherent system, the driver has to manually manage
43 * the data cache on the areas that it touches because the dma_* macro are
44 * basically no-ops.
45 *
46 * 3) There is an erratum (on PPC) where you can't use the instruction to do
47 * a DMA_TO_DEVICE/cache clean so DMA_BIDIRECTIONAL/flushes are used in places
48 * where a DMA_TO_DEVICE/clean would have [otherwise] sufficed.
49 *
50 * 4) AFAICT, hardware flow control isn't supported by the controller --MAG.
51 */
52
53
54 #if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
55 #define SUPPORT_SYSRQ
56 #endif
57
58 #include <linux/module.h>
59 #include <linux/moduleparam.h>
60 #include <linux/tty.h>
61 #include <linux/tty_flip.h>
62 #include <linux/ioport.h>
63 #include <linux/init.h>
64 #include <linux/console.h>
65 #include <linux/sysrq.h>
66 #include <linux/serial.h>
67 #include <linux/serial_core.h>
68 #include <linux/delay.h>
69 #include <linux/device.h>
70 #include <linux/dma-mapping.h>
71 #include <linux/mv643xx.h>
72 #include <linux/platform_device.h>
73
74 #include <asm/io.h>
75 #include <asm/irq.h>
76
77 #if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
78 #define SUPPORT_SYSRQ
79 #endif
80
81 #define MPSC_NUM_CTLRS 2
82
83 /*
84 * Descriptors and buffers must be cache line aligned.
85 * Buffers lengths must be multiple of cache line size.
86 * Number of Tx & Rx descriptors must be powers of 2.
87 */
88 #define MPSC_RXR_ENTRIES 32
89 #define MPSC_RXRE_SIZE dma_get_cache_alignment()
90 #define MPSC_RXR_SIZE (MPSC_RXR_ENTRIES * MPSC_RXRE_SIZE)
91 #define MPSC_RXBE_SIZE dma_get_cache_alignment()
92 #define MPSC_RXB_SIZE (MPSC_RXR_ENTRIES * MPSC_RXBE_SIZE)
93
94 #define MPSC_TXR_ENTRIES 32
95 #define MPSC_TXRE_SIZE dma_get_cache_alignment()
96 #define MPSC_TXR_SIZE (MPSC_TXR_ENTRIES * MPSC_TXRE_SIZE)
97 #define MPSC_TXBE_SIZE dma_get_cache_alignment()
98 #define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE)
99
100 #define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + \
101 MPSC_TXR_SIZE + MPSC_TXB_SIZE + \
102 dma_get_cache_alignment() /* for alignment */)
103
104 /* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */
105 struct mpsc_rx_desc {
106 u16 bufsize;
107 u16 bytecnt;
108 u32 cmdstat;
109 u32 link;
110 u32 buf_ptr;
111 } __attribute((packed));
112
113 struct mpsc_tx_desc {
114 u16 bytecnt;
115 u16 shadow;
116 u32 cmdstat;
117 u32 link;
118 u32 buf_ptr;
119 } __attribute((packed));
120
121 /*
122 * Some regs that have the erratum that you can't read them are are shared
123 * between the two MPSC controllers. This struct contains those shared regs.
124 */
125 struct mpsc_shared_regs {
126 phys_addr_t mpsc_routing_base_p;
127 phys_addr_t sdma_intr_base_p;
128
129 void __iomem *mpsc_routing_base;
130 void __iomem *sdma_intr_base;
131
132 u32 MPSC_MRR_m;
133 u32 MPSC_RCRR_m;
134 u32 MPSC_TCRR_m;
135 u32 SDMA_INTR_CAUSE_m;
136 u32 SDMA_INTR_MASK_m;
137 };
138
139 /* The main driver data structure */
140 struct mpsc_port_info {
141 struct uart_port port; /* Overlay uart_port structure */
142
143 /* Internal driver state for this ctlr */
144 u8 ready;
145 u8 rcv_data;
146 tcflag_t c_iflag; /* save termios->c_iflag */
147 tcflag_t c_cflag; /* save termios->c_cflag */
148
149 /* Info passed in from platform */
150 u8 mirror_regs; /* Need to mirror regs? */
151 u8 cache_mgmt; /* Need manual cache mgmt? */
152 u8 brg_can_tune; /* BRG has baud tuning? */
153 u32 brg_clk_src;
154 u16 mpsc_max_idle;
155 int default_baud;
156 int default_bits;
157 int default_parity;
158 int default_flow;
159
160 /* Physical addresses of various blocks of registers (from platform) */
161 phys_addr_t mpsc_base_p;
162 phys_addr_t sdma_base_p;
163 phys_addr_t brg_base_p;
164
165 /* Virtual addresses of various blocks of registers (from platform) */
166 void __iomem *mpsc_base;
167 void __iomem *sdma_base;
168 void __iomem *brg_base;
169
170 /* Descriptor ring and buffer allocations */
171 void *dma_region;
172 dma_addr_t dma_region_p;
173
174 dma_addr_t rxr; /* Rx descriptor ring */
175 dma_addr_t rxr_p; /* Phys addr of rxr */
176 u8 *rxb; /* Rx Ring I/O buf */
177 u8 *rxb_p; /* Phys addr of rxb */
178 u32 rxr_posn; /* First desc w/ Rx data */
179
180 dma_addr_t txr; /* Tx descriptor ring */
181 dma_addr_t txr_p; /* Phys addr of txr */
182 u8 *txb; /* Tx Ring I/O buf */
183 u8 *txb_p; /* Phys addr of txb */
184 int txr_head; /* Where new data goes */
185 int txr_tail; /* Where sent data comes off */
186 spinlock_t tx_lock; /* transmit lock */
187
188 /* Mirrored values of regs we can't read (if 'mirror_regs' set) */
189 u32 MPSC_MPCR_m;
190 u32 MPSC_CHR_1_m;
191 u32 MPSC_CHR_2_m;
192 u32 MPSC_CHR_10_m;
193 u32 BRG_BCR_m;
194 struct mpsc_shared_regs *shared_regs;
195 };
196
197 /* Hooks to platform-specific code */
198 int mpsc_platform_register_driver(void);
199 void mpsc_platform_unregister_driver(void);
200
201 /* Hooks back in to mpsc common to be called by platform-specific code */
202 struct mpsc_port_info *mpsc_device_probe(int index);
203 struct mpsc_port_info *mpsc_device_remove(int index);
204
205 /* Main MPSC Configuration Register Offsets */
206 #define MPSC_MMCRL 0x0000
207 #define MPSC_MMCRH 0x0004
208 #define MPSC_MPCR 0x0008
209 #define MPSC_CHR_1 0x000c
210 #define MPSC_CHR_2 0x0010
211 #define MPSC_CHR_3 0x0014
212 #define MPSC_CHR_4 0x0018
213 #define MPSC_CHR_5 0x001c
214 #define MPSC_CHR_6 0x0020
215 #define MPSC_CHR_7 0x0024
216 #define MPSC_CHR_8 0x0028
217 #define MPSC_CHR_9 0x002c
218 #define MPSC_CHR_10 0x0030
219 #define MPSC_CHR_11 0x0034
220
221 #define MPSC_MPCR_FRZ (1 << 9)
222 #define MPSC_MPCR_CL_5 0
223 #define MPSC_MPCR_CL_6 1
224 #define MPSC_MPCR_CL_7 2
225 #define MPSC_MPCR_CL_8 3
226 #define MPSC_MPCR_SBL_1 0
227 #define MPSC_MPCR_SBL_2 1
228
229 #define MPSC_CHR_2_TEV (1<<1)
230 #define MPSC_CHR_2_TA (1<<7)
231 #define MPSC_CHR_2_TTCS (1<<9)
232 #define MPSC_CHR_2_REV (1<<17)
233 #define MPSC_CHR_2_RA (1<<23)
234 #define MPSC_CHR_2_CRD (1<<25)
235 #define MPSC_CHR_2_EH (1<<31)
236 #define MPSC_CHR_2_PAR_ODD 0
237 #define MPSC_CHR_2_PAR_SPACE 1
238 #define MPSC_CHR_2_PAR_EVEN 2
239 #define MPSC_CHR_2_PAR_MARK 3
240
241 /* MPSC Signal Routing */
242 #define MPSC_MRR 0x0000
243 #define MPSC_RCRR 0x0004
244 #define MPSC_TCRR 0x0008
245
246 /* Serial DMA Controller Interface Registers */
247 #define SDMA_SDC 0x0000
248 #define SDMA_SDCM 0x0008
249 #define SDMA_RX_DESC 0x0800
250 #define SDMA_RX_BUF_PTR 0x0808
251 #define SDMA_SCRDP 0x0810
252 #define SDMA_TX_DESC 0x0c00
253 #define SDMA_SCTDP 0x0c10
254 #define SDMA_SFTDP 0x0c14
255
256 #define SDMA_DESC_CMDSTAT_PE (1<<0)
257 #define SDMA_DESC_CMDSTAT_CDL (1<<1)
258 #define SDMA_DESC_CMDSTAT_FR (1<<3)
259 #define SDMA_DESC_CMDSTAT_OR (1<<6)
260 #define SDMA_DESC_CMDSTAT_BR (1<<9)
261 #define SDMA_DESC_CMDSTAT_MI (1<<10)
262 #define SDMA_DESC_CMDSTAT_A (1<<11)
263 #define SDMA_DESC_CMDSTAT_AM (1<<12)
264 #define SDMA_DESC_CMDSTAT_CT (1<<13)
265 #define SDMA_DESC_CMDSTAT_C (1<<14)
266 #define SDMA_DESC_CMDSTAT_ES (1<<15)
267 #define SDMA_DESC_CMDSTAT_L (1<<16)
268 #define SDMA_DESC_CMDSTAT_F (1<<17)
269 #define SDMA_DESC_CMDSTAT_P (1<<18)
270 #define SDMA_DESC_CMDSTAT_EI (1<<23)
271 #define SDMA_DESC_CMDSTAT_O (1<<31)
272
273 #define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \
274 SDMA_DESC_CMDSTAT_EI)
275
276 #define SDMA_SDC_RFT (1<<0)
277 #define SDMA_SDC_SFM (1<<1)
278 #define SDMA_SDC_BLMR (1<<6)
279 #define SDMA_SDC_BLMT (1<<7)
280 #define SDMA_SDC_POVR (1<<8)
281 #define SDMA_SDC_RIFB (1<<9)
282
283 #define SDMA_SDCM_ERD (1<<7)
284 #define SDMA_SDCM_AR (1<<15)
285 #define SDMA_SDCM_STD (1<<16)
286 #define SDMA_SDCM_TXD (1<<23)
287 #define SDMA_SDCM_AT (1<<31)
288
289 #define SDMA_0_CAUSE_RXBUF (1<<0)
290 #define SDMA_0_CAUSE_RXERR (1<<1)
291 #define SDMA_0_CAUSE_TXBUF (1<<2)
292 #define SDMA_0_CAUSE_TXEND (1<<3)
293 #define SDMA_1_CAUSE_RXBUF (1<<8)
294 #define SDMA_1_CAUSE_RXERR (1<<9)
295 #define SDMA_1_CAUSE_TXBUF (1<<10)
296 #define SDMA_1_CAUSE_TXEND (1<<11)
297
298 #define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \
299 SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
300 #define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \
301 SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
302
303 /* SDMA Interrupt registers */
304 #define SDMA_INTR_CAUSE 0x0000
305 #define SDMA_INTR_MASK 0x0080
306
307 /* Baud Rate Generator Interface Registers */
308 #define BRG_BCR 0x0000
309 #define BRG_BTR 0x0004
310
311 /*
312 * Define how this driver is known to the outside (we've been assigned a
313 * range on the "Low-density serial ports" major).
314 */
315 #define MPSC_MAJOR 204
316 #define MPSC_MINOR_START 44
317 #define MPSC_DRIVER_NAME "MPSC"
318 #define MPSC_DEV_NAME "ttyMM"
319 #define MPSC_VERSION "1.00"
320
321 static struct mpsc_port_info mpsc_ports[MPSC_NUM_CTLRS];
322 static struct mpsc_shared_regs mpsc_shared_regs;
323 static struct uart_driver mpsc_reg;
324
325 static void mpsc_start_rx(struct mpsc_port_info *pi);
326 static void mpsc_free_ring_mem(struct mpsc_port_info *pi);
327 static void mpsc_release_port(struct uart_port *port);
328 /*
329 ******************************************************************************
330 *
331 * Baud Rate Generator Routines (BRG)
332 *
333 ******************************************************************************
334 */
335 static void
336 mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
337 {
338 u32 v;
339
340 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
341 v = (v & ~(0xf << 18)) | ((clk_src & 0xf) << 18);
342
343 if (pi->brg_can_tune)
344 v &= ~(1 << 25);
345
346 if (pi->mirror_regs)
347 pi->BRG_BCR_m = v;
348 writel(v, pi->brg_base + BRG_BCR);
349
350 writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000,
351 pi->brg_base + BRG_BTR);
352 return;
353 }
354
355 static void
356 mpsc_brg_enable(struct mpsc_port_info *pi)
357 {
358 u32 v;
359
360 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
361 v |= (1 << 16);
362
363 if (pi->mirror_regs)
364 pi->BRG_BCR_m = v;
365 writel(v, pi->brg_base + BRG_BCR);
366 return;
367 }
368
369 static void
370 mpsc_brg_disable(struct mpsc_port_info *pi)
371 {
372 u32 v;
373
374 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
375 v &= ~(1 << 16);
376
377 if (pi->mirror_regs)
378 pi->BRG_BCR_m = v;
379 writel(v, pi->brg_base + BRG_BCR);
380 return;
381 }
382
383 static inline void
384 mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
385 {
386 /*
387 * To set the baud, we adjust the CDV field in the BRG_BCR reg.
388 * From manual: Baud = clk / ((CDV+1)*2) ==> CDV = (clk / (baud*2)) - 1.
389 * However, the input clock is divided by 16 in the MPSC b/c of how
390 * 'MPSC_MMCRH' was set up so we have to divide the 'clk' used in our
391 * calculation by 16 to account for that. So the real calculation
392 * that accounts for the way the mpsc is set up is:
393 * CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1.
394 */
395 u32 cdv = (pi->port.uartclk / (baud << 5)) - 1;
396 u32 v;
397
398 mpsc_brg_disable(pi);
399 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
400 v = (v & 0xffff0000) | (cdv & 0xffff);
401
402 if (pi->mirror_regs)
403 pi->BRG_BCR_m = v;
404 writel(v, pi->brg_base + BRG_BCR);
405 mpsc_brg_enable(pi);
406
407 return;
408 }
409
410 /*
411 ******************************************************************************
412 *
413 * Serial DMA Routines (SDMA)
414 *
415 ******************************************************************************
416 */
417
418 static void
419 mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
420 {
421 u32 v;
422
423 pr_debug("mpsc_sdma_burstsize[%d]: burst_size: %d\n",
424 pi->port.line, burst_size);
425
426 burst_size >>= 3; /* Divide by 8 b/c reg values are 8-byte chunks */
427
428 if (burst_size < 2)
429 v = 0x0; /* 1 64-bit word */
430 else if (burst_size < 4)
431 v = 0x1; /* 2 64-bit words */
432 else if (burst_size < 8)
433 v = 0x2; /* 4 64-bit words */
434 else
435 v = 0x3; /* 8 64-bit words */
436
437 writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12),
438 pi->sdma_base + SDMA_SDC);
439 return;
440 }
441
442 static void
443 mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size)
444 {
445 pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line,
446 burst_size);
447
448 writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f,
449 pi->sdma_base + SDMA_SDC);
450 mpsc_sdma_burstsize(pi, burst_size);
451 return;
452 }
453
454 static inline u32
455 mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask)
456 {
457 u32 old, v;
458
459 pr_debug("mpsc_sdma_intr_mask[%d]: mask: 0x%x\n", pi->port.line, mask);
460
461 old = v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m :
462 readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
463
464 mask &= 0xf;
465 if (pi->port.line)
466 mask <<= 8;
467 v &= ~mask;
468
469 if (pi->mirror_regs)
470 pi->shared_regs->SDMA_INTR_MASK_m = v;
471 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
472
473 if (pi->port.line)
474 old >>= 8;
475 return old & 0xf;
476 }
477
478 static inline void
479 mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask)
480 {
481 u32 v;
482
483 pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask);
484
485 v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m :
486 readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
487
488 mask &= 0xf;
489 if (pi->port.line)
490 mask <<= 8;
491 v |= mask;
492
493 if (pi->mirror_regs)
494 pi->shared_regs->SDMA_INTR_MASK_m = v;
495 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
496 return;
497 }
498
499 static inline void
500 mpsc_sdma_intr_ack(struct mpsc_port_info *pi)
501 {
502 pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line);
503
504 if (pi->mirror_regs)
505 pi->shared_regs->SDMA_INTR_CAUSE_m = 0;
506 writel(0, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE);
507 return;
508 }
509
510 static inline void
511 mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi, struct mpsc_rx_desc *rxre_p)
512 {
513 pr_debug("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n",
514 pi->port.line, (u32) rxre_p);
515
516 writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP);
517 return;
518 }
519
520 static inline void
521 mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi, struct mpsc_tx_desc *txre_p)
522 {
523 writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP);
524 writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP);
525 return;
526 }
527
528 static inline void
529 mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val)
530 {
531 u32 v;
532
533 v = readl(pi->sdma_base + SDMA_SDCM);
534 if (val)
535 v |= val;
536 else
537 v = 0;
538 wmb();
539 writel(v, pi->sdma_base + SDMA_SDCM);
540 wmb();
541 return;
542 }
543
544 static inline uint
545 mpsc_sdma_tx_active(struct mpsc_port_info *pi)
546 {
547 return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD;
548 }
549
550 static inline void
551 mpsc_sdma_start_tx(struct mpsc_port_info *pi)
552 {
553 struct mpsc_tx_desc *txre, *txre_p;
554
555 /* If tx isn't running & there's a desc ready to go, start it */
556 if (!mpsc_sdma_tx_active(pi)) {
557 txre = (struct mpsc_tx_desc *)(pi->txr +
558 (pi->txr_tail * MPSC_TXRE_SIZE));
559 dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE, DMA_FROM_DEVICE);
560 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
561 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
562 invalidate_dcache_range((ulong)txre,
563 (ulong)txre + MPSC_TXRE_SIZE);
564 #endif
565
566 if (be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O) {
567 txre_p = (struct mpsc_tx_desc *)(pi->txr_p +
568 (pi->txr_tail *
569 MPSC_TXRE_SIZE));
570
571 mpsc_sdma_set_tx_ring(pi, txre_p);
572 mpsc_sdma_cmd(pi, SDMA_SDCM_STD | SDMA_SDCM_TXD);
573 }
574 }
575
576 return;
577 }
578
579 static inline void
580 mpsc_sdma_stop(struct mpsc_port_info *pi)
581 {
582 pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line);
583
584 /* Abort any SDMA transfers */
585 mpsc_sdma_cmd(pi, 0);
586 mpsc_sdma_cmd(pi, SDMA_SDCM_AR | SDMA_SDCM_AT);
587
588 /* Clear the SDMA current and first TX and RX pointers */
589 mpsc_sdma_set_tx_ring(pi, NULL);
590 mpsc_sdma_set_rx_ring(pi, NULL);
591
592 /* Disable interrupts */
593 mpsc_sdma_intr_mask(pi, 0xf);
594 mpsc_sdma_intr_ack(pi);
595
596 return;
597 }
598
599 /*
600 ******************************************************************************
601 *
602 * Multi-Protocol Serial Controller Routines (MPSC)
603 *
604 ******************************************************************************
605 */
606
607 static void
608 mpsc_hw_init(struct mpsc_port_info *pi)
609 {
610 u32 v;
611
612 pr_debug("mpsc_hw_init[%d]: Initializing hardware\n", pi->port.line);
613
614 /* Set up clock routing */
615 if (pi->mirror_regs) {
616 v = pi->shared_regs->MPSC_MRR_m;
617 v &= ~0x1c7;
618 pi->shared_regs->MPSC_MRR_m = v;
619 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
620
621 v = pi->shared_regs->MPSC_RCRR_m;
622 v = (v & ~0xf0f) | 0x100;
623 pi->shared_regs->MPSC_RCRR_m = v;
624 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
625
626 v = pi->shared_regs->MPSC_TCRR_m;
627 v = (v & ~0xf0f) | 0x100;
628 pi->shared_regs->MPSC_TCRR_m = v;
629 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
630 }
631 else {
632 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR);
633 v &= ~0x1c7;
634 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
635
636 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
637 v = (v & ~0xf0f) | 0x100;
638 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
639
640 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
641 v = (v & ~0xf0f) | 0x100;
642 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
643 }
644
645 /* Put MPSC in UART mode & enabel Tx/Rx egines */
646 writel(0x000004c4, pi->mpsc_base + MPSC_MMCRL);
647
648 /* No preamble, 16x divider, low-latency, */
649 writel(0x04400400, pi->mpsc_base + MPSC_MMCRH);
650
651 if (pi->mirror_regs) {
652 pi->MPSC_CHR_1_m = 0;
653 pi->MPSC_CHR_2_m = 0;
654 }
655 writel(0, pi->mpsc_base + MPSC_CHR_1);
656 writel(0, pi->mpsc_base + MPSC_CHR_2);
657 writel(pi->mpsc_max_idle, pi->mpsc_base + MPSC_CHR_3);
658 writel(0, pi->mpsc_base + MPSC_CHR_4);
659 writel(0, pi->mpsc_base + MPSC_CHR_5);
660 writel(0, pi->mpsc_base + MPSC_CHR_6);
661 writel(0, pi->mpsc_base + MPSC_CHR_7);
662 writel(0, pi->mpsc_base + MPSC_CHR_8);
663 writel(0, pi->mpsc_base + MPSC_CHR_9);
664 writel(0, pi->mpsc_base + MPSC_CHR_10);
665
666 return;
667 }
668
669 static inline void
670 mpsc_enter_hunt(struct mpsc_port_info *pi)
671 {
672 pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line);
673
674 if (pi->mirror_regs) {
675 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_EH,
676 pi->mpsc_base + MPSC_CHR_2);
677 /* Erratum prevents reading CHR_2 so just delay for a while */
678 udelay(100);
679 }
680 else {
681 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH,
682 pi->mpsc_base + MPSC_CHR_2);
683
684 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH)
685 udelay(10);
686 }
687
688 return;
689 }
690
691 static inline void
692 mpsc_freeze(struct mpsc_port_info *pi)
693 {
694 u32 v;
695
696 pr_debug("mpsc_freeze[%d]: Freezing\n", pi->port.line);
697
698 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
699 readl(pi->mpsc_base + MPSC_MPCR);
700 v |= MPSC_MPCR_FRZ;
701
702 if (pi->mirror_regs)
703 pi->MPSC_MPCR_m = v;
704 writel(v, pi->mpsc_base + MPSC_MPCR);
705 return;
706 }
707
708 static inline void
709 mpsc_unfreeze(struct mpsc_port_info *pi)
710 {
711 u32 v;
712
713 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
714 readl(pi->mpsc_base + MPSC_MPCR);
715 v &= ~MPSC_MPCR_FRZ;
716
717 if (pi->mirror_regs)
718 pi->MPSC_MPCR_m = v;
719 writel(v, pi->mpsc_base + MPSC_MPCR);
720
721 pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line);
722 return;
723 }
724
725 static inline void
726 mpsc_set_char_length(struct mpsc_port_info *pi, u32 len)
727 {
728 u32 v;
729
730 pr_debug("mpsc_set_char_length[%d]: char len: %d\n", pi->port.line,len);
731
732 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
733 readl(pi->mpsc_base + MPSC_MPCR);
734 v = (v & ~(0x3 << 12)) | ((len & 0x3) << 12);
735
736 if (pi->mirror_regs)
737 pi->MPSC_MPCR_m = v;
738 writel(v, pi->mpsc_base + MPSC_MPCR);
739 return;
740 }
741
742 static inline void
743 mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len)
744 {
745 u32 v;
746
747 pr_debug("mpsc_set_stop_bit_length[%d]: stop bits: %d\n",
748 pi->port.line, len);
749
750 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
751 readl(pi->mpsc_base + MPSC_MPCR);
752
753 v = (v & ~(1 << 14)) | ((len & 0x1) << 14);
754
755 if (pi->mirror_regs)
756 pi->MPSC_MPCR_m = v;
757 writel(v, pi->mpsc_base + MPSC_MPCR);
758 return;
759 }
760
761 static inline void
762 mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
763 {
764 u32 v;
765
766 pr_debug("mpsc_set_parity[%d]: parity bits: 0x%x\n", pi->port.line, p);
767
768 v = (pi->mirror_regs) ? pi->MPSC_CHR_2_m :
769 readl(pi->mpsc_base + MPSC_CHR_2);
770
771 p &= 0x3;
772 v = (v & ~0xc000c) | (p << 18) | (p << 2);
773
774 if (pi->mirror_regs)
775 pi->MPSC_CHR_2_m = v;
776 writel(v, pi->mpsc_base + MPSC_CHR_2);
777 return;
778 }
779
780 /*
781 ******************************************************************************
782 *
783 * Driver Init Routines
784 *
785 ******************************************************************************
786 */
787
788 static void
789 mpsc_init_hw(struct mpsc_port_info *pi)
790 {
791 pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line);
792
793 mpsc_brg_init(pi, pi->brg_clk_src);
794 mpsc_brg_enable(pi);
795 mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */
796 mpsc_sdma_stop(pi);
797 mpsc_hw_init(pi);
798
799 return;
800 }
801
802 static int
803 mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
804 {
805 int rc = 0;
806
807 pr_debug("mpsc_alloc_ring_mem[%d]: Allocating ring mem\n",
808 pi->port.line);
809
810 if (!pi->dma_region) {
811 if (!dma_supported(pi->port.dev, 0xffffffff)) {
812 printk(KERN_ERR "MPSC: Inadequate DMA support\n");
813 rc = -ENXIO;
814 }
815 else if ((pi->dma_region = dma_alloc_noncoherent(pi->port.dev,
816 MPSC_DMA_ALLOC_SIZE, &pi->dma_region_p, GFP_KERNEL))
817 == NULL) {
818
819 printk(KERN_ERR "MPSC: Can't alloc Desc region\n");
820 rc = -ENOMEM;
821 }
822 }
823
824 return rc;
825 }
826
827 static void
828 mpsc_free_ring_mem(struct mpsc_port_info *pi)
829 {
830 pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line);
831
832 if (pi->dma_region) {
833 dma_free_noncoherent(pi->port.dev, MPSC_DMA_ALLOC_SIZE,
834 pi->dma_region, pi->dma_region_p);
835 pi->dma_region = NULL;
836 pi->dma_region_p = (dma_addr_t) NULL;
837 }
838
839 return;
840 }
841
842 static void
843 mpsc_init_rings(struct mpsc_port_info *pi)
844 {
845 struct mpsc_rx_desc *rxre;
846 struct mpsc_tx_desc *txre;
847 dma_addr_t dp, dp_p;
848 u8 *bp, *bp_p;
849 int i;
850
851 pr_debug("mpsc_init_rings[%d]: Initializing rings\n", pi->port.line);
852
853 BUG_ON(pi->dma_region == NULL);
854
855 memset(pi->dma_region, 0, MPSC_DMA_ALLOC_SIZE);
856
857 /*
858 * Descriptors & buffers are multiples of cacheline size and must be
859 * cacheline aligned.
860 */
861 dp = ALIGN((u32) pi->dma_region, dma_get_cache_alignment());
862 dp_p = ALIGN((u32) pi->dma_region_p, dma_get_cache_alignment());
863
864 /*
865 * Partition dma region into rx ring descriptor, rx buffers,
866 * tx ring descriptors, and tx buffers.
867 */
868 pi->rxr = dp;
869 pi->rxr_p = dp_p;
870 dp += MPSC_RXR_SIZE;
871 dp_p += MPSC_RXR_SIZE;
872
873 pi->rxb = (u8 *) dp;
874 pi->rxb_p = (u8 *) dp_p;
875 dp += MPSC_RXB_SIZE;
876 dp_p += MPSC_RXB_SIZE;
877
878 pi->rxr_posn = 0;
879
880 pi->txr = dp;
881 pi->txr_p = dp_p;
882 dp += MPSC_TXR_SIZE;
883 dp_p += MPSC_TXR_SIZE;
884
885 pi->txb = (u8 *) dp;
886 pi->txb_p = (u8 *) dp_p;
887
888 pi->txr_head = 0;
889 pi->txr_tail = 0;
890
891 /* Init rx ring descriptors */
892 dp = pi->rxr;
893 dp_p = pi->rxr_p;
894 bp = pi->rxb;
895 bp_p = pi->rxb_p;
896
897 for (i = 0; i < MPSC_RXR_ENTRIES; i++) {
898 rxre = (struct mpsc_rx_desc *)dp;
899
900 rxre->bufsize = cpu_to_be16(MPSC_RXBE_SIZE);
901 rxre->bytecnt = cpu_to_be16(0);
902 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O |
903 SDMA_DESC_CMDSTAT_EI |
904 SDMA_DESC_CMDSTAT_F |
905 SDMA_DESC_CMDSTAT_L);
906 rxre->link = cpu_to_be32(dp_p + MPSC_RXRE_SIZE);
907 rxre->buf_ptr = cpu_to_be32(bp_p);
908
909 dp += MPSC_RXRE_SIZE;
910 dp_p += MPSC_RXRE_SIZE;
911 bp += MPSC_RXBE_SIZE;
912 bp_p += MPSC_RXBE_SIZE;
913 }
914 rxre->link = cpu_to_be32(pi->rxr_p); /* Wrap last back to first */
915
916 /* Init tx ring descriptors */
917 dp = pi->txr;
918 dp_p = pi->txr_p;
919 bp = pi->txb;
920 bp_p = pi->txb_p;
921
922 for (i = 0; i < MPSC_TXR_ENTRIES; i++) {
923 txre = (struct mpsc_tx_desc *)dp;
924
925 txre->link = cpu_to_be32(dp_p + MPSC_TXRE_SIZE);
926 txre->buf_ptr = cpu_to_be32(bp_p);
927
928 dp += MPSC_TXRE_SIZE;
929 dp_p += MPSC_TXRE_SIZE;
930 bp += MPSC_TXBE_SIZE;
931 bp_p += MPSC_TXBE_SIZE;
932 }
933 txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */
934
935 dma_cache_sync(pi->port.dev, (void *) pi->dma_region, MPSC_DMA_ALLOC_SIZE,
936 DMA_BIDIRECTIONAL);
937 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
938 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
939 flush_dcache_range((ulong)pi->dma_region,
940 (ulong)pi->dma_region + MPSC_DMA_ALLOC_SIZE);
941 #endif
942
943 return;
944 }
945
946 static void
947 mpsc_uninit_rings(struct mpsc_port_info *pi)
948 {
949 pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line);
950
951 BUG_ON(pi->dma_region == NULL);
952
953 pi->rxr = 0;
954 pi->rxr_p = 0;
955 pi->rxb = NULL;
956 pi->rxb_p = NULL;
957 pi->rxr_posn = 0;
958
959 pi->txr = 0;
960 pi->txr_p = 0;
961 pi->txb = NULL;
962 pi->txb_p = NULL;
963 pi->txr_head = 0;
964 pi->txr_tail = 0;
965
966 return;
967 }
968
969 static int
970 mpsc_make_ready(struct mpsc_port_info *pi)
971 {
972 int rc;
973
974 pr_debug("mpsc_make_ready[%d]: Making cltr ready\n", pi->port.line);
975
976 if (!pi->ready) {
977 mpsc_init_hw(pi);
978 if ((rc = mpsc_alloc_ring_mem(pi)))
979 return rc;
980 mpsc_init_rings(pi);
981 pi->ready = 1;
982 }
983
984 return 0;
985 }
986
987 /*
988 ******************************************************************************
989 *
990 * Interrupt Handling Routines
991 *
992 ******************************************************************************
993 */
994
995 static inline int
996 mpsc_rx_intr(struct mpsc_port_info *pi)
997 {
998 struct mpsc_rx_desc *rxre;
999 struct tty_struct *tty = pi->port.info->tty;
1000 u32 cmdstat, bytes_in, i;
1001 int rc = 0;
1002 u8 *bp;
1003 char flag = TTY_NORMAL;
1004
1005 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line);
1006
1007 rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE));
1008
1009 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
1010 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1011 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1012 invalidate_dcache_range((ulong)rxre,
1013 (ulong)rxre + MPSC_RXRE_SIZE);
1014 #endif
1015
1016 /*
1017 * Loop through Rx descriptors handling ones that have been completed.
1018 */
1019 while (!((cmdstat = be32_to_cpu(rxre->cmdstat)) & SDMA_DESC_CMDSTAT_O)){
1020 bytes_in = be16_to_cpu(rxre->bytecnt);
1021
1022 /* Following use of tty struct directly is deprecated */
1023 if (unlikely(tty_buffer_request_room(tty, bytes_in) < bytes_in)) {
1024 if (tty->low_latency)
1025 tty_flip_buffer_push(tty);
1026 /*
1027 * If this failed then we will throw away the bytes
1028 * but must do so to clear interrupts.
1029 */
1030 }
1031
1032 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
1033 dma_cache_sync(pi->port.dev, (void *) bp, MPSC_RXBE_SIZE, DMA_FROM_DEVICE);
1034 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1035 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1036 invalidate_dcache_range((ulong)bp,
1037 (ulong)bp + MPSC_RXBE_SIZE);
1038 #endif
1039
1040 /*
1041 * Other than for parity error, the manual provides little
1042 * info on what data will be in a frame flagged by any of
1043 * these errors. For parity error, it is the last byte in
1044 * the buffer that had the error. As for the rest, I guess
1045 * we'll assume there is no data in the buffer.
1046 * If there is...it gets lost.
1047 */
1048 if (unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR |
1049 SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) {
1050
1051 pi->port.icount.rx++;
1052
1053 if (cmdstat & SDMA_DESC_CMDSTAT_BR) { /* Break */
1054 pi->port.icount.brk++;
1055
1056 if (uart_handle_break(&pi->port))
1057 goto next_frame;
1058 }
1059 else if (cmdstat & SDMA_DESC_CMDSTAT_FR)/* Framing */
1060 pi->port.icount.frame++;
1061 else if (cmdstat & SDMA_DESC_CMDSTAT_OR) /* Overrun */
1062 pi->port.icount.overrun++;
1063
1064 cmdstat &= pi->port.read_status_mask;
1065
1066 if (cmdstat & SDMA_DESC_CMDSTAT_BR)
1067 flag = TTY_BREAK;
1068 else if (cmdstat & SDMA_DESC_CMDSTAT_FR)
1069 flag = TTY_FRAME;
1070 else if (cmdstat & SDMA_DESC_CMDSTAT_OR)
1071 flag = TTY_OVERRUN;
1072 else if (cmdstat & SDMA_DESC_CMDSTAT_PE)
1073 flag = TTY_PARITY;
1074 }
1075
1076 if (uart_handle_sysrq_char(&pi->port, *bp)) {
1077 bp++;
1078 bytes_in--;
1079 goto next_frame;
1080 }
1081
1082 if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR |
1083 SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) &&
1084 !(cmdstat & pi->port.ignore_status_mask))
1085
1086 tty_insert_flip_char(tty, *bp, flag);
1087 else {
1088 for (i=0; i<bytes_in; i++)
1089 tty_insert_flip_char(tty, *bp++, TTY_NORMAL);
1090
1091 pi->port.icount.rx += bytes_in;
1092 }
1093
1094 next_frame:
1095 rxre->bytecnt = cpu_to_be16(0);
1096 wmb();
1097 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O |
1098 SDMA_DESC_CMDSTAT_EI |
1099 SDMA_DESC_CMDSTAT_F |
1100 SDMA_DESC_CMDSTAT_L);
1101 wmb();
1102 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, DMA_BIDIRECTIONAL);
1103 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1104 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1105 flush_dcache_range((ulong)rxre,
1106 (ulong)rxre + MPSC_RXRE_SIZE);
1107 #endif
1108
1109 /* Advance to next descriptor */
1110 pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1);
1111 rxre = (struct mpsc_rx_desc *)(pi->rxr +
1112 (pi->rxr_posn * MPSC_RXRE_SIZE));
1113 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
1114 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1115 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1116 invalidate_dcache_range((ulong)rxre,
1117 (ulong)rxre + MPSC_RXRE_SIZE);
1118 #endif
1119
1120 rc = 1;
1121 }
1122
1123 /* Restart rx engine, if its stopped */
1124 if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0)
1125 mpsc_start_rx(pi);
1126
1127 tty_flip_buffer_push(tty);
1128 return rc;
1129 }
1130
1131 static inline void
1132 mpsc_setup_tx_desc(struct mpsc_port_info *pi, u32 count, u32 intr)
1133 {
1134 struct mpsc_tx_desc *txre;
1135
1136 txre = (struct mpsc_tx_desc *)(pi->txr +
1137 (pi->txr_head * MPSC_TXRE_SIZE));
1138
1139 txre->bytecnt = cpu_to_be16(count);
1140 txre->shadow = txre->bytecnt;
1141 wmb(); /* ensure cmdstat is last field updated */
1142 txre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | SDMA_DESC_CMDSTAT_F |
1143 SDMA_DESC_CMDSTAT_L | ((intr) ?
1144 SDMA_DESC_CMDSTAT_EI
1145 : 0));
1146 wmb();
1147 dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE, DMA_BIDIRECTIONAL);
1148 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1149 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1150 flush_dcache_range((ulong)txre,
1151 (ulong)txre + MPSC_TXRE_SIZE);
1152 #endif
1153
1154 return;
1155 }
1156
1157 static inline void
1158 mpsc_copy_tx_data(struct mpsc_port_info *pi)
1159 {
1160 struct circ_buf *xmit = &pi->port.info->xmit;
1161 u8 *bp;
1162 u32 i;
1163
1164 /* Make sure the desc ring isn't full */
1165 while (CIRC_CNT(pi->txr_head, pi->txr_tail, MPSC_TXR_ENTRIES) <
1166 (MPSC_TXR_ENTRIES - 1)) {
1167 if (pi->port.x_char) {
1168 /*
1169 * Ideally, we should use the TCS field in
1170 * CHR_1 to put the x_char out immediately but
1171 * errata prevents us from being able to read
1172 * CHR_2 to know that its safe to write to
1173 * CHR_1. Instead, just put it in-band with
1174 * all the other Tx data.
1175 */
1176 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1177 *bp = pi->port.x_char;
1178 pi->port.x_char = 0;
1179 i = 1;
1180 }
1181 else if (!uart_circ_empty(xmit) && !uart_tx_stopped(&pi->port)){
1182 i = min((u32) MPSC_TXBE_SIZE,
1183 (u32) uart_circ_chars_pending(xmit));
1184 i = min(i, (u32) CIRC_CNT_TO_END(xmit->head, xmit->tail,
1185 UART_XMIT_SIZE));
1186 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1187 memcpy(bp, &xmit->buf[xmit->tail], i);
1188 xmit->tail = (xmit->tail + i) & (UART_XMIT_SIZE - 1);
1189
1190 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1191 uart_write_wakeup(&pi->port);
1192 }
1193 else /* All tx data copied into ring bufs */
1194 return;
1195
1196 dma_cache_sync(pi->port.dev, (void *) bp, MPSC_TXBE_SIZE, DMA_BIDIRECTIONAL);
1197 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1198 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1199 flush_dcache_range((ulong)bp,
1200 (ulong)bp + MPSC_TXBE_SIZE);
1201 #endif
1202 mpsc_setup_tx_desc(pi, i, 1);
1203
1204 /* Advance to next descriptor */
1205 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
1206 }
1207
1208 return;
1209 }
1210
1211 static inline int
1212 mpsc_tx_intr(struct mpsc_port_info *pi)
1213 {
1214 struct mpsc_tx_desc *txre;
1215 int rc = 0;
1216 unsigned long iflags;
1217
1218 spin_lock_irqsave(&pi->tx_lock, iflags);
1219
1220 if (!mpsc_sdma_tx_active(pi)) {
1221 txre = (struct mpsc_tx_desc *)(pi->txr +
1222 (pi->txr_tail * MPSC_TXRE_SIZE));
1223
1224 dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE, DMA_FROM_DEVICE);
1225 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1226 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1227 invalidate_dcache_range((ulong)txre,
1228 (ulong)txre + MPSC_TXRE_SIZE);
1229 #endif
1230
1231 while (!(be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O)) {
1232 rc = 1;
1233 pi->port.icount.tx += be16_to_cpu(txre->bytecnt);
1234 pi->txr_tail = (pi->txr_tail+1) & (MPSC_TXR_ENTRIES-1);
1235
1236 /* If no more data to tx, fall out of loop */
1237 if (pi->txr_head == pi->txr_tail)
1238 break;
1239
1240 txre = (struct mpsc_tx_desc *)(pi->txr +
1241 (pi->txr_tail * MPSC_TXRE_SIZE));
1242 dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE,
1243 DMA_FROM_DEVICE);
1244 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1245 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1246 invalidate_dcache_range((ulong)txre,
1247 (ulong)txre + MPSC_TXRE_SIZE);
1248 #endif
1249 }
1250
1251 mpsc_copy_tx_data(pi);
1252 mpsc_sdma_start_tx(pi); /* start next desc if ready */
1253 }
1254
1255 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1256 return rc;
1257 }
1258
1259 /*
1260 * This is the driver's interrupt handler. To avoid a race, we first clear
1261 * the interrupt, then handle any completed Rx/Tx descriptors. When done
1262 * handling those descriptors, we restart the Rx/Tx engines if they're stopped.
1263 */
1264 static irqreturn_t
1265 mpsc_sdma_intr(int irq, void *dev_id)
1266 {
1267 struct mpsc_port_info *pi = dev_id;
1268 ulong iflags;
1269 int rc = IRQ_NONE;
1270
1271 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Received\n",pi->port.line);
1272
1273 spin_lock_irqsave(&pi->port.lock, iflags);
1274 mpsc_sdma_intr_ack(pi);
1275 if (mpsc_rx_intr(pi))
1276 rc = IRQ_HANDLED;
1277 if (mpsc_tx_intr(pi))
1278 rc = IRQ_HANDLED;
1279 spin_unlock_irqrestore(&pi->port.lock, iflags);
1280
1281 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Handled\n", pi->port.line);
1282 return rc;
1283 }
1284
1285 /*
1286 ******************************************************************************
1287 *
1288 * serial_core.c Interface routines
1289 *
1290 ******************************************************************************
1291 */
1292 static uint
1293 mpsc_tx_empty(struct uart_port *port)
1294 {
1295 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1296 ulong iflags;
1297 uint rc;
1298
1299 spin_lock_irqsave(&pi->port.lock, iflags);
1300 rc = mpsc_sdma_tx_active(pi) ? 0 : TIOCSER_TEMT;
1301 spin_unlock_irqrestore(&pi->port.lock, iflags);
1302
1303 return rc;
1304 }
1305
1306 static void
1307 mpsc_set_mctrl(struct uart_port *port, uint mctrl)
1308 {
1309 /* Have no way to set modem control lines AFAICT */
1310 return;
1311 }
1312
1313 static uint
1314 mpsc_get_mctrl(struct uart_port *port)
1315 {
1316 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1317 u32 mflags, status;
1318
1319 status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m :
1320 readl(pi->mpsc_base + MPSC_CHR_10);
1321
1322 mflags = 0;
1323 if (status & 0x1)
1324 mflags |= TIOCM_CTS;
1325 if (status & 0x2)
1326 mflags |= TIOCM_CAR;
1327
1328 return mflags | TIOCM_DSR; /* No way to tell if DSR asserted */
1329 }
1330
1331 static void
1332 mpsc_stop_tx(struct uart_port *port)
1333 {
1334 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1335
1336 pr_debug("mpsc_stop_tx[%d]\n", port->line);
1337
1338 mpsc_freeze(pi);
1339 return;
1340 }
1341
1342 static void
1343 mpsc_start_tx(struct uart_port *port)
1344 {
1345 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1346 unsigned long iflags;
1347
1348 spin_lock_irqsave(&pi->tx_lock, iflags);
1349
1350 mpsc_unfreeze(pi);
1351 mpsc_copy_tx_data(pi);
1352 mpsc_sdma_start_tx(pi);
1353
1354 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1355
1356 pr_debug("mpsc_start_tx[%d]\n", port->line);
1357 return;
1358 }
1359
1360 static void
1361 mpsc_start_rx(struct mpsc_port_info *pi)
1362 {
1363 pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line);
1364
1365 /* Issue a Receive Abort to clear any receive errors */
1366 writel(MPSC_CHR_2_RA, pi->mpsc_base + MPSC_CHR_2);
1367 if (pi->rcv_data) {
1368 mpsc_enter_hunt(pi);
1369 mpsc_sdma_cmd(pi, SDMA_SDCM_ERD);
1370 }
1371 return;
1372 }
1373
1374 static void
1375 mpsc_stop_rx(struct uart_port *port)
1376 {
1377 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1378
1379 pr_debug("mpsc_stop_rx[%d]: Stopping...\n", port->line);
1380
1381 mpsc_sdma_cmd(pi, SDMA_SDCM_AR);
1382 return;
1383 }
1384
1385 static void
1386 mpsc_enable_ms(struct uart_port *port)
1387 {
1388 return; /* Not supported */
1389 }
1390
1391 static void
1392 mpsc_break_ctl(struct uart_port *port, int ctl)
1393 {
1394 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1395 ulong flags;
1396 u32 v;
1397
1398 v = ctl ? 0x00ff0000 : 0;
1399
1400 spin_lock_irqsave(&pi->port.lock, flags);
1401 if (pi->mirror_regs)
1402 pi->MPSC_CHR_1_m = v;
1403 writel(v, pi->mpsc_base + MPSC_CHR_1);
1404 spin_unlock_irqrestore(&pi->port.lock, flags);
1405
1406 return;
1407 }
1408
1409 static int
1410 mpsc_startup(struct uart_port *port)
1411 {
1412 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1413 u32 flag = 0;
1414 int rc;
1415
1416 pr_debug("mpsc_startup[%d]: Starting up MPSC, irq: %d\n",
1417 port->line, pi->port.irq);
1418
1419 if ((rc = mpsc_make_ready(pi)) == 0) {
1420 /* Setup IRQ handler */
1421 mpsc_sdma_intr_ack(pi);
1422
1423 /* If irq's are shared, need to set flag */
1424 if (mpsc_ports[0].port.irq == mpsc_ports[1].port.irq)
1425 flag = IRQF_SHARED;
1426
1427 if (request_irq(pi->port.irq, mpsc_sdma_intr, flag,
1428 "mpsc-sdma", pi))
1429 printk(KERN_ERR "MPSC: Can't get SDMA IRQ %d\n",
1430 pi->port.irq);
1431
1432 mpsc_sdma_intr_unmask(pi, 0xf);
1433 mpsc_sdma_set_rx_ring(pi, (struct mpsc_rx_desc *)(pi->rxr_p +
1434 (pi->rxr_posn * MPSC_RXRE_SIZE)));
1435 }
1436
1437 return rc;
1438 }
1439
1440 static void
1441 mpsc_shutdown(struct uart_port *port)
1442 {
1443 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1444
1445 pr_debug("mpsc_shutdown[%d]: Shutting down MPSC\n", port->line);
1446
1447 mpsc_sdma_stop(pi);
1448 free_irq(pi->port.irq, pi);
1449 return;
1450 }
1451
1452 static void
1453 mpsc_set_termios(struct uart_port *port, struct ktermios *termios,
1454 struct ktermios *old)
1455 {
1456 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1457 u32 baud;
1458 ulong flags;
1459 u32 chr_bits, stop_bits, par;
1460
1461 pi->c_iflag = termios->c_iflag;
1462 pi->c_cflag = termios->c_cflag;
1463
1464 switch (termios->c_cflag & CSIZE) {
1465 case CS5:
1466 chr_bits = MPSC_MPCR_CL_5;
1467 break;
1468 case CS6:
1469 chr_bits = MPSC_MPCR_CL_6;
1470 break;
1471 case CS7:
1472 chr_bits = MPSC_MPCR_CL_7;
1473 break;
1474 case CS8:
1475 default:
1476 chr_bits = MPSC_MPCR_CL_8;
1477 break;
1478 }
1479
1480 if (termios->c_cflag & CSTOPB)
1481 stop_bits = MPSC_MPCR_SBL_2;
1482 else
1483 stop_bits = MPSC_MPCR_SBL_1;
1484
1485 par = MPSC_CHR_2_PAR_EVEN;
1486 if (termios->c_cflag & PARENB)
1487 if (termios->c_cflag & PARODD)
1488 par = MPSC_CHR_2_PAR_ODD;
1489 #ifdef CMSPAR
1490 if (termios->c_cflag & CMSPAR) {
1491 if (termios->c_cflag & PARODD)
1492 par = MPSC_CHR_2_PAR_MARK;
1493 else
1494 par = MPSC_CHR_2_PAR_SPACE;
1495 }
1496 #endif
1497
1498 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk);
1499
1500 spin_lock_irqsave(&pi->port.lock, flags);
1501
1502 uart_update_timeout(port, termios->c_cflag, baud);
1503
1504 mpsc_set_char_length(pi, chr_bits);
1505 mpsc_set_stop_bit_length(pi, stop_bits);
1506 mpsc_set_parity(pi, par);
1507 mpsc_set_baudrate(pi, baud);
1508
1509 /* Characters/events to read */
1510 pi->rcv_data = 1;
1511 pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR;
1512
1513 if (termios->c_iflag & INPCK)
1514 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE |
1515 SDMA_DESC_CMDSTAT_FR;
1516
1517 if (termios->c_iflag & (BRKINT | PARMRK))
1518 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR;
1519
1520 /* Characters/events to ignore */
1521 pi->port.ignore_status_mask = 0;
1522
1523 if (termios->c_iflag & IGNPAR)
1524 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_PE |
1525 SDMA_DESC_CMDSTAT_FR;
1526
1527 if (termios->c_iflag & IGNBRK) {
1528 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_BR;
1529
1530 if (termios->c_iflag & IGNPAR)
1531 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_OR;
1532 }
1533
1534 /* Ignore all chars if CREAD not set */
1535 if (!(termios->c_cflag & CREAD))
1536 pi->rcv_data = 0;
1537 else
1538 mpsc_start_rx(pi);
1539
1540 spin_unlock_irqrestore(&pi->port.lock, flags);
1541 return;
1542 }
1543
1544 static const char *
1545 mpsc_type(struct uart_port *port)
1546 {
1547 pr_debug("mpsc_type[%d]: port type: %s\n", port->line,MPSC_DRIVER_NAME);
1548 return MPSC_DRIVER_NAME;
1549 }
1550
1551 static int
1552 mpsc_request_port(struct uart_port *port)
1553 {
1554 /* Should make chip/platform specific call */
1555 return 0;
1556 }
1557
1558 static void
1559 mpsc_release_port(struct uart_port *port)
1560 {
1561 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1562
1563 if (pi->ready) {
1564 mpsc_uninit_rings(pi);
1565 mpsc_free_ring_mem(pi);
1566 pi->ready = 0;
1567 }
1568
1569 return;
1570 }
1571
1572 static void
1573 mpsc_config_port(struct uart_port *port, int flags)
1574 {
1575 return;
1576 }
1577
1578 static int
1579 mpsc_verify_port(struct uart_port *port, struct serial_struct *ser)
1580 {
1581 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1582 int rc = 0;
1583
1584 pr_debug("mpsc_verify_port[%d]: Verifying port data\n", pi->port.line);
1585
1586 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPSC)
1587 rc = -EINVAL;
1588 else if (pi->port.irq != ser->irq)
1589 rc = -EINVAL;
1590 else if (ser->io_type != SERIAL_IO_MEM)
1591 rc = -EINVAL;
1592 else if (pi->port.uartclk / 16 != ser->baud_base) /* Not sure */
1593 rc = -EINVAL;
1594 else if ((void *)pi->port.mapbase != ser->iomem_base)
1595 rc = -EINVAL;
1596 else if (pi->port.iobase != ser->port)
1597 rc = -EINVAL;
1598 else if (ser->hub6 != 0)
1599 rc = -EINVAL;
1600
1601 return rc;
1602 }
1603
1604 static struct uart_ops mpsc_pops = {
1605 .tx_empty = mpsc_tx_empty,
1606 .set_mctrl = mpsc_set_mctrl,
1607 .get_mctrl = mpsc_get_mctrl,
1608 .stop_tx = mpsc_stop_tx,
1609 .start_tx = mpsc_start_tx,
1610 .stop_rx = mpsc_stop_rx,
1611 .enable_ms = mpsc_enable_ms,
1612 .break_ctl = mpsc_break_ctl,
1613 .startup = mpsc_startup,
1614 .shutdown = mpsc_shutdown,
1615 .set_termios = mpsc_set_termios,
1616 .type = mpsc_type,
1617 .release_port = mpsc_release_port,
1618 .request_port = mpsc_request_port,
1619 .config_port = mpsc_config_port,
1620 .verify_port = mpsc_verify_port,
1621 };
1622
1623 /*
1624 ******************************************************************************
1625 *
1626 * Console Interface Routines
1627 *
1628 ******************************************************************************
1629 */
1630
1631 #ifdef CONFIG_SERIAL_MPSC_CONSOLE
1632 static void
1633 mpsc_console_write(struct console *co, const char *s, uint count)
1634 {
1635 struct mpsc_port_info *pi = &mpsc_ports[co->index];
1636 u8 *bp, *dp, add_cr = 0;
1637 int i;
1638 unsigned long iflags;
1639
1640 spin_lock_irqsave(&pi->tx_lock, iflags);
1641
1642 while (pi->txr_head != pi->txr_tail) {
1643 while (mpsc_sdma_tx_active(pi))
1644 udelay(100);
1645 mpsc_sdma_intr_ack(pi);
1646 mpsc_tx_intr(pi);
1647 }
1648
1649 while (mpsc_sdma_tx_active(pi))
1650 udelay(100);
1651
1652 while (count > 0) {
1653 bp = dp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1654
1655 for (i = 0; i < MPSC_TXBE_SIZE; i++) {
1656 if (count == 0)
1657 break;
1658
1659 if (add_cr) {
1660 *(dp++) = '\r';
1661 add_cr = 0;
1662 }
1663 else {
1664 *(dp++) = *s;
1665
1666 if (*(s++) == '\n') { /* add '\r' after '\n' */
1667 add_cr = 1;
1668 count++;
1669 }
1670 }
1671
1672 count--;
1673 }
1674
1675 dma_cache_sync(pi->port.dev, (void *) bp, MPSC_TXBE_SIZE, DMA_BIDIRECTIONAL);
1676 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1677 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1678 flush_dcache_range((ulong)bp,
1679 (ulong)bp + MPSC_TXBE_SIZE);
1680 #endif
1681 mpsc_setup_tx_desc(pi, i, 0);
1682 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
1683 mpsc_sdma_start_tx(pi);
1684
1685 while (mpsc_sdma_tx_active(pi))
1686 udelay(100);
1687
1688 pi->txr_tail = (pi->txr_tail + 1) & (MPSC_TXR_ENTRIES - 1);
1689 }
1690
1691 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1692 return;
1693 }
1694
1695 static int __init
1696 mpsc_console_setup(struct console *co, char *options)
1697 {
1698 struct mpsc_port_info *pi;
1699 int baud, bits, parity, flow;
1700
1701 pr_debug("mpsc_console_setup[%d]: options: %s\n", co->index, options);
1702
1703 if (co->index >= MPSC_NUM_CTLRS)
1704 co->index = 0;
1705
1706 pi = &mpsc_ports[co->index];
1707
1708 baud = pi->default_baud;
1709 bits = pi->default_bits;
1710 parity = pi->default_parity;
1711 flow = pi->default_flow;
1712
1713 if (!pi->port.ops)
1714 return -ENODEV;
1715
1716 spin_lock_init(&pi->port.lock); /* Temporary fix--copied from 8250.c */
1717
1718 if (options)
1719 uart_parse_options(options, &baud, &parity, &bits, &flow);
1720
1721 return uart_set_options(&pi->port, co, baud, parity, bits, flow);
1722 }
1723
1724 static struct console mpsc_console = {
1725 .name = MPSC_DEV_NAME,
1726 .write = mpsc_console_write,
1727 .device = uart_console_device,
1728 .setup = mpsc_console_setup,
1729 .flags = CON_PRINTBUFFER,
1730 .index = -1,
1731 .data = &mpsc_reg,
1732 };
1733
1734 static int __init
1735 mpsc_late_console_init(void)
1736 {
1737 pr_debug("mpsc_late_console_init: Enter\n");
1738
1739 if (!(mpsc_console.flags & CON_ENABLED))
1740 register_console(&mpsc_console);
1741 return 0;
1742 }
1743
1744 late_initcall(mpsc_late_console_init);
1745
1746 #define MPSC_CONSOLE &mpsc_console
1747 #else
1748 #define MPSC_CONSOLE NULL
1749 #endif
1750 /*
1751 ******************************************************************************
1752 *
1753 * Dummy Platform Driver to extract & map shared register regions
1754 *
1755 ******************************************************************************
1756 */
1757 static void
1758 mpsc_resource_err(char *s)
1759 {
1760 printk(KERN_WARNING "MPSC: Platform device resource error in %s\n", s);
1761 return;
1762 }
1763
1764 static int
1765 mpsc_shared_map_regs(struct platform_device *pd)
1766 {
1767 struct resource *r;
1768
1769 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1770 MPSC_ROUTING_BASE_ORDER)) && request_mem_region(r->start,
1771 MPSC_ROUTING_REG_BLOCK_SIZE, "mpsc_routing_regs")) {
1772
1773 mpsc_shared_regs.mpsc_routing_base = ioremap(r->start,
1774 MPSC_ROUTING_REG_BLOCK_SIZE);
1775 mpsc_shared_regs.mpsc_routing_base_p = r->start;
1776 }
1777 else {
1778 mpsc_resource_err("MPSC routing base");
1779 return -ENOMEM;
1780 }
1781
1782 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1783 MPSC_SDMA_INTR_BASE_ORDER)) && request_mem_region(r->start,
1784 MPSC_SDMA_INTR_REG_BLOCK_SIZE, "sdma_intr_regs")) {
1785
1786 mpsc_shared_regs.sdma_intr_base = ioremap(r->start,
1787 MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1788 mpsc_shared_regs.sdma_intr_base_p = r->start;
1789 }
1790 else {
1791 iounmap(mpsc_shared_regs.mpsc_routing_base);
1792 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
1793 MPSC_ROUTING_REG_BLOCK_SIZE);
1794 mpsc_resource_err("SDMA intr base");
1795 return -ENOMEM;
1796 }
1797
1798 return 0;
1799 }
1800
1801 static void
1802 mpsc_shared_unmap_regs(void)
1803 {
1804 if (!mpsc_shared_regs.mpsc_routing_base) {
1805 iounmap(mpsc_shared_regs.mpsc_routing_base);
1806 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
1807 MPSC_ROUTING_REG_BLOCK_SIZE);
1808 }
1809 if (!mpsc_shared_regs.sdma_intr_base) {
1810 iounmap(mpsc_shared_regs.sdma_intr_base);
1811 release_mem_region(mpsc_shared_regs.sdma_intr_base_p,
1812 MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1813 }
1814
1815 mpsc_shared_regs.mpsc_routing_base = NULL;
1816 mpsc_shared_regs.sdma_intr_base = NULL;
1817
1818 mpsc_shared_regs.mpsc_routing_base_p = 0;
1819 mpsc_shared_regs.sdma_intr_base_p = 0;
1820
1821 return;
1822 }
1823
1824 static int
1825 mpsc_shared_drv_probe(struct platform_device *dev)
1826 {
1827 struct mpsc_shared_pdata *pdata;
1828 int rc = -ENODEV;
1829
1830 if (dev->id == 0) {
1831 if (!(rc = mpsc_shared_map_regs(dev))) {
1832 pdata = (struct mpsc_shared_pdata *)dev->dev.platform_data;
1833
1834 mpsc_shared_regs.MPSC_MRR_m = pdata->mrr_val;
1835 mpsc_shared_regs.MPSC_RCRR_m= pdata->rcrr_val;
1836 mpsc_shared_regs.MPSC_TCRR_m= pdata->tcrr_val;
1837 mpsc_shared_regs.SDMA_INTR_CAUSE_m =
1838 pdata->intr_cause_val;
1839 mpsc_shared_regs.SDMA_INTR_MASK_m =
1840 pdata->intr_mask_val;
1841
1842 rc = 0;
1843 }
1844 }
1845
1846 return rc;
1847 }
1848
1849 static int
1850 mpsc_shared_drv_remove(struct platform_device *dev)
1851 {
1852 int rc = -ENODEV;
1853
1854 if (dev->id == 0) {
1855 mpsc_shared_unmap_regs();
1856 mpsc_shared_regs.MPSC_MRR_m = 0;
1857 mpsc_shared_regs.MPSC_RCRR_m = 0;
1858 mpsc_shared_regs.MPSC_TCRR_m = 0;
1859 mpsc_shared_regs.SDMA_INTR_CAUSE_m = 0;
1860 mpsc_shared_regs.SDMA_INTR_MASK_m = 0;
1861 rc = 0;
1862 }
1863
1864 return rc;
1865 }
1866
1867 static struct platform_driver mpsc_shared_driver = {
1868 .probe = mpsc_shared_drv_probe,
1869 .remove = mpsc_shared_drv_remove,
1870 .driver = {
1871 .name = MPSC_SHARED_NAME,
1872 },
1873 };
1874
1875 /*
1876 ******************************************************************************
1877 *
1878 * Driver Interface Routines
1879 *
1880 ******************************************************************************
1881 */
1882 static struct uart_driver mpsc_reg = {
1883 .owner = THIS_MODULE,
1884 .driver_name = MPSC_DRIVER_NAME,
1885 .dev_name = MPSC_DEV_NAME,
1886 .major = MPSC_MAJOR,
1887 .minor = MPSC_MINOR_START,
1888 .nr = MPSC_NUM_CTLRS,
1889 .cons = MPSC_CONSOLE,
1890 };
1891
1892 static int
1893 mpsc_drv_map_regs(struct mpsc_port_info *pi, struct platform_device *pd)
1894 {
1895 struct resource *r;
1896
1897 if ((r = platform_get_resource(pd, IORESOURCE_MEM, MPSC_BASE_ORDER)) &&
1898 request_mem_region(r->start, MPSC_REG_BLOCK_SIZE, "mpsc_regs")){
1899
1900 pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE);
1901 pi->mpsc_base_p = r->start;
1902 }
1903 else {
1904 mpsc_resource_err("MPSC base");
1905 return -ENOMEM;
1906 }
1907
1908 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1909 MPSC_SDMA_BASE_ORDER)) && request_mem_region(r->start,
1910 MPSC_SDMA_REG_BLOCK_SIZE, "sdma_regs")) {
1911
1912 pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE);
1913 pi->sdma_base_p = r->start;
1914 }
1915 else {
1916 mpsc_resource_err("SDMA base");
1917 if (pi->mpsc_base) {
1918 iounmap(pi->mpsc_base);
1919 pi->mpsc_base = NULL;
1920 }
1921 return -ENOMEM;
1922 }
1923
1924 if ((r = platform_get_resource(pd,IORESOURCE_MEM,MPSC_BRG_BASE_ORDER))
1925 && request_mem_region(r->start, MPSC_BRG_REG_BLOCK_SIZE,
1926 "brg_regs")) {
1927
1928 pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE);
1929 pi->brg_base_p = r->start;
1930 }
1931 else {
1932 mpsc_resource_err("BRG base");
1933 if (pi->mpsc_base) {
1934 iounmap(pi->mpsc_base);
1935 pi->mpsc_base = NULL;
1936 }
1937 if (pi->sdma_base) {
1938 iounmap(pi->sdma_base);
1939 pi->sdma_base = NULL;
1940 }
1941 return -ENOMEM;
1942 }
1943
1944 return 0;
1945 }
1946
1947 static void
1948 mpsc_drv_unmap_regs(struct mpsc_port_info *pi)
1949 {
1950 if (!pi->mpsc_base) {
1951 iounmap(pi->mpsc_base);
1952 release_mem_region(pi->mpsc_base_p, MPSC_REG_BLOCK_SIZE);
1953 }
1954 if (!pi->sdma_base) {
1955 iounmap(pi->sdma_base);
1956 release_mem_region(pi->sdma_base_p, MPSC_SDMA_REG_BLOCK_SIZE);
1957 }
1958 if (!pi->brg_base) {
1959 iounmap(pi->brg_base);
1960 release_mem_region(pi->brg_base_p, MPSC_BRG_REG_BLOCK_SIZE);
1961 }
1962
1963 pi->mpsc_base = NULL;
1964 pi->sdma_base = NULL;
1965 pi->brg_base = NULL;
1966
1967 pi->mpsc_base_p = 0;
1968 pi->sdma_base_p = 0;
1969 pi->brg_base_p = 0;
1970
1971 return;
1972 }
1973
1974 static void
1975 mpsc_drv_get_platform_data(struct mpsc_port_info *pi,
1976 struct platform_device *pd, int num)
1977 {
1978 struct mpsc_pdata *pdata;
1979
1980 pdata = (struct mpsc_pdata *)pd->dev.platform_data;
1981
1982 pi->port.uartclk = pdata->brg_clk_freq;
1983 pi->port.iotype = UPIO_MEM;
1984 pi->port.line = num;
1985 pi->port.type = PORT_MPSC;
1986 pi->port.fifosize = MPSC_TXBE_SIZE;
1987 pi->port.membase = pi->mpsc_base;
1988 pi->port.mapbase = (ulong)pi->mpsc_base;
1989 pi->port.ops = &mpsc_pops;
1990
1991 pi->mirror_regs = pdata->mirror_regs;
1992 pi->cache_mgmt = pdata->cache_mgmt;
1993 pi->brg_can_tune = pdata->brg_can_tune;
1994 pi->brg_clk_src = pdata->brg_clk_src;
1995 pi->mpsc_max_idle = pdata->max_idle;
1996 pi->default_baud = pdata->default_baud;
1997 pi->default_bits = pdata->default_bits;
1998 pi->default_parity = pdata->default_parity;
1999 pi->default_flow = pdata->default_flow;
2000
2001 /* Initial values of mirrored regs */
2002 pi->MPSC_CHR_1_m = pdata->chr_1_val;
2003 pi->MPSC_CHR_2_m = pdata->chr_2_val;
2004 pi->MPSC_CHR_10_m = pdata->chr_10_val;
2005 pi->MPSC_MPCR_m = pdata->mpcr_val;
2006 pi->BRG_BCR_m = pdata->bcr_val;
2007
2008 pi->shared_regs = &mpsc_shared_regs;
2009
2010 pi->port.irq = platform_get_irq(pd, 0);
2011
2012 return;
2013 }
2014
2015 static int
2016 mpsc_drv_probe(struct platform_device *dev)
2017 {
2018 struct mpsc_port_info *pi;
2019 int rc = -ENODEV;
2020
2021 pr_debug("mpsc_drv_probe: Adding MPSC %d\n", dev->id);
2022
2023 if (dev->id < MPSC_NUM_CTLRS) {
2024 pi = &mpsc_ports[dev->id];
2025
2026 if (!(rc = mpsc_drv_map_regs(pi, dev))) {
2027 mpsc_drv_get_platform_data(pi, dev, dev->id);
2028
2029 if (!(rc = mpsc_make_ready(pi))) {
2030 spin_lock_init(&pi->tx_lock);
2031 if (!(rc = uart_add_one_port(&mpsc_reg,
2032 &pi->port)))
2033 rc = 0;
2034 else {
2035 mpsc_release_port(
2036 (struct uart_port *)pi);
2037 mpsc_drv_unmap_regs(pi);
2038 }
2039 }
2040 else
2041 mpsc_drv_unmap_regs(pi);
2042 }
2043 }
2044
2045 return rc;
2046 }
2047
2048 static int
2049 mpsc_drv_remove(struct platform_device *dev)
2050 {
2051 pr_debug("mpsc_drv_exit: Removing MPSC %d\n", dev->id);
2052
2053 if (dev->id < MPSC_NUM_CTLRS) {
2054 uart_remove_one_port(&mpsc_reg, &mpsc_ports[dev->id].port);
2055 mpsc_release_port((struct uart_port *)&mpsc_ports[dev->id].port);
2056 mpsc_drv_unmap_regs(&mpsc_ports[dev->id]);
2057 return 0;
2058 }
2059 else
2060 return -ENODEV;
2061 }
2062
2063 static struct platform_driver mpsc_driver = {
2064 .probe = mpsc_drv_probe,
2065 .remove = mpsc_drv_remove,
2066 .driver = {
2067 .name = MPSC_CTLR_NAME,
2068 },
2069 };
2070
2071 static int __init
2072 mpsc_drv_init(void)
2073 {
2074 int rc;
2075
2076 printk(KERN_INFO "Serial: MPSC driver $Revision: 1.00 $\n");
2077
2078 memset(mpsc_ports, 0, sizeof(mpsc_ports));
2079 memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs));
2080
2081 if (!(rc = uart_register_driver(&mpsc_reg))) {
2082 if (!(rc = platform_driver_register(&mpsc_shared_driver))) {
2083 if ((rc = platform_driver_register(&mpsc_driver))) {
2084 platform_driver_unregister(&mpsc_shared_driver);
2085 uart_unregister_driver(&mpsc_reg);
2086 }
2087 }
2088 else
2089 uart_unregister_driver(&mpsc_reg);
2090 }
2091
2092 return rc;
2093
2094 }
2095
2096 static void __exit
2097 mpsc_drv_exit(void)
2098 {
2099 platform_driver_unregister(&mpsc_driver);
2100 platform_driver_unregister(&mpsc_shared_driver);
2101 uart_unregister_driver(&mpsc_reg);
2102 memset(mpsc_ports, 0, sizeof(mpsc_ports));
2103 memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs));
2104 return;
2105 }
2106
2107 module_init(mpsc_drv_init);
2108 module_exit(mpsc_drv_exit);
2109
2110 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
2111 MODULE_DESCRIPTION("Generic Marvell MPSC serial/UART driver $Revision: 1.00 $");
2112 MODULE_VERSION(MPSC_VERSION);
2113 MODULE_LICENSE("GPL");
2114 MODULE_ALIAS_CHARDEV_MAJOR(MPSC_MAJOR);
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