include/asm-sh/irq.h

   1 #ifndef __ASM_SH_IRQ_H
   2 #define __ASM_SH_IRQ_H
   3
   4 /*
   5  *
   6  * linux/include/asm-sh/irq.h
   7  *
   8  * Copyright (C) 1999  Niibe Yutaka & Takeshi Yaegashi
   9  * Copyright (C) 2000  Kazumoto Kojima
  10  * Copyright (C) 2003  Paul Mundt
  11  *
  12  */
  13
  14 #include <asm/machvec.h>
  15 #include <asm/ptrace.h>         /* for pt_regs */
  16
  17 #if defined(CONFIG_SH_HP6XX) || \
  18     defined(CONFIG_SH_RTS7751R2D) || \
  19     defined(CONFIG_SH_HS7751RVOIP) || \
  20     defined(CONFIG_SH_HS7751RVOIP) || \
  21     defined(CONFIG_SH_SH03) || \
  22     defined(CONFIG_SH_R7780RP) || \
  23     defined(CONFIG_SH_LANDISK)
  24 #include <asm/mach/ide.h>
  25 #endif
  26
  27 #ifndef CONFIG_CPU_SUBTYPE_SH7780
  28
  29 #define INTC_DMAC0_MSK  0
  30
  31 #if defined(CONFIG_CPU_SH3)
  32 #define INTC_IPRA       0xfffffee2UL
  33 #define INTC_IPRB       0xfffffee4UL
  34 #elif defined(CONFIG_CPU_SH4)
  35 #define INTC_IPRA       0xffd00004UL
  36 #define INTC_IPRB       0xffd00008UL
  37 #define INTC_IPRC       0xffd0000cUL
  38 #define INTC_IPRD       0xffd00010UL
  39 #endif
  40
  41 #ifdef CONFIG_IDE
  42 # ifndef IRQ_CFCARD
  43 #  define IRQ_CFCARD    14
  44 # endif
  45 # ifndef IRQ_PCMCIA
  46 #  define IRQ_PCMCIA    15
  47 # endif
  48 #endif
  49
  50 #define TIMER_IRQ       16
  51 #define TIMER_IPR_ADDR  INTC_IPRA
  52 #define TIMER_IPR_POS    3
  53 #define TIMER_PRIORITY   2
  54
  55 #define TIMER1_IRQ      17
  56 #define TIMER1_IPR_ADDR INTC_IPRA
  57 #define TIMER1_IPR_POS   2
  58 #define TIMER1_PRIORITY  4
  59
  60 #define RTC_IRQ         22
  61 #define RTC_IPR_ADDR    INTC_IPRA
  62 #define RTC_IPR_POS      0
  63 #define RTC_PRIORITY    TIMER_PRIORITY
  64
  65 #if defined(CONFIG_CPU_SH3)
  66 #define DMTE0_IRQ       48
  67 #define DMTE1_IRQ       49
  68 #define DMTE2_IRQ       50
  69 #define DMTE3_IRQ       51
  70 #define DMA_IPR_ADDR    INTC_IPRE
  71 #define DMA_IPR_POS     3
  72 #define DMA_PRIORITY    7
  73 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
  74 /* TMU2 */
  75 #define TIMER2_IRQ      18
  76 #define TIMER2_IPR_ADDR INTC_IPRA
  77 #define TIMER2_IPR_POS   1
  78 #define TIMER2_PRIORITY  2
  79
  80 /* WDT */
  81 #define WDT_IRQ         27
  82 #define WDT_IPR_ADDR    INTC_IPRB
  83 #define WDT_IPR_POS      3
  84 #define WDT_PRIORITY     2
  85
  86 /* SIM (SIM Card Module) */
  87 #define SIM_ERI_IRQ     23
  88 #define SIM_RXI_IRQ     24
  89 #define SIM_TXI_IRQ     25
  90 #define SIM_TEND_IRQ    26
  91 #define SIM_IPR_ADDR    INTC_IPRB
  92 #define SIM_IPR_POS      1
  93 #define SIM_PRIORITY     2
  94
  95 /* VIO (Video I/O) */
  96 #define VIO_IRQ         52
  97 #define VIO_IPR_ADDR    INTC_IPRE
  98 #define VIO_IPR_POS      2
  99 #define VIO_PRIORITY     2
 100
 101 /* MFI (Multi Functional Interface) */
 102 #define MFI_IRQ         56
 103 #define MFI_IPR_ADDR    INTC_IPRE
 104 #define MFI_IPR_POS      1
 105 #define MFI_PRIORITY     2
 106
 107 /* VPU (Video Processing Unit) */
 108 #define VPU_IRQ         60
 109 #define VPU_IPR_ADDR    INTC_IPRE
 110 #define VPU_IPR_POS      0
 111 #define VPU_PRIORITY     2
 112
 113 /* KEY (Key Scan Interface) */
 114 #define KEY_IRQ         79
 115 #define KEY_IPR_ADDR    INTC_IPRF
 116 #define KEY_IPR_POS      3
 117 #define KEY_PRIORITY     2
 118
 119 /* CMT (Compare Match Timer) */
 120 #define CMT_IRQ         104
 121 #define CMT_IPR_ADDR    INTC_IPRF
 122 #define CMT_IPR_POS      0
 123 #define CMT_PRIORITY     2
 124
 125 /* DMAC(1) */
 126 #define DMTE0_IRQ       48
 127 #define DMTE1_IRQ       49
 128 #define DMTE2_IRQ       50
 129 #define DMTE3_IRQ       51
 130 #define DMA1_IPR_ADDR   INTC_IPRE
 131 #define DMA1_IPR_POS    3
 132 #define DMA1_PRIORITY   7
 133
 134 /* DMAC(2) */
 135 #define DMTE4_IRQ       76
 136 #define DMTE5_IRQ       77
 137 #define DMA2_IPR_ADDR   INTC_IPRF
 138 #define DMA2_IPR_POS    2
 139 #define DMA2_PRIORITY   7
 140
 141 /* SIOF0 */
 142 #define SIOF0_IRQ       84
 143 #define SIOF0_IPR_ADDR  INTC_IPRH
 144 #define SIOF0_IPR_POS   3
 145 #define SIOF0_PRIORITY  3
 146
 147 /* FLCTL (Flash Memory Controller) */
 148 #define FLSTE_IRQ       92
 149 #define FLTEND_IRQ      93
 150 #define FLTRQ0_IRQ      94
 151 #define FLTRQ1_IRQ      95
 152 #define FLCTL_IPR_ADDR  INTC_IPRH
 153 #define FLCTL_IPR_POS   1
 154 #define FLCTL_PRIORITY  3
 155
 156 /* IIC (IIC Bus Interface) */
 157 #define IIC_ALI_IRQ     96
 158 #define IIC_TACKI_IRQ   97
 159 #define IIC_WAITI_IRQ   98
 160 #define IIC_DTEI_IRQ    99
 161 #define IIC_IPR_ADDR    INTC_IPRH
 162 #define IIC_IPR_POS     0
 163 #define IIC_PRIORITY    3
 164
 165 /* SIO0 */
 166 #define SIO0_IRQ        88
 167 #define SIO0_IPR_ADDR   INTC_IPRI
 168 #define SIO0_IPR_POS    3
 169 #define SIO0_PRIORITY   3
 170
 171 /* SIU (Sound Interface Unit) */
 172 #define SIU_IRQ         108
 173 #define SIU_IPR_ADDR    INTC_IPRJ
 174 #define SIU_IPR_POS     1
 175 #define SIU_PRIORITY    3
 176
 177 #endif
 178 #elif defined(CONFIG_CPU_SH4)
 179 #define DMTE0_IRQ       34
 180 #define DMTE1_IRQ       35
 181 #define DMTE2_IRQ       36
 182 #define DMTE3_IRQ       37
 183 #define DMTE4_IRQ       44      /* 7751R only */
 184 #define DMTE5_IRQ       45      /* 7751R only */
 185 #define DMTE6_IRQ       46      /* 7751R only */
 186 #define DMTE7_IRQ       47      /* 7751R only */
 187 #define DMAE_IRQ        38
 188 #define DMA_IPR_ADDR    INTC_IPRC
 189 #define DMA_IPR_POS     2
 190 #define DMA_PRIORITY    7
 191 #endif
 192
 193 #if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
 194     defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
 195     defined (CONFIG_CPU_SUBTYPE_SH7751) || defined (CONFIG_CPU_SUBTYPE_SH7706)
 196 #define SCI_ERI_IRQ     23
 197 #define SCI_RXI_IRQ     24
 198 #define SCI_TXI_IRQ     25
 199 #define SCI_IPR_ADDR    INTC_IPRB
 200 #define SCI_IPR_POS     1
 201 #define SCI_PRIORITY    3
 202 #endif
 203
 204 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
 205 #define SCIF0_IRQ       80
 206 #define SCIF0_IPR_ADDR  INTC_IPRG
 207 #define SCIF0_IPR_POS   3
 208 #define SCIF0_PRIORITY  3
 209 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 210       defined(CONFIG_CPU_SUBTYPE_SH7706) || \
 211       defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 212       defined(CONFIG_CPU_SUBTYPE_SH7709)
 213 #define SCIF_ERI_IRQ    56
 214 #define SCIF_RXI_IRQ    57
 215 #define SCIF_BRI_IRQ    58
 216 #define SCIF_TXI_IRQ    59
 217 #define SCIF_IPR_ADDR   INTC_IPRE
 218 #define SCIF_IPR_POS    1
 219 #define SCIF_PRIORITY   3
 220
 221 #define IRDA_ERI_IRQ    52
 222 #define IRDA_RXI_IRQ    53
 223 #define IRDA_BRI_IRQ    54
 224 #define IRDA_TXI_IRQ    55
 225 #define IRDA_IPR_ADDR   INTC_IPRE
 226 #define IRDA_IPR_POS    2
 227 #define IRDA_PRIORITY   3
 228 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 229       defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
 230 #define SCIF_ERI_IRQ    40
 231 #define SCIF_RXI_IRQ    41
 232 #define SCIF_BRI_IRQ    42
 233 #define SCIF_TXI_IRQ    43
 234 #define SCIF_IPR_ADDR   INTC_IPRC
 235 #define SCIF_IPR_POS    1
 236 #define SCIF_PRIORITY   3
 237 #if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 238 #define SCIF1_ERI_IRQ   23
 239 #define SCIF1_RXI_IRQ   24
 240 #define SCIF1_BRI_IRQ   25
 241 #define SCIF1_TXI_IRQ   26
 242 #define SCIF1_IPR_ADDR  INTC_IPRB
 243 #define SCIF1_IPR_POS   1
 244 #define SCIF1_PRIORITY  3
 245 #endif /* ST40STB1 */
 246
 247 #endif /* 775x / SH4-202 / ST40STB1 */
 248 #endif /* 7780 */
 249
 250 /* NR_IRQS is made from three components:
 251  *   1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
 252  *   2. PINT_NR_IRQS   - number of PINT interrupts
 253  *   3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
 254  */
 255
 256 /* 1. ONCHIP_NR_IRQS */
 257 #if defined(CONFIG_CPU_SUBTYPE_SH7604)
 258 # define ONCHIP_NR_IRQS 24      // Actually 21
 259 #elif defined(CONFIG_CPU_SUBTYPE_SH7707)
 260 # define ONCHIP_NR_IRQS 64
 261 # define PINT_NR_IRQS   16
 262 #elif defined(CONFIG_CPU_SUBTYPE_SH7708)
 263 # define ONCHIP_NR_IRQS 32
 264 #elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
 265       defined(CONFIG_CPU_SUBTYPE_SH7706) || \
 266       defined(CONFIG_CPU_SUBTYPE_SH7705)
 267 # define ONCHIP_NR_IRQS 64      // Actually 61
 268 # define PINT_NR_IRQS   16
 269 #elif defined(CONFIG_CPU_SUBTYPE_SH7710)
 270 # define ONCHIP_NR_IRQS 104
 271 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)
 272 # define ONCHIP_NR_IRQS 48      // Actually 44
 273 #elif defined(CONFIG_CPU_SUBTYPE_SH7751)
 274 # define ONCHIP_NR_IRQS 72
 275 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
 276 # define ONCHIP_NR_IRQS 112     /* XXX */
 277 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
 278 # define ONCHIP_NR_IRQS 72
 279 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 280 # define ONCHIP_NR_IRQS 144
 281 #elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
 282       defined(CONFIG_CPU_SUBTYPE_SH73180) || \
 283       defined(CONFIG_CPU_SUBTYPE_SH7343)
 284 # define ONCHIP_NR_IRQS 109
 285 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 286 # define ONCHIP_NR_IRQS 111
 287 #elif defined(CONFIG_SH_UNKNOWN)        /* Most be last */
 288 # define ONCHIP_NR_IRQS 144
 289 #endif
 290
 291 /* 2. PINT_NR_IRQS */
 292 #ifdef CONFIG_SH_UNKNOWN
 293 # define PINT_NR_IRQS 16
 294 #else
 295 # ifndef PINT_NR_IRQS
 296 #  define PINT_NR_IRQS 0
 297 # endif
 298 #endif
 299
 300 #if PINT_NR_IRQS > 0
 301 # define PINT_IRQ_BASE  ONCHIP_NR_IRQS
 302 #endif
 303
 304 /* 3. OFFCHIP_NR_IRQS */
 305 #if defined(CONFIG_HD64461)
 306 # define OFFCHIP_NR_IRQS 18
 307 #elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
 308 # define OFFCHIP_NR_IRQS 48
 309 #elif defined(CONFIG_HD64465)
 310 # define OFFCHIP_NR_IRQS 16
 311 #elif defined (CONFIG_SH_EC3104)
 312 # define OFFCHIP_NR_IRQS 16
 313 #elif defined (CONFIG_SH_DREAMCAST)
 314 # define OFFCHIP_NR_IRQS 96
 315 #elif defined (CONFIG_SH_TITAN)
 316 # define OFFCHIP_NR_IRQS 4
 317 #elif defined(CONFIG_SH_R7780RP)
 318 # define OFFCHIP_NR_IRQS 16
 319 #elif defined(CONFIG_SH_7343_SOLUTION_ENGINE)
 320 # define OFFCHIP_NR_IRQS 12
 321 #elif defined(CONFIG_SH_UNKNOWN)
 322 # define OFFCHIP_NR_IRQS 16     /* Must also be last */
 323 #else
 324 # define OFFCHIP_NR_IRQS 0
 325 #endif
 326
 327 #if OFFCHIP_NR_IRQS > 0
 328 # define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
 329 #endif
 330
 331 /* NR_IRQS. 1+2+3 */
 332 #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
 333
 334 extern void disable_irq(unsigned int);
 335 extern void disable_irq_nosync(unsigned int);
 336 extern void enable_irq(unsigned int);
 337
 338 /*
 339  * Simple Mask Register Support
 340  */
 341 extern void make_maskreg_irq(unsigned int irq);
 342 extern unsigned short *irq_mask_register;
 343
 344 /*
 345  * PINT IRQs
 346  */
 347 void init_IRQ_pint(void);
 348
 349 /*
 350  * Function for "on chip support modules".
 351  */
 352 extern void make_ipr_irq(unsigned int irq, unsigned int addr,
 353                          int pos,  int priority);
 354 extern void make_imask_irq(unsigned int irq);
 355
 356 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
 357 #undef INTC_IPRA
 358 #undef INTC_IPRB
 359 #define INTC_IPRA       0xA414FEE2UL
 360 #define INTC_IPRB       0xA414FEE4UL
 361 #define INTC_IPRC       0xA4140016UL
 362 #define INTC_IPRD       0xA4140018UL
 363 #define INTC_IPRE       0xA414001AUL
 364 #define INTC_IPRF       0xA4080000UL
 365 #define INTC_IPRG       0xA4080002UL
 366 #define INTC_IPRH       0xA4080004UL
 367 #define INTC_IPRI       0xA4080006UL
 368 #define INTC_IPRJ       0xA4080008UL
 369
 370 #define INTC_IMR0       0xA4080040UL
 371 #define INTC_IMR1       0xA4080042UL
 372 #define INTC_IMR2       0xA4080044UL
 373 #define INTC_IMR3       0xA4080046UL
 374 #define INTC_IMR4       0xA4080048UL
 375 #define INTC_IMR5       0xA408004AUL
 376 #define INTC_IMR6       0xA408004CUL
 377 #define INTC_IMR7       0xA408004EUL
 378 #define INTC_IMR8       0xA4080050UL
 379 #define INTC_IMR9       0xA4080052UL
 380 #define INTC_IMR10      0xA4080054UL
 381
 382 #define INTC_IMCR0      0xA4080060UL
 383 #define INTC_IMCR1      0xA4080062UL
 384 #define INTC_IMCR2      0xA4080064UL
 385 #define INTC_IMCR3      0xA4080066UL
 386 #define INTC_IMCR4      0xA4080068UL
 387 #define INTC_IMCR5      0xA408006AUL
 388 #define INTC_IMCR6      0xA408006CUL
 389 #define INTC_IMCR7      0xA408006EUL
 390 #define INTC_IMCR8      0xA4080070UL
 391 #define INTC_IMCR9      0xA4080072UL
 392 #define INTC_IMCR10     0xA4080074UL
 393
 394 #define INTC_ICR0       0xA414FEE0UL
 395 #define INTC_ICR1       0xA4140010UL
 396
 397 #define INTC_IRR0       0xA4140004UL
 398
 399 #define PORT_PACR       0xA4050100UL
 400 #define PORT_PBCR       0xA4050102UL
 401 #define PORT_PCCR       0xA4050104UL
 402 #define PORT_PDCR       0xA4050106UL
 403 #define PORT_PECR       0xA4050108UL
 404 #define PORT_PFCR       0xA405010AUL
 405 #define PORT_PGCR       0xA405010CUL
 406 #define PORT_PHCR       0xA405010EUL
 407 #define PORT_PJCR       0xA4050110UL
 408 #define PORT_PKCR       0xA4050112UL
 409 #define PORT_PLCR       0xA4050114UL
 410 #define PORT_SCPCR      0xA4050116UL
 411 #define PORT_PMCR       0xA4050118UL
 412 #define PORT_PNCR       0xA405011AUL
 413 #define PORT_PQCR       0xA405011CUL
 414
 415 #define PORT_PSELA      0xA4050140UL
 416 #define PORT_PSELB      0xA4050142UL
 417 #define PORT_PSELC      0xA4050144UL
 418
 419 #define PORT_HIZCRA     0xA4050146UL
 420 #define PORT_HIZCRB     0xA4050148UL
 421 #define PORT_DRVCR      0xA4050150UL
 422
 423 #define PORT_PADR       0xA4050120UL
 424 #define PORT_PBDR       0xA4050122UL
 425 #define PORT_PCDR       0xA4050124UL
 426 #define PORT_PDDR       0xA4050126UL
 427 #define PORT_PEDR       0xA4050128UL
 428 #define PORT_PFDR       0xA405012AUL
 429 #define PORT_PGDR       0xA405012CUL
 430 #define PORT_PHDR       0xA405012EUL
 431 #define PORT_PJDR       0xA4050130UL
 432 #define PORT_PKDR       0xA4050132UL
 433 #define PORT_PLDR       0xA4050134UL
 434 #define PORT_SCPDR      0xA4050136UL
 435 #define PORT_PMDR       0xA4050138UL
 436 #define PORT_PNDR       0xA405013AUL
 437 #define PORT_PQDR       0xA405013CUL
 438
 439 #define IRQ0_IRQ        32
 440 #define IRQ1_IRQ        33
 441 #define IRQ2_IRQ        34
 442 #define IRQ3_IRQ        35
 443 #define IRQ4_IRQ        36
 444 #define IRQ5_IRQ        37
 445
 446 #define IRQ0_IPR_ADDR   INTC_IPRC
 447 #define IRQ1_IPR_ADDR   INTC_IPRC
 448 #define IRQ2_IPR_ADDR   INTC_IPRC
 449 #define IRQ3_IPR_ADDR   INTC_IPRC
 450 #define IRQ4_IPR_ADDR   INTC_IPRD
 451 #define IRQ5_IPR_ADDR   INTC_IPRD
 452
 453 #define IRQ0_IPR_POS    0
 454 #define IRQ1_IPR_POS    1
 455 #define IRQ2_IPR_POS    2
 456 #define IRQ3_IPR_POS    3
 457 #define IRQ4_IPR_POS    0
 458 #define IRQ5_IPR_POS    1
 459
 460 #define IRQ0_PRIORITY   1
 461 #define IRQ1_PRIORITY   1
 462 #define IRQ2_PRIORITY   1
 463 #define IRQ3_PRIORITY   1
 464 #define IRQ4_PRIORITY   1
 465 #define IRQ5_PRIORITY   1
 466
 467 extern int ipr_irq_demux(int irq);
 468 #define __irq_demux(irq) ipr_irq_demux(irq)
 469
 470 #elif defined(CONFIG_CPU_SUBTYPE_SH7604)
 471 #define INTC_IPRA       0xfffffee2UL
 472 #define INTC_IPRB       0xfffffe60UL
 473
 474 #define INTC_VCRA       0xfffffe62UL
 475 #define INTC_VCRB       0xfffffe64UL
 476 #define INTC_VCRC       0xfffffe66UL
 477 #define INTC_VCRD       0xfffffe68UL
 478
 479 #define INTC_VCRWDT     0xfffffee4UL
 480 #define INTC_VCRDIV     0xffffff0cUL
 481 #define INTC_VCRDMA0    0xffffffa0UL
 482 #define INTC_VCRDMA1    0xffffffa8UL
 483
 484 #define INTC_ICR        0xfffffee0UL
 485 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 486       defined(CONFIG_CPU_SUBTYPE_SH7706) || \
 487       defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 488       defined(CONFIG_CPU_SUBTYPE_SH7709) || \
 489       defined(CONFIG_CPU_SUBTYPE_SH7710)
 490 #define INTC_IRR0       0xa4000004UL
 491 #define INTC_IRR1       0xa4000006UL
 492 #define INTC_IRR2       0xa4000008UL
 493
 494 #define INTC_ICR0       0xfffffee0UL
 495 #define INTC_ICR1       0xa4000010UL
 496 #define INTC_ICR2       0xa4000012UL
 497 #define INTC_INTER      0xa4000014UL
 498
 499 #define INTC_IPRC       0xa4000016UL
 500 #define INTC_IPRD       0xa4000018UL
 501 #define INTC_IPRE       0xa400001aUL
 502 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
 503 #define INTC_IPRF       0xa400001cUL
 504 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
 505 #define INTC_IPRF       0xa4080000UL
 506 #define INTC_IPRG       0xa4080002UL
 507 #define INTC_IPRH       0xa4080004UL
 508 #elif defined(CONFIG_CPU_SUBTYPE_SH7710)
 509 /* Interrupt Controller Registers */
 510 #undef INTC_IPRA
 511 #undef INTC_IPRB
 512 #define INTC_IPRA       0xA414FEE2UL
 513 #define INTC_IPRB       0xA414FEE4UL
 514 #define INTC_IPRF       0xA4080000UL
 515 #define INTC_IPRG       0xA4080002UL
 516 #define INTC_IPRH       0xA4080004UL
 517 #define INTC_IPRI       0xA4080006UL
 518
 519 #undef INTC_ICR0
 520 #undef INTC_ICR1
 521 #define INTC_ICR0       0xA414FEE0UL
 522 #define INTC_ICR1       0xA4140010UL
 523
 524 #define INTC_IRR0       0xa4000004UL
 525 #define INTC_IRR1       0xa4000006UL
 526 #define INTC_IRR2       0xa4000008UL
 527 #define INTC_IRR3       0xa400000AUL
 528 #define INTC_IRR4       0xa400000CUL
 529 #define INTC_IRR5       0xa4080020UL
 530 #define INTC_IRR7       0xa4080024UL
 531 #define INTC_IRR8       0xa4080026UL
 532
 533 /* Interrupt numbers */
 534 #define TIMER2_IRQ      18
 535 #define TIMER2_IPR_ADDR INTC_IPRA
 536 #define TIMER2_IPR_POS   1
 537 #define TIMER2_PRIORITY  2
 538
 539 /* WDT */
 540 #define WDT_IRQ         27
 541 #define WDT_IPR_ADDR    INTC_IPRB
 542 #define WDT_IPR_POS      3
 543 #define WDT_PRIORITY     2
 544
 545 #define SCIF0_ERI_IRQ   52
 546 #define SCIF0_RXI_IRQ   53
 547 #define SCIF0_BRI_IRQ   54
 548 #define SCIF0_TXI_IRQ   55
 549 #define SCIF0_IPR_ADDR  INTC_IPRE
 550 #define SCIF0_IPR_POS   2
 551 #define SCIF0_PRIORITY  3
 552
 553 #define DMTE4_IRQ       76
 554 #define DMTE5_IRQ       77
 555 #define DMA2_IPR_ADDR   INTC_IPRF
 556 #define DMA2_IPR_POS    2
 557 #define DMA2_PRIORITY   7
 558
 559 #define IPSEC_IRQ       79
 560 #define IPSEC_IPR_ADDR  INTC_IPRF
 561 #define IPSEC_IPR_POS   3
 562 #define IPSEC_PRIORITY  3
 563
 564 /* EDMAC */
 565 #define EDMAC0_IRQ      80
 566 #define EDMAC0_IPR_ADDR INTC_IPRG
 567 #define EDMAC0_IPR_POS  3
 568 #define EDMAC0_PRIORITY 3
 569
 570 #define EDMAC1_IRQ      81
 571 #define EDMAC1_IPR_ADDR INTC_IPRG
 572 #define EDMAC1_IPR_POS  2
 573 #define EDMAC1_PRIORITY 3
 574
 575 #define EDMAC2_IRQ      82
 576 #define EDMAC2_IPR_ADDR INTC_IPRG
 577 #define EDMAC2_IPR_POS  1
 578 #define EDMAC2_PRIORITY 3
 579
 580 /* SIOF */
 581 #define SIOF0_ERI_IRQ   96
 582 #define SIOF0_TXI_IRQ   97
 583 #define SIOF0_RXI_IRQ   98
 584 #define SIOF0_CCI_IRQ   99
 585 #define SIOF0_IPR_ADDR  INTC_IPRH
 586 #define SIOF0_IPR_POS   0
 587 #define SIOF0_PRIORITY  7
 588
 589 #define SIOF1_ERI_IRQ   100
 590 #define SIOF1_TXI_IRQ   101
 591 #define SIOF1_RXI_IRQ   102
 592 #define SIOF1_CCI_IRQ   103
 593 #define SIOF1_IPR_ADDR  INTC_IPRI
 594 #define SIOF1_IPR_POS   1
 595 #define SIOF1_PRIORITY  7
 596 #endif /* CONFIG_CPU_SUBTYPE_SH7710 */
 597
 598 #if defined(CONFIG_CPU_SUBTYPE_SH7710)
 599 #define PORT_PACR       0xa4050100UL
 600 #define PORT_PBCR       0xa4050102UL
 601 #define PORT_PCCR       0xa4050104UL
 602 #define PORT_PETCR      0xa4050106UL
 603 #define PORT_PADR       0xa4050120UL
 604 #define PORT_PBDR       0xa4050122UL
 605 #define PORT_PCDR       0xa4050124UL
 606 #else
 607 #define PORT_PACR       0xa4000100UL
 608 #define PORT_PBCR       0xa4000102UL
 609 #define PORT_PCCR       0xa4000104UL
 610 #define PORT_PFCR       0xa400010aUL
 611 #define PORT_PADR       0xa4000120UL
 612 #define PORT_PBDR       0xa4000122UL
 613 #define PORT_PCDR       0xa4000124UL
 614 #define PORT_PFDR       0xa400012aUL
 615 #endif
 616
 617 #define IRQ0_IRQ        32
 618 #define IRQ1_IRQ        33
 619 #define IRQ2_IRQ        34
 620 #define IRQ3_IRQ        35
 621 #define IRQ4_IRQ        36
 622 #define IRQ5_IRQ        37
 623
 624 #define IRQ0_IPR_ADDR   INTC_IPRC
 625 #define IRQ1_IPR_ADDR   INTC_IPRC
 626 #define IRQ2_IPR_ADDR   INTC_IPRC
 627 #define IRQ3_IPR_ADDR   INTC_IPRC
 628 #define IRQ4_IPR_ADDR   INTC_IPRD
 629 #define IRQ5_IPR_ADDR   INTC_IPRD
 630
 631 #define IRQ0_IPR_POS    0
 632 #define IRQ1_IPR_POS    1
 633 #define IRQ2_IPR_POS    2
 634 #define IRQ3_IPR_POS    3
 635 #define IRQ4_IPR_POS    0
 636 #define IRQ5_IPR_POS    1
 637
 638 #define IRQ0_PRIORITY   1
 639 #define IRQ1_PRIORITY   1
 640 #define IRQ2_PRIORITY   1
 641 #define IRQ3_PRIORITY   1
 642 #define IRQ4_PRIORITY   1
 643 #define IRQ5_PRIORITY   1
 644
 645 #define PINT0_IRQ       40
 646 #define PINT8_IRQ       41
 647
 648 #define PINT0_IPR_ADDR  INTC_IPRD
 649 #define PINT8_IPR_ADDR  INTC_IPRD
 650
 651 #define PINT0_IPR_POS   3
 652 #define PINT8_IPR_POS   2
 653 #define PINT0_PRIORITY  2
 654 #define PINT8_PRIORITY  2
 655
 656 extern int ipr_irq_demux(int irq);
 657 #define __irq_demux(irq) ipr_irq_demux(irq)
 658 #endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
 659
 660 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 661     defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
 662 #define INTC_ICR        0xffd00000
 663 #define INTC_ICR_NMIL   (1<<15)
 664 #define INTC_ICR_MAI    (1<<14)
 665 #define INTC_ICR_NMIB   (1<<9)
 666 #define INTC_ICR_NMIE   (1<<8)
 667 #define INTC_ICR_IRLM   (1<<7)
 668 #endif
 669
 670 #ifdef CONFIG_CPU_SUBTYPE_SH7780
 671 #include <asm/irq-sh7780.h>
 672 #endif
 673
 674 /* SH with INTC2-style interrupts */
 675 #ifdef CONFIG_CPU_HAS_INTC2_IRQ
 676 #if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 677 #define INTC2_BASE      0xfe080000
 678 #define INTC2_FIRST_IRQ 64
 679 #define INTC2_INTREQ_OFFSET     0x20
 680 #define INTC2_INTMSK_OFFSET     0x40
 681 #define INTC2_INTMSKCLR_OFFSET  0x60
 682 #define NR_INTC2_IRQS   25
 683 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
 684 #define INTC2_BASE      0xfe080000
 685 #define INTC2_FIRST_IRQ 48      /* INTEVT 0x800 */
 686 #define INTC2_INTREQ_OFFSET     0x20
 687 #define INTC2_INTMSK_OFFSET     0x40
 688 #define INTC2_INTMSKCLR_OFFSET  0x60
 689 #define NR_INTC2_IRQS   64
 690 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 691 #define INTC2_BASE      0xffd40000
 692 #define INTC2_FIRST_IRQ 21
 693 #define INTC2_INTMSK_OFFSET     (0x38)
 694 #define INTC2_INTMSKCLR_OFFSET  (0x3c)
 695 #define NR_INTC2_IRQS   60
 696 #endif
 697
 698 #define INTC2_INTPRI_OFFSET     0x00
 699
 700 void make_intc2_irq(unsigned int irq,
 701                     unsigned int ipr_offset, unsigned int ipr_shift,
 702                     unsigned int msk_offset, unsigned int msk_shift,
 703                     unsigned int priority);
 704 void init_IRQ_intc2(void);
 705 void intc2_add_clear_irq(int irq, int (*fn)(int));
 706
 707 #endif
 708
 709 extern int shmse_irq_demux(int irq);
 710
 711 static inline int generic_irq_demux(int irq)
 712 {
 713         return irq;
 714 }
 715
 716 #ifndef __irq_demux
 717 #define __irq_demux(irq)        (irq)
 718 #endif
 719 #define irq_canonicalize(irq)   (irq)
 720 #define irq_demux(irq)          __irq_demux(sh_mv.mv_irq_demux(irq))
 721
 722 #ifdef CONFIG_4KSTACKS
 723 extern void irq_ctx_init(int cpu);
 724 extern void irq_ctx_exit(int cpu);
 725 # define __ARCH_HAS_DO_SOFTIRQ
 726 #else
 727 # define irq_ctx_init(cpu) do { } while (0)
 728 # define irq_ctx_exit(cpu) do { } while (0)
 729 #endif
 730
 731 #if defined(CONFIG_CPU_SUBTYPE_SH73180)
 732 #include <asm/irq-sh73180.h>
 733 #endif
 734
 735 #if defined(CONFIG_CPU_SUBTYPE_SH7343)
 736 #include <asm/irq-sh7343.h>
 737 #endif
 738
 739 #endif /* __ASM_SH_IRQ_H */