arch/x86/kernel/quirks.c

   1 /*
   2  * This file contains work-arounds for x86 and x86_64 platform bugs.
   3  */
   4 #include <linux/pci.h>
   5 #include <linux/irq.h>
   6
   7 #include <asm/hpet.h>
   8
   9 #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
  10
  11 static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
  12 {
  13         u8 config, rev;
  14         u16 word;
  15
  16         /* BIOS may enable hardware IRQ balancing for
  17          * E7520/E7320/E7525(revision ID 0x9 and below)
  18          * based platforms.
  19          * Disable SW irqbalance/affinity on those platforms.
  20          */
  21         pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
  22         if (rev > 0x9)
  23                 return;
  24
  25         /* enable access to config space*/
  26         pci_read_config_byte(dev, 0xf4, &config);
  27         pci_write_config_byte(dev, 0xf4, config|0x2);
  28
  29         /*
  30          * read xTPR register.  We may not have a pci_dev for device 8
  31          * because it might be hidden until the above write.
  32          */
  33         pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word);
  34
  35         if (!(word & (1 << 13))) {
  36                 dev_info(&dev->dev, "Intel E7520/7320/7525 detected; "
  37                         "disabling irq balancing and affinity\n");
  38 #ifdef CONFIG_IRQBALANCE
  39                 irqbalance_disable("");
  40 #endif
  41                 noirqdebug_setup("");
  42 #ifdef CONFIG_PROC_FS
  43                 no_irq_affinity = 1;
  44 #endif
  45         }
  46
  47         /* put back the original value for config space*/
  48         if (!(config & 0x2))
  49                 pci_write_config_byte(dev, 0xf4, config);
  50 }
  51 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
  52                         quirk_intel_irqbalance);
  53 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
  54                         quirk_intel_irqbalance);
  55 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
  56                         quirk_intel_irqbalance);
  57 #endif
  58
  59 #if defined(CONFIG_HPET_TIMER)
  60 unsigned long force_hpet_address;
  61
  62 static enum {
  63         NONE_FORCE_HPET_RESUME,
  64         OLD_ICH_FORCE_HPET_RESUME,
  65         ICH_FORCE_HPET_RESUME,
  66         VT8237_FORCE_HPET_RESUME,
  67         NVIDIA_FORCE_HPET_RESUME,
  68 } force_hpet_resume_type;
  69
  70 static void __iomem *rcba_base;
  71
  72 static void ich_force_hpet_resume(void)
  73 {
  74         u32 val;
  75
  76         if (!force_hpet_address)
  77                 return;
  78
  79         if (rcba_base == NULL)
  80                 BUG();
  81
  82         /* read the Function Disable register, dword mode only */
  83         val = readl(rcba_base + 0x3404);
  84         if (!(val & 0x80)) {
  85                 /* HPET disabled in HPTC. Trying to enable */
  86                 writel(val | 0x80, rcba_base + 0x3404);
  87         }
  88
  89         val = readl(rcba_base + 0x3404);
  90         if (!(val & 0x80))
  91                 BUG();
  92         else
  93                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
  94
  95         return;
  96 }
  97
  98 static void ich_force_enable_hpet(struct pci_dev *dev)
  99 {
 100         u32 val;
 101         u32 uninitialized_var(rcba);
 102         int err = 0;
 103
 104         if (hpet_address || force_hpet_address)
 105                 return;
 106
 107         pci_read_config_dword(dev, 0xF0, &rcba);
 108         rcba &= 0xFFFFC000;
 109         if (rcba == 0) {
 110                 dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; "
 111                         "cannot force enable HPET\n");
 112                 return;
 113         }
 114
 115         /* use bits 31:14, 16 kB aligned */
 116         rcba_base = ioremap_nocache(rcba, 0x4000);
 117         if (rcba_base == NULL) {
 118                 dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; "
 119                         "cannot force enable HPET\n");
 120                 return;
 121         }
 122
 123         /* read the Function Disable register, dword mode only */
 124         val = readl(rcba_base + 0x3404);
 125
 126         if (val & 0x80) {
 127                 /* HPET is enabled in HPTC. Just not reported by BIOS */
 128                 val = val & 0x3;
 129                 force_hpet_address = 0xFED00000 | (val << 12);
 130                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
 131                         "0x%lx\n", force_hpet_address);
 132                 iounmap(rcba_base);
 133                 return;
 134         }
 135
 136         /* HPET disabled in HPTC. Trying to enable */
 137         writel(val | 0x80, rcba_base + 0x3404);
 138
 139         val = readl(rcba_base + 0x3404);
 140         if (!(val & 0x80)) {
 141                 err = 1;
 142         } else {
 143                 val = val & 0x3;
 144                 force_hpet_address = 0xFED00000 | (val << 12);
 145         }
 146
 147         if (err) {
 148                 force_hpet_address = 0;
 149                 iounmap(rcba_base);
 150                 dev_printk(KERN_DEBUG, &dev->dev,
 151                         "Failed to force enable HPET\n");
 152         } else {
 153                 force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
 154                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
 155                         "0x%lx\n", force_hpet_address);
 156         }
 157 }
 158
 159 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
 160                          ich_force_enable_hpet);
 161 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0,
 162                          ich_force_enable_hpet);
 163 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
 164                          ich_force_enable_hpet);
 165 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
 166                          ich_force_enable_hpet);
 167 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
 168                          ich_force_enable_hpet);
 169 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
 170                          ich_force_enable_hpet);
 171 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
 172                          ich_force_enable_hpet);
 173 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7,
 174                          ich_force_enable_hpet);
 175
 176
 177 static struct pci_dev *cached_dev;
 178
 179 static void old_ich_force_hpet_resume(void)
 180 {
 181         u32 val;
 182         u32 uninitialized_var(gen_cntl);
 183
 184         if (!force_hpet_address || !cached_dev)
 185                 return;
 186
 187         pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
 188         gen_cntl &= (~(0x7 << 15));
 189         gen_cntl |= (0x4 << 15);
 190
 191         pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
 192         pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
 193         val = gen_cntl >> 15;
 194         val &= 0x7;
 195         if (val == 0x4)
 196                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
 197         else
 198                 BUG();
 199 }
 200
 201 static void old_ich_force_enable_hpet(struct pci_dev *dev)
 202 {
 203         u32 val;
 204         u32 uninitialized_var(gen_cntl);
 205
 206         if (hpet_address || force_hpet_address)
 207                 return;
 208
 209         pci_read_config_dword(dev, 0xD0, &gen_cntl);
 210         /*
 211          * Bit 17 is HPET enable bit.
 212          * Bit 16:15 control the HPET base address.
 213          */
 214         val = gen_cntl >> 15;
 215         val &= 0x7;
 216         if (val & 0x4) {
 217                 val &= 0x3;
 218                 force_hpet_address = 0xFED00000 | (val << 12);
 219                 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
 220                         force_hpet_address);
 221                 return;
 222         }
 223
 224         /*
 225          * HPET is disabled. Trying enabling at FED00000 and check
 226          * whether it sticks
 227          */
 228         gen_cntl &= (~(0x7 << 15));
 229         gen_cntl |= (0x4 << 15);
 230         pci_write_config_dword(dev, 0xD0, gen_cntl);
 231
 232         pci_read_config_dword(dev, 0xD0, &gen_cntl);
 233
 234         val = gen_cntl >> 15;
 235         val &= 0x7;
 236         if (val & 0x4) {
 237                 /* HPET is enabled in HPTC. Just not reported by BIOS */
 238                 val &= 0x3;
 239                 force_hpet_address = 0xFED00000 | (val << 12);
 240                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
 241                         "0x%lx\n", force_hpet_address);
 242                 cached_dev = dev;
 243                 force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
 244                 return;
 245         }
 246
 247         dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
 248 }
 249
 250 /*
 251  * Undocumented chipset features. Make sure that the user enforced
 252  * this.
 253  */
 254 static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
 255 {
 256         if (hpet_force_user)
 257                 old_ich_force_enable_hpet(dev);
 258 }
 259
 260 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
 261                          old_ich_force_enable_hpet_user);
 262 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
 263                          old_ich_force_enable_hpet_user);
 264 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12,
 265                          old_ich_force_enable_hpet_user);
 266 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
 267                          old_ich_force_enable_hpet_user);
 268 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
 269                          old_ich_force_enable_hpet_user);
 270 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
 271                          old_ich_force_enable_hpet);
 272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
 273                          old_ich_force_enable_hpet);
 274
 275
 276 static void vt8237_force_hpet_resume(void)
 277 {
 278         u32 val;
 279
 280         if (!force_hpet_address || !cached_dev)
 281                 return;
 282
 283         val = 0xfed00000 | 0x80;
 284         pci_write_config_dword(cached_dev, 0x68, val);
 285
 286         pci_read_config_dword(cached_dev, 0x68, &val);
 287         if (val & 0x80)
 288                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
 289         else
 290                 BUG();
 291 }
 292
 293 static void vt8237_force_enable_hpet(struct pci_dev *dev)
 294 {
 295         u32 uninitialized_var(val);
 296
 297         if (!hpet_force_user || hpet_address || force_hpet_address)
 298                 return;
 299
 300         pci_read_config_dword(dev, 0x68, &val);
 301         /*
 302          * Bit 7 is HPET enable bit.
 303          * Bit 31:10 is HPET base address (contrary to what datasheet claims)
 304          */
 305         if (val & 0x80) {
 306                 force_hpet_address = (val & ~0x3ff);
 307                 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
 308                         force_hpet_address);
 309                 return;
 310         }
 311
 312         /*
 313          * HPET is disabled. Trying enabling at FED00000 and check
 314          * whether it sticks
 315          */
 316         val = 0xfed00000 | 0x80;
 317         pci_write_config_dword(dev, 0x68, val);
 318
 319         pci_read_config_dword(dev, 0x68, &val);
 320         if (val & 0x80) {
 321                 force_hpet_address = (val & ~0x3ff);
 322                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
 323                         "0x%lx\n", force_hpet_address);
 324                 cached_dev = dev;
 325                 force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
 326                 return;
 327         }
 328
 329         dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
 330 }
 331
 332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
 333                          vt8237_force_enable_hpet);
 334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
 335                          vt8237_force_enable_hpet);
 336
 337 /*
 338  * Undocumented chipset feature taken from LinuxBIOS.
 339  */
 340 static void nvidia_force_hpet_resume(void)
 341 {
 342         pci_write_config_dword(cached_dev, 0x44, 0xfed00001);
 343         printk(KERN_DEBUG "Force enabled HPET at resume\n");
 344 }
 345
 346 static void nvidia_force_enable_hpet(struct pci_dev *dev)
 347 {
 348         u32 uninitialized_var(val);
 349
 350         if (!hpet_force_user || hpet_address || force_hpet_address)
 351                 return;
 352
 353         pci_write_config_dword(dev, 0x44, 0xfed00001);
 354         pci_read_config_dword(dev, 0x44, &val);
 355         force_hpet_address = val & 0xfffffffe;
 356         force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME;
 357         dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
 358                 force_hpet_address);
 359         cached_dev = dev;
 360         return;
 361 }
 362
 363 /* ISA Bridges */
 364 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050,
 365                         nvidia_force_enable_hpet);
 366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051,
 367                         nvidia_force_enable_hpet);
 368
 369 /* LPC bridges */
 370 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260,
 371                         nvidia_force_enable_hpet);
 372 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360,
 373                         nvidia_force_enable_hpet);
 374 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361,
 375                         nvidia_force_enable_hpet);
 376 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362,
 377                         nvidia_force_enable_hpet);
 378 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363,
 379                         nvidia_force_enable_hpet);
 380 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364,
 381                         nvidia_force_enable_hpet);
 382 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365,
 383                         nvidia_force_enable_hpet);
 384 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366,
 385                         nvidia_force_enable_hpet);
 386 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367,
 387                         nvidia_force_enable_hpet);
 388
 389 void force_hpet_resume(void)
 390 {
 391         switch (force_hpet_resume_type) {
 392         case ICH_FORCE_HPET_RESUME:
 393                 ich_force_hpet_resume();
 394                 return;
 395         case OLD_ICH_FORCE_HPET_RESUME:
 396                 old_ich_force_hpet_resume();
 397                 return;
 398         case VT8237_FORCE_HPET_RESUME:
 399                 vt8237_force_hpet_resume();
 400                 return;
 401         case NVIDIA_FORCE_HPET_RESUME:
 402                 nvidia_force_hpet_resume();
 403                 return;
 404         default:
 405                 break;
 406         }
 407 }
 408
 409 #endif