2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/pci.h>
26 #include <linux/delay.h>
27 #include <linux/poll.h>
28 #include <linux/dma-mapping.h>
31 #include <asm/uaccess.h>
32 #include <asm/semaphore.h>
34 #include "fw-transaction.h"
37 #define DESCRIPTOR_OUTPUT_MORE 0
38 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
39 #define DESCRIPTOR_INPUT_MORE (2 << 12)
40 #define DESCRIPTOR_INPUT_LAST (3 << 12)
41 #define DESCRIPTOR_STATUS (1 << 11)
42 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
43 #define DESCRIPTOR_PING (1 << 7)
44 #define DESCRIPTOR_YY (1 << 6)
45 #define DESCRIPTOR_NO_IRQ (0 << 4)
46 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
47 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
48 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
49 #define DESCRIPTOR_WAIT (3 << 0)
55 __le32 branch_address
;
57 __le16 transfer_status
;
58 } __attribute__((aligned(16)));
60 struct db_descriptor
{
63 __le16 second_req_count
;
64 __le16 first_req_count
;
65 __le32 branch_address
;
66 __le16 second_res_count
;
67 __le16 first_res_count
;
72 } __attribute__((aligned(16)));
74 #define CONTROL_SET(regs) (regs)
75 #define CONTROL_CLEAR(regs) ((regs) + 4)
76 #define COMMAND_PTR(regs) ((regs) + 12)
77 #define CONTEXT_MATCH(regs) ((regs) + 16)
80 struct descriptor descriptor
;
81 struct ar_buffer
*next
;
87 struct ar_buffer
*current_buffer
;
88 struct ar_buffer
*last_buffer
;
91 struct tasklet_struct tasklet
;
96 typedef int (*descriptor_callback_t
)(struct context
*ctx
,
98 struct descriptor
*last
);
100 struct fw_ohci
*ohci
;
103 struct descriptor
*buffer
;
104 dma_addr_t buffer_bus
;
106 struct descriptor
*head_descriptor
;
107 struct descriptor
*tail_descriptor
;
108 struct descriptor
*tail_descriptor_last
;
109 struct descriptor
*prev_descriptor
;
111 descriptor_callback_t callback
;
113 struct tasklet_struct tasklet
;
116 #define IT_HEADER_SY(v) ((v) << 0)
117 #define IT_HEADER_TCODE(v) ((v) << 4)
118 #define IT_HEADER_CHANNEL(v) ((v) << 8)
119 #define IT_HEADER_TAG(v) ((v) << 14)
120 #define IT_HEADER_SPEED(v) ((v) << 16)
121 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
124 struct fw_iso_context base
;
125 struct context context
;
127 size_t header_length
;
130 #define CONFIG_ROM_SIZE 1024
136 __iomem
char *registers
;
137 dma_addr_t self_id_bus
;
139 struct tasklet_struct bus_reset_tasklet
;
142 int request_generation
;
146 * Spinlock for accessing fw_ohci data. Never call out of
147 * this driver with this lock held.
150 u32 self_id_buffer
[512];
152 /* Config rom buffers */
154 dma_addr_t config_rom_bus
;
155 __be32
*next_config_rom
;
156 dma_addr_t next_config_rom_bus
;
159 struct ar_context ar_request_ctx
;
160 struct ar_context ar_response_ctx
;
161 struct context at_request_ctx
;
162 struct context at_response_ctx
;
165 struct iso_context
*it_context_list
;
167 struct iso_context
*ir_context_list
;
170 static inline struct fw_ohci
*fw_ohci(struct fw_card
*card
)
172 return container_of(card
, struct fw_ohci
, card
);
175 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
176 #define IR_CONTEXT_BUFFER_FILL 0x80000000
177 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
178 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
179 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
180 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
182 #define CONTEXT_RUN 0x8000
183 #define CONTEXT_WAKE 0x1000
184 #define CONTEXT_DEAD 0x0800
185 #define CONTEXT_ACTIVE 0x0400
187 #define OHCI1394_MAX_AT_REQ_RETRIES 0x2
188 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
189 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
191 #define FW_OHCI_MAJOR 240
192 #define OHCI1394_REGISTER_SIZE 0x800
193 #define OHCI_LOOP_COUNT 500
194 #define OHCI1394_PCI_HCI_Control 0x40
195 #define SELF_ID_BUF_SIZE 0x800
196 #define OHCI_TCODE_PHY_PACKET 0x0e
197 #define OHCI_VERSION_1_1 0x010010
198 #define ISO_BUFFER_SIZE (64 * 1024)
199 #define AT_BUFFER_SIZE 4096
201 static char ohci_driver_name
[] = KBUILD_MODNAME
;
203 static inline void reg_write(const struct fw_ohci
*ohci
, int offset
, u32 data
)
205 writel(data
, ohci
->registers
+ offset
);
208 static inline u32
reg_read(const struct fw_ohci
*ohci
, int offset
)
210 return readl(ohci
->registers
+ offset
);
213 static inline void flush_writes(const struct fw_ohci
*ohci
)
215 /* Do a dummy read to flush writes. */
216 reg_read(ohci
, OHCI1394_Version
);
220 ohci_update_phy_reg(struct fw_card
*card
, int addr
,
221 int clear_bits
, int set_bits
)
223 struct fw_ohci
*ohci
= fw_ohci(card
);
226 reg_write(ohci
, OHCI1394_PhyControl
, OHCI1394_PhyControl_Read(addr
));
229 val
= reg_read(ohci
, OHCI1394_PhyControl
);
230 if ((val
& OHCI1394_PhyControl_ReadDone
) == 0) {
231 fw_error("failed to set phy reg bits.\n");
235 old
= OHCI1394_PhyControl_ReadData(val
);
236 old
= (old
& ~clear_bits
) | set_bits
;
237 reg_write(ohci
, OHCI1394_PhyControl
,
238 OHCI1394_PhyControl_Write(addr
, old
));
243 static int ar_context_add_page(struct ar_context
*ctx
)
245 struct device
*dev
= ctx
->ohci
->card
.device
;
246 struct ar_buffer
*ab
;
250 ab
= (struct ar_buffer
*) __get_free_page(GFP_ATOMIC
);
254 ab_bus
= dma_map_single(dev
, ab
, PAGE_SIZE
, DMA_BIDIRECTIONAL
);
255 if (dma_mapping_error(ab_bus
)) {
256 free_page((unsigned long) ab
);
260 memset(&ab
->descriptor
, 0, sizeof(ab
->descriptor
));
261 ab
->descriptor
.control
= cpu_to_le16(DESCRIPTOR_INPUT_MORE
|
263 DESCRIPTOR_BRANCH_ALWAYS
);
264 offset
= offsetof(struct ar_buffer
, data
);
265 ab
->descriptor
.req_count
= cpu_to_le16(PAGE_SIZE
- offset
);
266 ab
->descriptor
.data_address
= cpu_to_le32(ab_bus
+ offset
);
267 ab
->descriptor
.res_count
= cpu_to_le16(PAGE_SIZE
- offset
);
268 ab
->descriptor
.branch_address
= 0;
270 dma_sync_single_for_device(dev
, ab_bus
, PAGE_SIZE
, DMA_BIDIRECTIONAL
);
272 ctx
->last_buffer
->descriptor
.branch_address
= cpu_to_le32(ab_bus
| 1);
273 ctx
->last_buffer
->next
= ab
;
274 ctx
->last_buffer
= ab
;
276 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_WAKE
);
277 flush_writes(ctx
->ohci
);
282 static __le32
*handle_ar_packet(struct ar_context
*ctx
, __le32
*buffer
)
284 struct fw_ohci
*ohci
= ctx
->ohci
;
286 u32 status
, length
, tcode
;
288 p
.header
[0] = le32_to_cpu(buffer
[0]);
289 p
.header
[1] = le32_to_cpu(buffer
[1]);
290 p
.header
[2] = le32_to_cpu(buffer
[2]);
292 tcode
= (p
.header
[0] >> 4) & 0x0f;
294 case TCODE_WRITE_QUADLET_REQUEST
:
295 case TCODE_READ_QUADLET_RESPONSE
:
296 p
.header
[3] = (__force __u32
) buffer
[3];
297 p
.header_length
= 16;
298 p
.payload_length
= 0;
301 case TCODE_READ_BLOCK_REQUEST
:
302 p
.header
[3] = le32_to_cpu(buffer
[3]);
303 p
.header_length
= 16;
304 p
.payload_length
= 0;
307 case TCODE_WRITE_BLOCK_REQUEST
:
308 case TCODE_READ_BLOCK_RESPONSE
:
309 case TCODE_LOCK_REQUEST
:
310 case TCODE_LOCK_RESPONSE
:
311 p
.header
[3] = le32_to_cpu(buffer
[3]);
312 p
.header_length
= 16;
313 p
.payload_length
= p
.header
[3] >> 16;
316 case TCODE_WRITE_RESPONSE
:
317 case TCODE_READ_QUADLET_REQUEST
:
318 case OHCI_TCODE_PHY_PACKET
:
319 p
.header_length
= 12;
320 p
.payload_length
= 0;
324 p
.payload
= (void *) buffer
+ p
.header_length
;
326 /* FIXME: What to do about evt_* errors? */
327 length
= (p
.header_length
+ p
.payload_length
+ 3) / 4;
328 status
= le32_to_cpu(buffer
[length
]);
330 p
.ack
= ((status
>> 16) & 0x1f) - 16;
331 p
.speed
= (status
>> 21) & 0x7;
332 p
.timestamp
= status
& 0xffff;
333 p
.generation
= ohci
->request_generation
;
336 * The OHCI bus reset handler synthesizes a phy packet with
337 * the new generation number when a bus reset happens (see
338 * section 8.4.2.3). This helps us determine when a request
339 * was received and make sure we send the response in the same
340 * generation. We only need this for requests; for responses
341 * we use the unique tlabel for finding the matching
345 if (p
.ack
+ 16 == 0x09)
346 ohci
->request_generation
= (buffer
[2] >> 16) & 0xff;
347 else if (ctx
== &ohci
->ar_request_ctx
)
348 fw_core_handle_request(&ohci
->card
, &p
);
350 fw_core_handle_response(&ohci
->card
, &p
);
352 return buffer
+ length
+ 1;
355 static void ar_context_tasklet(unsigned long data
)
357 struct ar_context
*ctx
= (struct ar_context
*)data
;
358 struct fw_ohci
*ohci
= ctx
->ohci
;
359 struct ar_buffer
*ab
;
360 struct descriptor
*d
;
363 ab
= ctx
->current_buffer
;
366 if (d
->res_count
== 0) {
367 size_t size
, rest
, offset
;
370 * This descriptor is finished and we may have a
371 * packet split across this and the next buffer. We
372 * reuse the page for reassembling the split packet.
375 offset
= offsetof(struct ar_buffer
, data
);
376 dma_unmap_single(ohci
->card
.device
,
377 le32_to_cpu(ab
->descriptor
.data_address
) - offset
,
378 PAGE_SIZE
, DMA_BIDIRECTIONAL
);
383 size
= buffer
+ PAGE_SIZE
- ctx
->pointer
;
384 rest
= le16_to_cpu(d
->req_count
) - le16_to_cpu(d
->res_count
);
385 memmove(buffer
, ctx
->pointer
, size
);
386 memcpy(buffer
+ size
, ab
->data
, rest
);
387 ctx
->current_buffer
= ab
;
388 ctx
->pointer
= (void *) ab
->data
+ rest
;
389 end
= buffer
+ size
+ rest
;
392 buffer
= handle_ar_packet(ctx
, buffer
);
394 free_page((unsigned long)buffer
);
395 ar_context_add_page(ctx
);
397 buffer
= ctx
->pointer
;
399 (void *) ab
+ PAGE_SIZE
- le16_to_cpu(d
->res_count
);
402 buffer
= handle_ar_packet(ctx
, buffer
);
407 ar_context_init(struct ar_context
*ctx
, struct fw_ohci
*ohci
, u32 regs
)
413 ctx
->last_buffer
= &ab
;
414 tasklet_init(&ctx
->tasklet
, ar_context_tasklet
, (unsigned long)ctx
);
416 ar_context_add_page(ctx
);
417 ar_context_add_page(ctx
);
418 ctx
->current_buffer
= ab
.next
;
419 ctx
->pointer
= ctx
->current_buffer
->data
;
424 static void ar_context_run(struct ar_context
*ctx
)
426 struct ar_buffer
*ab
= ctx
->current_buffer
;
430 offset
= offsetof(struct ar_buffer
, data
);
431 ab_bus
= le32_to_cpu(ab
->descriptor
.data_address
) - offset
;
433 reg_write(ctx
->ohci
, COMMAND_PTR(ctx
->regs
), ab_bus
| 1);
434 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_RUN
);
435 flush_writes(ctx
->ohci
);
438 static void context_tasklet(unsigned long data
)
440 struct context
*ctx
= (struct context
*) data
;
441 struct fw_ohci
*ohci
= ctx
->ohci
;
442 struct descriptor
*d
, *last
;
446 dma_sync_single_for_cpu(ohci
->card
.device
, ctx
->buffer_bus
,
447 ctx
->buffer_size
, DMA_TO_DEVICE
);
449 d
= ctx
->tail_descriptor
;
450 last
= ctx
->tail_descriptor_last
;
452 while (last
->branch_address
!= 0) {
453 address
= le32_to_cpu(last
->branch_address
);
455 d
= ctx
->buffer
+ (address
- ctx
->buffer_bus
) / sizeof(*d
);
456 last
= (z
== 2) ? d
: d
+ z
- 1;
458 if (!ctx
->callback(ctx
, d
, last
))
461 ctx
->tail_descriptor
= d
;
462 ctx
->tail_descriptor_last
= last
;
467 context_init(struct context
*ctx
, struct fw_ohci
*ohci
,
468 size_t buffer_size
, u32 regs
,
469 descriptor_callback_t callback
)
473 ctx
->buffer_size
= buffer_size
;
474 ctx
->buffer
= kmalloc(buffer_size
, GFP_KERNEL
);
475 if (ctx
->buffer
== NULL
)
478 tasklet_init(&ctx
->tasklet
, context_tasklet
, (unsigned long)ctx
);
479 ctx
->callback
= callback
;
482 dma_map_single(ohci
->card
.device
, ctx
->buffer
,
483 buffer_size
, DMA_TO_DEVICE
);
484 if (dma_mapping_error(ctx
->buffer_bus
)) {
489 ctx
->head_descriptor
= ctx
->buffer
;
490 ctx
->prev_descriptor
= ctx
->buffer
;
491 ctx
->tail_descriptor
= ctx
->buffer
;
492 ctx
->tail_descriptor_last
= ctx
->buffer
;
495 * We put a dummy descriptor in the buffer that has a NULL
496 * branch address and looks like it's been sent. That way we
497 * have a descriptor to append DMA programs to. Also, the
498 * ring buffer invariant is that it always has at least one
499 * element so that head == tail means buffer full.
502 memset(ctx
->head_descriptor
, 0, sizeof(*ctx
->head_descriptor
));
503 ctx
->head_descriptor
->control
= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
);
504 ctx
->head_descriptor
->transfer_status
= cpu_to_le16(0x8011);
505 ctx
->head_descriptor
++;
511 context_release(struct context
*ctx
)
513 struct fw_card
*card
= &ctx
->ohci
->card
;
515 dma_unmap_single(card
->device
, ctx
->buffer_bus
,
516 ctx
->buffer_size
, DMA_TO_DEVICE
);
520 static struct descriptor
*
521 context_get_descriptors(struct context
*ctx
, int z
, dma_addr_t
*d_bus
)
523 struct descriptor
*d
, *tail
, *end
;
525 d
= ctx
->head_descriptor
;
526 tail
= ctx
->tail_descriptor
;
527 end
= ctx
->buffer
+ ctx
->buffer_size
/ sizeof(*d
);
531 } else if (d
> tail
&& d
+ z
<= end
) {
533 } else if (d
> tail
&& ctx
->buffer
+ z
<= tail
) {
541 memset(d
, 0, z
* sizeof(*d
));
542 *d_bus
= ctx
->buffer_bus
+ (d
- ctx
->buffer
) * sizeof(*d
);
547 static void context_run(struct context
*ctx
, u32 extra
)
549 struct fw_ohci
*ohci
= ctx
->ohci
;
551 reg_write(ohci
, COMMAND_PTR(ctx
->regs
),
552 le32_to_cpu(ctx
->tail_descriptor_last
->branch_address
));
553 reg_write(ohci
, CONTROL_CLEAR(ctx
->regs
), ~0);
554 reg_write(ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_RUN
| extra
);
558 static void context_append(struct context
*ctx
,
559 struct descriptor
*d
, int z
, int extra
)
563 d_bus
= ctx
->buffer_bus
+ (d
- ctx
->buffer
) * sizeof(*d
);
565 ctx
->head_descriptor
= d
+ z
+ extra
;
566 ctx
->prev_descriptor
->branch_address
= cpu_to_le32(d_bus
| z
);
567 ctx
->prev_descriptor
= z
== 2 ? d
: d
+ z
- 1;
569 dma_sync_single_for_device(ctx
->ohci
->card
.device
, ctx
->buffer_bus
,
570 ctx
->buffer_size
, DMA_TO_DEVICE
);
572 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_WAKE
);
573 flush_writes(ctx
->ohci
);
576 static void context_stop(struct context
*ctx
)
581 reg_write(ctx
->ohci
, CONTROL_CLEAR(ctx
->regs
), CONTEXT_RUN
);
582 flush_writes(ctx
->ohci
);
584 for (i
= 0; i
< 10; i
++) {
585 reg
= reg_read(ctx
->ohci
, CONTROL_SET(ctx
->regs
));
586 if ((reg
& CONTEXT_ACTIVE
) == 0)
589 fw_notify("context_stop: still active (0x%08x)\n", reg
);
595 struct fw_packet
*packet
;
599 * This function apppends a packet to the DMA queue for transmission.
600 * Must always be called with the ochi->lock held to ensure proper
601 * generation handling and locking around packet queue manipulation.
604 at_context_queue_packet(struct context
*ctx
, struct fw_packet
*packet
)
606 struct fw_ohci
*ohci
= ctx
->ohci
;
607 dma_addr_t d_bus
, payload_bus
;
608 struct driver_data
*driver_data
;
609 struct descriptor
*d
, *last
;
614 d
= context_get_descriptors(ctx
, 4, &d_bus
);
616 packet
->ack
= RCODE_SEND_ERROR
;
620 d
[0].control
= cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE
);
621 d
[0].res_count
= cpu_to_le16(packet
->timestamp
);
624 * The DMA format for asyncronous link packets is different
625 * from the IEEE1394 layout, so shift the fields around
626 * accordingly. If header_length is 8, it's a PHY packet, to
627 * which we need to prepend an extra quadlet.
630 header
= (__le32
*) &d
[1];
631 if (packet
->header_length
> 8) {
632 header
[0] = cpu_to_le32((packet
->header
[0] & 0xffff) |
633 (packet
->speed
<< 16));
634 header
[1] = cpu_to_le32((packet
->header
[1] & 0xffff) |
635 (packet
->header
[0] & 0xffff0000));
636 header
[2] = cpu_to_le32(packet
->header
[2]);
638 tcode
= (packet
->header
[0] >> 4) & 0x0f;
639 if (TCODE_IS_BLOCK_PACKET(tcode
))
640 header
[3] = cpu_to_le32(packet
->header
[3]);
642 header
[3] = (__force __le32
) packet
->header
[3];
644 d
[0].req_count
= cpu_to_le16(packet
->header_length
);
646 header
[0] = cpu_to_le32((OHCI1394_phy_tcode
<< 4) |
647 (packet
->speed
<< 16));
648 header
[1] = cpu_to_le32(packet
->header
[0]);
649 header
[2] = cpu_to_le32(packet
->header
[1]);
650 d
[0].req_count
= cpu_to_le16(12);
653 driver_data
= (struct driver_data
*) &d
[3];
654 driver_data
->packet
= packet
;
655 packet
->driver_data
= driver_data
;
657 if (packet
->payload_length
> 0) {
659 dma_map_single(ohci
->card
.device
, packet
->payload
,
660 packet
->payload_length
, DMA_TO_DEVICE
);
661 if (dma_mapping_error(payload_bus
)) {
662 packet
->ack
= RCODE_SEND_ERROR
;
666 d
[2].req_count
= cpu_to_le16(packet
->payload_length
);
667 d
[2].data_address
= cpu_to_le32(payload_bus
);
675 last
->control
|= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
|
676 DESCRIPTOR_IRQ_ALWAYS
|
677 DESCRIPTOR_BRANCH_ALWAYS
);
679 /* FIXME: Document how the locking works. */
680 if (ohci
->generation
!= packet
->generation
) {
681 packet
->ack
= RCODE_GENERATION
;
685 context_append(ctx
, d
, z
, 4 - z
);
687 /* If the context isn't already running, start it up. */
688 reg
= reg_read(ctx
->ohci
, CONTROL_SET(ctx
->regs
));
689 if ((reg
& CONTEXT_RUN
) == 0)
695 static int handle_at_packet(struct context
*context
,
696 struct descriptor
*d
,
697 struct descriptor
*last
)
699 struct driver_data
*driver_data
;
700 struct fw_packet
*packet
;
701 struct fw_ohci
*ohci
= context
->ohci
;
702 dma_addr_t payload_bus
;
705 if (last
->transfer_status
== 0)
706 /* This descriptor isn't done yet, stop iteration. */
709 driver_data
= (struct driver_data
*) &d
[3];
710 packet
= driver_data
->packet
;
712 /* This packet was cancelled, just continue. */
715 payload_bus
= le32_to_cpu(last
->data_address
);
716 if (payload_bus
!= 0)
717 dma_unmap_single(ohci
->card
.device
, payload_bus
,
718 packet
->payload_length
, DMA_TO_DEVICE
);
720 evt
= le16_to_cpu(last
->transfer_status
) & 0x1f;
721 packet
->timestamp
= le16_to_cpu(last
->res_count
);
724 case OHCI1394_evt_timeout
:
725 /* Async response transmit timed out. */
726 packet
->ack
= RCODE_CANCELLED
;
729 case OHCI1394_evt_flushed
:
731 * The packet was flushed should give same error as
732 * when we try to use a stale generation count.
734 packet
->ack
= RCODE_GENERATION
;
737 case OHCI1394_evt_missing_ack
:
739 * Using a valid (current) generation count, but the
740 * node is not on the bus or not sending acks.
742 packet
->ack
= RCODE_NO_ACK
;
745 case ACK_COMPLETE
+ 0x10:
746 case ACK_PENDING
+ 0x10:
747 case ACK_BUSY_X
+ 0x10:
748 case ACK_BUSY_A
+ 0x10:
749 case ACK_BUSY_B
+ 0x10:
750 case ACK_DATA_ERROR
+ 0x10:
751 case ACK_TYPE_ERROR
+ 0x10:
752 packet
->ack
= evt
- 0x10;
756 packet
->ack
= RCODE_SEND_ERROR
;
760 packet
->callback(packet
, &ohci
->card
, packet
->ack
);
765 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
766 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
767 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
768 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
769 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
772 handle_local_rom(struct fw_ohci
*ohci
, struct fw_packet
*packet
, u32 csr
)
774 struct fw_packet response
;
775 int tcode
, length
, i
;
777 tcode
= HEADER_GET_TCODE(packet
->header
[0]);
778 if (TCODE_IS_BLOCK_PACKET(tcode
))
779 length
= HEADER_GET_DATA_LENGTH(packet
->header
[3]);
783 i
= csr
- CSR_CONFIG_ROM
;
784 if (i
+ length
> CONFIG_ROM_SIZE
) {
785 fw_fill_response(&response
, packet
->header
,
786 RCODE_ADDRESS_ERROR
, NULL
, 0);
787 } else if (!TCODE_IS_READ_REQUEST(tcode
)) {
788 fw_fill_response(&response
, packet
->header
,
789 RCODE_TYPE_ERROR
, NULL
, 0);
791 fw_fill_response(&response
, packet
->header
, RCODE_COMPLETE
,
792 (void *) ohci
->config_rom
+ i
, length
);
795 fw_core_handle_response(&ohci
->card
, &response
);
799 handle_local_lock(struct fw_ohci
*ohci
, struct fw_packet
*packet
, u32 csr
)
801 struct fw_packet response
;
802 int tcode
, length
, ext_tcode
, sel
;
803 __be32
*payload
, lock_old
;
804 u32 lock_arg
, lock_data
;
806 tcode
= HEADER_GET_TCODE(packet
->header
[0]);
807 length
= HEADER_GET_DATA_LENGTH(packet
->header
[3]);
808 payload
= packet
->payload
;
809 ext_tcode
= HEADER_GET_EXTENDED_TCODE(packet
->header
[3]);
811 if (tcode
== TCODE_LOCK_REQUEST
&&
812 ext_tcode
== EXTCODE_COMPARE_SWAP
&& length
== 8) {
813 lock_arg
= be32_to_cpu(payload
[0]);
814 lock_data
= be32_to_cpu(payload
[1]);
815 } else if (tcode
== TCODE_READ_QUADLET_REQUEST
) {
819 fw_fill_response(&response
, packet
->header
,
820 RCODE_TYPE_ERROR
, NULL
, 0);
824 sel
= (csr
- CSR_BUS_MANAGER_ID
) / 4;
825 reg_write(ohci
, OHCI1394_CSRData
, lock_data
);
826 reg_write(ohci
, OHCI1394_CSRCompareData
, lock_arg
);
827 reg_write(ohci
, OHCI1394_CSRControl
, sel
);
829 if (reg_read(ohci
, OHCI1394_CSRControl
) & 0x80000000)
830 lock_old
= cpu_to_be32(reg_read(ohci
, OHCI1394_CSRData
));
832 fw_notify("swap not done yet\n");
834 fw_fill_response(&response
, packet
->header
,
835 RCODE_COMPLETE
, &lock_old
, sizeof(lock_old
));
837 fw_core_handle_response(&ohci
->card
, &response
);
841 handle_local_request(struct context
*ctx
, struct fw_packet
*packet
)
846 if (ctx
== &ctx
->ohci
->at_request_ctx
) {
847 packet
->ack
= ACK_PENDING
;
848 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
852 ((unsigned long long)
853 HEADER_GET_OFFSET_HIGH(packet
->header
[1]) << 32) |
855 csr
= offset
- CSR_REGISTER_BASE
;
857 /* Handle config rom reads. */
858 if (csr
>= CSR_CONFIG_ROM
&& csr
< CSR_CONFIG_ROM_END
)
859 handle_local_rom(ctx
->ohci
, packet
, csr
);
861 case CSR_BUS_MANAGER_ID
:
862 case CSR_BANDWIDTH_AVAILABLE
:
863 case CSR_CHANNELS_AVAILABLE_HI
:
864 case CSR_CHANNELS_AVAILABLE_LO
:
865 handle_local_lock(ctx
->ohci
, packet
, csr
);
868 if (ctx
== &ctx
->ohci
->at_request_ctx
)
869 fw_core_handle_request(&ctx
->ohci
->card
, packet
);
871 fw_core_handle_response(&ctx
->ohci
->card
, packet
);
875 if (ctx
== &ctx
->ohci
->at_response_ctx
) {
876 packet
->ack
= ACK_COMPLETE
;
877 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
882 at_context_transmit(struct context
*ctx
, struct fw_packet
*packet
)
887 spin_lock_irqsave(&ctx
->ohci
->lock
, flags
);
889 if (HEADER_GET_DESTINATION(packet
->header
[0]) == ctx
->ohci
->node_id
&&
890 ctx
->ohci
->generation
== packet
->generation
) {
891 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
892 handle_local_request(ctx
, packet
);
896 retval
= at_context_queue_packet(ctx
, packet
);
897 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
900 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
904 static void bus_reset_tasklet(unsigned long data
)
906 struct fw_ohci
*ohci
= (struct fw_ohci
*)data
;
907 int self_id_count
, i
, j
, reg
;
908 int generation
, new_generation
;
911 reg
= reg_read(ohci
, OHCI1394_NodeID
);
912 if (!(reg
& OHCI1394_NodeID_idValid
)) {
913 fw_error("node ID not valid, new bus reset in progress\n");
916 ohci
->node_id
= reg
& 0xffff;
919 * The count in the SelfIDCount register is the number of
920 * bytes in the self ID receive buffer. Since we also receive
921 * the inverted quadlets and a header quadlet, we shift one
922 * bit extra to get the actual number of self IDs.
925 self_id_count
= (reg_read(ohci
, OHCI1394_SelfIDCount
) >> 3) & 0x3ff;
926 generation
= (le32_to_cpu(ohci
->self_id_cpu
[0]) >> 16) & 0xff;
928 for (i
= 1, j
= 0; j
< self_id_count
; i
+= 2, j
++) {
929 if (ohci
->self_id_cpu
[i
] != ~ohci
->self_id_cpu
[i
+ 1])
930 fw_error("inconsistent self IDs\n");
931 ohci
->self_id_buffer
[j
] = le32_to_cpu(ohci
->self_id_cpu
[i
]);
935 * Check the consistency of the self IDs we just read. The
936 * problem we face is that a new bus reset can start while we
937 * read out the self IDs from the DMA buffer. If this happens,
938 * the DMA buffer will be overwritten with new self IDs and we
939 * will read out inconsistent data. The OHCI specification
940 * (section 11.2) recommends a technique similar to
941 * linux/seqlock.h, where we remember the generation of the
942 * self IDs in the buffer before reading them out and compare
943 * it to the current generation after reading them out. If
944 * the two generations match we know we have a consistent set
948 new_generation
= (reg_read(ohci
, OHCI1394_SelfIDCount
) >> 16) & 0xff;
949 if (new_generation
!= generation
) {
950 fw_notify("recursive bus reset detected, "
951 "discarding self ids\n");
955 /* FIXME: Document how the locking works. */
956 spin_lock_irqsave(&ohci
->lock
, flags
);
958 ohci
->generation
= generation
;
959 context_stop(&ohci
->at_request_ctx
);
960 context_stop(&ohci
->at_response_ctx
);
961 reg_write(ohci
, OHCI1394_IntEventClear
, OHCI1394_busReset
);
964 * This next bit is unrelated to the AT context stuff but we
965 * have to do it under the spinlock also. If a new config rom
966 * was set up before this reset, the old one is now no longer
967 * in use and we can free it. Update the config rom pointers
968 * to point to the current config rom and clear the
969 * next_config_rom pointer so a new udpate can take place.
972 if (ohci
->next_config_rom
!= NULL
) {
973 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
974 ohci
->config_rom
, ohci
->config_rom_bus
);
975 ohci
->config_rom
= ohci
->next_config_rom
;
976 ohci
->config_rom_bus
= ohci
->next_config_rom_bus
;
977 ohci
->next_config_rom
= NULL
;
980 * Restore config_rom image and manually update
981 * config_rom registers. Writing the header quadlet
982 * will indicate that the config rom is ready, so we
985 reg_write(ohci
, OHCI1394_BusOptions
,
986 be32_to_cpu(ohci
->config_rom
[2]));
987 ohci
->config_rom
[0] = cpu_to_be32(ohci
->next_header
);
988 reg_write(ohci
, OHCI1394_ConfigROMhdr
, ohci
->next_header
);
991 spin_unlock_irqrestore(&ohci
->lock
, flags
);
993 fw_core_handle_bus_reset(&ohci
->card
, ohci
->node_id
, generation
,
994 self_id_count
, ohci
->self_id_buffer
);
997 static irqreturn_t
irq_handler(int irq
, void *data
)
999 struct fw_ohci
*ohci
= data
;
1000 u32 event
, iso_event
, cycle_time
;
1003 event
= reg_read(ohci
, OHCI1394_IntEventClear
);
1005 if (!event
|| !~event
)
1008 reg_write(ohci
, OHCI1394_IntEventClear
, event
);
1010 if (event
& OHCI1394_selfIDComplete
)
1011 tasklet_schedule(&ohci
->bus_reset_tasklet
);
1013 if (event
& OHCI1394_RQPkt
)
1014 tasklet_schedule(&ohci
->ar_request_ctx
.tasklet
);
1016 if (event
& OHCI1394_RSPkt
)
1017 tasklet_schedule(&ohci
->ar_response_ctx
.tasklet
);
1019 if (event
& OHCI1394_reqTxComplete
)
1020 tasklet_schedule(&ohci
->at_request_ctx
.tasklet
);
1022 if (event
& OHCI1394_respTxComplete
)
1023 tasklet_schedule(&ohci
->at_response_ctx
.tasklet
);
1025 iso_event
= reg_read(ohci
, OHCI1394_IsoRecvIntEventClear
);
1026 reg_write(ohci
, OHCI1394_IsoRecvIntEventClear
, iso_event
);
1029 i
= ffs(iso_event
) - 1;
1030 tasklet_schedule(&ohci
->ir_context_list
[i
].context
.tasklet
);
1031 iso_event
&= ~(1 << i
);
1034 iso_event
= reg_read(ohci
, OHCI1394_IsoXmitIntEventClear
);
1035 reg_write(ohci
, OHCI1394_IsoXmitIntEventClear
, iso_event
);
1038 i
= ffs(iso_event
) - 1;
1039 tasklet_schedule(&ohci
->it_context_list
[i
].context
.tasklet
);
1040 iso_event
&= ~(1 << i
);
1043 if (event
& OHCI1394_cycle64Seconds
) {
1044 cycle_time
= reg_read(ohci
, OHCI1394_IsochronousCycleTimer
);
1045 if ((cycle_time
& 0x80000000) == 0)
1046 ohci
->bus_seconds
++;
1052 static int software_reset(struct fw_ohci
*ohci
)
1056 reg_write(ohci
, OHCI1394_HCControlSet
, OHCI1394_HCControl_softReset
);
1058 for (i
= 0; i
< OHCI_LOOP_COUNT
; i
++) {
1059 if ((reg_read(ohci
, OHCI1394_HCControlSet
) &
1060 OHCI1394_HCControl_softReset
) == 0)
1068 static int ohci_enable(struct fw_card
*card
, u32
*config_rom
, size_t length
)
1070 struct fw_ohci
*ohci
= fw_ohci(card
);
1071 struct pci_dev
*dev
= to_pci_dev(card
->device
);
1073 if (software_reset(ohci
)) {
1074 fw_error("Failed to reset ohci card.\n");
1079 * Now enable LPS, which we need in order to start accessing
1080 * most of the registers. In fact, on some cards (ALI M5251),
1081 * accessing registers in the SClk domain without LPS enabled
1082 * will lock up the machine. Wait 50msec to make sure we have
1083 * full link enabled.
1085 reg_write(ohci
, OHCI1394_HCControlSet
,
1086 OHCI1394_HCControl_LPS
|
1087 OHCI1394_HCControl_postedWriteEnable
);
1091 reg_write(ohci
, OHCI1394_HCControlClear
,
1092 OHCI1394_HCControl_noByteSwapData
);
1094 reg_write(ohci
, OHCI1394_LinkControlSet
,
1095 OHCI1394_LinkControl_rcvSelfID
|
1096 OHCI1394_LinkControl_cycleTimerEnable
|
1097 OHCI1394_LinkControl_cycleMaster
);
1099 reg_write(ohci
, OHCI1394_ATRetries
,
1100 OHCI1394_MAX_AT_REQ_RETRIES
|
1101 (OHCI1394_MAX_AT_RESP_RETRIES
<< 4) |
1102 (OHCI1394_MAX_PHYS_RESP_RETRIES
<< 8));
1104 ar_context_run(&ohci
->ar_request_ctx
);
1105 ar_context_run(&ohci
->ar_response_ctx
);
1107 reg_write(ohci
, OHCI1394_SelfIDBuffer
, ohci
->self_id_bus
);
1108 reg_write(ohci
, OHCI1394_PhyUpperBound
, 0x00010000);
1109 reg_write(ohci
, OHCI1394_IntEventClear
, ~0);
1110 reg_write(ohci
, OHCI1394_IntMaskClear
, ~0);
1111 reg_write(ohci
, OHCI1394_IntMaskSet
,
1112 OHCI1394_selfIDComplete
|
1113 OHCI1394_RQPkt
| OHCI1394_RSPkt
|
1114 OHCI1394_reqTxComplete
| OHCI1394_respTxComplete
|
1115 OHCI1394_isochRx
| OHCI1394_isochTx
|
1116 OHCI1394_masterIntEnable
|
1117 OHCI1394_cycle64Seconds
);
1119 /* Activate link_on bit and contender bit in our self ID packets.*/
1120 if (ohci_update_phy_reg(card
, 4, 0,
1121 PHY_LINK_ACTIVE
| PHY_CONTENDER
) < 0)
1125 * When the link is not yet enabled, the atomic config rom
1126 * update mechanism described below in ohci_set_config_rom()
1127 * is not active. We have to update ConfigRomHeader and
1128 * BusOptions manually, and the write to ConfigROMmap takes
1129 * effect immediately. We tie this to the enabling of the
1130 * link, so we have a valid config rom before enabling - the
1131 * OHCI requires that ConfigROMhdr and BusOptions have valid
1132 * values before enabling.
1134 * However, when the ConfigROMmap is written, some controllers
1135 * always read back quadlets 0 and 2 from the config rom to
1136 * the ConfigRomHeader and BusOptions registers on bus reset.
1137 * They shouldn't do that in this initial case where the link
1138 * isn't enabled. This means we have to use the same
1139 * workaround here, setting the bus header to 0 and then write
1140 * the right values in the bus reset tasklet.
1143 ohci
->next_config_rom
=
1144 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1145 &ohci
->next_config_rom_bus
, GFP_KERNEL
);
1146 if (ohci
->next_config_rom
== NULL
)
1149 memset(ohci
->next_config_rom
, 0, CONFIG_ROM_SIZE
);
1150 fw_memcpy_to_be32(ohci
->next_config_rom
, config_rom
, length
* 4);
1152 ohci
->next_header
= config_rom
[0];
1153 ohci
->next_config_rom
[0] = 0;
1154 reg_write(ohci
, OHCI1394_ConfigROMhdr
, 0);
1155 reg_write(ohci
, OHCI1394_BusOptions
, config_rom
[2]);
1156 reg_write(ohci
, OHCI1394_ConfigROMmap
, ohci
->next_config_rom_bus
);
1158 reg_write(ohci
, OHCI1394_AsReqFilterHiSet
, 0x80000000);
1160 if (request_irq(dev
->irq
, irq_handler
,
1161 IRQF_SHARED
, ohci_driver_name
, ohci
)) {
1162 fw_error("Failed to allocate shared interrupt %d.\n",
1164 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1165 ohci
->config_rom
, ohci
->config_rom_bus
);
1169 reg_write(ohci
, OHCI1394_HCControlSet
,
1170 OHCI1394_HCControl_linkEnable
|
1171 OHCI1394_HCControl_BIBimageValid
);
1175 * We are ready to go, initiate bus reset to finish the
1179 fw_core_initiate_bus_reset(&ohci
->card
, 1);
1185 ohci_set_config_rom(struct fw_card
*card
, u32
*config_rom
, size_t length
)
1187 struct fw_ohci
*ohci
;
1188 unsigned long flags
;
1190 __be32
*next_config_rom
;
1191 dma_addr_t next_config_rom_bus
;
1193 ohci
= fw_ohci(card
);
1196 * When the OHCI controller is enabled, the config rom update
1197 * mechanism is a bit tricky, but easy enough to use. See
1198 * section 5.5.6 in the OHCI specification.
1200 * The OHCI controller caches the new config rom address in a
1201 * shadow register (ConfigROMmapNext) and needs a bus reset
1202 * for the changes to take place. When the bus reset is
1203 * detected, the controller loads the new values for the
1204 * ConfigRomHeader and BusOptions registers from the specified
1205 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1206 * shadow register. All automatically and atomically.
1208 * Now, there's a twist to this story. The automatic load of
1209 * ConfigRomHeader and BusOptions doesn't honor the
1210 * noByteSwapData bit, so with a be32 config rom, the
1211 * controller will load be32 values in to these registers
1212 * during the atomic update, even on litte endian
1213 * architectures. The workaround we use is to put a 0 in the
1214 * header quadlet; 0 is endian agnostic and means that the
1215 * config rom isn't ready yet. In the bus reset tasklet we
1216 * then set up the real values for the two registers.
1218 * We use ohci->lock to avoid racing with the code that sets
1219 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1223 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1224 &next_config_rom_bus
, GFP_KERNEL
);
1225 if (next_config_rom
== NULL
)
1228 spin_lock_irqsave(&ohci
->lock
, flags
);
1230 if (ohci
->next_config_rom
== NULL
) {
1231 ohci
->next_config_rom
= next_config_rom
;
1232 ohci
->next_config_rom_bus
= next_config_rom_bus
;
1234 memset(ohci
->next_config_rom
, 0, CONFIG_ROM_SIZE
);
1235 fw_memcpy_to_be32(ohci
->next_config_rom
, config_rom
,
1238 ohci
->next_header
= config_rom
[0];
1239 ohci
->next_config_rom
[0] = 0;
1241 reg_write(ohci
, OHCI1394_ConfigROMmap
,
1242 ohci
->next_config_rom_bus
);
1244 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1245 next_config_rom
, next_config_rom_bus
);
1249 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1252 * Now initiate a bus reset to have the changes take
1253 * effect. We clean up the old config rom memory and DMA
1254 * mappings in the bus reset tasklet, since the OHCI
1255 * controller could need to access it before the bus reset
1259 fw_core_initiate_bus_reset(&ohci
->card
, 1);
1264 static void ohci_send_request(struct fw_card
*card
, struct fw_packet
*packet
)
1266 struct fw_ohci
*ohci
= fw_ohci(card
);
1268 at_context_transmit(&ohci
->at_request_ctx
, packet
);
1271 static void ohci_send_response(struct fw_card
*card
, struct fw_packet
*packet
)
1273 struct fw_ohci
*ohci
= fw_ohci(card
);
1275 at_context_transmit(&ohci
->at_response_ctx
, packet
);
1278 static int ohci_cancel_packet(struct fw_card
*card
, struct fw_packet
*packet
)
1280 struct fw_ohci
*ohci
= fw_ohci(card
);
1281 struct context
*ctx
= &ohci
->at_request_ctx
;
1282 struct driver_data
*driver_data
= packet
->driver_data
;
1283 int retval
= -ENOENT
;
1285 tasklet_disable(&ctx
->tasklet
);
1287 if (packet
->ack
!= 0)
1290 driver_data
->packet
= NULL
;
1291 packet
->ack
= RCODE_CANCELLED
;
1292 packet
->callback(packet
, &ohci
->card
, packet
->ack
);
1296 tasklet_enable(&ctx
->tasklet
);
1302 ohci_enable_phys_dma(struct fw_card
*card
, int node_id
, int generation
)
1304 struct fw_ohci
*ohci
= fw_ohci(card
);
1305 unsigned long flags
;
1309 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1310 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1313 spin_lock_irqsave(&ohci
->lock
, flags
);
1315 if (ohci
->generation
!= generation
) {
1321 * Note, if the node ID contains a non-local bus ID, physical DMA is
1322 * enabled for _all_ nodes on remote buses.
1325 n
= (node_id
& 0xffc0) == LOCAL_BUS
? node_id
& 0x3f : 63;
1327 reg_write(ohci
, OHCI1394_PhyReqFilterLoSet
, 1 << n
);
1329 reg_write(ohci
, OHCI1394_PhyReqFilterHiSet
, 1 << (n
- 32));
1333 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1338 ohci_get_bus_time(struct fw_card
*card
)
1340 struct fw_ohci
*ohci
= fw_ohci(card
);
1344 cycle_time
= reg_read(ohci
, OHCI1394_IsochronousCycleTimer
);
1345 bus_time
= ((u64
) ohci
->bus_seconds
<< 32) | cycle_time
;
1350 static int handle_ir_dualbuffer_packet(struct context
*context
,
1351 struct descriptor
*d
,
1352 struct descriptor
*last
)
1354 struct iso_context
*ctx
=
1355 container_of(context
, struct iso_context
, context
);
1356 struct db_descriptor
*db
= (struct db_descriptor
*) d
;
1358 size_t header_length
;
1362 if (db
->first_res_count
> 0 && db
->second_res_count
> 0)
1363 /* This descriptor isn't done yet, stop iteration. */
1366 header_length
= le16_to_cpu(db
->first_req_count
) -
1367 le16_to_cpu(db
->first_res_count
);
1369 i
= ctx
->header_length
;
1371 end
= p
+ header_length
;
1372 while (p
< end
&& i
+ ctx
->base
.header_size
<= PAGE_SIZE
) {
1374 * The iso header is byteswapped to little endian by
1375 * the controller, but the remaining header quadlets
1376 * are big endian. We want to present all the headers
1377 * as big endian, so we have to swap the first
1380 *(u32
*) (ctx
->header
+ i
) = __swab32(*(u32
*) (p
+ 4));
1381 memcpy(ctx
->header
+ i
+ 4, p
+ 8, ctx
->base
.header_size
- 4);
1382 i
+= ctx
->base
.header_size
;
1383 p
+= ctx
->base
.header_size
+ 4;
1386 ctx
->header_length
= i
;
1388 if (le16_to_cpu(db
->control
) & DESCRIPTOR_IRQ_ALWAYS
) {
1389 ir_header
= (__le32
*) (db
+ 1);
1390 ctx
->base
.callback(&ctx
->base
,
1391 le32_to_cpu(ir_header
[0]) & 0xffff,
1392 ctx
->header_length
, ctx
->header
,
1393 ctx
->base
.callback_data
);
1394 ctx
->header_length
= 0;
1400 static int handle_it_packet(struct context
*context
,
1401 struct descriptor
*d
,
1402 struct descriptor
*last
)
1404 struct iso_context
*ctx
=
1405 container_of(context
, struct iso_context
, context
);
1407 if (last
->transfer_status
== 0)
1408 /* This descriptor isn't done yet, stop iteration. */
1411 if (le16_to_cpu(last
->control
) & DESCRIPTOR_IRQ_ALWAYS
)
1412 ctx
->base
.callback(&ctx
->base
, le16_to_cpu(last
->res_count
),
1413 0, NULL
, ctx
->base
.callback_data
);
1418 static struct fw_iso_context
*
1419 ohci_allocate_iso_context(struct fw_card
*card
, int type
, size_t header_size
)
1421 struct fw_ohci
*ohci
= fw_ohci(card
);
1422 struct iso_context
*ctx
, *list
;
1423 descriptor_callback_t callback
;
1425 unsigned long flags
;
1426 int index
, retval
= -ENOMEM
;
1428 if (type
== FW_ISO_CONTEXT_TRANSMIT
) {
1429 mask
= &ohci
->it_context_mask
;
1430 list
= ohci
->it_context_list
;
1431 callback
= handle_it_packet
;
1433 mask
= &ohci
->ir_context_mask
;
1434 list
= ohci
->ir_context_list
;
1435 callback
= handle_ir_dualbuffer_packet
;
1438 /* FIXME: We need a fallback for pre 1.1 OHCI. */
1439 if (callback
== handle_ir_dualbuffer_packet
&&
1440 ohci
->version
< OHCI_VERSION_1_1
)
1441 return ERR_PTR(-EINVAL
);
1443 spin_lock_irqsave(&ohci
->lock
, flags
);
1444 index
= ffs(*mask
) - 1;
1446 *mask
&= ~(1 << index
);
1447 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1450 return ERR_PTR(-EBUSY
);
1452 if (type
== FW_ISO_CONTEXT_TRANSMIT
)
1453 regs
= OHCI1394_IsoXmitContextBase(index
);
1455 regs
= OHCI1394_IsoRcvContextBase(index
);
1458 memset(ctx
, 0, sizeof(*ctx
));
1459 ctx
->header_length
= 0;
1460 ctx
->header
= (void *) __get_free_page(GFP_KERNEL
);
1461 if (ctx
->header
== NULL
)
1464 retval
= context_init(&ctx
->context
, ohci
, ISO_BUFFER_SIZE
,
1467 goto out_with_header
;
1472 free_page((unsigned long)ctx
->header
);
1474 spin_lock_irqsave(&ohci
->lock
, flags
);
1475 *mask
|= 1 << index
;
1476 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1478 return ERR_PTR(retval
);
1481 static int ohci_start_iso(struct fw_iso_context
*base
,
1482 s32 cycle
, u32 sync
, u32 tags
)
1484 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1485 struct fw_ohci
*ohci
= ctx
->context
.ohci
;
1489 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
1490 index
= ctx
- ohci
->it_context_list
;
1493 match
= IT_CONTEXT_CYCLE_MATCH_ENABLE
|
1494 (cycle
& 0x7fff) << 16;
1496 reg_write(ohci
, OHCI1394_IsoXmitIntEventClear
, 1 << index
);
1497 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, 1 << index
);
1498 context_run(&ctx
->context
, match
);
1500 index
= ctx
- ohci
->ir_context_list
;
1501 control
= IR_CONTEXT_DUAL_BUFFER_MODE
| IR_CONTEXT_ISOCH_HEADER
;
1502 match
= (tags
<< 28) | (sync
<< 8) | ctx
->base
.channel
;
1504 match
|= (cycle
& 0x07fff) << 12;
1505 control
|= IR_CONTEXT_CYCLE_MATCH_ENABLE
;
1508 reg_write(ohci
, OHCI1394_IsoRecvIntEventClear
, 1 << index
);
1509 reg_write(ohci
, OHCI1394_IsoRecvIntMaskSet
, 1 << index
);
1510 reg_write(ohci
, CONTEXT_MATCH(ctx
->context
.regs
), match
);
1511 context_run(&ctx
->context
, control
);
1517 static int ohci_stop_iso(struct fw_iso_context
*base
)
1519 struct fw_ohci
*ohci
= fw_ohci(base
->card
);
1520 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1523 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
1524 index
= ctx
- ohci
->it_context_list
;
1525 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, 1 << index
);
1527 index
= ctx
- ohci
->ir_context_list
;
1528 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, 1 << index
);
1531 context_stop(&ctx
->context
);
1536 static void ohci_free_iso_context(struct fw_iso_context
*base
)
1538 struct fw_ohci
*ohci
= fw_ohci(base
->card
);
1539 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1540 unsigned long flags
;
1543 ohci_stop_iso(base
);
1544 context_release(&ctx
->context
);
1545 free_page((unsigned long)ctx
->header
);
1547 spin_lock_irqsave(&ohci
->lock
, flags
);
1549 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
1550 index
= ctx
- ohci
->it_context_list
;
1551 ohci
->it_context_mask
|= 1 << index
;
1553 index
= ctx
- ohci
->ir_context_list
;
1554 ohci
->ir_context_mask
|= 1 << index
;
1557 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1561 ohci_queue_iso_transmit(struct fw_iso_context
*base
,
1562 struct fw_iso_packet
*packet
,
1563 struct fw_iso_buffer
*buffer
,
1564 unsigned long payload
)
1566 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1567 struct descriptor
*d
, *last
, *pd
;
1568 struct fw_iso_packet
*p
;
1570 dma_addr_t d_bus
, page_bus
;
1571 u32 z
, header_z
, payload_z
, irq
;
1572 u32 payload_index
, payload_end_index
, next_page_index
;
1573 int page
, end_page
, i
, length
, offset
;
1576 * FIXME: Cycle lost behavior should be configurable: lose
1577 * packet, retransmit or terminate..
1581 payload_index
= payload
;
1587 if (p
->header_length
> 0)
1590 /* Determine the first page the payload isn't contained in. */
1591 end_page
= PAGE_ALIGN(payload_index
+ p
->payload_length
) >> PAGE_SHIFT
;
1592 if (p
->payload_length
> 0)
1593 payload_z
= end_page
- (payload_index
>> PAGE_SHIFT
);
1599 /* Get header size in number of descriptors. */
1600 header_z
= DIV_ROUND_UP(p
->header_length
, sizeof(*d
));
1602 d
= context_get_descriptors(&ctx
->context
, z
+ header_z
, &d_bus
);
1607 d
[0].control
= cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE
);
1608 d
[0].req_count
= cpu_to_le16(8);
1610 header
= (__le32
*) &d
[1];
1611 header
[0] = cpu_to_le32(IT_HEADER_SY(p
->sy
) |
1612 IT_HEADER_TAG(p
->tag
) |
1613 IT_HEADER_TCODE(TCODE_STREAM_DATA
) |
1614 IT_HEADER_CHANNEL(ctx
->base
.channel
) |
1615 IT_HEADER_SPEED(ctx
->base
.speed
));
1617 cpu_to_le32(IT_HEADER_DATA_LENGTH(p
->header_length
+
1618 p
->payload_length
));
1621 if (p
->header_length
> 0) {
1622 d
[2].req_count
= cpu_to_le16(p
->header_length
);
1623 d
[2].data_address
= cpu_to_le32(d_bus
+ z
* sizeof(*d
));
1624 memcpy(&d
[z
], p
->header
, p
->header_length
);
1627 pd
= d
+ z
- payload_z
;
1628 payload_end_index
= payload_index
+ p
->payload_length
;
1629 for (i
= 0; i
< payload_z
; i
++) {
1630 page
= payload_index
>> PAGE_SHIFT
;
1631 offset
= payload_index
& ~PAGE_MASK
;
1632 next_page_index
= (page
+ 1) << PAGE_SHIFT
;
1634 min(next_page_index
, payload_end_index
) - payload_index
;
1635 pd
[i
].req_count
= cpu_to_le16(length
);
1637 page_bus
= page_private(buffer
->pages
[page
]);
1638 pd
[i
].data_address
= cpu_to_le32(page_bus
+ offset
);
1640 payload_index
+= length
;
1644 irq
= DESCRIPTOR_IRQ_ALWAYS
;
1646 irq
= DESCRIPTOR_NO_IRQ
;
1648 last
= z
== 2 ? d
: d
+ z
- 1;
1649 last
->control
|= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
|
1651 DESCRIPTOR_BRANCH_ALWAYS
|
1654 context_append(&ctx
->context
, d
, z
, header_z
);
1660 ohci_queue_iso_receive_dualbuffer(struct fw_iso_context
*base
,
1661 struct fw_iso_packet
*packet
,
1662 struct fw_iso_buffer
*buffer
,
1663 unsigned long payload
)
1665 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1666 struct db_descriptor
*db
= NULL
;
1667 struct descriptor
*d
;
1668 struct fw_iso_packet
*p
;
1669 dma_addr_t d_bus
, page_bus
;
1670 u32 z
, header_z
, length
, rest
;
1671 int page
, offset
, packet_count
, header_size
;
1674 * FIXME: Cycle lost behavior should be configurable: lose
1675 * packet, retransmit or terminate..
1679 d
= context_get_descriptors(&ctx
->context
, 2, &d_bus
);
1683 db
= (struct db_descriptor
*) d
;
1684 db
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
1685 DESCRIPTOR_BRANCH_ALWAYS
|
1687 db
->first_size
= cpu_to_le16(ctx
->base
.header_size
+ 4);
1688 context_append(&ctx
->context
, d
, 2, 0);
1695 * The OHCI controller puts the status word in the header
1696 * buffer too, so we need 4 extra bytes per packet.
1698 packet_count
= p
->header_length
/ ctx
->base
.header_size
;
1699 header_size
= packet_count
* (ctx
->base
.header_size
+ 4);
1701 /* Get header size in number of descriptors. */
1702 header_z
= DIV_ROUND_UP(header_size
, sizeof(*d
));
1703 page
= payload
>> PAGE_SHIFT
;
1704 offset
= payload
& ~PAGE_MASK
;
1705 rest
= p
->payload_length
;
1707 /* FIXME: OHCI 1.0 doesn't support dual buffer receive */
1708 /* FIXME: make packet-per-buffer/dual-buffer a context option */
1710 d
= context_get_descriptors(&ctx
->context
,
1711 z
+ header_z
, &d_bus
);
1715 db
= (struct db_descriptor
*) d
;
1716 db
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
1717 DESCRIPTOR_BRANCH_ALWAYS
);
1718 db
->first_size
= cpu_to_le16(ctx
->base
.header_size
+ 4);
1719 db
->first_req_count
= cpu_to_le16(header_size
);
1720 db
->first_res_count
= db
->first_req_count
;
1721 db
->first_buffer
= cpu_to_le32(d_bus
+ sizeof(*db
));
1723 if (offset
+ rest
< PAGE_SIZE
)
1726 length
= PAGE_SIZE
- offset
;
1728 db
->second_req_count
= cpu_to_le16(length
);
1729 db
->second_res_count
= db
->second_req_count
;
1730 page_bus
= page_private(buffer
->pages
[page
]);
1731 db
->second_buffer
= cpu_to_le32(page_bus
+ offset
);
1733 if (p
->interrupt
&& length
== rest
)
1734 db
->control
|= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS
);
1736 context_append(&ctx
->context
, d
, z
, header_z
);
1737 offset
= (offset
+ length
) & ~PAGE_MASK
;
1746 ohci_queue_iso(struct fw_iso_context
*base
,
1747 struct fw_iso_packet
*packet
,
1748 struct fw_iso_buffer
*buffer
,
1749 unsigned long payload
)
1751 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1753 if (base
->type
== FW_ISO_CONTEXT_TRANSMIT
)
1754 return ohci_queue_iso_transmit(base
, packet
, buffer
, payload
);
1755 else if (ctx
->context
.ohci
->version
>= OHCI_VERSION_1_1
)
1756 return ohci_queue_iso_receive_dualbuffer(base
, packet
,
1759 /* FIXME: Implement fallback for OHCI 1.0 controllers. */
1763 static const struct fw_card_driver ohci_driver
= {
1764 .name
= ohci_driver_name
,
1765 .enable
= ohci_enable
,
1766 .update_phy_reg
= ohci_update_phy_reg
,
1767 .set_config_rom
= ohci_set_config_rom
,
1768 .send_request
= ohci_send_request
,
1769 .send_response
= ohci_send_response
,
1770 .cancel_packet
= ohci_cancel_packet
,
1771 .enable_phys_dma
= ohci_enable_phys_dma
,
1772 .get_bus_time
= ohci_get_bus_time
,
1774 .allocate_iso_context
= ohci_allocate_iso_context
,
1775 .free_iso_context
= ohci_free_iso_context
,
1776 .queue_iso
= ohci_queue_iso
,
1777 .start_iso
= ohci_start_iso
,
1778 .stop_iso
= ohci_stop_iso
,
1781 static int __devinit
1782 pci_probe(struct pci_dev
*dev
, const struct pci_device_id
*ent
)
1784 struct fw_ohci
*ohci
;
1785 u32 bus_options
, max_receive
, link_speed
;
1790 ohci
= kzalloc(sizeof(*ohci
), GFP_KERNEL
);
1792 fw_error("Could not malloc fw_ohci data.\n");
1796 fw_card_initialize(&ohci
->card
, &ohci_driver
, &dev
->dev
);
1798 err
= pci_enable_device(dev
);
1800 fw_error("Failed to enable OHCI hardware.\n");
1804 pci_set_master(dev
);
1805 pci_write_config_dword(dev
, OHCI1394_PCI_HCI_Control
, 0);
1806 pci_set_drvdata(dev
, ohci
);
1808 spin_lock_init(&ohci
->lock
);
1810 tasklet_init(&ohci
->bus_reset_tasklet
,
1811 bus_reset_tasklet
, (unsigned long)ohci
);
1813 err
= pci_request_region(dev
, 0, ohci_driver_name
);
1815 fw_error("MMIO resource unavailable\n");
1819 ohci
->registers
= pci_iomap(dev
, 0, OHCI1394_REGISTER_SIZE
);
1820 if (ohci
->registers
== NULL
) {
1821 fw_error("Failed to remap registers\n");
1826 ar_context_init(&ohci
->ar_request_ctx
, ohci
,
1827 OHCI1394_AsReqRcvContextControlSet
);
1829 ar_context_init(&ohci
->ar_response_ctx
, ohci
,
1830 OHCI1394_AsRspRcvContextControlSet
);
1832 context_init(&ohci
->at_request_ctx
, ohci
, AT_BUFFER_SIZE
,
1833 OHCI1394_AsReqTrContextControlSet
, handle_at_packet
);
1835 context_init(&ohci
->at_response_ctx
, ohci
, AT_BUFFER_SIZE
,
1836 OHCI1394_AsRspTrContextControlSet
, handle_at_packet
);
1838 reg_write(ohci
, OHCI1394_IsoRecvIntMaskSet
, ~0);
1839 ohci
->it_context_mask
= reg_read(ohci
, OHCI1394_IsoRecvIntMaskSet
);
1840 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, ~0);
1841 size
= sizeof(struct iso_context
) * hweight32(ohci
->it_context_mask
);
1842 ohci
->it_context_list
= kzalloc(size
, GFP_KERNEL
);
1844 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, ~0);
1845 ohci
->ir_context_mask
= reg_read(ohci
, OHCI1394_IsoXmitIntMaskSet
);
1846 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, ~0);
1847 size
= sizeof(struct iso_context
) * hweight32(ohci
->ir_context_mask
);
1848 ohci
->ir_context_list
= kzalloc(size
, GFP_KERNEL
);
1850 if (ohci
->it_context_list
== NULL
|| ohci
->ir_context_list
== NULL
) {
1851 fw_error("Out of memory for it/ir contexts.\n");
1853 goto fail_registers
;
1856 /* self-id dma buffer allocation */
1857 ohci
->self_id_cpu
= dma_alloc_coherent(ohci
->card
.device
,
1861 if (ohci
->self_id_cpu
== NULL
) {
1862 fw_error("Out of memory for self ID buffer.\n");
1864 goto fail_registers
;
1867 bus_options
= reg_read(ohci
, OHCI1394_BusOptions
);
1868 max_receive
= (bus_options
>> 12) & 0xf;
1869 link_speed
= bus_options
& 0x7;
1870 guid
= ((u64
) reg_read(ohci
, OHCI1394_GUIDHi
) << 32) |
1871 reg_read(ohci
, OHCI1394_GUIDLo
);
1873 err
= fw_card_add(&ohci
->card
, max_receive
, link_speed
, guid
);
1877 ohci
->version
= reg_read(ohci
, OHCI1394_Version
) & 0x00ff00ff;
1878 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
1879 dev
->dev
.bus_id
, ohci
->version
>> 16, ohci
->version
& 0xff);
1884 dma_free_coherent(ohci
->card
.device
, SELF_ID_BUF_SIZE
,
1885 ohci
->self_id_cpu
, ohci
->self_id_bus
);
1887 kfree(ohci
->it_context_list
);
1888 kfree(ohci
->ir_context_list
);
1889 pci_iounmap(dev
, ohci
->registers
);
1891 pci_release_region(dev
, 0);
1893 pci_disable_device(dev
);
1895 fw_card_put(&ohci
->card
);
1900 static void pci_remove(struct pci_dev
*dev
)
1902 struct fw_ohci
*ohci
;
1904 ohci
= pci_get_drvdata(dev
);
1905 reg_write(ohci
, OHCI1394_IntMaskClear
, ~0);
1907 fw_core_remove_card(&ohci
->card
);
1910 * FIXME: Fail all pending packets here, now that the upper
1911 * layers can't queue any more.
1914 software_reset(ohci
);
1915 free_irq(dev
->irq
, ohci
);
1916 dma_free_coherent(ohci
->card
.device
, SELF_ID_BUF_SIZE
,
1917 ohci
->self_id_cpu
, ohci
->self_id_bus
);
1918 kfree(ohci
->it_context_list
);
1919 kfree(ohci
->ir_context_list
);
1920 pci_iounmap(dev
, ohci
->registers
);
1921 pci_release_region(dev
, 0);
1922 pci_disable_device(dev
);
1923 fw_card_put(&ohci
->card
);
1925 fw_notify("Removed fw-ohci device.\n");
1929 static int pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1931 struct fw_ohci
*ohci
= pci_get_drvdata(pdev
);
1934 software_reset(ohci
);
1935 free_irq(pdev
->irq
, ohci
);
1936 err
= pci_save_state(pdev
);
1938 fw_error("pci_save_state failed\n");
1941 err
= pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
1943 fw_error("pci_set_power_state failed\n");
1950 static int pci_resume(struct pci_dev
*pdev
)
1952 struct fw_ohci
*ohci
= pci_get_drvdata(pdev
);
1955 pci_set_power_state(pdev
, PCI_D0
);
1956 pci_restore_state(pdev
);
1957 err
= pci_enable_device(pdev
);
1959 fw_error("pci_enable_device failed\n");
1963 return ohci_enable(&ohci
->card
, ohci
->config_rom
, CONFIG_ROM_SIZE
);
1967 static struct pci_device_id pci_table
[] = {
1968 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI
, ~0) },
1972 MODULE_DEVICE_TABLE(pci
, pci_table
);
1974 static struct pci_driver fw_ohci_pci_driver
= {
1975 .name
= ohci_driver_name
,
1976 .id_table
= pci_table
,
1978 .remove
= pci_remove
,
1980 .resume
= pci_resume
,
1981 .suspend
= pci_suspend
,
1985 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
1986 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
1987 MODULE_LICENSE("GPL");
1989 /* Provide a module alias so root-on-sbp2 initrds don't break. */
1990 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
1991 MODULE_ALIAS("ohci1394");
1994 static int __init
fw_ohci_init(void)
1996 return pci_register_driver(&fw_ohci_pci_driver
);
1999 static void __exit
fw_ohci_cleanup(void)
2001 pci_unregister_driver(&fw_ohci_pci_driver
);
2004 module_init(fw_ohci_init
);
2005 module_exit(fw_ohci_cleanup
);