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sky2: add new chip ids
[linux-2.6/verdex.git] / drivers / net / sky2.c
blobe86ca3d408494468346144b0c460af2cb6564cc2
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/ip.h>
35 #include <linux/tcp.h>
36 #include <linux/in.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/mii.h>
42
43 #include <asm/irq.h>
44
45 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
46 #define SKY2_VLAN_TAG_USED 1
47 #endif
48
49 #include "sky2.h"
50
51 #define DRV_NAME "sky2"
52 #define DRV_VERSION "1.11.1"
53 #define PFX DRV_NAME " "
54
55 /*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
58 * similar to Tigon3.
59 */
60
61 #define RX_LE_SIZE 1024
62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
63 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
64 #define RX_DEF_PENDING RX_MAX_PENDING
65 #define RX_SKB_ALIGN 8
66 #define RX_BUF_WRITE 16
67
68 #define TX_RING_SIZE 512
69 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
70 #define TX_MIN_PENDING 64
71 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
72
73 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
74 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
75 #define TX_WATCHDOG (5 * HZ)
76 #define NAPI_WEIGHT 64
77 #define PHY_RETRIES 1000
78
79 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
80
81 static const u32 default_msg =
82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
85
86 static int debug = -1; /* defaults above */
87 module_param(debug, int, 0);
88 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
90 static int copybreak __read_mostly = 128;
91 module_param(copybreak, int, 0);
92 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
94 static int disable_msi = 0;
95 module_param(disable_msi, int, 0);
96 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
98 static int idle_timeout = 0;
99 module_param(idle_timeout, int, 0);
100 MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
101
102 static const struct pci_device_id sky2_id_table[] = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
133 { 0 }
134 };
135
136 MODULE_DEVICE_TABLE(pci, sky2_id_table);
137
138 /* Avoid conditionals by using array */
139 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
140 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
141 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
142
143 /* This driver supports yukon2 chipset only */
144 static const char *yukon2_name[] = {
145 "XL", /* 0xb3 */
146 "EC Ultra", /* 0xb4 */
147 "Extreme", /* 0xb5 */
148 "EC", /* 0xb6 */
149 "FE", /* 0xb7 */
150 };
151
152 /* Access to external PHY */
153 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
154 {
155 int i;
156
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160
161 for (i = 0; i < PHY_RETRIES; i++) {
162 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
163 return 0;
164 udelay(1);
165 }
166
167 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
168 return -ETIMEDOUT;
169 }
170
171 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
172 {
173 int i;
174
175 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
176 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
177
178 for (i = 0; i < PHY_RETRIES; i++) {
179 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
180 *val = gma_read16(hw, port, GM_SMI_DATA);
181 return 0;
182 }
183
184 udelay(1);
185 }
186
187 return -ETIMEDOUT;
188 }
189
190 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
191 {
192 u16 v;
193
194 if (__gm_phy_read(hw, port, reg, &v) != 0)
195 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
196 return v;
197 }
198
199
200 static void sky2_power_on(struct sky2_hw *hw)
201 {
202 /* switch power to VCC (WA for VAUX problem) */
203 sky2_write8(hw, B0_POWER_CTRL,
204 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
205
206 /* disable Core Clock Division, */
207 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
208
209 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
210 /* enable bits are inverted */
211 sky2_write8(hw, B2_Y2_CLK_GATE,
212 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
213 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
214 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
215 else
216 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
217
218 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
219 u32 reg1;
220
221 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
222 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
223 reg1 &= P_ASPM_CONTROL_MSK;
224 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
225 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
226 }
227 }
228
229 static void sky2_power_aux(struct sky2_hw *hw)
230 {
231 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
232 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
233 else
234 /* enable bits are inverted */
235 sky2_write8(hw, B2_Y2_CLK_GATE,
236 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
237 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
238 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
239
240 /* switch power to VAUX */
241 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
242 sky2_write8(hw, B0_POWER_CTRL,
243 (PC_VAUX_ENA | PC_VCC_ENA |
244 PC_VAUX_ON | PC_VCC_OFF));
245 }
246
247 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
248 {
249 u16 reg;
250
251 /* disable all GMAC IRQ's */
252 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
253 /* disable PHY IRQs */
254 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
255
256 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
257 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
258 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
259 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
260
261 reg = gma_read16(hw, port, GM_RX_CTRL);
262 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
263 gma_write16(hw, port, GM_RX_CTRL, reg);
264 }
265
266 /* flow control to advertise bits */
267 static const u16 copper_fc_adv[] = {
268 [FC_NONE] = 0,
269 [FC_TX] = PHY_M_AN_ASP,
270 [FC_RX] = PHY_M_AN_PC,
271 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
272 };
273
274 /* flow control to advertise bits when using 1000BaseX */
275 static const u16 fiber_fc_adv[] = {
276 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
277 [FC_TX] = PHY_M_P_ASYM_MD_X,
278 [FC_RX] = PHY_M_P_SYM_MD_X,
279 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
280 };
281
282 /* flow control to GMA disable bits */
283 static const u16 gm_fc_disable[] = {
284 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
285 [FC_TX] = GM_GPCR_FC_RX_DIS,
286 [FC_RX] = GM_GPCR_FC_TX_DIS,
287 [FC_BOTH] = 0,
288 };
289
290
291 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
292 {
293 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
294 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
295
296 if (sky2->autoneg == AUTONEG_ENABLE
297 && !(hw->chip_id == CHIP_ID_YUKON_XL
298 || hw->chip_id == CHIP_ID_YUKON_EC_U
299 || hw->chip_id == CHIP_ID_YUKON_EX)) {
300 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
301
302 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
303 PHY_M_EC_MAC_S_MSK);
304 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
305
306 if (hw->chip_id == CHIP_ID_YUKON_EC)
307 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
308 else
309 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
310
311 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
312 }
313
314 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
315 if (sky2_is_copper(hw)) {
316 if (hw->chip_id == CHIP_ID_YUKON_FE) {
317 /* enable automatic crossover */
318 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
319 } else {
320 /* disable energy detect */
321 ctrl &= ~PHY_M_PC_EN_DET_MSK;
322
323 /* enable automatic crossover */
324 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
325
326 if (sky2->autoneg == AUTONEG_ENABLE
327 && (hw->chip_id == CHIP_ID_YUKON_XL
328 || hw->chip_id == CHIP_ID_YUKON_EC_U
329 || hw->chip_id == CHIP_ID_YUKON_EX)) {
330 ctrl &= ~PHY_M_PC_DSC_MSK;
331 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
332 }
333 }
334 } else {
335 /* workaround for deviation #4.88 (CRC errors) */
336 /* disable Automatic Crossover */
337
338 ctrl &= ~PHY_M_PC_MDIX_MSK;
339 }
340
341 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
342
343 /* special setup for PHY 88E1112 Fiber */
344 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
345 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
346
347 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
348 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
349 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
350 ctrl &= ~PHY_M_MAC_MD_MSK;
351 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
352 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
353
354 if (hw->pmd_type == 'P') {
355 /* select page 1 to access Fiber registers */
356 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
357
358 /* for SFP-module set SIGDET polarity to low */
359 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
360 ctrl |= PHY_M_FIB_SIGD_POL;
361 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
362 }
363
364 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
365 }
366
367 ctrl = PHY_CT_RESET;
368 ct1000 = 0;
369 adv = PHY_AN_CSMA;
370 reg = 0;
371
372 if (sky2->autoneg == AUTONEG_ENABLE) {
373 if (sky2_is_copper(hw)) {
374 if (sky2->advertising & ADVERTISED_1000baseT_Full)
375 ct1000 |= PHY_M_1000C_AFD;
376 if (sky2->advertising & ADVERTISED_1000baseT_Half)
377 ct1000 |= PHY_M_1000C_AHD;
378 if (sky2->advertising & ADVERTISED_100baseT_Full)
379 adv |= PHY_M_AN_100_FD;
380 if (sky2->advertising & ADVERTISED_100baseT_Half)
381 adv |= PHY_M_AN_100_HD;
382 if (sky2->advertising & ADVERTISED_10baseT_Full)
383 adv |= PHY_M_AN_10_FD;
384 if (sky2->advertising & ADVERTISED_10baseT_Half)
385 adv |= PHY_M_AN_10_HD;
386
387 adv |= copper_fc_adv[sky2->flow_mode];
388 } else { /* special defines for FIBER (88E1040S only) */
389 if (sky2->advertising & ADVERTISED_1000baseT_Full)
390 adv |= PHY_M_AN_1000X_AFD;
391 if (sky2->advertising & ADVERTISED_1000baseT_Half)
392 adv |= PHY_M_AN_1000X_AHD;
393
394 adv |= fiber_fc_adv[sky2->flow_mode];
395 }
396
397 /* Restart Auto-negotiation */
398 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
399 } else {
400 /* forced speed/duplex settings */
401 ct1000 = PHY_M_1000C_MSE;
402
403 /* Disable auto update for duplex flow control and speed */
404 reg |= GM_GPCR_AU_ALL_DIS;
405
406 switch (sky2->speed) {
407 case SPEED_1000:
408 ctrl |= PHY_CT_SP1000;
409 reg |= GM_GPCR_SPEED_1000;
410 break;
411 case SPEED_100:
412 ctrl |= PHY_CT_SP100;
413 reg |= GM_GPCR_SPEED_100;
414 break;
415 }
416
417 if (sky2->duplex == DUPLEX_FULL) {
418 reg |= GM_GPCR_DUP_FULL;
419 ctrl |= PHY_CT_DUP_MD;
420 } else if (sky2->speed < SPEED_1000)
421 sky2->flow_mode = FC_NONE;
422
423
424 reg |= gm_fc_disable[sky2->flow_mode];
425
426 /* Forward pause packets to GMAC? */
427 if (sky2->flow_mode & FC_RX)
428 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
429 else
430 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
431 }
432
433 gma_write16(hw, port, GM_GP_CTRL, reg);
434
435 if (hw->chip_id != CHIP_ID_YUKON_FE)
436 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
437
438 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
439 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
440
441 /* Setup Phy LED's */
442 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
443 ledover = 0;
444
445 switch (hw->chip_id) {
446 case CHIP_ID_YUKON_FE:
447 /* on 88E3082 these bits are at 11..9 (shifted left) */
448 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
449
450 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
451
452 /* delete ACT LED control bits */
453 ctrl &= ~PHY_M_FELP_LED1_MSK;
454 /* change ACT LED control to blink mode */
455 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
456 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
457 break;
458
459 case CHIP_ID_YUKON_XL:
460 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
461
462 /* select page 3 to access LED control register */
463 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
464
465 /* set LED Function Control register */
466 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
467 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
468 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
469 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
470 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
471
472 /* set Polarity Control register */
473 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
474 (PHY_M_POLC_LS1_P_MIX(4) |
475 PHY_M_POLC_IS0_P_MIX(4) |
476 PHY_M_POLC_LOS_CTRL(2) |
477 PHY_M_POLC_INIT_CTRL(2) |
478 PHY_M_POLC_STA1_CTRL(2) |
479 PHY_M_POLC_STA0_CTRL(2)));
480
481 /* restore page register */
482 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
483 break;
484
485 case CHIP_ID_YUKON_EC_U:
486 case CHIP_ID_YUKON_EX:
487 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
488
489 /* select page 3 to access LED control register */
490 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
491
492 /* set LED Function Control register */
493 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
494 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
495 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
496 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
497 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
498
499 /* set Blink Rate in LED Timer Control Register */
500 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
501 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
502 /* restore page register */
503 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
504 break;
505
506 default:
507 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
508 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
509 /* turn off the Rx LED (LED_RX) */
510 ledover &= ~PHY_M_LED_MO_RX;
511 }
512
513 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
514 /* apply fixes in PHY AFE */
515 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
516 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
517
518 /* increase differential signal amplitude in 10BASE-T */
519 gm_phy_write(hw, port, 0x18, 0xaa99);
520 gm_phy_write(hw, port, 0x17, 0x2011);
521
522 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
523 gm_phy_write(hw, port, 0x18, 0xa204);
524 gm_phy_write(hw, port, 0x17, 0x2002);
525
526 /* set page register to 0 */
527 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
528 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
529 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
530
531 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
532 /* turn on 100 Mbps LED (LED_LINK100) */
533 ledover |= PHY_M_LED_MO_100;
534 }
535
536 if (ledover)
537 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
538
539 }
540
541 /* Enable phy interrupt on auto-negotiation complete (or link up) */
542 if (sky2->autoneg == AUTONEG_ENABLE)
543 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
544 else
545 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
546 }
547
548 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
549 {
550 u32 reg1;
551 static const u32 phy_power[]
552 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
553
554 /* looks like this XL is back asswards .. */
555 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
556 onoff = !onoff;
557
558 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
559 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
560 if (onoff)
561 /* Turn off phy power saving */
562 reg1 &= ~phy_power[port];
563 else
564 reg1 |= phy_power[port];
565
566 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
567 sky2_pci_read32(hw, PCI_DEV_REG1);
568 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
569 udelay(100);
570 }
571
572 /* Force a renegotiation */
573 static void sky2_phy_reinit(struct sky2_port *sky2)
574 {
575 spin_lock_bh(&sky2->phy_lock);
576 sky2_phy_init(sky2->hw, sky2->port);
577 spin_unlock_bh(&sky2->phy_lock);
578 }
579
580 /* Put device in state to listen for Wake On Lan */
581 static void sky2_wol_init(struct sky2_port *sky2)
582 {
583 struct sky2_hw *hw = sky2->hw;
584 unsigned port = sky2->port;
585 enum flow_control save_mode;
586 u16 ctrl;
587 u32 reg1;
588
589 /* Bring hardware out of reset */
590 sky2_write16(hw, B0_CTST, CS_RST_CLR);
591 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
592
593 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
594 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
595
596 /* Force to 10/100
597 * sky2_reset will re-enable on resume
598 */
599 save_mode = sky2->flow_mode;
600 ctrl = sky2->advertising;
601
602 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
603 sky2->flow_mode = FC_NONE;
604 sky2_phy_power(hw, port, 1);
605 sky2_phy_reinit(sky2);
606
607 sky2->flow_mode = save_mode;
608 sky2->advertising = ctrl;
609
610 /* Set GMAC to no flow control and auto update for speed/duplex */
611 gma_write16(hw, port, GM_GP_CTRL,
612 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
613 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
614
615 /* Set WOL address */
616 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
617 sky2->netdev->dev_addr, ETH_ALEN);
618
619 /* Turn on appropriate WOL control bits */
620 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
621 ctrl = 0;
622 if (sky2->wol & WAKE_PHY)
623 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
624 else
625 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
626
627 if (sky2->wol & WAKE_MAGIC)
628 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
629 else
630 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
631
632 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
633 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
634
635 /* Turn on legacy PCI-Express PME mode */
636 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
637 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
638 reg1 |= PCI_Y2_PME_LEGACY;
639 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
640 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
641
642 /* block receiver */
643 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
644
645 }
646
647 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
648 {
649 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
650 u16 reg;
651 int i;
652 const u8 *addr = hw->dev[port]->dev_addr;
653
654 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
655 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
656
657 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
658
659 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
660 /* WA DEV_472 -- looks like crossed wires on port 2 */
661 /* clear GMAC 1 Control reset */
662 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
663 do {
664 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
665 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
666 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
667 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
668 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
669 }
670
671 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
672
673 /* Enable Transmit FIFO Underrun */
674 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
675
676 spin_lock_bh(&sky2->phy_lock);
677 sky2_phy_init(hw, port);
678 spin_unlock_bh(&sky2->phy_lock);
679
680 /* MIB clear */
681 reg = gma_read16(hw, port, GM_PHY_ADDR);
682 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
683
684 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
685 gma_read16(hw, port, i);
686 gma_write16(hw, port, GM_PHY_ADDR, reg);
687
688 /* transmit control */
689 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
690
691 /* receive control reg: unicast + multicast + no FCS */
692 gma_write16(hw, port, GM_RX_CTRL,
693 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
694
695 /* transmit flow control */
696 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
697
698 /* transmit parameter */
699 gma_write16(hw, port, GM_TX_PARAM,
700 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
701 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
702 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
703 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
704
705 /* serial mode register */
706 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
707 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
708
709 if (hw->dev[port]->mtu > ETH_DATA_LEN)
710 reg |= GM_SMOD_JUMBO_ENA;
711
712 gma_write16(hw, port, GM_SERIAL_MODE, reg);
713
714 /* virtual address for data */
715 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
716
717 /* physical address: used for pause frames */
718 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
719
720 /* ignore counter overflows */
721 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
722 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
723 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
724
725 /* Configure Rx MAC FIFO */
726 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
727 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
728 GMF_OPER_ON | GMF_RX_F_FL_ON);
729
730 /* Flush Rx MAC FIFO on any flow control or error */
731 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
732
733 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
734 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
735
736 /* Configure Tx MAC FIFO */
737 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
738 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
739
740 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
741 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
742 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
743 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
744 /* set Tx GMAC FIFO Almost Empty Threshold */
745 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
746 /* Disable Store & Forward mode for TX */
747 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
748 }
749 }
750
751 }
752
753 /* Assign Ram Buffer allocation to queue */
754 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
755 {
756 u32 end;
757
758 /* convert from K bytes to qwords used for hw register */
759 start *= 1024/8;
760 space *= 1024/8;
761 end = start + space - 1;
762
763 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
764 sky2_write32(hw, RB_ADDR(q, RB_START), start);
765 sky2_write32(hw, RB_ADDR(q, RB_END), end);
766 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
767 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
768
769 if (q == Q_R1 || q == Q_R2) {
770 u32 tp = space - space/4;
771
772 /* On receive queue's set the thresholds
773 * give receiver priority when > 3/4 full
774 * send pause when down to 2K
775 */
776 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
777 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
778
779 tp = space - 2048/8;
780 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
781 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
782 } else {
783 /* Enable store & forward on Tx queue's because
784 * Tx FIFO is only 1K on Yukon
785 */
786 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
787 }
788
789 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
790 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
791 }
792
793 /* Setup Bus Memory Interface */
794 static void sky2_qset(struct sky2_hw *hw, u16 q)
795 {
796 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
797 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
798 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
799 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
800 }
801
802 /* Setup prefetch unit registers. This is the interface between
803 * hardware and driver list elements
804 */
805 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
806 u64 addr, u32 last)
807 {
808 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
809 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
810 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
811 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
812 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
813 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
814
815 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
816 }
817
818 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
819 {
820 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
821
822 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
823 le->ctrl = 0;
824 return le;
825 }
826
827 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
828 struct sky2_tx_le *le)
829 {
830 return sky2->tx_ring + (le - sky2->tx_le);
831 }
832
833 /* Update chip's next pointer */
834 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
835 {
836 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
837 wmb();
838 sky2_write16(hw, q, idx);
839 sky2_read16(hw, q);
840 }
841
842
843 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
844 {
845 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
846 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
847 le->ctrl = 0;
848 return le;
849 }
850
851 /* Return high part of DMA address (could be 32 or 64 bit) */
852 static inline u32 high32(dma_addr_t a)
853 {
854 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
855 }
856
857 /* Build description to hardware for one receive segment */
858 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
859 dma_addr_t map, unsigned len)
860 {
861 struct sky2_rx_le *le;
862 u32 hi = high32(map);
863
864 if (sky2->rx_addr64 != hi) {
865 le = sky2_next_rx(sky2);
866 le->addr = cpu_to_le32(hi);
867 le->opcode = OP_ADDR64 | HW_OWNER;
868 sky2->rx_addr64 = high32(map + len);
869 }
870
871 le = sky2_next_rx(sky2);
872 le->addr = cpu_to_le32((u32) map);
873 le->length = cpu_to_le16(len);
874 le->opcode = op | HW_OWNER;
875 }
876
877 /* Build description to hardware for one possibly fragmented skb */
878 static void sky2_rx_submit(struct sky2_port *sky2,
879 const struct rx_ring_info *re)
880 {
881 int i;
882
883 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
884
885 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
886 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
887 }
888
889
890 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
891 unsigned size)
892 {
893 struct sk_buff *skb = re->skb;
894 int i;
895
896 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
897 pci_unmap_len_set(re, data_size, size);
898
899 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
900 re->frag_addr[i] = pci_map_page(pdev,
901 skb_shinfo(skb)->frags[i].page,
902 skb_shinfo(skb)->frags[i].page_offset,
903 skb_shinfo(skb)->frags[i].size,
904 PCI_DMA_FROMDEVICE);
905 }
906
907 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
908 {
909 struct sk_buff *skb = re->skb;
910 int i;
911
912 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
913 PCI_DMA_FROMDEVICE);
914
915 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
916 pci_unmap_page(pdev, re->frag_addr[i],
917 skb_shinfo(skb)->frags[i].size,
918 PCI_DMA_FROMDEVICE);
919 }
920
921 /* Tell chip where to start receive checksum.
922 * Actually has two checksums, but set both same to avoid possible byte
923 * order problems.
924 */
925 static void rx_set_checksum(struct sky2_port *sky2)
926 {
927 struct sky2_rx_le *le;
928
929 le = sky2_next_rx(sky2);
930 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
931 le->ctrl = 0;
932 le->opcode = OP_TCPSTART | HW_OWNER;
933
934 sky2_write32(sky2->hw,
935 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
936 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
937
938 }
939
940 /*
941 * The RX Stop command will not work for Yukon-2 if the BMU does not
942 * reach the end of packet and since we can't make sure that we have
943 * incoming data, we must reset the BMU while it is not doing a DMA
944 * transfer. Since it is possible that the RX path is still active,
945 * the RX RAM buffer will be stopped first, so any possible incoming
946 * data will not trigger a DMA. After the RAM buffer is stopped, the
947 * BMU is polled until any DMA in progress is ended and only then it
948 * will be reset.
949 */
950 static void sky2_rx_stop(struct sky2_port *sky2)
951 {
952 struct sky2_hw *hw = sky2->hw;
953 unsigned rxq = rxqaddr[sky2->port];
954 int i;
955
956 /* disable the RAM Buffer receive queue */
957 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
958
959 for (i = 0; i < 0xffff; i++)
960 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
961 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
962 goto stopped;
963
964 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
965 sky2->netdev->name);
966 stopped:
967 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
968
969 /* reset the Rx prefetch unit */
970 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
971 }
972
973 /* Clean out receive buffer area, assumes receiver hardware stopped */
974 static void sky2_rx_clean(struct sky2_port *sky2)
975 {
976 unsigned i;
977
978 memset(sky2->rx_le, 0, RX_LE_BYTES);
979 for (i = 0; i < sky2->rx_pending; i++) {
980 struct rx_ring_info *re = sky2->rx_ring + i;
981
982 if (re->skb) {
983 sky2_rx_unmap_skb(sky2->hw->pdev, re);
984 kfree_skb(re->skb);
985 re->skb = NULL;
986 }
987 }
988 }
989
990 /* Basic MII support */
991 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
992 {
993 struct mii_ioctl_data *data = if_mii(ifr);
994 struct sky2_port *sky2 = netdev_priv(dev);
995 struct sky2_hw *hw = sky2->hw;
996 int err = -EOPNOTSUPP;
997
998 if (!netif_running(dev))
999 return -ENODEV; /* Phy still in reset */
1000
1001 switch (cmd) {
1002 case SIOCGMIIPHY:
1003 data->phy_id = PHY_ADDR_MARV;
1004
1005 /* fallthru */
1006 case SIOCGMIIREG: {
1007 u16 val = 0;
1008
1009 spin_lock_bh(&sky2->phy_lock);
1010 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1011 spin_unlock_bh(&sky2->phy_lock);
1012
1013 data->val_out = val;
1014 break;
1015 }
1016
1017 case SIOCSMIIREG:
1018 if (!capable(CAP_NET_ADMIN))
1019 return -EPERM;
1020
1021 spin_lock_bh(&sky2->phy_lock);
1022 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1023 data->val_in);
1024 spin_unlock_bh(&sky2->phy_lock);
1025 break;
1026 }
1027 return err;
1028 }
1029
1030 #ifdef SKY2_VLAN_TAG_USED
1031 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1032 {
1033 struct sky2_port *sky2 = netdev_priv(dev);
1034 struct sky2_hw *hw = sky2->hw;
1035 u16 port = sky2->port;
1036
1037 netif_tx_lock_bh(dev);
1038
1039 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
1040 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
1041 sky2->vlgrp = grp;
1042
1043 netif_tx_unlock_bh(dev);
1044 }
1045
1046 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1047 {
1048 struct sky2_port *sky2 = netdev_priv(dev);
1049 struct sky2_hw *hw = sky2->hw;
1050 u16 port = sky2->port;
1051
1052 netif_tx_lock_bh(dev);
1053
1054 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1055 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
1056 if (sky2->vlgrp)
1057 sky2->vlgrp->vlan_devices[vid] = NULL;
1058
1059 netif_tx_unlock_bh(dev);
1060 }
1061 #endif
1062
1063 /*
1064 * Allocate an skb for receiving. If the MTU is large enough
1065 * make the skb non-linear with a fragment list of pages.
1066 *
1067 * It appears the hardware has a bug in the FIFO logic that
1068 * cause it to hang if the FIFO gets overrun and the receive buffer
1069 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1070 * aligned except if slab debugging is enabled.
1071 */
1072 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1073 {
1074 struct sk_buff *skb;
1075 unsigned long p;
1076 int i;
1077
1078 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1079 if (!skb)
1080 goto nomem;
1081
1082 p = (unsigned long) skb->data;
1083 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1084
1085 for (i = 0; i < sky2->rx_nfrags; i++) {
1086 struct page *page = alloc_page(GFP_ATOMIC);
1087
1088 if (!page)
1089 goto free_partial;
1090 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1091 }
1092
1093 return skb;
1094 free_partial:
1095 kfree_skb(skb);
1096 nomem:
1097 return NULL;
1098 }
1099
1100 /*
1101 * Allocate and setup receiver buffer pool.
1102 * Normal case this ends up creating one list element for skb
1103 * in the receive ring. Worst case if using large MTU and each
1104 * allocation falls on a different 64 bit region, that results
1105 * in 6 list elements per ring entry.
1106 * One element is used for checksum enable/disable, and one
1107 * extra to avoid wrap.
1108 */
1109 static int sky2_rx_start(struct sky2_port *sky2)
1110 {
1111 struct sky2_hw *hw = sky2->hw;
1112 struct rx_ring_info *re;
1113 unsigned rxq = rxqaddr[sky2->port];
1114 unsigned i, size, space, thresh;
1115
1116 sky2->rx_put = sky2->rx_next = 0;
1117 sky2_qset(hw, rxq);
1118
1119 /* On PCI express lowering the watermark gives better performance */
1120 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1121 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1122
1123 /* These chips have no ram buffer?
1124 * MAC Rx RAM Read is controlled by hardware */
1125 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1126 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1127 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1128 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1129
1130 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1131
1132 rx_set_checksum(sky2);
1133
1134 /* Space needed for frame data + headers rounded up */
1135 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1136 + 8;
1137
1138 /* Stopping point for hardware truncation */
1139 thresh = (size - 8) / sizeof(u32);
1140
1141 /* Account for overhead of skb - to avoid order > 0 allocation */
1142 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1143 + sizeof(struct skb_shared_info);
1144
1145 sky2->rx_nfrags = space >> PAGE_SHIFT;
1146 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1147
1148 if (sky2->rx_nfrags != 0) {
1149 /* Compute residue after pages */
1150 space = sky2->rx_nfrags << PAGE_SHIFT;
1151
1152 if (space < size)
1153 size -= space;
1154 else
1155 size = 0;
1156
1157 /* Optimize to handle small packets and headers */
1158 if (size < copybreak)
1159 size = copybreak;
1160 if (size < ETH_HLEN)
1161 size = ETH_HLEN;
1162 }
1163 sky2->rx_data_size = size;
1164
1165 /* Fill Rx ring */
1166 for (i = 0; i < sky2->rx_pending; i++) {
1167 re = sky2->rx_ring + i;
1168
1169 re->skb = sky2_rx_alloc(sky2);
1170 if (!re->skb)
1171 goto nomem;
1172
1173 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1174 sky2_rx_submit(sky2, re);
1175 }
1176
1177 /*
1178 * The receiver hangs if it receives frames larger than the
1179 * packet buffer. As a workaround, truncate oversize frames, but
1180 * the register is limited to 9 bits, so if you do frames > 2052
1181 * you better get the MTU right!
1182 */
1183 if (thresh > 0x1ff)
1184 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1185 else {
1186 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1187 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1188 }
1189
1190 /* Tell chip about available buffers */
1191 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
1192 return 0;
1193 nomem:
1194 sky2_rx_clean(sky2);
1195 return -ENOMEM;
1196 }
1197
1198 /* Bring up network interface. */
1199 static int sky2_up(struct net_device *dev)
1200 {
1201 struct sky2_port *sky2 = netdev_priv(dev);
1202 struct sky2_hw *hw = sky2->hw;
1203 unsigned port = sky2->port;
1204 u32 ramsize, imask;
1205 int cap, err = -ENOMEM;
1206 struct net_device *otherdev = hw->dev[sky2->port^1];
1207
1208 /*
1209 * On dual port PCI-X card, there is an problem where status
1210 * can be received out of order due to split transactions
1211 */
1212 if (otherdev && netif_running(otherdev) &&
1213 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1214 struct sky2_port *osky2 = netdev_priv(otherdev);
1215 u16 cmd;
1216
1217 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1218 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1219 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1220
1221 sky2->rx_csum = 0;
1222 osky2->rx_csum = 0;
1223 }
1224
1225 if (netif_msg_ifup(sky2))
1226 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1227
1228 /* must be power of 2 */
1229 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1230 TX_RING_SIZE *
1231 sizeof(struct sky2_tx_le),
1232 &sky2->tx_le_map);
1233 if (!sky2->tx_le)
1234 goto err_out;
1235
1236 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1237 GFP_KERNEL);
1238 if (!sky2->tx_ring)
1239 goto err_out;
1240 sky2->tx_prod = sky2->tx_cons = 0;
1241
1242 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1243 &sky2->rx_le_map);
1244 if (!sky2->rx_le)
1245 goto err_out;
1246 memset(sky2->rx_le, 0, RX_LE_BYTES);
1247
1248 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1249 GFP_KERNEL);
1250 if (!sky2->rx_ring)
1251 goto err_out;
1252
1253 sky2_phy_power(hw, port, 1);
1254
1255 sky2_mac_init(hw, port);
1256
1257 /* Register is number of 4K blocks on internal RAM buffer. */
1258 ramsize = sky2_read8(hw, B2_E_0) * 4;
1259 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1260
1261 if (ramsize > 0) {
1262 u32 rxspace;
1263
1264 if (ramsize < 16)
1265 rxspace = ramsize / 2;
1266 else
1267 rxspace = 8 + (2*(ramsize - 16))/3;
1268
1269 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1270 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1271
1272 /* Make sure SyncQ is disabled */
1273 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1274 RB_RST_SET);
1275 }
1276
1277 sky2_qset(hw, txqaddr[port]);
1278
1279 /* Set almost empty threshold */
1280 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1281 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1282 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1283
1284 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1285 TX_RING_SIZE - 1);
1286
1287 err = sky2_rx_start(sky2);
1288 if (err)
1289 goto err_out;
1290
1291 /* Enable interrupts from phy/mac for port */
1292 imask = sky2_read32(hw, B0_IMSK);
1293 imask |= portirq_msk[port];
1294 sky2_write32(hw, B0_IMSK, imask);
1295
1296 return 0;
1297
1298 err_out:
1299 if (sky2->rx_le) {
1300 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1301 sky2->rx_le, sky2->rx_le_map);
1302 sky2->rx_le = NULL;
1303 }
1304 if (sky2->tx_le) {
1305 pci_free_consistent(hw->pdev,
1306 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1307 sky2->tx_le, sky2->tx_le_map);
1308 sky2->tx_le = NULL;
1309 }
1310 kfree(sky2->tx_ring);
1311 kfree(sky2->rx_ring);
1312
1313 sky2->tx_ring = NULL;
1314 sky2->rx_ring = NULL;
1315 return err;
1316 }
1317
1318 /* Modular subtraction in ring */
1319 static inline int tx_dist(unsigned tail, unsigned head)
1320 {
1321 return (head - tail) & (TX_RING_SIZE - 1);
1322 }
1323
1324 /* Number of list elements available for next tx */
1325 static inline int tx_avail(const struct sky2_port *sky2)
1326 {
1327 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1328 }
1329
1330 /* Estimate of number of transmit list elements required */
1331 static unsigned tx_le_req(const struct sk_buff *skb)
1332 {
1333 unsigned count;
1334
1335 count = sizeof(dma_addr_t) / sizeof(u32);
1336 count += skb_shinfo(skb)->nr_frags * count;
1337
1338 if (skb_is_gso(skb))
1339 ++count;
1340
1341 if (skb->ip_summed == CHECKSUM_PARTIAL)
1342 ++count;
1343
1344 return count;
1345 }
1346
1347 /*
1348 * Put one packet in ring for transmit.
1349 * A single packet can generate multiple list elements, and
1350 * the number of ring elements will probably be less than the number
1351 * of list elements used.
1352 */
1353 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1354 {
1355 struct sky2_port *sky2 = netdev_priv(dev);
1356 struct sky2_hw *hw = sky2->hw;
1357 struct sky2_tx_le *le = NULL;
1358 struct tx_ring_info *re;
1359 unsigned i, len;
1360 dma_addr_t mapping;
1361 u32 addr64;
1362 u16 mss;
1363 u8 ctrl;
1364
1365 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1366 return NETDEV_TX_BUSY;
1367
1368 if (unlikely(netif_msg_tx_queued(sky2)))
1369 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1370 dev->name, sky2->tx_prod, skb->len);
1371
1372 len = skb_headlen(skb);
1373 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1374 addr64 = high32(mapping);
1375
1376 /* Send high bits if changed or crosses boundary */
1377 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1378 le = get_tx_le(sky2);
1379 le->addr = cpu_to_le32(addr64);
1380 le->opcode = OP_ADDR64 | HW_OWNER;
1381 sky2->tx_addr64 = high32(mapping + len);
1382 }
1383
1384 /* Check for TCP Segmentation Offload */
1385 mss = skb_shinfo(skb)->gso_size;
1386 if (mss != 0) {
1387 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1388 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1389 mss += ETH_HLEN;
1390
1391 if (mss != sky2->tx_last_mss) {
1392 le = get_tx_le(sky2);
1393 le->addr = cpu_to_le32(mss);
1394 le->opcode = OP_LRGLEN | HW_OWNER;
1395 sky2->tx_last_mss = mss;
1396 }
1397 }
1398
1399 ctrl = 0;
1400 #ifdef SKY2_VLAN_TAG_USED
1401 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1402 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1403 if (!le) {
1404 le = get_tx_le(sky2);
1405 le->addr = 0;
1406 le->opcode = OP_VLAN|HW_OWNER;
1407 } else
1408 le->opcode |= OP_VLAN;
1409 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1410 ctrl |= INS_VLAN;
1411 }
1412 #endif
1413
1414 /* Handle TCP checksum offload */
1415 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1416 unsigned offset = skb->h.raw - skb->data;
1417 u32 tcpsum;
1418
1419 tcpsum = offset << 16; /* sum start */
1420 tcpsum |= offset + skb->csum_offset; /* sum write */
1421
1422 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1423 if (skb->nh.iph->protocol == IPPROTO_UDP)
1424 ctrl |= UDPTCP;
1425
1426 if (tcpsum != sky2->tx_tcpsum) {
1427 sky2->tx_tcpsum = tcpsum;
1428
1429 le = get_tx_le(sky2);
1430 le->addr = cpu_to_le32(tcpsum);
1431 le->length = 0; /* initial checksum value */
1432 le->ctrl = 1; /* one packet */
1433 le->opcode = OP_TCPLISW | HW_OWNER;
1434 }
1435 }
1436
1437 le = get_tx_le(sky2);
1438 le->addr = cpu_to_le32((u32) mapping);
1439 le->length = cpu_to_le16(len);
1440 le->ctrl = ctrl;
1441 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1442
1443 re = tx_le_re(sky2, le);
1444 re->skb = skb;
1445 pci_unmap_addr_set(re, mapaddr, mapping);
1446 pci_unmap_len_set(re, maplen, len);
1447
1448 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1449 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1450
1451 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1452 frag->size, PCI_DMA_TODEVICE);
1453 addr64 = high32(mapping);
1454 if (addr64 != sky2->tx_addr64) {
1455 le = get_tx_le(sky2);
1456 le->addr = cpu_to_le32(addr64);
1457 le->ctrl = 0;
1458 le->opcode = OP_ADDR64 | HW_OWNER;
1459 sky2->tx_addr64 = addr64;
1460 }
1461
1462 le = get_tx_le(sky2);
1463 le->addr = cpu_to_le32((u32) mapping);
1464 le->length = cpu_to_le16(frag->size);
1465 le->ctrl = ctrl;
1466 le->opcode = OP_BUFFER | HW_OWNER;
1467
1468 re = tx_le_re(sky2, le);
1469 re->skb = skb;
1470 pci_unmap_addr_set(re, mapaddr, mapping);
1471 pci_unmap_len_set(re, maplen, frag->size);
1472 }
1473
1474 le->ctrl |= EOP;
1475
1476 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1477 netif_stop_queue(dev);
1478
1479 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1480
1481 dev->trans_start = jiffies;
1482 return NETDEV_TX_OK;
1483 }
1484
1485 /*
1486 * Free ring elements from starting at tx_cons until "done"
1487 *
1488 * NB: the hardware will tell us about partial completion of multi-part
1489 * buffers so make sure not to free skb to early.
1490 */
1491 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1492 {
1493 struct net_device *dev = sky2->netdev;
1494 struct pci_dev *pdev = sky2->hw->pdev;
1495 unsigned idx;
1496
1497 BUG_ON(done >= TX_RING_SIZE);
1498
1499 for (idx = sky2->tx_cons; idx != done;
1500 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1501 struct sky2_tx_le *le = sky2->tx_le + idx;
1502 struct tx_ring_info *re = sky2->tx_ring + idx;
1503
1504 switch(le->opcode & ~HW_OWNER) {
1505 case OP_LARGESEND:
1506 case OP_PACKET:
1507 pci_unmap_single(pdev,
1508 pci_unmap_addr(re, mapaddr),
1509 pci_unmap_len(re, maplen),
1510 PCI_DMA_TODEVICE);
1511 break;
1512 case OP_BUFFER:
1513 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1514 pci_unmap_len(re, maplen),
1515 PCI_DMA_TODEVICE);
1516 break;
1517 }
1518
1519 if (le->ctrl & EOP) {
1520 if (unlikely(netif_msg_tx_done(sky2)))
1521 printk(KERN_DEBUG "%s: tx done %u\n",
1522 dev->name, idx);
1523 sky2->net_stats.tx_packets++;
1524 sky2->net_stats.tx_bytes += re->skb->len;
1525
1526 dev_kfree_skb_any(re->skb);
1527 }
1528
1529 le->opcode = 0; /* paranoia */
1530 }
1531
1532 sky2->tx_cons = idx;
1533 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1534 netif_wake_queue(dev);
1535 }
1536
1537 /* Cleanup all untransmitted buffers, assume transmitter not running */
1538 static void sky2_tx_clean(struct net_device *dev)
1539 {
1540 struct sky2_port *sky2 = netdev_priv(dev);
1541
1542 netif_tx_lock_bh(dev);
1543 sky2_tx_complete(sky2, sky2->tx_prod);
1544 netif_tx_unlock_bh(dev);
1545 }
1546
1547 /* Network shutdown */
1548 static int sky2_down(struct net_device *dev)
1549 {
1550 struct sky2_port *sky2 = netdev_priv(dev);
1551 struct sky2_hw *hw = sky2->hw;
1552 unsigned port = sky2->port;
1553 u16 ctrl;
1554 u32 imask;
1555
1556 /* Never really got started! */
1557 if (!sky2->tx_le)
1558 return 0;
1559
1560 if (netif_msg_ifdown(sky2))
1561 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1562
1563 /* Stop more packets from being queued */
1564 netif_stop_queue(dev);
1565
1566 /* Disable port IRQ */
1567 imask = sky2_read32(hw, B0_IMSK);
1568 imask &= ~portirq_msk[port];
1569 sky2_write32(hw, B0_IMSK, imask);
1570
1571 /*
1572 * Both ports share the NAPI poll on port 0, so if necessary undo the
1573 * the disable that is done in dev_close.
1574 */
1575 if (sky2->port == 0 && hw->ports > 1)
1576 netif_poll_enable(dev);
1577
1578 sky2_gmac_reset(hw, port);
1579
1580 /* Stop transmitter */
1581 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1582 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1583
1584 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1585 RB_RST_SET | RB_DIS_OP_MD);
1586
1587 /* WA for dev. #4.209 */
1588 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1589 && (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1590 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1591 sky2->speed != SPEED_1000 ?
1592 TX_STFW_ENA : TX_STFW_DIS);
1593
1594 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1595 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1596 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1597
1598 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1599
1600 /* Workaround shared GMAC reset */
1601 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1602 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1603 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1604
1605 /* Disable Force Sync bit and Enable Alloc bit */
1606 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1607 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1608
1609 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1610 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1611 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1612
1613 /* Reset the PCI FIFO of the async Tx queue */
1614 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1615 BMU_RST_SET | BMU_FIFO_RST);
1616
1617 /* Reset the Tx prefetch units */
1618 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1619 PREF_UNIT_RST_SET);
1620
1621 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1622
1623 sky2_rx_stop(sky2);
1624
1625 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1626 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1627
1628 sky2_phy_power(hw, port, 0);
1629
1630 /* turn off LED's */
1631 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1632
1633 synchronize_irq(hw->pdev->irq);
1634
1635 sky2_tx_clean(dev);
1636 sky2_rx_clean(sky2);
1637
1638 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1639 sky2->rx_le, sky2->rx_le_map);
1640 kfree(sky2->rx_ring);
1641
1642 pci_free_consistent(hw->pdev,
1643 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1644 sky2->tx_le, sky2->tx_le_map);
1645 kfree(sky2->tx_ring);
1646
1647 sky2->tx_le = NULL;
1648 sky2->rx_le = NULL;
1649
1650 sky2->rx_ring = NULL;
1651 sky2->tx_ring = NULL;
1652
1653 return 0;
1654 }
1655
1656 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1657 {
1658 if (!sky2_is_copper(hw))
1659 return SPEED_1000;
1660
1661 if (hw->chip_id == CHIP_ID_YUKON_FE)
1662 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1663
1664 switch (aux & PHY_M_PS_SPEED_MSK) {
1665 case PHY_M_PS_SPEED_1000:
1666 return SPEED_1000;
1667 case PHY_M_PS_SPEED_100:
1668 return SPEED_100;
1669 default:
1670 return SPEED_10;
1671 }
1672 }
1673
1674 static void sky2_link_up(struct sky2_port *sky2)
1675 {
1676 struct sky2_hw *hw = sky2->hw;
1677 unsigned port = sky2->port;
1678 u16 reg;
1679 static const char *fc_name[] = {
1680 [FC_NONE] = "none",
1681 [FC_TX] = "tx",
1682 [FC_RX] = "rx",
1683 [FC_BOTH] = "both",
1684 };
1685
1686 /* enable Rx/Tx */
1687 reg = gma_read16(hw, port, GM_GP_CTRL);
1688 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1689 gma_write16(hw, port, GM_GP_CTRL, reg);
1690
1691 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1692
1693 netif_carrier_on(sky2->netdev);
1694 netif_wake_queue(sky2->netdev);
1695
1696 /* Turn on link LED */
1697 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1698 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1699
1700 if (hw->chip_id == CHIP_ID_YUKON_XL
1701 || hw->chip_id == CHIP_ID_YUKON_EC_U
1702 || hw->chip_id == CHIP_ID_YUKON_EX) {
1703 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1704 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1705
1706 switch(sky2->speed) {
1707 case SPEED_10:
1708 led |= PHY_M_LEDC_INIT_CTRL(7);
1709 break;
1710
1711 case SPEED_100:
1712 led |= PHY_M_LEDC_STA1_CTRL(7);
1713 break;
1714
1715 case SPEED_1000:
1716 led |= PHY_M_LEDC_STA0_CTRL(7);
1717 break;
1718 }
1719
1720 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1721 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1722 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1723 }
1724
1725 if (netif_msg_link(sky2))
1726 printk(KERN_INFO PFX
1727 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1728 sky2->netdev->name, sky2->speed,
1729 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1730 fc_name[sky2->flow_status]);
1731 }
1732
1733 static void sky2_link_down(struct sky2_port *sky2)
1734 {
1735 struct sky2_hw *hw = sky2->hw;
1736 unsigned port = sky2->port;
1737 u16 reg;
1738
1739 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1740
1741 reg = gma_read16(hw, port, GM_GP_CTRL);
1742 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1743 gma_write16(hw, port, GM_GP_CTRL, reg);
1744
1745 if (sky2->flow_status == FC_RX) {
1746 /* restore Asymmetric Pause bit */
1747 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1748 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1749 | PHY_M_AN_ASP);
1750 }
1751
1752 netif_carrier_off(sky2->netdev);
1753 netif_stop_queue(sky2->netdev);
1754
1755 /* Turn on link LED */
1756 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1757
1758 if (netif_msg_link(sky2))
1759 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1760
1761 sky2_phy_init(hw, port);
1762 }
1763
1764 static enum flow_control sky2_flow(int rx, int tx)
1765 {
1766 if (rx)
1767 return tx ? FC_BOTH : FC_RX;
1768 else
1769 return tx ? FC_TX : FC_NONE;
1770 }
1771
1772 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1773 {
1774 struct sky2_hw *hw = sky2->hw;
1775 unsigned port = sky2->port;
1776 u16 lpa;
1777
1778 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1779
1780 if (lpa & PHY_M_AN_RF) {
1781 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1782 return -1;
1783 }
1784
1785 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1786 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1787 sky2->netdev->name);
1788 return -1;
1789 }
1790
1791 sky2->speed = sky2_phy_speed(hw, aux);
1792 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1793
1794 /* Pause bits are offset (9..8) */
1795 if (hw->chip_id == CHIP_ID_YUKON_XL
1796 || hw->chip_id == CHIP_ID_YUKON_EC_U
1797 || hw->chip_id == CHIP_ID_YUKON_EX)
1798 aux >>= 6;
1799
1800 sky2->flow_status = sky2_flow(aux & PHY_M_PS_RX_P_EN,
1801 aux & PHY_M_PS_TX_P_EN);
1802
1803 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1804 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1805 sky2->flow_status = FC_NONE;
1806
1807 if (aux & PHY_M_PS_RX_P_EN)
1808 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1809 else
1810 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1811
1812 return 0;
1813 }
1814
1815 /* Interrupt from PHY */
1816 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1817 {
1818 struct net_device *dev = hw->dev[port];
1819 struct sky2_port *sky2 = netdev_priv(dev);
1820 u16 istatus, phystat;
1821
1822 if (!netif_running(dev))
1823 return;
1824
1825 spin_lock(&sky2->phy_lock);
1826 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1827 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1828
1829 if (netif_msg_intr(sky2))
1830 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1831 sky2->netdev->name, istatus, phystat);
1832
1833 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1834 if (sky2_autoneg_done(sky2, phystat) == 0)
1835 sky2_link_up(sky2);
1836 goto out;
1837 }
1838
1839 if (istatus & PHY_M_IS_LSP_CHANGE)
1840 sky2->speed = sky2_phy_speed(hw, phystat);
1841
1842 if (istatus & PHY_M_IS_DUP_CHANGE)
1843 sky2->duplex =
1844 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1845
1846 if (istatus & PHY_M_IS_LST_CHANGE) {
1847 if (phystat & PHY_M_PS_LINK_UP)
1848 sky2_link_up(sky2);
1849 else
1850 sky2_link_down(sky2);
1851 }
1852 out:
1853 spin_unlock(&sky2->phy_lock);
1854 }
1855
1856
1857 /* Transmit timeout is only called if we are running, carrier is up
1858 * and tx queue is full (stopped).
1859 * Called with netif_tx_lock held.
1860 */
1861 static void sky2_tx_timeout(struct net_device *dev)
1862 {
1863 struct sky2_port *sky2 = netdev_priv(dev);
1864 struct sky2_hw *hw = sky2->hw;
1865 u32 imask;
1866
1867 if (netif_msg_timer(sky2))
1868 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1869
1870 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1871 dev->name, sky2->tx_cons, sky2->tx_prod,
1872 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1873 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1874
1875 imask = sky2_read32(hw, B0_IMSK); /* block IRQ in hw */
1876 sky2_write32(hw, B0_IMSK, 0);
1877 sky2_read32(hw, B0_IMSK);
1878
1879 netif_poll_disable(hw->dev[0]); /* stop NAPI poll */
1880 synchronize_irq(hw->pdev->irq);
1881
1882 netif_start_queue(dev); /* don't wakeup during flush */
1883 sky2_tx_complete(sky2, sky2->tx_prod); /* Flush transmit queue */
1884
1885 sky2_write32(hw, B0_IMSK, imask);
1886
1887 sky2_phy_reinit(sky2); /* this clears flow control etc */
1888 }
1889
1890 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1891 {
1892 struct sky2_port *sky2 = netdev_priv(dev);
1893 struct sky2_hw *hw = sky2->hw;
1894 int err;
1895 u16 ctl, mode;
1896 u32 imask;
1897
1898 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1899 return -EINVAL;
1900
1901 /* TSO on Yukon Ultra and MTU > 1500 not supported */
1902 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1903 dev->features &= ~NETIF_F_TSO;
1904
1905 if (!netif_running(dev)) {
1906 dev->mtu = new_mtu;
1907 return 0;
1908 }
1909
1910 imask = sky2_read32(hw, B0_IMSK);
1911 sky2_write32(hw, B0_IMSK, 0);
1912
1913 dev->trans_start = jiffies; /* prevent tx timeout */
1914 netif_stop_queue(dev);
1915 netif_poll_disable(hw->dev[0]);
1916
1917 synchronize_irq(hw->pdev->irq);
1918
1919 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1920 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1921 sky2_rx_stop(sky2);
1922 sky2_rx_clean(sky2);
1923
1924 dev->mtu = new_mtu;
1925
1926 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1927 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1928
1929 if (dev->mtu > ETH_DATA_LEN)
1930 mode |= GM_SMOD_JUMBO_ENA;
1931
1932 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1933
1934 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1935
1936 err = sky2_rx_start(sky2);
1937 sky2_write32(hw, B0_IMSK, imask);
1938
1939 if (err)
1940 dev_close(dev);
1941 else {
1942 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1943
1944 netif_poll_enable(hw->dev[0]);
1945 netif_wake_queue(dev);
1946 }
1947
1948 return err;
1949 }
1950
1951 /* For small just reuse existing skb for next receive */
1952 static struct sk_buff *receive_copy(struct sky2_port *sky2,
1953 const struct rx_ring_info *re,
1954 unsigned length)
1955 {
1956 struct sk_buff *skb;
1957
1958 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1959 if (likely(skb)) {
1960 skb_reserve(skb, 2);
1961 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1962 length, PCI_DMA_FROMDEVICE);
1963 memcpy(skb->data, re->skb->data, length);
1964 skb->ip_summed = re->skb->ip_summed;
1965 skb->csum = re->skb->csum;
1966 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1967 length, PCI_DMA_FROMDEVICE);
1968 re->skb->ip_summed = CHECKSUM_NONE;
1969 skb_put(skb, length);
1970 }
1971 return skb;
1972 }
1973
1974 /* Adjust length of skb with fragments to match received data */
1975 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1976 unsigned int length)
1977 {
1978 int i, num_frags;
1979 unsigned int size;
1980
1981 /* put header into skb */
1982 size = min(length, hdr_space);
1983 skb->tail += size;
1984 skb->len += size;
1985 length -= size;
1986
1987 num_frags = skb_shinfo(skb)->nr_frags;
1988 for (i = 0; i < num_frags; i++) {
1989 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1990
1991 if (length == 0) {
1992 /* don't need this page */
1993 __free_page(frag->page);
1994 --skb_shinfo(skb)->nr_frags;
1995 } else {
1996 size = min(length, (unsigned) PAGE_SIZE);
1997
1998 frag->size = size;
1999 skb->data_len += size;
2000 skb->truesize += size;
2001 skb->len += size;
2002 length -= size;
2003 }
2004 }
2005 }
2006
2007 /* Normal packet - take skb from ring element and put in a new one */
2008 static struct sk_buff *receive_new(struct sky2_port *sky2,
2009 struct rx_ring_info *re,
2010 unsigned int length)
2011 {
2012 struct sk_buff *skb, *nskb;
2013 unsigned hdr_space = sky2->rx_data_size;
2014
2015 pr_debug(PFX "receive new length=%d\n", length);
2016
2017 /* Don't be tricky about reusing pages (yet) */
2018 nskb = sky2_rx_alloc(sky2);
2019 if (unlikely(!nskb))
2020 return NULL;
2021
2022 skb = re->skb;
2023 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2024
2025 prefetch(skb->data);
2026 re->skb = nskb;
2027 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2028
2029 if (skb_shinfo(skb)->nr_frags)
2030 skb_put_frags(skb, hdr_space, length);
2031 else
2032 skb_put(skb, length);
2033 return skb;
2034 }
2035
2036 /*
2037 * Receive one packet.
2038 * For larger packets, get new buffer.
2039 */
2040 static struct sk_buff *sky2_receive(struct net_device *dev,
2041 u16 length, u32 status)
2042 {
2043 struct sky2_port *sky2 = netdev_priv(dev);
2044 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2045 struct sk_buff *skb = NULL;
2046
2047 if (unlikely(netif_msg_rx_status(sky2)))
2048 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2049 dev->name, sky2->rx_next, status, length);
2050
2051 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2052 prefetch(sky2->rx_ring + sky2->rx_next);
2053
2054 if (status & GMR_FS_ANY_ERR)
2055 goto error;
2056
2057 if (!(status & GMR_FS_RX_OK))
2058 goto resubmit;
2059
2060 if (length > dev->mtu + ETH_HLEN)
2061 goto oversize;
2062
2063 if (length < copybreak)
2064 skb = receive_copy(sky2, re, length);
2065 else
2066 skb = receive_new(sky2, re, length);
2067 resubmit:
2068 sky2_rx_submit(sky2, re);
2069
2070 return skb;
2071
2072 oversize:
2073 ++sky2->net_stats.rx_over_errors;
2074 goto resubmit;
2075
2076 error:
2077 ++sky2->net_stats.rx_errors;
2078 if (status & GMR_FS_RX_FF_OV) {
2079 sky2->net_stats.rx_fifo_errors++;
2080 goto resubmit;
2081 }
2082
2083 if (netif_msg_rx_err(sky2) && net_ratelimit())
2084 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2085 dev->name, status, length);
2086
2087 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2088 sky2->net_stats.rx_length_errors++;
2089 if (status & GMR_FS_FRAGMENT)
2090 sky2->net_stats.rx_frame_errors++;
2091 if (status & GMR_FS_CRC_ERR)
2092 sky2->net_stats.rx_crc_errors++;
2093
2094 goto resubmit;
2095 }
2096
2097 /* Transmit complete */
2098 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2099 {
2100 struct sky2_port *sky2 = netdev_priv(dev);
2101
2102 if (netif_running(dev)) {
2103 netif_tx_lock(dev);
2104 sky2_tx_complete(sky2, last);
2105 netif_tx_unlock(dev);
2106 }
2107 }
2108
2109 /* Process status response ring */
2110 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2111 {
2112 struct sky2_port *sky2;
2113 int work_done = 0;
2114 unsigned buf_write[2] = { 0, 0 };
2115 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
2116
2117 rmb();
2118
2119 while (hw->st_idx != hwidx) {
2120 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2121 struct net_device *dev;
2122 struct sk_buff *skb;
2123 u32 status;
2124 u16 length;
2125
2126 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2127
2128 BUG_ON(le->link >= 2);
2129 dev = hw->dev[le->link];
2130
2131 sky2 = netdev_priv(dev);
2132 length = le16_to_cpu(le->length);
2133 status = le32_to_cpu(le->status);
2134
2135 switch (le->opcode & ~HW_OWNER) {
2136 case OP_RXSTAT:
2137 skb = sky2_receive(dev, length, status);
2138 if (!skb)
2139 goto force_update;
2140
2141 skb->protocol = eth_type_trans(skb, dev);
2142 sky2->net_stats.rx_packets++;
2143 sky2->net_stats.rx_bytes += skb->len;
2144 dev->last_rx = jiffies;
2145
2146 #ifdef SKY2_VLAN_TAG_USED
2147 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2148 vlan_hwaccel_receive_skb(skb,
2149 sky2->vlgrp,
2150 be16_to_cpu(sky2->rx_tag));
2151 } else
2152 #endif
2153 netif_receive_skb(skb);
2154
2155 /* Update receiver after 16 frames */
2156 if (++buf_write[le->link] == RX_BUF_WRITE) {
2157 force_update:
2158 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
2159 buf_write[le->link] = 0;
2160 }
2161
2162 /* Stop after net poll weight */
2163 if (++work_done >= to_do)
2164 goto exit_loop;
2165 break;
2166
2167 #ifdef SKY2_VLAN_TAG_USED
2168 case OP_RXVLAN:
2169 sky2->rx_tag = length;
2170 break;
2171
2172 case OP_RXCHKSVLAN:
2173 sky2->rx_tag = length;
2174 /* fall through */
2175 #endif
2176 case OP_RXCHKS:
2177 skb = sky2->rx_ring[sky2->rx_next].skb;
2178 skb->ip_summed = CHECKSUM_COMPLETE;
2179 skb->csum = status & 0xffff;
2180 break;
2181
2182 case OP_TXINDEXLE:
2183 /* TX index reports status for both ports */
2184 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2185 sky2_tx_done(hw->dev[0], status & 0xfff);
2186 if (hw->dev[1])
2187 sky2_tx_done(hw->dev[1],
2188 ((status >> 24) & 0xff)
2189 | (u16)(length & 0xf) << 8);
2190 break;
2191
2192 default:
2193 if (net_ratelimit())
2194 printk(KERN_WARNING PFX
2195 "unknown status opcode 0x%x\n", le->opcode);
2196 goto exit_loop;
2197 }
2198 }
2199
2200 /* Fully processed status ring so clear irq */
2201 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2202
2203 exit_loop:
2204 if (buf_write[0]) {
2205 sky2 = netdev_priv(hw->dev[0]);
2206 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2207 }
2208
2209 if (buf_write[1]) {
2210 sky2 = netdev_priv(hw->dev[1]);
2211 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2212 }
2213
2214 return work_done;
2215 }
2216
2217 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2218 {
2219 struct net_device *dev = hw->dev[port];
2220
2221 if (net_ratelimit())
2222 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2223 dev->name, status);
2224
2225 if (status & Y2_IS_PAR_RD1) {
2226 if (net_ratelimit())
2227 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2228 dev->name);
2229 /* Clear IRQ */
2230 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2231 }
2232
2233 if (status & Y2_IS_PAR_WR1) {
2234 if (net_ratelimit())
2235 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2236 dev->name);
2237
2238 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2239 }
2240
2241 if (status & Y2_IS_PAR_MAC1) {
2242 if (net_ratelimit())
2243 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2244 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2245 }
2246
2247 if (status & Y2_IS_PAR_RX1) {
2248 if (net_ratelimit())
2249 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2250 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2251 }
2252
2253 if (status & Y2_IS_TCP_TXA1) {
2254 if (net_ratelimit())
2255 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2256 dev->name);
2257 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2258 }
2259 }
2260
2261 static void sky2_hw_intr(struct sky2_hw *hw)
2262 {
2263 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2264
2265 if (status & Y2_IS_TIST_OV)
2266 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2267
2268 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2269 u16 pci_err;
2270
2271 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2272 if (net_ratelimit())
2273 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2274 pci_err);
2275
2276 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2277 sky2_pci_write16(hw, PCI_STATUS,
2278 pci_err | PCI_STATUS_ERROR_BITS);
2279 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2280 }
2281
2282 if (status & Y2_IS_PCI_EXP) {
2283 /* PCI-Express uncorrectable Error occurred */
2284 u32 pex_err;
2285
2286 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2287
2288 if (net_ratelimit())
2289 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2290 pex_err);
2291
2292 /* clear the interrupt */
2293 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2294 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2295 0xffffffffUL);
2296 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2297
2298 if (pex_err & PEX_FATAL_ERRORS) {
2299 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2300 hwmsk &= ~Y2_IS_PCI_EXP;
2301 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2302 }
2303 }
2304
2305 if (status & Y2_HWE_L1_MASK)
2306 sky2_hw_error(hw, 0, status);
2307 status >>= 8;
2308 if (status & Y2_HWE_L1_MASK)
2309 sky2_hw_error(hw, 1, status);
2310 }
2311
2312 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2313 {
2314 struct net_device *dev = hw->dev[port];
2315 struct sky2_port *sky2 = netdev_priv(dev);
2316 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2317
2318 if (netif_msg_intr(sky2))
2319 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2320 dev->name, status);
2321
2322 if (status & GM_IS_RX_FF_OR) {
2323 ++sky2->net_stats.rx_fifo_errors;
2324 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2325 }
2326
2327 if (status & GM_IS_TX_FF_UR) {
2328 ++sky2->net_stats.tx_fifo_errors;
2329 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2330 }
2331 }
2332
2333 /* This should never happen it is a fatal situation */
2334 static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2335 const char *rxtx, u32 mask)
2336 {
2337 struct net_device *dev = hw->dev[port];
2338 struct sky2_port *sky2 = netdev_priv(dev);
2339 u32 imask;
2340
2341 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2342 dev ? dev->name : "<not registered>", rxtx);
2343
2344 imask = sky2_read32(hw, B0_IMSK);
2345 imask &= ~mask;
2346 sky2_write32(hw, B0_IMSK, imask);
2347
2348 if (dev) {
2349 spin_lock(&sky2->phy_lock);
2350 sky2_link_down(sky2);
2351 spin_unlock(&sky2->phy_lock);
2352 }
2353 }
2354
2355 /* If idle then force a fake soft NAPI poll once a second
2356 * to work around cases where sharing an edge triggered interrupt.
2357 */
2358 static inline void sky2_idle_start(struct sky2_hw *hw)
2359 {
2360 if (idle_timeout > 0)
2361 mod_timer(&hw->idle_timer,
2362 jiffies + msecs_to_jiffies(idle_timeout));
2363 }
2364
2365 static void sky2_idle(unsigned long arg)
2366 {
2367 struct sky2_hw *hw = (struct sky2_hw *) arg;
2368 struct net_device *dev = hw->dev[0];
2369
2370 if (__netif_rx_schedule_prep(dev))
2371 __netif_rx_schedule(dev);
2372
2373 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
2374 }
2375
2376
2377 static int sky2_poll(struct net_device *dev0, int *budget)
2378 {
2379 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2380 int work_limit = min(dev0->quota, *budget);
2381 int work_done = 0;
2382 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2383
2384 if (status & Y2_IS_HW_ERR)
2385 sky2_hw_intr(hw);
2386
2387 if (status & Y2_IS_IRQ_PHY1)
2388 sky2_phy_intr(hw, 0);
2389
2390 if (status & Y2_IS_IRQ_PHY2)
2391 sky2_phy_intr(hw, 1);
2392
2393 if (status & Y2_IS_IRQ_MAC1)
2394 sky2_mac_intr(hw, 0);
2395
2396 if (status & Y2_IS_IRQ_MAC2)
2397 sky2_mac_intr(hw, 1);
2398
2399 if (status & Y2_IS_CHK_RX1)
2400 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
2401
2402 if (status & Y2_IS_CHK_RX2)
2403 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
2404
2405 if (status & Y2_IS_CHK_TXA1)
2406 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
2407
2408 if (status & Y2_IS_CHK_TXA2)
2409 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
2410
2411 work_done = sky2_status_intr(hw, work_limit);
2412 if (work_done < work_limit) {
2413 netif_rx_complete(dev0);
2414
2415 sky2_read32(hw, B0_Y2_SP_LISR);
2416 return 0;
2417 } else {
2418 *budget -= work_done;
2419 dev0->quota -= work_done;
2420 return 1;
2421 }
2422 }
2423
2424 static irqreturn_t sky2_intr(int irq, void *dev_id)
2425 {
2426 struct sky2_hw *hw = dev_id;
2427 struct net_device *dev0 = hw->dev[0];
2428 u32 status;
2429
2430 /* Reading this mask interrupts as side effect */
2431 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2432 if (status == 0 || status == ~0)
2433 return IRQ_NONE;
2434
2435 prefetch(&hw->st_le[hw->st_idx]);
2436 if (likely(__netif_rx_schedule_prep(dev0)))
2437 __netif_rx_schedule(dev0);
2438
2439 return IRQ_HANDLED;
2440 }
2441
2442 #ifdef CONFIG_NET_POLL_CONTROLLER
2443 static void sky2_netpoll(struct net_device *dev)
2444 {
2445 struct sky2_port *sky2 = netdev_priv(dev);
2446 struct net_device *dev0 = sky2->hw->dev[0];
2447
2448 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2449 __netif_rx_schedule(dev0);
2450 }
2451 #endif
2452
2453 /* Chip internal frequency for clock calculations */
2454 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2455 {
2456 switch (hw->chip_id) {
2457 case CHIP_ID_YUKON_EC:
2458 case CHIP_ID_YUKON_EC_U:
2459 case CHIP_ID_YUKON_EX:
2460 return 125; /* 125 Mhz */
2461 case CHIP_ID_YUKON_FE:
2462 return 100; /* 100 Mhz */
2463 default: /* YUKON_XL */
2464 return 156; /* 156 Mhz */
2465 }
2466 }
2467
2468 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2469 {
2470 return sky2_mhz(hw) * us;
2471 }
2472
2473 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2474 {
2475 return clk / sky2_mhz(hw);
2476 }
2477
2478
2479 static int __devinit sky2_init(struct sky2_hw *hw)
2480 {
2481 u8 t8;
2482
2483 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2484
2485 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2486 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2487 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2488 hw->chip_id);
2489 return -EOPNOTSUPP;
2490 }
2491
2492 if (hw->chip_id == CHIP_ID_YUKON_EX)
2493 dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n"
2494 "Please report success or failure to <netdev@vger.kernel.org>\n");
2495
2496 /* Make sure and enable all clocks */
2497 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
2498 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2499
2500 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2501
2502 /* This rev is really old, and requires untested workarounds */
2503 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2504 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2505 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2506 hw->chip_id, hw->chip_rev);
2507 return -EOPNOTSUPP;
2508 }
2509
2510 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2511 hw->ports = 1;
2512 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2513 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2514 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2515 ++hw->ports;
2516 }
2517
2518 return 0;
2519 }
2520
2521 static void sky2_reset(struct sky2_hw *hw)
2522 {
2523 u16 status;
2524 int i;
2525
2526 /* disable ASF */
2527 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2528 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2529 status = sky2_read16(hw, HCU_CCSR);
2530 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2531 HCU_CCSR_UC_STATE_MSK);
2532 sky2_write16(hw, HCU_CCSR, status);
2533 } else
2534 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2535 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2536 }
2537
2538 /* do a SW reset */
2539 sky2_write8(hw, B0_CTST, CS_RST_SET);
2540 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2541
2542 /* clear PCI errors, if any */
2543 status = sky2_pci_read16(hw, PCI_STATUS);
2544
2545 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2546 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2547
2548
2549 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2550
2551 /* clear any PEX errors */
2552 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2553 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2554
2555
2556 sky2_power_on(hw);
2557
2558 for (i = 0; i < hw->ports; i++) {
2559 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2560 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2561 }
2562
2563 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2564
2565 /* Clear I2C IRQ noise */
2566 sky2_write32(hw, B2_I2C_IRQ, 1);
2567
2568 /* turn off hardware timer (unused) */
2569 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2570 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2571
2572 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2573
2574 /* Turn off descriptor polling */
2575 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2576
2577 /* Turn off receive timestamp */
2578 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2579 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2580
2581 /* enable the Tx Arbiters */
2582 for (i = 0; i < hw->ports; i++)
2583 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2584
2585 /* Initialize ram interface */
2586 for (i = 0; i < hw->ports; i++) {
2587 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2588
2589 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2590 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2591 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2592 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2593 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2594 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2595 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2596 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2597 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2598 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2599 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2600 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2601 }
2602
2603 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2604
2605 for (i = 0; i < hw->ports; i++)
2606 sky2_gmac_reset(hw, i);
2607
2608 memset(hw->st_le, 0, STATUS_LE_BYTES);
2609 hw->st_idx = 0;
2610
2611 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2612 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2613
2614 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2615 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2616
2617 /* Set the list last index */
2618 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2619
2620 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2621 sky2_write8(hw, STAT_FIFO_WM, 16);
2622
2623 /* set Status-FIFO ISR watermark */
2624 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2625 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2626 else
2627 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2628
2629 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2630 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2631 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2632
2633 /* enable status unit */
2634 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2635
2636 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2637 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2638 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2639 }
2640
2641 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2642 {
2643 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2644 }
2645
2646 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2647 {
2648 const struct sky2_port *sky2 = netdev_priv(dev);
2649
2650 wol->supported = sky2_wol_supported(sky2->hw);
2651 wol->wolopts = sky2->wol;
2652 }
2653
2654 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2655 {
2656 struct sky2_port *sky2 = netdev_priv(dev);
2657 struct sky2_hw *hw = sky2->hw;
2658
2659 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2660 return -EOPNOTSUPP;
2661
2662 sky2->wol = wol->wolopts;
2663
2664 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
2665 sky2_write32(hw, B0_CTST, sky2->wol
2666 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2667
2668 if (!netif_running(dev))
2669 sky2_wol_init(sky2);
2670 return 0;
2671 }
2672
2673 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2674 {
2675 if (sky2_is_copper(hw)) {
2676 u32 modes = SUPPORTED_10baseT_Half
2677 | SUPPORTED_10baseT_Full
2678 | SUPPORTED_100baseT_Half
2679 | SUPPORTED_100baseT_Full
2680 | SUPPORTED_Autoneg | SUPPORTED_TP;
2681
2682 if (hw->chip_id != CHIP_ID_YUKON_FE)
2683 modes |= SUPPORTED_1000baseT_Half
2684 | SUPPORTED_1000baseT_Full;
2685 return modes;
2686 } else
2687 return SUPPORTED_1000baseT_Half
2688 | SUPPORTED_1000baseT_Full
2689 | SUPPORTED_Autoneg
2690 | SUPPORTED_FIBRE;
2691 }
2692
2693 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2694 {
2695 struct sky2_port *sky2 = netdev_priv(dev);
2696 struct sky2_hw *hw = sky2->hw;
2697
2698 ecmd->transceiver = XCVR_INTERNAL;
2699 ecmd->supported = sky2_supported_modes(hw);
2700 ecmd->phy_address = PHY_ADDR_MARV;
2701 if (sky2_is_copper(hw)) {
2702 ecmd->supported = SUPPORTED_10baseT_Half
2703 | SUPPORTED_10baseT_Full
2704 | SUPPORTED_100baseT_Half
2705 | SUPPORTED_100baseT_Full
2706 | SUPPORTED_1000baseT_Half
2707 | SUPPORTED_1000baseT_Full
2708 | SUPPORTED_Autoneg | SUPPORTED_TP;
2709 ecmd->port = PORT_TP;
2710 ecmd->speed = sky2->speed;
2711 } else {
2712 ecmd->speed = SPEED_1000;
2713 ecmd->port = PORT_FIBRE;
2714 }
2715
2716 ecmd->advertising = sky2->advertising;
2717 ecmd->autoneg = sky2->autoneg;
2718 ecmd->duplex = sky2->duplex;
2719 return 0;
2720 }
2721
2722 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2723 {
2724 struct sky2_port *sky2 = netdev_priv(dev);
2725 const struct sky2_hw *hw = sky2->hw;
2726 u32 supported = sky2_supported_modes(hw);
2727
2728 if (ecmd->autoneg == AUTONEG_ENABLE) {
2729 ecmd->advertising = supported;
2730 sky2->duplex = -1;
2731 sky2->speed = -1;
2732 } else {
2733 u32 setting;
2734
2735 switch (ecmd->speed) {
2736 case SPEED_1000:
2737 if (ecmd->duplex == DUPLEX_FULL)
2738 setting = SUPPORTED_1000baseT_Full;
2739 else if (ecmd->duplex == DUPLEX_HALF)
2740 setting = SUPPORTED_1000baseT_Half;
2741 else
2742 return -EINVAL;
2743 break;
2744 case SPEED_100:
2745 if (ecmd->duplex == DUPLEX_FULL)
2746 setting = SUPPORTED_100baseT_Full;
2747 else if (ecmd->duplex == DUPLEX_HALF)
2748 setting = SUPPORTED_100baseT_Half;
2749 else
2750 return -EINVAL;
2751 break;
2752
2753 case SPEED_10:
2754 if (ecmd->duplex == DUPLEX_FULL)
2755 setting = SUPPORTED_10baseT_Full;
2756 else if (ecmd->duplex == DUPLEX_HALF)
2757 setting = SUPPORTED_10baseT_Half;
2758 else
2759 return -EINVAL;
2760 break;
2761 default:
2762 return -EINVAL;
2763 }
2764
2765 if ((setting & supported) == 0)
2766 return -EINVAL;
2767
2768 sky2->speed = ecmd->speed;
2769 sky2->duplex = ecmd->duplex;
2770 }
2771
2772 sky2->autoneg = ecmd->autoneg;
2773 sky2->advertising = ecmd->advertising;
2774
2775 if (netif_running(dev))
2776 sky2_phy_reinit(sky2);
2777
2778 return 0;
2779 }
2780
2781 static void sky2_get_drvinfo(struct net_device *dev,
2782 struct ethtool_drvinfo *info)
2783 {
2784 struct sky2_port *sky2 = netdev_priv(dev);
2785
2786 strcpy(info->driver, DRV_NAME);
2787 strcpy(info->version, DRV_VERSION);
2788 strcpy(info->fw_version, "N/A");
2789 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2790 }
2791
2792 static const struct sky2_stat {
2793 char name[ETH_GSTRING_LEN];
2794 u16 offset;
2795 } sky2_stats[] = {
2796 { "tx_bytes", GM_TXO_OK_HI },
2797 { "rx_bytes", GM_RXO_OK_HI },
2798 { "tx_broadcast", GM_TXF_BC_OK },
2799 { "rx_broadcast", GM_RXF_BC_OK },
2800 { "tx_multicast", GM_TXF_MC_OK },
2801 { "rx_multicast", GM_RXF_MC_OK },
2802 { "tx_unicast", GM_TXF_UC_OK },
2803 { "rx_unicast", GM_RXF_UC_OK },
2804 { "tx_mac_pause", GM_TXF_MPAUSE },
2805 { "rx_mac_pause", GM_RXF_MPAUSE },
2806 { "collisions", GM_TXF_COL },
2807 { "late_collision",GM_TXF_LAT_COL },
2808 { "aborted", GM_TXF_ABO_COL },
2809 { "single_collisions", GM_TXF_SNG_COL },
2810 { "multi_collisions", GM_TXF_MUL_COL },
2811
2812 { "rx_short", GM_RXF_SHT },
2813 { "rx_runt", GM_RXE_FRAG },
2814 { "rx_64_byte_packets", GM_RXF_64B },
2815 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2816 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2817 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2818 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2819 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2820 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2821 { "rx_too_long", GM_RXF_LNG_ERR },
2822 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2823 { "rx_jabber", GM_RXF_JAB_PKT },
2824 { "rx_fcs_error", GM_RXF_FCS_ERR },
2825
2826 { "tx_64_byte_packets", GM_TXF_64B },
2827 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2828 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2829 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2830 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2831 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2832 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2833 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2834 };
2835
2836 static u32 sky2_get_rx_csum(struct net_device *dev)
2837 {
2838 struct sky2_port *sky2 = netdev_priv(dev);
2839
2840 return sky2->rx_csum;
2841 }
2842
2843 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2844 {
2845 struct sky2_port *sky2 = netdev_priv(dev);
2846
2847 sky2->rx_csum = data;
2848
2849 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2850 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2851
2852 return 0;
2853 }
2854
2855 static u32 sky2_get_msglevel(struct net_device *netdev)
2856 {
2857 struct sky2_port *sky2 = netdev_priv(netdev);
2858 return sky2->msg_enable;
2859 }
2860
2861 static int sky2_nway_reset(struct net_device *dev)
2862 {
2863 struct sky2_port *sky2 = netdev_priv(dev);
2864
2865 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
2866 return -EINVAL;
2867
2868 sky2_phy_reinit(sky2);
2869
2870 return 0;
2871 }
2872
2873 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2874 {
2875 struct sky2_hw *hw = sky2->hw;
2876 unsigned port = sky2->port;
2877 int i;
2878
2879 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2880 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2881 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2882 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2883
2884 for (i = 2; i < count; i++)
2885 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2886 }
2887
2888 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2889 {
2890 struct sky2_port *sky2 = netdev_priv(netdev);
2891 sky2->msg_enable = value;
2892 }
2893
2894 static int sky2_get_stats_count(struct net_device *dev)
2895 {
2896 return ARRAY_SIZE(sky2_stats);
2897 }
2898
2899 static void sky2_get_ethtool_stats(struct net_device *dev,
2900 struct ethtool_stats *stats, u64 * data)
2901 {
2902 struct sky2_port *sky2 = netdev_priv(dev);
2903
2904 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2905 }
2906
2907 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2908 {
2909 int i;
2910
2911 switch (stringset) {
2912 case ETH_SS_STATS:
2913 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2914 memcpy(data + i * ETH_GSTRING_LEN,
2915 sky2_stats[i].name, ETH_GSTRING_LEN);
2916 break;
2917 }
2918 }
2919
2920 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2921 {
2922 struct sky2_port *sky2 = netdev_priv(dev);
2923 return &sky2->net_stats;
2924 }
2925
2926 static int sky2_set_mac_address(struct net_device *dev, void *p)
2927 {
2928 struct sky2_port *sky2 = netdev_priv(dev);
2929 struct sky2_hw *hw = sky2->hw;
2930 unsigned port = sky2->port;
2931 const struct sockaddr *addr = p;
2932
2933 if (!is_valid_ether_addr(addr->sa_data))
2934 return -EADDRNOTAVAIL;
2935
2936 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2937 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2938 dev->dev_addr, ETH_ALEN);
2939 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2940 dev->dev_addr, ETH_ALEN);
2941
2942 /* virtual address for data */
2943 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2944
2945 /* physical address: used for pause frames */
2946 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2947
2948 return 0;
2949 }
2950
2951 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
2952 {
2953 u32 bit;
2954
2955 bit = ether_crc(ETH_ALEN, addr) & 63;
2956 filter[bit >> 3] |= 1 << (bit & 7);
2957 }
2958
2959 static void sky2_set_multicast(struct net_device *dev)
2960 {
2961 struct sky2_port *sky2 = netdev_priv(dev);
2962 struct sky2_hw *hw = sky2->hw;
2963 unsigned port = sky2->port;
2964 struct dev_mc_list *list = dev->mc_list;
2965 u16 reg;
2966 u8 filter[8];
2967 int rx_pause;
2968 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2969
2970 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
2971 memset(filter, 0, sizeof(filter));
2972
2973 reg = gma_read16(hw, port, GM_RX_CTRL);
2974 reg |= GM_RXCR_UCF_ENA;
2975
2976 if (dev->flags & IFF_PROMISC) /* promiscuous */
2977 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2978 else if (dev->flags & IFF_ALLMULTI)
2979 memset(filter, 0xff, sizeof(filter));
2980 else if (dev->mc_count == 0 && !rx_pause)
2981 reg &= ~GM_RXCR_MCF_ENA;
2982 else {
2983 int i;
2984 reg |= GM_RXCR_MCF_ENA;
2985
2986 if (rx_pause)
2987 sky2_add_filter(filter, pause_mc_addr);
2988
2989 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2990 sky2_add_filter(filter, list->dmi_addr);
2991 }
2992
2993 gma_write16(hw, port, GM_MC_ADDR_H1,
2994 (u16) filter[0] | ((u16) filter[1] << 8));
2995 gma_write16(hw, port, GM_MC_ADDR_H2,
2996 (u16) filter[2] | ((u16) filter[3] << 8));
2997 gma_write16(hw, port, GM_MC_ADDR_H3,
2998 (u16) filter[4] | ((u16) filter[5] << 8));
2999 gma_write16(hw, port, GM_MC_ADDR_H4,
3000 (u16) filter[6] | ((u16) filter[7] << 8));
3001
3002 gma_write16(hw, port, GM_RX_CTRL, reg);
3003 }
3004
3005 /* Can have one global because blinking is controlled by
3006 * ethtool and that is always under RTNL mutex
3007 */
3008 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3009 {
3010 u16 pg;
3011
3012 switch (hw->chip_id) {
3013 case CHIP_ID_YUKON_XL:
3014 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3015 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3016 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3017 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3018 PHY_M_LEDC_INIT_CTRL(7) |
3019 PHY_M_LEDC_STA1_CTRL(7) |
3020 PHY_M_LEDC_STA0_CTRL(7))
3021 : 0);
3022
3023 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3024 break;
3025
3026 default:
3027 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3028 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3029 on ? PHY_M_LED_ALL : 0);
3030 }
3031 }
3032
3033 /* blink LED's for finding board */
3034 static int sky2_phys_id(struct net_device *dev, u32 data)
3035 {
3036 struct sky2_port *sky2 = netdev_priv(dev);
3037 struct sky2_hw *hw = sky2->hw;
3038 unsigned port = sky2->port;
3039 u16 ledctrl, ledover = 0;
3040 long ms;
3041 int interrupted;
3042 int onoff = 1;
3043
3044 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3045 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3046 else
3047 ms = data * 1000;
3048
3049 /* save initial values */
3050 spin_lock_bh(&sky2->phy_lock);
3051 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3052 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3053 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3054 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3055 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3056 } else {
3057 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3058 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3059 }
3060
3061 interrupted = 0;
3062 while (!interrupted && ms > 0) {
3063 sky2_led(hw, port, onoff);
3064 onoff = !onoff;
3065
3066 spin_unlock_bh(&sky2->phy_lock);
3067 interrupted = msleep_interruptible(250);
3068 spin_lock_bh(&sky2->phy_lock);
3069
3070 ms -= 250;
3071 }
3072
3073 /* resume regularly scheduled programming */
3074 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3075 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3076 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3077 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3078 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3079 } else {
3080 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3081 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3082 }
3083 spin_unlock_bh(&sky2->phy_lock);
3084
3085 return 0;
3086 }
3087
3088 static void sky2_get_pauseparam(struct net_device *dev,
3089 struct ethtool_pauseparam *ecmd)
3090 {
3091 struct sky2_port *sky2 = netdev_priv(dev);
3092
3093 switch (sky2->flow_mode) {
3094 case FC_NONE:
3095 ecmd->tx_pause = ecmd->rx_pause = 0;
3096 break;
3097 case FC_TX:
3098 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3099 break;
3100 case FC_RX:
3101 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3102 break;
3103 case FC_BOTH:
3104 ecmd->tx_pause = ecmd->rx_pause = 1;
3105 }
3106
3107 ecmd->autoneg = sky2->autoneg;
3108 }
3109
3110 static int sky2_set_pauseparam(struct net_device *dev,
3111 struct ethtool_pauseparam *ecmd)
3112 {
3113 struct sky2_port *sky2 = netdev_priv(dev);
3114
3115 sky2->autoneg = ecmd->autoneg;
3116 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3117
3118 if (netif_running(dev))
3119 sky2_phy_reinit(sky2);
3120
3121 return 0;
3122 }
3123
3124 static int sky2_get_coalesce(struct net_device *dev,
3125 struct ethtool_coalesce *ecmd)
3126 {
3127 struct sky2_port *sky2 = netdev_priv(dev);
3128 struct sky2_hw *hw = sky2->hw;
3129
3130 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3131 ecmd->tx_coalesce_usecs = 0;
3132 else {
3133 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3134 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3135 }
3136 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3137
3138 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3139 ecmd->rx_coalesce_usecs = 0;
3140 else {
3141 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3142 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3143 }
3144 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3145
3146 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3147 ecmd->rx_coalesce_usecs_irq = 0;
3148 else {
3149 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3150 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3151 }
3152
3153 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3154
3155 return 0;
3156 }
3157
3158 /* Note: this affect both ports */
3159 static int sky2_set_coalesce(struct net_device *dev,
3160 struct ethtool_coalesce *ecmd)
3161 {
3162 struct sky2_port *sky2 = netdev_priv(dev);
3163 struct sky2_hw *hw = sky2->hw;
3164 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3165
3166 if (ecmd->tx_coalesce_usecs > tmax ||
3167 ecmd->rx_coalesce_usecs > tmax ||
3168 ecmd->rx_coalesce_usecs_irq > tmax)
3169 return -EINVAL;
3170
3171 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3172 return -EINVAL;
3173 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3174 return -EINVAL;
3175 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3176 return -EINVAL;
3177
3178 if (ecmd->tx_coalesce_usecs == 0)
3179 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3180 else {
3181 sky2_write32(hw, STAT_TX_TIMER_INI,
3182 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3183 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3184 }
3185 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3186
3187 if (ecmd->rx_coalesce_usecs == 0)
3188 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3189 else {
3190 sky2_write32(hw, STAT_LEV_TIMER_INI,
3191 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3192 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3193 }
3194 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3195
3196 if (ecmd->rx_coalesce_usecs_irq == 0)
3197 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3198 else {
3199 sky2_write32(hw, STAT_ISR_TIMER_INI,
3200 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3201 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3202 }
3203 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3204 return 0;
3205 }
3206
3207 static void sky2_get_ringparam(struct net_device *dev,
3208 struct ethtool_ringparam *ering)
3209 {
3210 struct sky2_port *sky2 = netdev_priv(dev);
3211
3212 ering->rx_max_pending = RX_MAX_PENDING;
3213 ering->rx_mini_max_pending = 0;
3214 ering->rx_jumbo_max_pending = 0;
3215 ering->tx_max_pending = TX_RING_SIZE - 1;
3216
3217 ering->rx_pending = sky2->rx_pending;
3218 ering->rx_mini_pending = 0;
3219 ering->rx_jumbo_pending = 0;
3220 ering->tx_pending = sky2->tx_pending;
3221 }
3222
3223 static int sky2_set_ringparam(struct net_device *dev,
3224 struct ethtool_ringparam *ering)
3225 {
3226 struct sky2_port *sky2 = netdev_priv(dev);
3227 int err = 0;
3228
3229 if (ering->rx_pending > RX_MAX_PENDING ||
3230 ering->rx_pending < 8 ||
3231 ering->tx_pending < MAX_SKB_TX_LE ||
3232 ering->tx_pending > TX_RING_SIZE - 1)
3233 return -EINVAL;
3234
3235 if (netif_running(dev))
3236 sky2_down(dev);
3237
3238 sky2->rx_pending = ering->rx_pending;
3239 sky2->tx_pending = ering->tx_pending;
3240
3241 if (netif_running(dev)) {
3242 err = sky2_up(dev);
3243 if (err)
3244 dev_close(dev);
3245 else
3246 sky2_set_multicast(dev);
3247 }
3248
3249 return err;
3250 }
3251
3252 static int sky2_get_regs_len(struct net_device *dev)
3253 {
3254 return 0x4000;
3255 }
3256
3257 /*
3258 * Returns copy of control register region
3259 * Note: access to the RAM address register set will cause timeouts.
3260 */
3261 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3262 void *p)
3263 {
3264 const struct sky2_port *sky2 = netdev_priv(dev);
3265 const void __iomem *io = sky2->hw->regs;
3266
3267 BUG_ON(regs->len < B3_RI_WTO_R1);
3268 regs->version = 1;
3269 memset(p, 0, regs->len);
3270
3271 memcpy_fromio(p, io, B3_RAM_ADDR);
3272
3273 memcpy_fromio(p + B3_RI_WTO_R1,
3274 io + B3_RI_WTO_R1,
3275 regs->len - B3_RI_WTO_R1);
3276 }
3277
3278 static const struct ethtool_ops sky2_ethtool_ops = {
3279 .get_settings = sky2_get_settings,
3280 .set_settings = sky2_set_settings,
3281 .get_drvinfo = sky2_get_drvinfo,
3282 .get_wol = sky2_get_wol,
3283 .set_wol = sky2_set_wol,
3284 .get_msglevel = sky2_get_msglevel,
3285 .set_msglevel = sky2_set_msglevel,
3286 .nway_reset = sky2_nway_reset,
3287 .get_regs_len = sky2_get_regs_len,
3288 .get_regs = sky2_get_regs,
3289 .get_link = ethtool_op_get_link,
3290 .get_sg = ethtool_op_get_sg,
3291 .set_sg = ethtool_op_set_sg,
3292 .get_tx_csum = ethtool_op_get_tx_csum,
3293 .set_tx_csum = ethtool_op_set_tx_csum,
3294 .get_tso = ethtool_op_get_tso,
3295 .set_tso = ethtool_op_set_tso,
3296 .get_rx_csum = sky2_get_rx_csum,
3297 .set_rx_csum = sky2_set_rx_csum,
3298 .get_strings = sky2_get_strings,
3299 .get_coalesce = sky2_get_coalesce,
3300 .set_coalesce = sky2_set_coalesce,
3301 .get_ringparam = sky2_get_ringparam,
3302 .set_ringparam = sky2_set_ringparam,
3303 .get_pauseparam = sky2_get_pauseparam,
3304 .set_pauseparam = sky2_set_pauseparam,
3305 .phys_id = sky2_phys_id,
3306 .get_stats_count = sky2_get_stats_count,
3307 .get_ethtool_stats = sky2_get_ethtool_stats,
3308 .get_perm_addr = ethtool_op_get_perm_addr,
3309 };
3310
3311 /* Initialize network device */
3312 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3313 unsigned port,
3314 int highmem, int wol)
3315 {
3316 struct sky2_port *sky2;
3317 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3318
3319 if (!dev) {
3320 dev_err(&hw->pdev->dev, "etherdev alloc failed");
3321 return NULL;
3322 }
3323
3324 SET_MODULE_OWNER(dev);
3325 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3326 dev->irq = hw->pdev->irq;
3327 dev->open = sky2_up;
3328 dev->stop = sky2_down;
3329 dev->do_ioctl = sky2_ioctl;
3330 dev->hard_start_xmit = sky2_xmit_frame;
3331 dev->get_stats = sky2_get_stats;
3332 dev->set_multicast_list = sky2_set_multicast;
3333 dev->set_mac_address = sky2_set_mac_address;
3334 dev->change_mtu = sky2_change_mtu;
3335 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3336 dev->tx_timeout = sky2_tx_timeout;
3337 dev->watchdog_timeo = TX_WATCHDOG;
3338 if (port == 0)
3339 dev->poll = sky2_poll;
3340 dev->weight = NAPI_WEIGHT;
3341 #ifdef CONFIG_NET_POLL_CONTROLLER
3342 /* Network console (only works on port 0)
3343 * because netpoll makes assumptions about NAPI
3344 */
3345 if (port == 0)
3346 dev->poll_controller = sky2_netpoll;
3347 #endif
3348
3349 sky2 = netdev_priv(dev);
3350 sky2->netdev = dev;
3351 sky2->hw = hw;
3352 sky2->msg_enable = netif_msg_init(debug, default_msg);
3353
3354 /* Auto speed and flow control */
3355 sky2->autoneg = AUTONEG_ENABLE;
3356 sky2->flow_mode = FC_BOTH;
3357
3358 sky2->duplex = -1;
3359 sky2->speed = -1;
3360 sky2->advertising = sky2_supported_modes(hw);
3361 sky2->rx_csum = 1;
3362 sky2->wol = wol;
3363
3364 spin_lock_init(&sky2->phy_lock);
3365 sky2->tx_pending = TX_DEF_PENDING;
3366 sky2->rx_pending = RX_DEF_PENDING;
3367
3368 hw->dev[port] = dev;
3369
3370 sky2->port = port;
3371
3372 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
3373 if (highmem)
3374 dev->features |= NETIF_F_HIGHDMA;
3375
3376 #ifdef SKY2_VLAN_TAG_USED
3377 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3378 dev->vlan_rx_register = sky2_vlan_rx_register;
3379 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3380 #endif
3381
3382 /* read the mac address */
3383 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3384 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3385
3386 /* device is off until link detection */
3387 netif_carrier_off(dev);
3388 netif_stop_queue(dev);
3389
3390 return dev;
3391 }
3392
3393 static void __devinit sky2_show_addr(struct net_device *dev)
3394 {
3395 const struct sky2_port *sky2 = netdev_priv(dev);
3396
3397 if (netif_msg_probe(sky2))
3398 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3399 dev->name,
3400 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3401 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3402 }
3403
3404 /* Handle software interrupt used during MSI test */
3405 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
3406 {
3407 struct sky2_hw *hw = dev_id;
3408 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3409
3410 if (status == 0)
3411 return IRQ_NONE;
3412
3413 if (status & Y2_IS_IRQ_SW) {
3414 hw->msi = 1;
3415 wake_up(&hw->msi_wait);
3416 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3417 }
3418 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3419
3420 return IRQ_HANDLED;
3421 }
3422
3423 /* Test interrupt path by forcing a a software IRQ */
3424 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3425 {
3426 struct pci_dev *pdev = hw->pdev;
3427 int err;
3428
3429 init_waitqueue_head (&hw->msi_wait);
3430
3431 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3432
3433 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
3434 if (err) {
3435 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3436 return err;
3437 }
3438
3439 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3440 sky2_read8(hw, B0_CTST);
3441
3442 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
3443
3444 if (!hw->msi) {
3445 /* MSI test failed, go back to INTx mode */
3446 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3447 "switching to INTx mode.\n");
3448
3449 err = -EOPNOTSUPP;
3450 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3451 }
3452
3453 sky2_write32(hw, B0_IMSK, 0);
3454 sky2_read32(hw, B0_IMSK);
3455
3456 free_irq(pdev->irq, hw);
3457
3458 return err;
3459 }
3460
3461 static int __devinit pci_wake_enabled(struct pci_dev *dev)
3462 {
3463 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3464 u16 value;
3465
3466 if (!pm)
3467 return 0;
3468 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3469 return 0;
3470 return value & PCI_PM_CTRL_PME_ENABLE;
3471 }
3472
3473 static int __devinit sky2_probe(struct pci_dev *pdev,
3474 const struct pci_device_id *ent)
3475 {
3476 struct net_device *dev;
3477 struct sky2_hw *hw;
3478 int err, using_dac = 0, wol_default;
3479
3480 err = pci_enable_device(pdev);
3481 if (err) {
3482 dev_err(&pdev->dev, "cannot enable PCI device\n");
3483 goto err_out;
3484 }
3485
3486 err = pci_request_regions(pdev, DRV_NAME);
3487 if (err) {
3488 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3489 goto err_out;
3490 }
3491
3492 pci_set_master(pdev);
3493
3494 if (sizeof(dma_addr_t) > sizeof(u32) &&
3495 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3496 using_dac = 1;
3497 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3498 if (err < 0) {
3499 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3500 "for consistent allocations\n");
3501 goto err_out_free_regions;
3502 }
3503 } else {
3504 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3505 if (err) {
3506 dev_err(&pdev->dev, "no usable DMA configuration\n");
3507 goto err_out_free_regions;
3508 }
3509 }
3510
3511 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3512
3513 err = -ENOMEM;
3514 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3515 if (!hw) {
3516 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3517 goto err_out_free_regions;
3518 }
3519
3520 hw->pdev = pdev;
3521
3522 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3523 if (!hw->regs) {
3524 dev_err(&pdev->dev, "cannot map device registers\n");
3525 goto err_out_free_hw;
3526 }
3527
3528 #ifdef __BIG_ENDIAN
3529 /* The sk98lin vendor driver uses hardware byte swapping but
3530 * this driver uses software swapping.
3531 */
3532 {
3533 u32 reg;
3534 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3535 reg &= ~PCI_REV_DESC;
3536 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3537 }
3538 #endif
3539
3540 /* ring for status responses */
3541 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3542 &hw->st_dma);
3543 if (!hw->st_le)
3544 goto err_out_iounmap;
3545
3546 err = sky2_init(hw);
3547 if (err)
3548 goto err_out_iounmap;
3549
3550 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3551 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3552 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3553 hw->chip_id, hw->chip_rev);
3554
3555 sky2_reset(hw);
3556
3557 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
3558 if (!dev) {
3559 err = -ENOMEM;
3560 goto err_out_free_pci;
3561 }
3562
3563 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3564 err = sky2_test_msi(hw);
3565 if (err == -EOPNOTSUPP)
3566 pci_disable_msi(pdev);
3567 else if (err)
3568 goto err_out_free_netdev;
3569 }
3570
3571 err = register_netdev(dev);
3572 if (err) {
3573 dev_err(&pdev->dev, "cannot register net device\n");
3574 goto err_out_free_netdev;
3575 }
3576
3577 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3578 dev->name, hw);
3579 if (err) {
3580 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3581 goto err_out_unregister;
3582 }
3583 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3584
3585 sky2_show_addr(dev);
3586
3587 if (hw->ports > 1) {
3588 struct net_device *dev1;
3589
3590 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
3591 if (!dev1)
3592 dev_warn(&pdev->dev, "allocation for second device failed\n");
3593 else if ((err = register_netdev(dev1))) {
3594 dev_warn(&pdev->dev,
3595 "register of second port failed (%d)\n", err);
3596 hw->dev[1] = NULL;
3597 free_netdev(dev1);
3598 } else
3599 sky2_show_addr(dev1);
3600 }
3601
3602 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3603 sky2_idle_start(hw);
3604
3605 pci_set_drvdata(pdev, hw);
3606
3607 return 0;
3608
3609 err_out_unregister:
3610 if (hw->msi)
3611 pci_disable_msi(pdev);
3612 unregister_netdev(dev);
3613 err_out_free_netdev:
3614 free_netdev(dev);
3615 err_out_free_pci:
3616 sky2_write8(hw, B0_CTST, CS_RST_SET);
3617 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3618 err_out_iounmap:
3619 iounmap(hw->regs);
3620 err_out_free_hw:
3621 kfree(hw);
3622 err_out_free_regions:
3623 pci_release_regions(pdev);
3624 pci_disable_device(pdev);
3625 err_out:
3626 return err;
3627 }
3628
3629 static void __devexit sky2_remove(struct pci_dev *pdev)
3630 {
3631 struct sky2_hw *hw = pci_get_drvdata(pdev);
3632 struct net_device *dev0, *dev1;
3633
3634 if (!hw)
3635 return;
3636
3637 del_timer_sync(&hw->idle_timer);
3638
3639 sky2_write32(hw, B0_IMSK, 0);
3640 synchronize_irq(hw->pdev->irq);
3641
3642 dev0 = hw->dev[0];
3643 dev1 = hw->dev[1];
3644 if (dev1)
3645 unregister_netdev(dev1);
3646 unregister_netdev(dev0);
3647
3648 sky2_power_aux(hw);
3649
3650 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3651 sky2_write8(hw, B0_CTST, CS_RST_SET);
3652 sky2_read8(hw, B0_CTST);
3653
3654 free_irq(pdev->irq, hw);
3655 if (hw->msi)
3656 pci_disable_msi(pdev);
3657 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3658 pci_release_regions(pdev);
3659 pci_disable_device(pdev);
3660
3661 if (dev1)
3662 free_netdev(dev1);
3663 free_netdev(dev0);
3664 iounmap(hw->regs);
3665 kfree(hw);
3666
3667 pci_set_drvdata(pdev, NULL);
3668 }
3669
3670 #ifdef CONFIG_PM
3671 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3672 {
3673 struct sky2_hw *hw = pci_get_drvdata(pdev);
3674 int i, wol = 0;
3675
3676 del_timer_sync(&hw->idle_timer);
3677 netif_poll_disable(hw->dev[0]);
3678
3679 for (i = 0; i < hw->ports; i++) {
3680 struct net_device *dev = hw->dev[i];
3681 struct sky2_port *sky2 = netdev_priv(dev);
3682
3683 if (netif_running(dev))
3684 sky2_down(dev);
3685
3686 if (sky2->wol)
3687 sky2_wol_init(sky2);
3688
3689 wol |= sky2->wol;
3690 }
3691
3692 sky2_write32(hw, B0_IMSK, 0);
3693 sky2_power_aux(hw);
3694
3695 pci_save_state(pdev);
3696 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3697 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3698
3699 return 0;
3700 }
3701
3702 static int sky2_resume(struct pci_dev *pdev)
3703 {
3704 struct sky2_hw *hw = pci_get_drvdata(pdev);
3705 int i, err;
3706
3707 err = pci_set_power_state(pdev, PCI_D0);
3708 if (err)
3709 goto out;
3710
3711 err = pci_restore_state(pdev);
3712 if (err)
3713 goto out;
3714
3715 pci_enable_wake(pdev, PCI_D0, 0);
3716 sky2_reset(hw);
3717
3718 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3719
3720 for (i = 0; i < hw->ports; i++) {
3721 struct net_device *dev = hw->dev[i];
3722 if (netif_running(dev)) {
3723 err = sky2_up(dev);
3724 if (err) {
3725 printk(KERN_ERR PFX "%s: could not up: %d\n",
3726 dev->name, err);
3727 dev_close(dev);
3728 goto out;
3729 }
3730 }
3731 }
3732
3733 netif_poll_enable(hw->dev[0]);
3734 sky2_idle_start(hw);
3735 return 0;
3736 out:
3737 dev_err(&pdev->dev, "resume failed (%d)\n", err);
3738 pci_disable_device(pdev);
3739 return err;
3740 }
3741 #endif
3742
3743 static void sky2_shutdown(struct pci_dev *pdev)
3744 {
3745 struct sky2_hw *hw = pci_get_drvdata(pdev);
3746 int i, wol = 0;
3747
3748 del_timer_sync(&hw->idle_timer);
3749 netif_poll_disable(hw->dev[0]);
3750
3751 for (i = 0; i < hw->ports; i++) {
3752 struct net_device *dev = hw->dev[i];
3753 struct sky2_port *sky2 = netdev_priv(dev);
3754
3755 if (sky2->wol) {
3756 wol = 1;
3757 sky2_wol_init(sky2);
3758 }
3759 }
3760
3761 if (wol)
3762 sky2_power_aux(hw);
3763
3764 pci_enable_wake(pdev, PCI_D3hot, wol);
3765 pci_enable_wake(pdev, PCI_D3cold, wol);
3766
3767 pci_disable_device(pdev);
3768 pci_set_power_state(pdev, PCI_D3hot);
3769
3770 }
3771
3772 static struct pci_driver sky2_driver = {
3773 .name = DRV_NAME,
3774 .id_table = sky2_id_table,
3775 .probe = sky2_probe,
3776 .remove = __devexit_p(sky2_remove),
3777 #ifdef CONFIG_PM
3778 .suspend = sky2_suspend,
3779 .resume = sky2_resume,
3780 #endif
3781 .shutdown = sky2_shutdown,
3782 };
3783
3784 static int __init sky2_init_module(void)
3785 {
3786 return pci_register_driver(&sky2_driver);
3787 }
3788
3789 static void __exit sky2_cleanup_module(void)
3790 {
3791 pci_unregister_driver(&sky2_driver);
3792 }
3793
3794 module_init(sky2_init_module);
3795 module_exit(sky2_cleanup_module);
3796
3797 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3798 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
3799 MODULE_LICENSE("GPL");
3800 MODULE_VERSION(DRV_VERSION);
Verdex Pro support