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[ALSA] hda-intel - Fix power-off hang on ASUS P5AD2
[linux-2.6/verdex.git] / sound / pci / hda / hda_intel.c
blob9a20fb1bef4f00da66174b01cc9dafec9f9f7b90
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <sound/core.h>
49 #include <sound/initval.h>
50 #include "hda_codec.h"
51
52
53 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
54 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
55 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
56 static char *model[SNDRV_CARDS];
57 static int position_fix[SNDRV_CARDS];
58 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
59 static int single_cmd;
60 static int enable_msi;
61
62 module_param_array(index, int, NULL, 0444);
63 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
64 module_param_array(id, charp, NULL, 0444);
65 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
66 module_param_array(enable, bool, NULL, 0444);
67 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
68 module_param_array(model, charp, NULL, 0444);
69 MODULE_PARM_DESC(model, "Use the given board model.");
70 module_param_array(position_fix, int, NULL, 0444);
71 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
72 "(0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
73 module_param_array(probe_mask, int, NULL, 0444);
74 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
75 module_param(single_cmd, bool, 0444);
76 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
77 "(for debugging only).");
78 module_param(enable_msi, int, 0444);
79 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
80
81 #ifdef CONFIG_SND_HDA_POWER_SAVE
82 /* power_save option is defined in hda_codec.c */
83
84 /* reset the HD-audio controller in power save mode.
85 * this may give more power-saving, but will take longer time to
86 * wake up.
87 */
88 static int power_save_controller = 1;
89 module_param(power_save_controller, bool, 0644);
90 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
91 #endif
92
93 MODULE_LICENSE("GPL");
94 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
95 "{Intel, ICH6M},"
96 "{Intel, ICH7},"
97 "{Intel, ESB2},"
98 "{Intel, ICH8},"
99 "{Intel, ICH9},"
100 "{Intel, ICH10},"
101 "{Intel, SCH},"
102 "{ATI, SB450},"
103 "{ATI, SB600},"
104 "{ATI, RS600},"
105 "{ATI, RS690},"
106 "{ATI, RS780},"
107 "{ATI, R600},"
108 "{ATI, RV630},"
109 "{ATI, RV610},"
110 "{ATI, RV670},"
111 "{ATI, RV635},"
112 "{ATI, RV620},"
113 "{ATI, RV770},"
114 "{VIA, VT8251},"
115 "{VIA, VT8237A},"
116 "{SiS, SIS966},"
117 "{ULI, M5461}}");
118 MODULE_DESCRIPTION("Intel HDA driver");
119
120 #define SFX "hda-intel: "
121
122
123 /*
124 * registers
125 */
126 #define ICH6_REG_GCAP 0x00
127 #define ICH6_REG_VMIN 0x02
128 #define ICH6_REG_VMAJ 0x03
129 #define ICH6_REG_OUTPAY 0x04
130 #define ICH6_REG_INPAY 0x06
131 #define ICH6_REG_GCTL 0x08
132 #define ICH6_REG_WAKEEN 0x0c
133 #define ICH6_REG_STATESTS 0x0e
134 #define ICH6_REG_GSTS 0x10
135 #define ICH6_REG_INTCTL 0x20
136 #define ICH6_REG_INTSTS 0x24
137 #define ICH6_REG_WALCLK 0x30
138 #define ICH6_REG_SYNC 0x34
139 #define ICH6_REG_CORBLBASE 0x40
140 #define ICH6_REG_CORBUBASE 0x44
141 #define ICH6_REG_CORBWP 0x48
142 #define ICH6_REG_CORBRP 0x4A
143 #define ICH6_REG_CORBCTL 0x4c
144 #define ICH6_REG_CORBSTS 0x4d
145 #define ICH6_REG_CORBSIZE 0x4e
146
147 #define ICH6_REG_RIRBLBASE 0x50
148 #define ICH6_REG_RIRBUBASE 0x54
149 #define ICH6_REG_RIRBWP 0x58
150 #define ICH6_REG_RINTCNT 0x5a
151 #define ICH6_REG_RIRBCTL 0x5c
152 #define ICH6_REG_RIRBSTS 0x5d
153 #define ICH6_REG_RIRBSIZE 0x5e
154
155 #define ICH6_REG_IC 0x60
156 #define ICH6_REG_IR 0x64
157 #define ICH6_REG_IRS 0x68
158 #define ICH6_IRS_VALID (1<<1)
159 #define ICH6_IRS_BUSY (1<<0)
160
161 #define ICH6_REG_DPLBASE 0x70
162 #define ICH6_REG_DPUBASE 0x74
163 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
164
165 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
166 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
167
168 /* stream register offsets from stream base */
169 #define ICH6_REG_SD_CTL 0x00
170 #define ICH6_REG_SD_STS 0x03
171 #define ICH6_REG_SD_LPIB 0x04
172 #define ICH6_REG_SD_CBL 0x08
173 #define ICH6_REG_SD_LVI 0x0c
174 #define ICH6_REG_SD_FIFOW 0x0e
175 #define ICH6_REG_SD_FIFOSIZE 0x10
176 #define ICH6_REG_SD_FORMAT 0x12
177 #define ICH6_REG_SD_BDLPL 0x18
178 #define ICH6_REG_SD_BDLPU 0x1c
179
180 /* PCI space */
181 #define ICH6_PCIREG_TCSEL 0x44
182
183 /*
184 * other constants
185 */
186
187 /* max number of SDs */
188 /* ICH, ATI and VIA have 4 playback and 4 capture */
189 #define ICH6_NUM_CAPTURE 4
190 #define ICH6_NUM_PLAYBACK 4
191
192 /* ULI has 6 playback and 5 capture */
193 #define ULI_NUM_CAPTURE 5
194 #define ULI_NUM_PLAYBACK 6
195
196 /* ATI HDMI has 1 playback and 0 capture */
197 #define ATIHDMI_NUM_CAPTURE 0
198 #define ATIHDMI_NUM_PLAYBACK 1
199
200 /* this number is statically defined for simplicity */
201 #define MAX_AZX_DEV 16
202
203 /* max number of fragments - we may use more if allocating more pages for BDL */
204 #define BDL_SIZE 4096
205 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
206 #define AZX_MAX_FRAG 32
207 /* max buffer size - no h/w limit, you can increase as you like */
208 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
209 /* max number of PCM devics per card */
210 #define AZX_MAX_PCMS 8
211
212 /* RIRB int mask: overrun[2], response[0] */
213 #define RIRB_INT_RESPONSE 0x01
214 #define RIRB_INT_OVERRUN 0x04
215 #define RIRB_INT_MASK 0x05
216
217 /* STATESTS int mask: SD2,SD1,SD0 */
218 #define AZX_MAX_CODECS 3
219 #define STATESTS_INT_MASK 0x07
220
221 /* SD_CTL bits */
222 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
223 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
224 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
225 #define SD_CTL_STREAM_TAG_SHIFT 20
226
227 /* SD_CTL and SD_STS */
228 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
229 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
230 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
231 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
232 SD_INT_COMPLETE)
233
234 /* SD_STS */
235 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
236
237 /* INTCTL and INTSTS */
238 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
239 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
240 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
241
242 /* GCTL unsolicited response enable bit */
243 #define ICH6_GCTL_UREN (1<<8)
244
245 /* GCTL reset bit */
246 #define ICH6_GCTL_RESET (1<<0)
247
248 /* CORB/RIRB control, read/write pointer */
249 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
250 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
251 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
252 /* below are so far hardcoded - should read registers in future */
253 #define ICH6_MAX_CORB_ENTRIES 256
254 #define ICH6_MAX_RIRB_ENTRIES 256
255
256 /* position fix mode */
257 enum {
258 POS_FIX_AUTO,
259 POS_FIX_NONE,
260 POS_FIX_POSBUF,
261 POS_FIX_FIFO,
262 };
263
264 /* Defines for ATI HD Audio support in SB450 south bridge */
265 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
266 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
267
268 /* Defines for Nvidia HDA support */
269 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
270 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
271
272 /* Defines for Intel SCH HDA snoop control */
273 #define INTEL_SCH_HDA_DEVC 0x78
274 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
275
276
277 /*
278 */
279
280 struct azx_dev {
281 struct snd_dma_buffer bdl; /* BDL buffer */
282 u32 *posbuf; /* position buffer pointer */
283
284 unsigned int bufsize; /* size of the play buffer in bytes */
285 unsigned int frags; /* number for period in the play buffer */
286 unsigned int fifo_size; /* FIFO size */
287
288 void __iomem *sd_addr; /* stream descriptor pointer */
289
290 u32 sd_int_sta_mask; /* stream int status mask */
291
292 /* pcm support */
293 struct snd_pcm_substream *substream; /* assigned substream,
294 * set in PCM open
295 */
296 unsigned int format_val; /* format value to be set in the
297 * controller and the codec
298 */
299 unsigned char stream_tag; /* assigned stream */
300 unsigned char index; /* stream index */
301 /* for sanity check of position buffer */
302 unsigned int period_intr;
303
304 unsigned int opened :1;
305 unsigned int running :1;
306 };
307
308 /* CORB/RIRB */
309 struct azx_rb {
310 u32 *buf; /* CORB/RIRB buffer
311 * Each CORB entry is 4byte, RIRB is 8byte
312 */
313 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
314 /* for RIRB */
315 unsigned short rp, wp; /* read/write pointers */
316 int cmds; /* number of pending requests */
317 u32 res; /* last read value */
318 };
319
320 struct azx {
321 struct snd_card *card;
322 struct pci_dev *pci;
323
324 /* chip type specific */
325 int driver_type;
326 int playback_streams;
327 int playback_index_offset;
328 int capture_streams;
329 int capture_index_offset;
330 int num_streams;
331
332 /* pci resources */
333 unsigned long addr;
334 void __iomem *remap_addr;
335 int irq;
336
337 /* locks */
338 spinlock_t reg_lock;
339 struct mutex open_mutex;
340
341 /* streams (x num_streams) */
342 struct azx_dev *azx_dev;
343
344 /* PCM */
345 struct snd_pcm *pcm[AZX_MAX_PCMS];
346
347 /* HD codec */
348 unsigned short codec_mask;
349 struct hda_bus *bus;
350
351 /* CORB/RIRB */
352 struct azx_rb corb;
353 struct azx_rb rirb;
354
355 /* CORB/RIRB and position buffers */
356 struct snd_dma_buffer rb;
357 struct snd_dma_buffer posbuf;
358
359 /* flags */
360 int position_fix;
361 unsigned int running :1;
362 unsigned int initialized :1;
363 unsigned int single_cmd :1;
364 unsigned int polling_mode :1;
365 unsigned int msi :1;
366
367 /* for debugging */
368 unsigned int last_cmd; /* last issued command (to sync) */
369 };
370
371 /* driver types */
372 enum {
373 AZX_DRIVER_ICH,
374 AZX_DRIVER_SCH,
375 AZX_DRIVER_ATI,
376 AZX_DRIVER_ATIHDMI,
377 AZX_DRIVER_VIA,
378 AZX_DRIVER_SIS,
379 AZX_DRIVER_ULI,
380 AZX_DRIVER_NVIDIA,
381 };
382
383 static char *driver_short_names[] __devinitdata = {
384 [AZX_DRIVER_ICH] = "HDA Intel",
385 [AZX_DRIVER_SCH] = "HDA Intel MID",
386 [AZX_DRIVER_ATI] = "HDA ATI SB",
387 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
388 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
389 [AZX_DRIVER_SIS] = "HDA SIS966",
390 [AZX_DRIVER_ULI] = "HDA ULI M5461",
391 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
392 };
393
394 /*
395 * macros for easy use
396 */
397 #define azx_writel(chip,reg,value) \
398 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
399 #define azx_readl(chip,reg) \
400 readl((chip)->remap_addr + ICH6_REG_##reg)
401 #define azx_writew(chip,reg,value) \
402 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
403 #define azx_readw(chip,reg) \
404 readw((chip)->remap_addr + ICH6_REG_##reg)
405 #define azx_writeb(chip,reg,value) \
406 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
407 #define azx_readb(chip,reg) \
408 readb((chip)->remap_addr + ICH6_REG_##reg)
409
410 #define azx_sd_writel(dev,reg,value) \
411 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
412 #define azx_sd_readl(dev,reg) \
413 readl((dev)->sd_addr + ICH6_REG_##reg)
414 #define azx_sd_writew(dev,reg,value) \
415 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
416 #define azx_sd_readw(dev,reg) \
417 readw((dev)->sd_addr + ICH6_REG_##reg)
418 #define azx_sd_writeb(dev,reg,value) \
419 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
420 #define azx_sd_readb(dev,reg) \
421 readb((dev)->sd_addr + ICH6_REG_##reg)
422
423 /* for pcm support */
424 #define get_azx_dev(substream) (substream->runtime->private_data)
425
426 /* Get the upper 32bit of the given dma_addr_t
427 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
428 */
429 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
430
431 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
432
433 /*
434 * Interface for HD codec
435 */
436
437 /*
438 * CORB / RIRB interface
439 */
440 static int azx_alloc_cmd_io(struct azx *chip)
441 {
442 int err;
443
444 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
445 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
446 snd_dma_pci_data(chip->pci),
447 PAGE_SIZE, &chip->rb);
448 if (err < 0) {
449 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
450 return err;
451 }
452 return 0;
453 }
454
455 static void azx_init_cmd_io(struct azx *chip)
456 {
457 /* CORB set up */
458 chip->corb.addr = chip->rb.addr;
459 chip->corb.buf = (u32 *)chip->rb.area;
460 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
461 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
462
463 /* set the corb size to 256 entries (ULI requires explicitly) */
464 azx_writeb(chip, CORBSIZE, 0x02);
465 /* set the corb write pointer to 0 */
466 azx_writew(chip, CORBWP, 0);
467 /* reset the corb hw read pointer */
468 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
469 /* enable corb dma */
470 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
471
472 /* RIRB set up */
473 chip->rirb.addr = chip->rb.addr + 2048;
474 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
475 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
476 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
477
478 /* set the rirb size to 256 entries (ULI requires explicitly) */
479 azx_writeb(chip, RIRBSIZE, 0x02);
480 /* reset the rirb hw write pointer */
481 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
482 /* set N=1, get RIRB response interrupt for new entry */
483 azx_writew(chip, RINTCNT, 1);
484 /* enable rirb dma and response irq */
485 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
486 chip->rirb.rp = chip->rirb.cmds = 0;
487 }
488
489 static void azx_free_cmd_io(struct azx *chip)
490 {
491 /* disable ringbuffer DMAs */
492 azx_writeb(chip, RIRBCTL, 0);
493 azx_writeb(chip, CORBCTL, 0);
494 }
495
496 /* send a command */
497 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
498 {
499 struct azx *chip = codec->bus->private_data;
500 unsigned int wp;
501
502 /* add command to corb */
503 wp = azx_readb(chip, CORBWP);
504 wp++;
505 wp %= ICH6_MAX_CORB_ENTRIES;
506
507 spin_lock_irq(&chip->reg_lock);
508 chip->rirb.cmds++;
509 chip->corb.buf[wp] = cpu_to_le32(val);
510 azx_writel(chip, CORBWP, wp);
511 spin_unlock_irq(&chip->reg_lock);
512
513 return 0;
514 }
515
516 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
517
518 /* retrieve RIRB entry - called from interrupt handler */
519 static void azx_update_rirb(struct azx *chip)
520 {
521 unsigned int rp, wp;
522 u32 res, res_ex;
523
524 wp = azx_readb(chip, RIRBWP);
525 if (wp == chip->rirb.wp)
526 return;
527 chip->rirb.wp = wp;
528
529 while (chip->rirb.rp != wp) {
530 chip->rirb.rp++;
531 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
532
533 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
534 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
535 res = le32_to_cpu(chip->rirb.buf[rp]);
536 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
537 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
538 else if (chip->rirb.cmds) {
539 chip->rirb.cmds--;
540 chip->rirb.res = res;
541 }
542 }
543 }
544
545 /* receive a response */
546 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
547 {
548 struct azx *chip = codec->bus->private_data;
549 unsigned long timeout;
550
551 again:
552 timeout = jiffies + msecs_to_jiffies(1000);
553 for (;;) {
554 if (chip->polling_mode) {
555 spin_lock_irq(&chip->reg_lock);
556 azx_update_rirb(chip);
557 spin_unlock_irq(&chip->reg_lock);
558 }
559 if (!chip->rirb.cmds)
560 return chip->rirb.res; /* the last value */
561 if (time_after(jiffies, timeout))
562 break;
563 if (codec->bus->needs_damn_long_delay)
564 msleep(2); /* temporary workaround */
565 else {
566 udelay(10);
567 cond_resched();
568 }
569 }
570
571 if (chip->msi) {
572 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
573 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
574 free_irq(chip->irq, chip);
575 chip->irq = -1;
576 pci_disable_msi(chip->pci);
577 chip->msi = 0;
578 if (azx_acquire_irq(chip, 1) < 0)
579 return -1;
580 goto again;
581 }
582
583 if (!chip->polling_mode) {
584 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
585 "switching to polling mode: last cmd=0x%08x\n",
586 chip->last_cmd);
587 chip->polling_mode = 1;
588 goto again;
589 }
590
591 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
592 "switching to single_cmd mode: last cmd=0x%08x\n",
593 chip->last_cmd);
594 chip->rirb.rp = azx_readb(chip, RIRBWP);
595 chip->rirb.cmds = 0;
596 /* switch to single_cmd mode */
597 chip->single_cmd = 1;
598 azx_free_cmd_io(chip);
599 return -1;
600 }
601
602 /*
603 * Use the single immediate command instead of CORB/RIRB for simplicity
604 *
605 * Note: according to Intel, this is not preferred use. The command was
606 * intended for the BIOS only, and may get confused with unsolicited
607 * responses. So, we shouldn't use it for normal operation from the
608 * driver.
609 * I left the codes, however, for debugging/testing purposes.
610 */
611
612 /* send a command */
613 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
614 {
615 struct azx *chip = codec->bus->private_data;
616 int timeout = 50;
617
618 while (timeout--) {
619 /* check ICB busy bit */
620 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
621 /* Clear IRV valid bit */
622 azx_writew(chip, IRS, azx_readw(chip, IRS) |
623 ICH6_IRS_VALID);
624 azx_writel(chip, IC, val);
625 azx_writew(chip, IRS, azx_readw(chip, IRS) |
626 ICH6_IRS_BUSY);
627 return 0;
628 }
629 udelay(1);
630 }
631 if (printk_ratelimit())
632 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
633 azx_readw(chip, IRS), val);
634 return -EIO;
635 }
636
637 /* receive a response */
638 static unsigned int azx_single_get_response(struct hda_codec *codec)
639 {
640 struct azx *chip = codec->bus->private_data;
641 int timeout = 50;
642
643 while (timeout--) {
644 /* check IRV busy bit */
645 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
646 return azx_readl(chip, IR);
647 udelay(1);
648 }
649 if (printk_ratelimit())
650 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
651 azx_readw(chip, IRS));
652 return (unsigned int)-1;
653 }
654
655 /*
656 * The below are the main callbacks from hda_codec.
657 *
658 * They are just the skeleton to call sub-callbacks according to the
659 * current setting of chip->single_cmd.
660 */
661
662 /* send a command */
663 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
664 int direct, unsigned int verb,
665 unsigned int para)
666 {
667 struct azx *chip = codec->bus->private_data;
668 u32 val;
669
670 val = (u32)(codec->addr & 0x0f) << 28;
671 val |= (u32)direct << 27;
672 val |= (u32)nid << 20;
673 val |= verb << 8;
674 val |= para;
675 chip->last_cmd = val;
676
677 if (chip->single_cmd)
678 return azx_single_send_cmd(codec, val);
679 else
680 return azx_corb_send_cmd(codec, val);
681 }
682
683 /* get a response */
684 static unsigned int azx_get_response(struct hda_codec *codec)
685 {
686 struct azx *chip = codec->bus->private_data;
687 if (chip->single_cmd)
688 return azx_single_get_response(codec);
689 else
690 return azx_rirb_get_response(codec);
691 }
692
693 #ifdef CONFIG_SND_HDA_POWER_SAVE
694 static void azx_power_notify(struct hda_codec *codec);
695 #endif
696
697 /* reset codec link */
698 static int azx_reset(struct azx *chip)
699 {
700 int count;
701
702 /* clear STATESTS */
703 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
704
705 /* reset controller */
706 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
707
708 count = 50;
709 while (azx_readb(chip, GCTL) && --count)
710 msleep(1);
711
712 /* delay for >= 100us for codec PLL to settle per spec
713 * Rev 0.9 section 5.5.1
714 */
715 msleep(1);
716
717 /* Bring controller out of reset */
718 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
719
720 count = 50;
721 while (!azx_readb(chip, GCTL) && --count)
722 msleep(1);
723
724 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
725 msleep(1);
726
727 /* check to see if controller is ready */
728 if (!azx_readb(chip, GCTL)) {
729 snd_printd("azx_reset: controller not ready!\n");
730 return -EBUSY;
731 }
732
733 /* Accept unsolicited responses */
734 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
735
736 /* detect codecs */
737 if (!chip->codec_mask) {
738 chip->codec_mask = azx_readw(chip, STATESTS);
739 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
740 }
741
742 return 0;
743 }
744
745
746 /*
747 * Lowlevel interface
748 */
749
750 /* enable interrupts */
751 static void azx_int_enable(struct azx *chip)
752 {
753 /* enable controller CIE and GIE */
754 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
755 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
756 }
757
758 /* disable interrupts */
759 static void azx_int_disable(struct azx *chip)
760 {
761 int i;
762
763 /* disable interrupts in stream descriptor */
764 for (i = 0; i < chip->num_streams; i++) {
765 struct azx_dev *azx_dev = &chip->azx_dev[i];
766 azx_sd_writeb(azx_dev, SD_CTL,
767 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
768 }
769
770 /* disable SIE for all streams */
771 azx_writeb(chip, INTCTL, 0);
772
773 /* disable controller CIE and GIE */
774 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
775 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
776 }
777
778 /* clear interrupts */
779 static void azx_int_clear(struct azx *chip)
780 {
781 int i;
782
783 /* clear stream status */
784 for (i = 0; i < chip->num_streams; i++) {
785 struct azx_dev *azx_dev = &chip->azx_dev[i];
786 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
787 }
788
789 /* clear STATESTS */
790 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
791
792 /* clear rirb status */
793 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
794
795 /* clear int status */
796 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
797 }
798
799 /* start a stream */
800 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
801 {
802 /* enable SIE */
803 azx_writeb(chip, INTCTL,
804 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
805 /* set DMA start and interrupt mask */
806 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
807 SD_CTL_DMA_START | SD_INT_MASK);
808 }
809
810 /* stop a stream */
811 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
812 {
813 /* stop DMA */
814 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
815 ~(SD_CTL_DMA_START | SD_INT_MASK));
816 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
817 /* disable SIE */
818 azx_writeb(chip, INTCTL,
819 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
820 }
821
822
823 /*
824 * reset and start the controller registers
825 */
826 static void azx_init_chip(struct azx *chip)
827 {
828 if (chip->initialized)
829 return;
830
831 /* reset controller */
832 azx_reset(chip);
833
834 /* initialize interrupts */
835 azx_int_clear(chip);
836 azx_int_enable(chip);
837
838 /* initialize the codec command I/O */
839 if (!chip->single_cmd)
840 azx_init_cmd_io(chip);
841
842 /* program the position buffer */
843 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
844 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
845
846 chip->initialized = 1;
847 }
848
849 /*
850 * initialize the PCI registers
851 */
852 /* update bits in a PCI register byte */
853 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
854 unsigned char mask, unsigned char val)
855 {
856 unsigned char data;
857
858 pci_read_config_byte(pci, reg, &data);
859 data &= ~mask;
860 data |= (val & mask);
861 pci_write_config_byte(pci, reg, data);
862 }
863
864 static void azx_init_pci(struct azx *chip)
865 {
866 unsigned short snoop;
867
868 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
869 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
870 * Ensuring these bits are 0 clears playback static on some HD Audio
871 * codecs
872 */
873 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
874
875 switch (chip->driver_type) {
876 case AZX_DRIVER_ATI:
877 /* For ATI SB450 azalia HD audio, we need to enable snoop */
878 update_pci_byte(chip->pci,
879 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
880 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
881 break;
882 case AZX_DRIVER_NVIDIA:
883 /* For NVIDIA HDA, enable snoop */
884 update_pci_byte(chip->pci,
885 NVIDIA_HDA_TRANSREG_ADDR,
886 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
887 break;
888 case AZX_DRIVER_SCH:
889 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
890 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
891 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
892 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
893 pci_read_config_word(chip->pci,
894 INTEL_SCH_HDA_DEVC, &snoop);
895 snd_printdd("HDA snoop disabled, enabling ... %s\n",\
896 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
897 ? "Failed" : "OK");
898 }
899 break;
900
901 }
902 }
903
904
905 /*
906 * interrupt handler
907 */
908 static irqreturn_t azx_interrupt(int irq, void *dev_id)
909 {
910 struct azx *chip = dev_id;
911 struct azx_dev *azx_dev;
912 u32 status;
913 int i;
914
915 spin_lock(&chip->reg_lock);
916
917 status = azx_readl(chip, INTSTS);
918 if (status == 0) {
919 spin_unlock(&chip->reg_lock);
920 return IRQ_NONE;
921 }
922
923 for (i = 0; i < chip->num_streams; i++) {
924 azx_dev = &chip->azx_dev[i];
925 if (status & azx_dev->sd_int_sta_mask) {
926 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
927 if (azx_dev->substream && azx_dev->running) {
928 azx_dev->period_intr++;
929 spin_unlock(&chip->reg_lock);
930 snd_pcm_period_elapsed(azx_dev->substream);
931 spin_lock(&chip->reg_lock);
932 }
933 }
934 }
935
936 /* clear rirb int */
937 status = azx_readb(chip, RIRBSTS);
938 if (status & RIRB_INT_MASK) {
939 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
940 azx_update_rirb(chip);
941 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
942 }
943
944 #if 0
945 /* clear state status int */
946 if (azx_readb(chip, STATESTS) & 0x04)
947 azx_writeb(chip, STATESTS, 0x04);
948 #endif
949 spin_unlock(&chip->reg_lock);
950
951 return IRQ_HANDLED;
952 }
953
954
955 /*
956 * set up BDL entries
957 */
958 static int azx_setup_periods(struct snd_pcm_substream *substream,
959 struct azx_dev *azx_dev)
960 {
961 struct snd_sg_buf *sgbuf = snd_pcm_substream_sgbuf(substream);
962 u32 *bdl;
963 int i, ofs, periods, period_bytes;
964
965 /* reset BDL address */
966 azx_sd_writel(azx_dev, SD_BDLPL, 0);
967 azx_sd_writel(azx_dev, SD_BDLPU, 0);
968
969 period_bytes = snd_pcm_lib_period_bytes(substream);
970 periods = azx_dev->bufsize / period_bytes;
971
972 /* program the initial BDL entries */
973 bdl = (u32 *)azx_dev->bdl.area;
974 ofs = 0;
975 azx_dev->frags = 0;
976 for (i = 0; i < periods; i++) {
977 int size, rest;
978 if (i >= AZX_MAX_BDL_ENTRIES) {
979 snd_printk(KERN_ERR "Too many BDL entries: "
980 "buffer=%d, period=%d\n",
981 azx_dev->bufsize, period_bytes);
982 /* reset */
983 azx_sd_writel(azx_dev, SD_BDLPL, 0);
984 azx_sd_writel(azx_dev, SD_BDLPU, 0);
985 return -EINVAL;
986 }
987 rest = period_bytes;
988 do {
989 dma_addr_t addr = snd_pcm_sgbuf_get_addr(sgbuf, ofs);
990 /* program the address field of the BDL entry */
991 bdl[0] = cpu_to_le32((u32)addr);
992 bdl[1] = cpu_to_le32(upper_32bit(addr));
993 /* program the size field of the BDL entry */
994 size = PAGE_SIZE - (ofs % PAGE_SIZE);
995 if (rest < size)
996 size = rest;
997 bdl[2] = cpu_to_le32(size);
998 /* program the IOC to enable interrupt
999 * only when the whole fragment is processed
1000 */
1001 rest -= size;
1002 bdl[3] = rest ? 0 : cpu_to_le32(0x01);
1003 bdl += 4;
1004 azx_dev->frags++;
1005 ofs += size;
1006 } while (rest > 0);
1007 }
1008 return 0;
1009 }
1010
1011 /*
1012 * set up the SD for streaming
1013 */
1014 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1015 {
1016 unsigned char val;
1017 int timeout;
1018
1019 /* make sure the run bit is zero for SD */
1020 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1021 ~SD_CTL_DMA_START);
1022 /* reset stream */
1023 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1024 SD_CTL_STREAM_RESET);
1025 udelay(3);
1026 timeout = 300;
1027 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1028 --timeout)
1029 ;
1030 val &= ~SD_CTL_STREAM_RESET;
1031 azx_sd_writeb(azx_dev, SD_CTL, val);
1032 udelay(3);
1033
1034 timeout = 300;
1035 /* waiting for hardware to report that the stream is out of reset */
1036 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1037 --timeout)
1038 ;
1039
1040 /* program the stream_tag */
1041 azx_sd_writel(azx_dev, SD_CTL,
1042 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1043 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1044
1045 /* program the length of samples in cyclic buffer */
1046 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1047
1048 /* program the stream format */
1049 /* this value needs to be the same as the one programmed */
1050 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1051
1052 /* program the stream LVI (last valid index) of the BDL */
1053 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1054
1055 /* program the BDL address */
1056 /* lower BDL address */
1057 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1058 /* upper BDL address */
1059 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl.addr));
1060
1061 /* enable the position buffer */
1062 if (chip->position_fix == POS_FIX_POSBUF ||
1063 chip->position_fix == POS_FIX_AUTO) {
1064 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1065 azx_writel(chip, DPLBASE,
1066 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1067 }
1068
1069 /* set the interrupt enable bits in the descriptor control register */
1070 azx_sd_writel(azx_dev, SD_CTL,
1071 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1072
1073 return 0;
1074 }
1075
1076
1077 /*
1078 * Codec initialization
1079 */
1080
1081 static unsigned int azx_max_codecs[] __devinitdata = {
1082 [AZX_DRIVER_ICH] = 3,
1083 [AZX_DRIVER_SCH] = 3,
1084 [AZX_DRIVER_ATI] = 4,
1085 [AZX_DRIVER_ATIHDMI] = 4,
1086 [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */
1087 [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */
1088 [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */
1089 [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */
1090 };
1091
1092 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1093 unsigned int codec_probe_mask)
1094 {
1095 struct hda_bus_template bus_temp;
1096 int c, codecs, audio_codecs, err;
1097
1098 memset(&bus_temp, 0, sizeof(bus_temp));
1099 bus_temp.private_data = chip;
1100 bus_temp.modelname = model;
1101 bus_temp.pci = chip->pci;
1102 bus_temp.ops.command = azx_send_cmd;
1103 bus_temp.ops.get_response = azx_get_response;
1104 #ifdef CONFIG_SND_HDA_POWER_SAVE
1105 bus_temp.ops.pm_notify = azx_power_notify;
1106 #endif
1107
1108 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1109 if (err < 0)
1110 return err;
1111
1112 codecs = audio_codecs = 0;
1113 for (c = 0; c < AZX_MAX_CODECS; c++) {
1114 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1115 struct hda_codec *codec;
1116 err = snd_hda_codec_new(chip->bus, c, &codec);
1117 if (err < 0)
1118 continue;
1119 codecs++;
1120 if (codec->afg)
1121 audio_codecs++;
1122 }
1123 }
1124 if (!audio_codecs) {
1125 /* probe additional slots if no codec is found */
1126 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1127 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1128 err = snd_hda_codec_new(chip->bus, c, NULL);
1129 if (err < 0)
1130 continue;
1131 codecs++;
1132 }
1133 }
1134 }
1135 if (!codecs) {
1136 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1137 return -ENXIO;
1138 }
1139
1140 return 0;
1141 }
1142
1143
1144 /*
1145 * PCM support
1146 */
1147
1148 /* assign a stream for the PCM */
1149 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1150 {
1151 int dev, i, nums;
1152 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1153 dev = chip->playback_index_offset;
1154 nums = chip->playback_streams;
1155 } else {
1156 dev = chip->capture_index_offset;
1157 nums = chip->capture_streams;
1158 }
1159 for (i = 0; i < nums; i++, dev++)
1160 if (!chip->azx_dev[dev].opened) {
1161 chip->azx_dev[dev].opened = 1;
1162 return &chip->azx_dev[dev];
1163 }
1164 return NULL;
1165 }
1166
1167 /* release the assigned stream */
1168 static inline void azx_release_device(struct azx_dev *azx_dev)
1169 {
1170 azx_dev->opened = 0;
1171 }
1172
1173 static struct snd_pcm_hardware azx_pcm_hw = {
1174 .info = (SNDRV_PCM_INFO_MMAP |
1175 SNDRV_PCM_INFO_INTERLEAVED |
1176 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1177 SNDRV_PCM_INFO_MMAP_VALID |
1178 /* No full-resume yet implemented */
1179 /* SNDRV_PCM_INFO_RESUME |*/
1180 SNDRV_PCM_INFO_PAUSE),
1181 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1182 .rates = SNDRV_PCM_RATE_48000,
1183 .rate_min = 48000,
1184 .rate_max = 48000,
1185 .channels_min = 2,
1186 .channels_max = 2,
1187 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1188 .period_bytes_min = 128,
1189 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1190 .periods_min = 2,
1191 .periods_max = AZX_MAX_FRAG,
1192 .fifo_size = 0,
1193 };
1194
1195 struct azx_pcm {
1196 struct azx *chip;
1197 struct hda_codec *codec;
1198 struct hda_pcm_stream *hinfo[2];
1199 };
1200
1201 static int azx_pcm_open(struct snd_pcm_substream *substream)
1202 {
1203 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1204 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1205 struct azx *chip = apcm->chip;
1206 struct azx_dev *azx_dev;
1207 struct snd_pcm_runtime *runtime = substream->runtime;
1208 unsigned long flags;
1209 int err;
1210
1211 mutex_lock(&chip->open_mutex);
1212 azx_dev = azx_assign_device(chip, substream->stream);
1213 if (azx_dev == NULL) {
1214 mutex_unlock(&chip->open_mutex);
1215 return -EBUSY;
1216 }
1217 runtime->hw = azx_pcm_hw;
1218 runtime->hw.channels_min = hinfo->channels_min;
1219 runtime->hw.channels_max = hinfo->channels_max;
1220 runtime->hw.formats = hinfo->formats;
1221 runtime->hw.rates = hinfo->rates;
1222 snd_pcm_limit_hw_rates(runtime);
1223 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1224 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1225 128);
1226 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1227 128);
1228 snd_hda_power_up(apcm->codec);
1229 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1230 if (err < 0) {
1231 azx_release_device(azx_dev);
1232 snd_hda_power_down(apcm->codec);
1233 mutex_unlock(&chip->open_mutex);
1234 return err;
1235 }
1236 spin_lock_irqsave(&chip->reg_lock, flags);
1237 azx_dev->substream = substream;
1238 azx_dev->running = 0;
1239 spin_unlock_irqrestore(&chip->reg_lock, flags);
1240
1241 runtime->private_data = azx_dev;
1242 mutex_unlock(&chip->open_mutex);
1243 return 0;
1244 }
1245
1246 static int azx_pcm_close(struct snd_pcm_substream *substream)
1247 {
1248 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1249 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1250 struct azx *chip = apcm->chip;
1251 struct azx_dev *azx_dev = get_azx_dev(substream);
1252 unsigned long flags;
1253
1254 mutex_lock(&chip->open_mutex);
1255 spin_lock_irqsave(&chip->reg_lock, flags);
1256 azx_dev->substream = NULL;
1257 azx_dev->running = 0;
1258 spin_unlock_irqrestore(&chip->reg_lock, flags);
1259 azx_release_device(azx_dev);
1260 hinfo->ops.close(hinfo, apcm->codec, substream);
1261 snd_hda_power_down(apcm->codec);
1262 mutex_unlock(&chip->open_mutex);
1263 return 0;
1264 }
1265
1266 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1267 struct snd_pcm_hw_params *hw_params)
1268 {
1269 return snd_pcm_lib_malloc_pages(substream,
1270 params_buffer_bytes(hw_params));
1271 }
1272
1273 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1274 {
1275 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1276 struct azx_dev *azx_dev = get_azx_dev(substream);
1277 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1278
1279 /* reset BDL address */
1280 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1281 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1282 azx_sd_writel(azx_dev, SD_CTL, 0);
1283
1284 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1285
1286 return snd_pcm_lib_free_pages(substream);
1287 }
1288
1289 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1290 {
1291 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1292 struct azx *chip = apcm->chip;
1293 struct azx_dev *azx_dev = get_azx_dev(substream);
1294 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1295 struct snd_pcm_runtime *runtime = substream->runtime;
1296
1297 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1298 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1299 runtime->channels,
1300 runtime->format,
1301 hinfo->maxbps);
1302 if (!azx_dev->format_val) {
1303 snd_printk(KERN_ERR SFX
1304 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1305 runtime->rate, runtime->channels, runtime->format);
1306 return -EINVAL;
1307 }
1308
1309 snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1310 azx_dev->bufsize, azx_dev->format_val);
1311 if (azx_setup_periods(substream, azx_dev) < 0)
1312 return -EINVAL;
1313 azx_setup_controller(chip, azx_dev);
1314 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1315 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1316 else
1317 azx_dev->fifo_size = 0;
1318
1319 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1320 azx_dev->format_val, substream);
1321 }
1322
1323 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1324 {
1325 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1326 struct azx_dev *azx_dev = get_azx_dev(substream);
1327 struct azx *chip = apcm->chip;
1328 int err = 0;
1329
1330 spin_lock(&chip->reg_lock);
1331 switch (cmd) {
1332 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1333 case SNDRV_PCM_TRIGGER_RESUME:
1334 case SNDRV_PCM_TRIGGER_START:
1335 azx_stream_start(chip, azx_dev);
1336 azx_dev->running = 1;
1337 break;
1338 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1339 case SNDRV_PCM_TRIGGER_SUSPEND:
1340 case SNDRV_PCM_TRIGGER_STOP:
1341 azx_stream_stop(chip, azx_dev);
1342 azx_dev->running = 0;
1343 break;
1344 default:
1345 err = -EINVAL;
1346 }
1347 spin_unlock(&chip->reg_lock);
1348 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1349 cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1350 cmd == SNDRV_PCM_TRIGGER_STOP) {
1351 int timeout = 5000;
1352 while ((azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START) &&
1353 --timeout)
1354 ;
1355 }
1356 return err;
1357 }
1358
1359 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1360 {
1361 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1362 struct azx *chip = apcm->chip;
1363 struct azx_dev *azx_dev = get_azx_dev(substream);
1364 unsigned int pos;
1365
1366 if (chip->position_fix == POS_FIX_POSBUF ||
1367 chip->position_fix == POS_FIX_AUTO) {
1368 /* use the position buffer */
1369 pos = le32_to_cpu(*azx_dev->posbuf);
1370 if (chip->position_fix == POS_FIX_AUTO &&
1371 azx_dev->period_intr == 1 && !pos) {
1372 printk(KERN_WARNING
1373 "hda-intel: Invalid position buffer, "
1374 "using LPIB read method instead.\n");
1375 chip->position_fix = POS_FIX_NONE;
1376 goto read_lpib;
1377 }
1378 } else {
1379 read_lpib:
1380 /* read LPIB */
1381 pos = azx_sd_readl(azx_dev, SD_LPIB);
1382 if (chip->position_fix == POS_FIX_FIFO)
1383 pos += azx_dev->fifo_size;
1384 }
1385 if (pos >= azx_dev->bufsize)
1386 pos = 0;
1387 return bytes_to_frames(substream->runtime, pos);
1388 }
1389
1390 static struct snd_pcm_ops azx_pcm_ops = {
1391 .open = azx_pcm_open,
1392 .close = azx_pcm_close,
1393 .ioctl = snd_pcm_lib_ioctl,
1394 .hw_params = azx_pcm_hw_params,
1395 .hw_free = azx_pcm_hw_free,
1396 .prepare = azx_pcm_prepare,
1397 .trigger = azx_pcm_trigger,
1398 .pointer = azx_pcm_pointer,
1399 .page = snd_pcm_sgbuf_ops_page,
1400 };
1401
1402 static void azx_pcm_free(struct snd_pcm *pcm)
1403 {
1404 kfree(pcm->private_data);
1405 }
1406
1407 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1408 struct hda_pcm *cpcm)
1409 {
1410 int err;
1411 struct snd_pcm *pcm;
1412 struct azx_pcm *apcm;
1413
1414 /* if no substreams are defined for both playback and capture,
1415 * it's just a placeholder. ignore it.
1416 */
1417 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1418 return 0;
1419
1420 snd_assert(cpcm->name, return -EINVAL);
1421
1422 err = snd_pcm_new(chip->card, cpcm->name, cpcm->device,
1423 cpcm->stream[0].substreams,
1424 cpcm->stream[1].substreams,
1425 &pcm);
1426 if (err < 0)
1427 return err;
1428 strcpy(pcm->name, cpcm->name);
1429 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1430 if (apcm == NULL)
1431 return -ENOMEM;
1432 apcm->chip = chip;
1433 apcm->codec = codec;
1434 apcm->hinfo[0] = &cpcm->stream[0];
1435 apcm->hinfo[1] = &cpcm->stream[1];
1436 pcm->private_data = apcm;
1437 pcm->private_free = azx_pcm_free;
1438 if (cpcm->stream[0].substreams)
1439 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1440 if (cpcm->stream[1].substreams)
1441 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1442 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1443 snd_dma_pci_data(chip->pci),
1444 1024 * 64, 1024 * 1024);
1445 chip->pcm[cpcm->device] = pcm;
1446 return 0;
1447 }
1448
1449 static int __devinit azx_pcm_create(struct azx *chip)
1450 {
1451 static const char *dev_name[HDA_PCM_NTYPES] = {
1452 "Audio", "SPDIF", "HDMI", "Modem"
1453 };
1454 /* starting device index for each PCM type */
1455 static int dev_idx[HDA_PCM_NTYPES] = {
1456 [HDA_PCM_TYPE_AUDIO] = 0,
1457 [HDA_PCM_TYPE_SPDIF] = 1,
1458 [HDA_PCM_TYPE_HDMI] = 3,
1459 [HDA_PCM_TYPE_MODEM] = 6
1460 };
1461 /* normal audio device indices; not linear to keep compatibility */
1462 static int audio_idx[4] = { 0, 2, 4, 5 };
1463 struct hda_codec *codec;
1464 int c, err;
1465 int num_devs[HDA_PCM_NTYPES];
1466
1467 err = snd_hda_build_pcms(chip->bus);
1468 if (err < 0)
1469 return err;
1470
1471 /* create audio PCMs */
1472 memset(num_devs, 0, sizeof(num_devs));
1473 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1474 for (c = 0; c < codec->num_pcms; c++) {
1475 struct hda_pcm *cpcm = &codec->pcm_info[c];
1476 int type = cpcm->pcm_type;
1477 switch (type) {
1478 case HDA_PCM_TYPE_AUDIO:
1479 if (num_devs[type] >= ARRAY_SIZE(audio_idx)) {
1480 snd_printk(KERN_WARNING
1481 "Too many audio devices\n");
1482 continue;
1483 }
1484 cpcm->device = audio_idx[num_devs[type]];
1485 break;
1486 case HDA_PCM_TYPE_SPDIF:
1487 case HDA_PCM_TYPE_HDMI:
1488 case HDA_PCM_TYPE_MODEM:
1489 if (num_devs[type]) {
1490 snd_printk(KERN_WARNING
1491 "%s already defined\n",
1492 dev_name[type]);
1493 continue;
1494 }
1495 cpcm->device = dev_idx[type];
1496 break;
1497 default:
1498 snd_printk(KERN_WARNING
1499 "Invalid PCM type %d\n", type);
1500 continue;
1501 }
1502 num_devs[type]++;
1503 err = create_codec_pcm(chip, codec, cpcm);
1504 if (err < 0)
1505 return err;
1506 }
1507 }
1508 return 0;
1509 }
1510
1511 /*
1512 * mixer creation - all stuff is implemented in hda module
1513 */
1514 static int __devinit azx_mixer_create(struct azx *chip)
1515 {
1516 return snd_hda_build_controls(chip->bus);
1517 }
1518
1519
1520 /*
1521 * initialize SD streams
1522 */
1523 static int __devinit azx_init_stream(struct azx *chip)
1524 {
1525 int i;
1526
1527 /* initialize each stream (aka device)
1528 * assign the starting bdl address to each stream (device)
1529 * and initialize
1530 */
1531 for (i = 0; i < chip->num_streams; i++) {
1532 struct azx_dev *azx_dev = &chip->azx_dev[i];
1533 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1534 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1535 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1536 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1537 azx_dev->sd_int_sta_mask = 1 << i;
1538 /* stream tag: must be non-zero and unique */
1539 azx_dev->index = i;
1540 azx_dev->stream_tag = i + 1;
1541 }
1542
1543 return 0;
1544 }
1545
1546 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1547 {
1548 if (request_irq(chip->pci->irq, azx_interrupt,
1549 chip->msi ? 0 : IRQF_SHARED,
1550 "HDA Intel", chip)) {
1551 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1552 "disabling device\n", chip->pci->irq);
1553 if (do_disconnect)
1554 snd_card_disconnect(chip->card);
1555 return -1;
1556 }
1557 chip->irq = chip->pci->irq;
1558 pci_intx(chip->pci, !chip->msi);
1559 return 0;
1560 }
1561
1562
1563 static void azx_stop_chip(struct azx *chip)
1564 {
1565 if (!chip->initialized)
1566 return;
1567
1568 /* disable interrupts */
1569 azx_int_disable(chip);
1570 azx_int_clear(chip);
1571
1572 /* disable CORB/RIRB */
1573 azx_free_cmd_io(chip);
1574
1575 /* disable position buffer */
1576 azx_writel(chip, DPLBASE, 0);
1577 azx_writel(chip, DPUBASE, 0);
1578
1579 chip->initialized = 0;
1580 }
1581
1582 #ifdef CONFIG_SND_HDA_POWER_SAVE
1583 /* power-up/down the controller */
1584 static void azx_power_notify(struct hda_codec *codec)
1585 {
1586 struct azx *chip = codec->bus->private_data;
1587 struct hda_codec *c;
1588 int power_on = 0;
1589
1590 list_for_each_entry(c, &codec->bus->codec_list, list) {
1591 if (c->power_on) {
1592 power_on = 1;
1593 break;
1594 }
1595 }
1596 if (power_on)
1597 azx_init_chip(chip);
1598 else if (chip->running && power_save_controller)
1599 azx_stop_chip(chip);
1600 }
1601 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1602
1603 #ifdef CONFIG_PM
1604 /*
1605 * power management
1606 */
1607 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1608 {
1609 struct snd_card *card = pci_get_drvdata(pci);
1610 struct azx *chip = card->private_data;
1611 int i;
1612
1613 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1614 for (i = 0; i < AZX_MAX_PCMS; i++)
1615 snd_pcm_suspend_all(chip->pcm[i]);
1616 if (chip->initialized)
1617 snd_hda_suspend(chip->bus, state);
1618 azx_stop_chip(chip);
1619 if (chip->irq >= 0) {
1620 synchronize_irq(chip->irq);
1621 free_irq(chip->irq, chip);
1622 chip->irq = -1;
1623 }
1624 if (chip->msi)
1625 pci_disable_msi(chip->pci);
1626 pci_disable_device(pci);
1627 pci_save_state(pci);
1628 pci_set_power_state(pci, pci_choose_state(pci, state));
1629 return 0;
1630 }
1631
1632 static int azx_resume(struct pci_dev *pci)
1633 {
1634 struct snd_card *card = pci_get_drvdata(pci);
1635 struct azx *chip = card->private_data;
1636
1637 pci_set_power_state(pci, PCI_D0);
1638 pci_restore_state(pci);
1639 if (pci_enable_device(pci) < 0) {
1640 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1641 "disabling device\n");
1642 snd_card_disconnect(card);
1643 return -EIO;
1644 }
1645 pci_set_master(pci);
1646 if (chip->msi)
1647 if (pci_enable_msi(pci) < 0)
1648 chip->msi = 0;
1649 if (azx_acquire_irq(chip, 1) < 0)
1650 return -EIO;
1651 azx_init_pci(chip);
1652
1653 if (snd_hda_codecs_inuse(chip->bus))
1654 azx_init_chip(chip);
1655
1656 snd_hda_resume(chip->bus);
1657 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1658 return 0;
1659 }
1660 #endif /* CONFIG_PM */
1661
1662
1663 /*
1664 * destructor
1665 */
1666 static int azx_free(struct azx *chip)
1667 {
1668 int i;
1669
1670 if (chip->initialized) {
1671 for (i = 0; i < chip->num_streams; i++)
1672 azx_stream_stop(chip, &chip->azx_dev[i]);
1673 azx_stop_chip(chip);
1674 }
1675
1676 if (chip->irq >= 0) {
1677 synchronize_irq(chip->irq);
1678 free_irq(chip->irq, (void*)chip);
1679 }
1680 if (chip->msi)
1681 pci_disable_msi(chip->pci);
1682 if (chip->remap_addr)
1683 iounmap(chip->remap_addr);
1684
1685 if (chip->azx_dev) {
1686 for (i = 0; i < chip->num_streams; i++)
1687 if (chip->azx_dev[i].bdl.area)
1688 snd_dma_free_pages(&chip->azx_dev[i].bdl);
1689 }
1690 if (chip->rb.area)
1691 snd_dma_free_pages(&chip->rb);
1692 if (chip->posbuf.area)
1693 snd_dma_free_pages(&chip->posbuf);
1694 pci_release_regions(chip->pci);
1695 pci_disable_device(chip->pci);
1696 kfree(chip->azx_dev);
1697 kfree(chip);
1698
1699 return 0;
1700 }
1701
1702 static int azx_dev_free(struct snd_device *device)
1703 {
1704 return azx_free(device->device_data);
1705 }
1706
1707 /*
1708 * white/black-listing for position_fix
1709 */
1710 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1711 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE),
1712 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_NONE),
1713 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_NONE),
1714 {}
1715 };
1716
1717 static int __devinit check_position_fix(struct azx *chip, int fix)
1718 {
1719 const struct snd_pci_quirk *q;
1720
1721 if (fix == POS_FIX_AUTO) {
1722 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1723 if (q) {
1724 printk(KERN_INFO
1725 "hda_intel: position_fix set to %d "
1726 "for device %04x:%04x\n",
1727 q->value, q->subvendor, q->subdevice);
1728 return q->value;
1729 }
1730 }
1731 return fix;
1732 }
1733
1734 /*
1735 * black-lists for probe_mask
1736 */
1737 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
1738 /* Thinkpad often breaks the controller communication when accessing
1739 * to the non-working (or non-existing) modem codec slot.
1740 */
1741 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1742 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1743 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1744 {}
1745 };
1746
1747 static void __devinit check_probe_mask(struct azx *chip, int dev)
1748 {
1749 const struct snd_pci_quirk *q;
1750
1751 if (probe_mask[dev] == -1) {
1752 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1753 if (q) {
1754 printk(KERN_INFO
1755 "hda_intel: probe_mask set to 0x%x "
1756 "for device %04x:%04x\n",
1757 q->value, q->subvendor, q->subdevice);
1758 probe_mask[dev] = q->value;
1759 }
1760 }
1761 }
1762
1763
1764 /*
1765 * constructor
1766 */
1767 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1768 int dev, int driver_type,
1769 struct azx **rchip)
1770 {
1771 struct azx *chip;
1772 int i, err;
1773 unsigned short gcap;
1774 static struct snd_device_ops ops = {
1775 .dev_free = azx_dev_free,
1776 };
1777
1778 *rchip = NULL;
1779
1780 err = pci_enable_device(pci);
1781 if (err < 0)
1782 return err;
1783
1784 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1785 if (!chip) {
1786 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1787 pci_disable_device(pci);
1788 return -ENOMEM;
1789 }
1790
1791 spin_lock_init(&chip->reg_lock);
1792 mutex_init(&chip->open_mutex);
1793 chip->card = card;
1794 chip->pci = pci;
1795 chip->irq = -1;
1796 chip->driver_type = driver_type;
1797 chip->msi = enable_msi;
1798
1799 chip->position_fix = check_position_fix(chip, position_fix[dev]);
1800 check_probe_mask(chip, dev);
1801
1802 chip->single_cmd = single_cmd;
1803
1804 #if BITS_PER_LONG != 64
1805 /* Fix up base address on ULI M5461 */
1806 if (chip->driver_type == AZX_DRIVER_ULI) {
1807 u16 tmp3;
1808 pci_read_config_word(pci, 0x40, &tmp3);
1809 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1810 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1811 }
1812 #endif
1813
1814 err = pci_request_regions(pci, "ICH HD audio");
1815 if (err < 0) {
1816 kfree(chip);
1817 pci_disable_device(pci);
1818 return err;
1819 }
1820
1821 chip->addr = pci_resource_start(pci, 0);
1822 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1823 if (chip->remap_addr == NULL) {
1824 snd_printk(KERN_ERR SFX "ioremap error\n");
1825 err = -ENXIO;
1826 goto errout;
1827 }
1828
1829 if (chip->msi)
1830 if (pci_enable_msi(pci) < 0)
1831 chip->msi = 0;
1832
1833 if (azx_acquire_irq(chip, 0) < 0) {
1834 err = -EBUSY;
1835 goto errout;
1836 }
1837
1838 pci_set_master(pci);
1839 synchronize_irq(chip->irq);
1840
1841 gcap = azx_readw(chip, GCAP);
1842 snd_printdd("chipset global capabilities = 0x%x\n", gcap);
1843
1844 /* allow 64bit DMA address if supported by H/W */
1845 if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
1846 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
1847
1848 /* read number of streams from GCAP register instead of using
1849 * hardcoded value
1850 */
1851 chip->capture_streams = (gcap >> 8) & 0x0f;
1852 chip->playback_streams = (gcap >> 12) & 0x0f;
1853 if (!chip->playback_streams && !chip->capture_streams) {
1854 /* gcap didn't give any info, switching to old method */
1855
1856 switch (chip->driver_type) {
1857 case AZX_DRIVER_ULI:
1858 chip->playback_streams = ULI_NUM_PLAYBACK;
1859 chip->capture_streams = ULI_NUM_CAPTURE;
1860 break;
1861 case AZX_DRIVER_ATIHDMI:
1862 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1863 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1864 break;
1865 default:
1866 chip->playback_streams = ICH6_NUM_PLAYBACK;
1867 chip->capture_streams = ICH6_NUM_CAPTURE;
1868 break;
1869 }
1870 }
1871 chip->capture_index_offset = 0;
1872 chip->playback_index_offset = chip->capture_streams;
1873 chip->num_streams = chip->playback_streams + chip->capture_streams;
1874 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1875 GFP_KERNEL);
1876 if (!chip->azx_dev) {
1877 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1878 goto errout;
1879 }
1880
1881 for (i = 0; i < chip->num_streams; i++) {
1882 /* allocate memory for the BDL for each stream */
1883 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1884 snd_dma_pci_data(chip->pci),
1885 BDL_SIZE, &chip->azx_dev[i].bdl);
1886 if (err < 0) {
1887 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1888 goto errout;
1889 }
1890 }
1891 /* allocate memory for the position buffer */
1892 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1893 snd_dma_pci_data(chip->pci),
1894 chip->num_streams * 8, &chip->posbuf);
1895 if (err < 0) {
1896 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1897 goto errout;
1898 }
1899 /* allocate CORB/RIRB */
1900 if (!chip->single_cmd) {
1901 err = azx_alloc_cmd_io(chip);
1902 if (err < 0)
1903 goto errout;
1904 }
1905
1906 /* initialize streams */
1907 azx_init_stream(chip);
1908
1909 /* initialize chip */
1910 azx_init_pci(chip);
1911 azx_init_chip(chip);
1912
1913 /* codec detection */
1914 if (!chip->codec_mask) {
1915 snd_printk(KERN_ERR SFX "no codecs found!\n");
1916 err = -ENODEV;
1917 goto errout;
1918 }
1919
1920 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1921 if (err <0) {
1922 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1923 goto errout;
1924 }
1925
1926 strcpy(card->driver, "HDA-Intel");
1927 strcpy(card->shortname, driver_short_names[chip->driver_type]);
1928 sprintf(card->longname, "%s at 0x%lx irq %i",
1929 card->shortname, chip->addr, chip->irq);
1930
1931 *rchip = chip;
1932 return 0;
1933
1934 errout:
1935 azx_free(chip);
1936 return err;
1937 }
1938
1939 static void power_down_all_codecs(struct azx *chip)
1940 {
1941 #ifdef CONFIG_SND_HDA_POWER_SAVE
1942 /* The codecs were powered up in snd_hda_codec_new().
1943 * Now all initialization done, so turn them down if possible
1944 */
1945 struct hda_codec *codec;
1946 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1947 snd_hda_power_down(codec);
1948 }
1949 #endif
1950 }
1951
1952 static int __devinit azx_probe(struct pci_dev *pci,
1953 const struct pci_device_id *pci_id)
1954 {
1955 static int dev;
1956 struct snd_card *card;
1957 struct azx *chip;
1958 int err;
1959
1960 if (dev >= SNDRV_CARDS)
1961 return -ENODEV;
1962 if (!enable[dev]) {
1963 dev++;
1964 return -ENOENT;
1965 }
1966
1967 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1968 if (!card) {
1969 snd_printk(KERN_ERR SFX "Error creating card!\n");
1970 return -ENOMEM;
1971 }
1972
1973 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1974 if (err < 0) {
1975 snd_card_free(card);
1976 return err;
1977 }
1978 card->private_data = chip;
1979
1980 /* create codec instances */
1981 err = azx_codec_create(chip, model[dev], probe_mask[dev]);
1982 if (err < 0) {
1983 snd_card_free(card);
1984 return err;
1985 }
1986
1987 /* create PCM streams */
1988 err = azx_pcm_create(chip);
1989 if (err < 0) {
1990 snd_card_free(card);
1991 return err;
1992 }
1993
1994 /* create mixer controls */
1995 err = azx_mixer_create(chip);
1996 if (err < 0) {
1997 snd_card_free(card);
1998 return err;
1999 }
2000
2001 snd_card_set_dev(card, &pci->dev);
2002
2003 err = snd_card_register(card);
2004 if (err < 0) {
2005 snd_card_free(card);
2006 return err;
2007 }
2008
2009 pci_set_drvdata(pci, card);
2010 chip->running = 1;
2011 power_down_all_codecs(chip);
2012
2013 dev++;
2014 return err;
2015 }
2016
2017 static void __devexit azx_remove(struct pci_dev *pci)
2018 {
2019 snd_card_free(pci_get_drvdata(pci));
2020 pci_set_drvdata(pci, NULL);
2021 }
2022
2023 /* PCI IDs */
2024 static struct pci_device_id azx_ids[] = {
2025 /* ICH 6..10 */
2026 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2027 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2028 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2029 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2030 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2031 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2032 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2033 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2034 /* SCH */
2035 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2036 /* ATI SB 450/600 */
2037 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2038 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2039 /* ATI HDMI */
2040 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2041 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2042 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2043 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2044 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2045 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2046 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2047 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2048 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2049 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2050 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2051 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2052 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2053 /* VIA VT8251/VT8237A */
2054 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2055 /* SIS966 */
2056 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2057 /* ULI M5461 */
2058 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2059 /* NVIDIA MCP */
2060 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2061 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2062 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2063 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2064 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2065 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2066 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2067 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2068 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2069 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2070 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2071 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2072 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2073 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2074 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2075 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2076 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2077 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2078 { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA },
2079 { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA },
2080 { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA },
2081 { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA },
2082 { 0, }
2083 };
2084 MODULE_DEVICE_TABLE(pci, azx_ids);
2085
2086 /* pci_driver definition */
2087 static struct pci_driver driver = {
2088 .name = "HDA Intel",
2089 .id_table = azx_ids,
2090 .probe = azx_probe,
2091 .remove = __devexit_p(azx_remove),
2092 #ifdef CONFIG_PM
2093 .suspend = azx_suspend,
2094 .resume = azx_resume,
2095 #endif
2096 };
2097
2098 static int __init alsa_card_azx_init(void)
2099 {
2100 return pci_register_driver(&driver);
2101 }
2102
2103 static void __exit alsa_card_azx_exit(void)
2104 {
2105 pci_unregister_driver(&driver);
2106 }
2107
2108 module_init(alsa_card_azx_init)
2109 module_exit(alsa_card_azx_exit)
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