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MIPS: TXx9: Add __init tag for tx4938_pcic1_map_irq.
[linux-2.6/verdex.git] / include / asm-x86 / processor.h
blob5eaf9bf0a62398b84c257f627ae6a6f8273e8b7d
1 #ifndef ASM_X86__PROCESSOR_H
2 #define ASM_X86__PROCESSOR_H
3
4 #include <asm/processor-flags.h>
5
6 /* Forward declaration, a strange C thing */
7 struct task_struct;
8 struct mm_struct;
9
10 #include <asm/vm86.h>
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
17 #include <asm/system.h>
18 #include <asm/page.h>
19 #include <asm/percpu.h>
20 #include <asm/msr.h>
21 #include <asm/desc_defs.h>
22 #include <asm/nops.h>
23 #include <asm/ds.h>
24
25 #include <linux/personality.h>
26 #include <linux/cpumask.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/init.h>
30
31 /*
32 * Default implementation of macro that returns current
33 * instruction pointer ("program counter").
34 */
35 static inline void *current_text_addr(void)
36 {
37 void *pc;
38
39 asm volatile("mov $1f, %0; 1:":"=r" (pc));
40
41 return pc;
42 }
43
44 #ifdef CONFIG_X86_VSMP
45 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
46 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
47 #else
48 # define ARCH_MIN_TASKALIGN 16
49 # define ARCH_MIN_MMSTRUCT_ALIGN 0
50 #endif
51
52 /*
53 * CPU type and hardware bug flags. Kept separately for each CPU.
54 * Members of this structure are referenced in head.S, so think twice
55 * before touching them. [mj]
56 */
57
58 struct cpuinfo_x86 {
59 __u8 x86; /* CPU family */
60 __u8 x86_vendor; /* CPU vendor */
61 __u8 x86_model;
62 __u8 x86_mask;
63 #ifdef CONFIG_X86_32
64 char wp_works_ok; /* It doesn't on 386's */
65
66 /* Problems on some 486Dx4's and old 386's: */
67 char hlt_works_ok;
68 char hard_math;
69 char rfu;
70 char fdiv_bug;
71 char f00f_bug;
72 char coma_bug;
73 char pad0;
74 #else
75 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
76 int x86_tlbsize;
77 __u8 x86_virt_bits;
78 __u8 x86_phys_bits;
79 /* CPUID returned core id bits: */
80 __u8 x86_coreid_bits;
81 /* Max extended CPUID function supported: */
82 __u32 extended_cpuid_level;
83 #endif
84 /* Maximum supported CPUID level, -1=no CPUID: */
85 int cpuid_level;
86 __u32 x86_capability[NCAPINTS];
87 char x86_vendor_id[16];
88 char x86_model_id[64];
89 /* in KB - valid for CPUS which support this call: */
90 int x86_cache_size;
91 int x86_cache_alignment; /* In bytes */
92 int x86_power;
93 unsigned long loops_per_jiffy;
94 #ifdef CONFIG_SMP
95 /* cpus sharing the last level cache: */
96 cpumask_t llc_shared_map;
97 #endif
98 /* cpuid returned max cores value: */
99 u16 x86_max_cores;
100 u16 apicid;
101 u16 initial_apicid;
102 u16 x86_clflush_size;
103 #ifdef CONFIG_SMP
104 /* number of cores as seen by the OS: */
105 u16 booted_cores;
106 /* Physical processor id: */
107 u16 phys_proc_id;
108 /* Core id: */
109 u16 cpu_core_id;
110 /* Index into per_cpu list: */
111 u16 cpu_index;
112 #endif
113 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
114
115 #define X86_VENDOR_INTEL 0
116 #define X86_VENDOR_CYRIX 1
117 #define X86_VENDOR_AMD 2
118 #define X86_VENDOR_UMC 3
119 #define X86_VENDOR_CENTAUR 5
120 #define X86_VENDOR_TRANSMETA 7
121 #define X86_VENDOR_NSC 8
122 #define X86_VENDOR_NUM 9
123
124 #define X86_VENDOR_UNKNOWN 0xff
125
126 /*
127 * capabilities of CPUs
128 */
129 extern struct cpuinfo_x86 boot_cpu_data;
130 extern struct cpuinfo_x86 new_cpu_data;
131
132 extern struct tss_struct doublefault_tss;
133 extern __u32 cleared_cpu_caps[NCAPINTS];
134
135 #ifdef CONFIG_SMP
136 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
137 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
138 #define current_cpu_data __get_cpu_var(cpu_info)
139 #else
140 #define cpu_data(cpu) boot_cpu_data
141 #define current_cpu_data boot_cpu_data
142 #endif
143
144 extern const struct seq_operations cpuinfo_op;
145
146 static inline int hlt_works(int cpu)
147 {
148 #ifdef CONFIG_X86_32
149 return cpu_data(cpu).hlt_works_ok;
150 #else
151 return 1;
152 #endif
153 }
154
155 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
156
157 extern void cpu_detect(struct cpuinfo_x86 *c);
158
159 extern struct pt_regs *idle_regs(struct pt_regs *);
160
161 extern void early_cpu_init(void);
162 extern void identify_boot_cpu(void);
163 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
164 extern void print_cpu_info(struct cpuinfo_x86 *);
165 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
166 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
167 extern unsigned short num_cache_leaves;
168
169 #if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64)
170 extern void detect_ht(struct cpuinfo_x86 *c);
171 #else
172 static inline void detect_ht(struct cpuinfo_x86 *c) {}
173 #endif
174
175 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
176 unsigned int *ecx, unsigned int *edx)
177 {
178 /* ecx is often an input as well as an output. */
179 asm("cpuid"
180 : "=a" (*eax),
181 "=b" (*ebx),
182 "=c" (*ecx),
183 "=d" (*edx)
184 : "0" (*eax), "2" (*ecx));
185 }
186
187 static inline void load_cr3(pgd_t *pgdir)
188 {
189 write_cr3(__pa(pgdir));
190 }
191
192 #ifdef CONFIG_X86_32
193 /* This is the TSS defined by the hardware. */
194 struct x86_hw_tss {
195 unsigned short back_link, __blh;
196 unsigned long sp0;
197 unsigned short ss0, __ss0h;
198 unsigned long sp1;
199 /* ss1 caches MSR_IA32_SYSENTER_CS: */
200 unsigned short ss1, __ss1h;
201 unsigned long sp2;
202 unsigned short ss2, __ss2h;
203 unsigned long __cr3;
204 unsigned long ip;
205 unsigned long flags;
206 unsigned long ax;
207 unsigned long cx;
208 unsigned long dx;
209 unsigned long bx;
210 unsigned long sp;
211 unsigned long bp;
212 unsigned long si;
213 unsigned long di;
214 unsigned short es, __esh;
215 unsigned short cs, __csh;
216 unsigned short ss, __ssh;
217 unsigned short ds, __dsh;
218 unsigned short fs, __fsh;
219 unsigned short gs, __gsh;
220 unsigned short ldt, __ldth;
221 unsigned short trace;
222 unsigned short io_bitmap_base;
223
224 } __attribute__((packed));
225 #else
226 struct x86_hw_tss {
227 u32 reserved1;
228 u64 sp0;
229 u64 sp1;
230 u64 sp2;
231 u64 reserved2;
232 u64 ist[7];
233 u32 reserved3;
234 u32 reserved4;
235 u16 reserved5;
236 u16 io_bitmap_base;
237
238 } __attribute__((packed)) ____cacheline_aligned;
239 #endif
240
241 /*
242 * IO-bitmap sizes:
243 */
244 #define IO_BITMAP_BITS 65536
245 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
246 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
247 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
248 #define INVALID_IO_BITMAP_OFFSET 0x8000
249 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
250
251 struct tss_struct {
252 /*
253 * The hardware state:
254 */
255 struct x86_hw_tss x86_tss;
256
257 /*
258 * The extra 1 is there because the CPU will access an
259 * additional byte beyond the end of the IO permission
260 * bitmap. The extra byte must be all 1 bits, and must
261 * be within the limit.
262 */
263 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
264 /*
265 * Cache the current maximum and the last task that used the bitmap:
266 */
267 unsigned long io_bitmap_max;
268 struct thread_struct *io_bitmap_owner;
269
270 /*
271 * .. and then another 0x100 bytes for the emergency kernel stack:
272 */
273 unsigned long stack[64];
274
275 } ____cacheline_aligned;
276
277 DECLARE_PER_CPU(struct tss_struct, init_tss);
278
279 /*
280 * Save the original ist values for checking stack pointers during debugging
281 */
282 struct orig_ist {
283 unsigned long ist[7];
284 };
285
286 #define MXCSR_DEFAULT 0x1f80
287
288 struct i387_fsave_struct {
289 u32 cwd; /* FPU Control Word */
290 u32 swd; /* FPU Status Word */
291 u32 twd; /* FPU Tag Word */
292 u32 fip; /* FPU IP Offset */
293 u32 fcs; /* FPU IP Selector */
294 u32 foo; /* FPU Operand Pointer Offset */
295 u32 fos; /* FPU Operand Pointer Selector */
296
297 /* 8*10 bytes for each FP-reg = 80 bytes: */
298 u32 st_space[20];
299
300 /* Software status information [not touched by FSAVE ]: */
301 u32 status;
302 };
303
304 struct i387_fxsave_struct {
305 u16 cwd; /* Control Word */
306 u16 swd; /* Status Word */
307 u16 twd; /* Tag Word */
308 u16 fop; /* Last Instruction Opcode */
309 union {
310 struct {
311 u64 rip; /* Instruction Pointer */
312 u64 rdp; /* Data Pointer */
313 };
314 struct {
315 u32 fip; /* FPU IP Offset */
316 u32 fcs; /* FPU IP Selector */
317 u32 foo; /* FPU Operand Offset */
318 u32 fos; /* FPU Operand Selector */
319 };
320 };
321 u32 mxcsr; /* MXCSR Register State */
322 u32 mxcsr_mask; /* MXCSR Mask */
323
324 /* 8*16 bytes for each FP-reg = 128 bytes: */
325 u32 st_space[32];
326
327 /* 16*16 bytes for each XMM-reg = 256 bytes: */
328 u32 xmm_space[64];
329
330 u32 padding[24];
331
332 } __attribute__((aligned(16)));
333
334 struct i387_soft_struct {
335 u32 cwd;
336 u32 swd;
337 u32 twd;
338 u32 fip;
339 u32 fcs;
340 u32 foo;
341 u32 fos;
342 /* 8*10 bytes for each FP-reg = 80 bytes: */
343 u32 st_space[20];
344 u8 ftop;
345 u8 changed;
346 u8 lookahead;
347 u8 no_update;
348 u8 rm;
349 u8 alimit;
350 struct info *info;
351 u32 entry_eip;
352 };
353
354 union thread_xstate {
355 struct i387_fsave_struct fsave;
356 struct i387_fxsave_struct fxsave;
357 struct i387_soft_struct soft;
358 };
359
360 #ifdef CONFIG_X86_64
361 DECLARE_PER_CPU(struct orig_ist, orig_ist);
362 #endif
363
364 extern void print_cpu_info(struct cpuinfo_x86 *);
365 extern unsigned int xstate_size;
366 extern void free_thread_xstate(struct task_struct *);
367 extern struct kmem_cache *task_xstate_cachep;
368 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
369 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
370 extern unsigned short num_cache_leaves;
371
372 struct thread_struct {
373 /* Cached TLS descriptors: */
374 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
375 unsigned long sp0;
376 unsigned long sp;
377 #ifdef CONFIG_X86_32
378 unsigned long sysenter_cs;
379 #else
380 unsigned long usersp; /* Copy from PDA */
381 unsigned short es;
382 unsigned short ds;
383 unsigned short fsindex;
384 unsigned short gsindex;
385 #endif
386 unsigned long ip;
387 unsigned long fs;
388 unsigned long gs;
389 /* Hardware debugging registers: */
390 unsigned long debugreg0;
391 unsigned long debugreg1;
392 unsigned long debugreg2;
393 unsigned long debugreg3;
394 unsigned long debugreg6;
395 unsigned long debugreg7;
396 /* Fault info: */
397 unsigned long cr2;
398 unsigned long trap_no;
399 unsigned long error_code;
400 /* floating point and extended processor state */
401 union thread_xstate *xstate;
402 #ifdef CONFIG_X86_32
403 /* Virtual 86 mode info */
404 struct vm86_struct __user *vm86_info;
405 unsigned long screen_bitmap;
406 unsigned long v86flags;
407 unsigned long v86mask;
408 unsigned long saved_sp0;
409 unsigned int saved_fs;
410 unsigned int saved_gs;
411 #endif
412 /* IO permissions: */
413 unsigned long *io_bitmap_ptr;
414 unsigned long iopl;
415 /* Max allowed port in the bitmap, in bytes: */
416 unsigned io_bitmap_max;
417 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
418 unsigned long debugctlmsr;
419 #ifdef CONFIG_X86_DS
420 /* Debug Store context; see include/asm-x86/ds.h; goes into MSR_IA32_DS_AREA */
421 struct ds_context *ds_ctx;
422 #endif /* CONFIG_X86_DS */
423 #ifdef CONFIG_X86_PTRACE_BTS
424 /* the signal to send on a bts buffer overflow */
425 unsigned int bts_ovfl_signal;
426 #endif /* CONFIG_X86_PTRACE_BTS */
427 };
428
429 static inline unsigned long native_get_debugreg(int regno)
430 {
431 unsigned long val = 0; /* Damn you, gcc! */
432
433 switch (regno) {
434 case 0:
435 asm("mov %%db0, %0" :"=r" (val));
436 break;
437 case 1:
438 asm("mov %%db1, %0" :"=r" (val));
439 break;
440 case 2:
441 asm("mov %%db2, %0" :"=r" (val));
442 break;
443 case 3:
444 asm("mov %%db3, %0" :"=r" (val));
445 break;
446 case 6:
447 asm("mov %%db6, %0" :"=r" (val));
448 break;
449 case 7:
450 asm("mov %%db7, %0" :"=r" (val));
451 break;
452 default:
453 BUG();
454 }
455 return val;
456 }
457
458 static inline void native_set_debugreg(int regno, unsigned long value)
459 {
460 switch (regno) {
461 case 0:
462 asm("mov %0, %%db0" ::"r" (value));
463 break;
464 case 1:
465 asm("mov %0, %%db1" ::"r" (value));
466 break;
467 case 2:
468 asm("mov %0, %%db2" ::"r" (value));
469 break;
470 case 3:
471 asm("mov %0, %%db3" ::"r" (value));
472 break;
473 case 6:
474 asm("mov %0, %%db6" ::"r" (value));
475 break;
476 case 7:
477 asm("mov %0, %%db7" ::"r" (value));
478 break;
479 default:
480 BUG();
481 }
482 }
483
484 /*
485 * Set IOPL bits in EFLAGS from given mask
486 */
487 static inline void native_set_iopl_mask(unsigned mask)
488 {
489 #ifdef CONFIG_X86_32
490 unsigned int reg;
491
492 asm volatile ("pushfl;"
493 "popl %0;"
494 "andl %1, %0;"
495 "orl %2, %0;"
496 "pushl %0;"
497 "popfl"
498 : "=&r" (reg)
499 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
500 #endif
501 }
502
503 static inline void
504 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
505 {
506 tss->x86_tss.sp0 = thread->sp0;
507 #ifdef CONFIG_X86_32
508 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
509 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
510 tss->x86_tss.ss1 = thread->sysenter_cs;
511 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
512 }
513 #endif
514 }
515
516 static inline void native_swapgs(void)
517 {
518 #ifdef CONFIG_X86_64
519 asm volatile("swapgs" ::: "memory");
520 #endif
521 }
522
523 #ifdef CONFIG_PARAVIRT
524 #include <asm/paravirt.h>
525 #else
526 #define __cpuid native_cpuid
527 #define paravirt_enabled() 0
528
529 /*
530 * These special macros can be used to get or set a debugging register
531 */
532 #define get_debugreg(var, register) \
533 (var) = native_get_debugreg(register)
534 #define set_debugreg(value, register) \
535 native_set_debugreg(register, value)
536
537 static inline void load_sp0(struct tss_struct *tss,
538 struct thread_struct *thread)
539 {
540 native_load_sp0(tss, thread);
541 }
542
543 #define set_iopl_mask native_set_iopl_mask
544 #endif /* CONFIG_PARAVIRT */
545
546 /*
547 * Save the cr4 feature set we're using (ie
548 * Pentium 4MB enable and PPro Global page
549 * enable), so that any CPU's that boot up
550 * after us can get the correct flags.
551 */
552 extern unsigned long mmu_cr4_features;
553
554 static inline void set_in_cr4(unsigned long mask)
555 {
556 unsigned cr4;
557
558 mmu_cr4_features |= mask;
559 cr4 = read_cr4();
560 cr4 |= mask;
561 write_cr4(cr4);
562 }
563
564 static inline void clear_in_cr4(unsigned long mask)
565 {
566 unsigned cr4;
567
568 mmu_cr4_features &= ~mask;
569 cr4 = read_cr4();
570 cr4 &= ~mask;
571 write_cr4(cr4);
572 }
573
574 struct microcode_header {
575 unsigned int hdrver;
576 unsigned int rev;
577 unsigned int date;
578 unsigned int sig;
579 unsigned int cksum;
580 unsigned int ldrver;
581 unsigned int pf;
582 unsigned int datasize;
583 unsigned int totalsize;
584 unsigned int reserved[3];
585 };
586
587 struct microcode {
588 struct microcode_header hdr;
589 unsigned int bits[0];
590 };
591
592 typedef struct microcode microcode_t;
593 typedef struct microcode_header microcode_header_t;
594
595 /* microcode format is extended from prescott processors */
596 struct extended_signature {
597 unsigned int sig;
598 unsigned int pf;
599 unsigned int cksum;
600 };
601
602 struct extended_sigtable {
603 unsigned int count;
604 unsigned int cksum;
605 unsigned int reserved[3];
606 struct extended_signature sigs[0];
607 };
608
609 typedef struct {
610 unsigned long seg;
611 } mm_segment_t;
612
613
614 /*
615 * create a kernel thread without removing it from tasklists
616 */
617 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
618
619 /* Free all resources held by a thread. */
620 extern void release_thread(struct task_struct *);
621
622 /* Prepare to copy thread state - unlazy all lazy state */
623 extern void prepare_to_copy(struct task_struct *tsk);
624
625 unsigned long get_wchan(struct task_struct *p);
626
627 /*
628 * Generic CPUID function
629 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
630 * resulting in stale register contents being returned.
631 */
632 static inline void cpuid(unsigned int op,
633 unsigned int *eax, unsigned int *ebx,
634 unsigned int *ecx, unsigned int *edx)
635 {
636 *eax = op;
637 *ecx = 0;
638 __cpuid(eax, ebx, ecx, edx);
639 }
640
641 /* Some CPUID calls want 'count' to be placed in ecx */
642 static inline void cpuid_count(unsigned int op, int count,
643 unsigned int *eax, unsigned int *ebx,
644 unsigned int *ecx, unsigned int *edx)
645 {
646 *eax = op;
647 *ecx = count;
648 __cpuid(eax, ebx, ecx, edx);
649 }
650
651 /*
652 * CPUID functions returning a single datum
653 */
654 static inline unsigned int cpuid_eax(unsigned int op)
655 {
656 unsigned int eax, ebx, ecx, edx;
657
658 cpuid(op, &eax, &ebx, &ecx, &edx);
659
660 return eax;
661 }
662
663 static inline unsigned int cpuid_ebx(unsigned int op)
664 {
665 unsigned int eax, ebx, ecx, edx;
666
667 cpuid(op, &eax, &ebx, &ecx, &edx);
668
669 return ebx;
670 }
671
672 static inline unsigned int cpuid_ecx(unsigned int op)
673 {
674 unsigned int eax, ebx, ecx, edx;
675
676 cpuid(op, &eax, &ebx, &ecx, &edx);
677
678 return ecx;
679 }
680
681 static inline unsigned int cpuid_edx(unsigned int op)
682 {
683 unsigned int eax, ebx, ecx, edx;
684
685 cpuid(op, &eax, &ebx, &ecx, &edx);
686
687 return edx;
688 }
689
690 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
691 static inline void rep_nop(void)
692 {
693 asm volatile("rep; nop" ::: "memory");
694 }
695
696 static inline void cpu_relax(void)
697 {
698 rep_nop();
699 }
700
701 /* Stop speculative execution: */
702 static inline void sync_core(void)
703 {
704 int tmp;
705
706 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
707 : "ebx", "ecx", "edx", "memory");
708 }
709
710 static inline void __monitor(const void *eax, unsigned long ecx,
711 unsigned long edx)
712 {
713 /* "monitor %eax, %ecx, %edx;" */
714 asm volatile(".byte 0x0f, 0x01, 0xc8;"
715 :: "a" (eax), "c" (ecx), "d"(edx));
716 }
717
718 static inline void __mwait(unsigned long eax, unsigned long ecx)
719 {
720 /* "mwait %eax, %ecx;" */
721 asm volatile(".byte 0x0f, 0x01, 0xc9;"
722 :: "a" (eax), "c" (ecx));
723 }
724
725 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
726 {
727 trace_hardirqs_on();
728 /* "mwait %eax, %ecx;" */
729 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
730 :: "a" (eax), "c" (ecx));
731 }
732
733 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
734
735 extern void select_idle_routine(const struct cpuinfo_x86 *c);
736
737 extern unsigned long boot_option_idle_override;
738 extern unsigned long idle_halt;
739 extern unsigned long idle_nomwait;
740
741 /*
742 * on systems with caches, caches must be flashed as the absolute
743 * last instruction before going into a suspended halt. Otherwise,
744 * dirty data can linger in the cache and become stale on resume,
745 * leading to strange errors.
746 *
747 * perform a variety of operations to guarantee that the compiler
748 * will not reorder instructions. wbinvd itself is serializing
749 * so the processor will not reorder.
750 *
751 * Systems without cache can just go into halt.
752 */
753 static inline void wbinvd_halt(void)
754 {
755 mb();
756 /* check for clflush to determine if wbinvd is legal */
757 if (cpu_has_clflush)
758 asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");
759 else
760 while (1)
761 halt();
762 }
763
764 extern void enable_sep_cpu(void);
765 extern int sysenter_setup(void);
766
767 /* Defined in head.S */
768 extern struct desc_ptr early_gdt_descr;
769
770 extern void cpu_set_gdt(int);
771 extern void switch_to_new_gdt(void);
772 extern void cpu_init(void);
773 extern void init_gdt(int cpu);
774
775 static inline void update_debugctlmsr(unsigned long debugctlmsr)
776 {
777 #ifndef CONFIG_X86_DEBUGCTLMSR
778 if (boot_cpu_data.x86 < 6)
779 return;
780 #endif
781 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
782 }
783
784 /*
785 * from system description table in BIOS. Mostly for MCA use, but
786 * others may find it useful:
787 */
788 extern unsigned int machine_id;
789 extern unsigned int machine_submodel_id;
790 extern unsigned int BIOS_revision;
791
792 /* Boot loader type from the setup header: */
793 extern int bootloader_type;
794
795 extern char ignore_fpu_irq;
796
797 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
798 #define ARCH_HAS_PREFETCHW
799 #define ARCH_HAS_SPINLOCK_PREFETCH
800
801 #ifdef CONFIG_X86_32
802 # define BASE_PREFETCH ASM_NOP4
803 # define ARCH_HAS_PREFETCH
804 #else
805 # define BASE_PREFETCH "prefetcht0 (%1)"
806 #endif
807
808 /*
809 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
810 *
811 * It's not worth to care about 3dnow prefetches for the K6
812 * because they are microcoded there and very slow.
813 */
814 static inline void prefetch(const void *x)
815 {
816 alternative_input(BASE_PREFETCH,
817 "prefetchnta (%1)",
818 X86_FEATURE_XMM,
819 "r" (x));
820 }
821
822 /*
823 * 3dnow prefetch to get an exclusive cache line.
824 * Useful for spinlocks to avoid one state transition in the
825 * cache coherency protocol:
826 */
827 static inline void prefetchw(const void *x)
828 {
829 alternative_input(BASE_PREFETCH,
830 "prefetchw (%1)",
831 X86_FEATURE_3DNOW,
832 "r" (x));
833 }
834
835 static inline void spin_lock_prefetch(const void *x)
836 {
837 prefetchw(x);
838 }
839
840 #ifdef CONFIG_X86_32
841 /*
842 * User space process size: 3GB (default).
843 */
844 #define TASK_SIZE PAGE_OFFSET
845 #define STACK_TOP TASK_SIZE
846 #define STACK_TOP_MAX STACK_TOP
847
848 #define INIT_THREAD { \
849 .sp0 = sizeof(init_stack) + (long)&init_stack, \
850 .vm86_info = NULL, \
851 .sysenter_cs = __KERNEL_CS, \
852 .io_bitmap_ptr = NULL, \
853 .fs = __KERNEL_PERCPU, \
854 }
855
856 /*
857 * Note that the .io_bitmap member must be extra-big. This is because
858 * the CPU will access an additional byte beyond the end of the IO
859 * permission bitmap. The extra byte must be all 1 bits, and must
860 * be within the limit.
861 */
862 #define INIT_TSS { \
863 .x86_tss = { \
864 .sp0 = sizeof(init_stack) + (long)&init_stack, \
865 .ss0 = __KERNEL_DS, \
866 .ss1 = __KERNEL_CS, \
867 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
868 }, \
869 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
870 }
871
872 extern unsigned long thread_saved_pc(struct task_struct *tsk);
873
874 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
875 #define KSTK_TOP(info) \
876 ({ \
877 unsigned long *__ptr = (unsigned long *)(info); \
878 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
879 })
880
881 /*
882 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
883 * This is necessary to guarantee that the entire "struct pt_regs"
884 * is accessable even if the CPU haven't stored the SS/ESP registers
885 * on the stack (interrupt gate does not save these registers
886 * when switching to the same priv ring).
887 * Therefore beware: accessing the ss/esp fields of the
888 * "struct pt_regs" is possible, but they may contain the
889 * completely wrong values.
890 */
891 #define task_pt_regs(task) \
892 ({ \
893 struct pt_regs *__regs__; \
894 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
895 __regs__ - 1; \
896 })
897
898 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
899
900 #else
901 /*
902 * User space process size. 47bits minus one guard page.
903 */
904 #define TASK_SIZE64 ((1UL << 47) - PAGE_SIZE)
905
906 /* This decides where the kernel will search for a free chunk of vm
907 * space during mmap's.
908 */
909 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
910 0xc0000000 : 0xFFFFe000)
911
912 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
913 IA32_PAGE_OFFSET : TASK_SIZE64)
914 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
915 IA32_PAGE_OFFSET : TASK_SIZE64)
916
917 #define STACK_TOP TASK_SIZE
918 #define STACK_TOP_MAX TASK_SIZE64
919
920 #define INIT_THREAD { \
921 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
922 }
923
924 #define INIT_TSS { \
925 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
926 }
927
928 /*
929 * Return saved PC of a blocked thread.
930 * What is this good for? it will be always the scheduler or ret_from_fork.
931 */
932 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
933
934 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
935 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
936 #endif /* CONFIG_X86_64 */
937
938 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
939 unsigned long new_sp);
940
941 /*
942 * This decides where the kernel will search for a free chunk of vm
943 * space during mmap's.
944 */
945 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
946
947 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
948
949 /* Get/set a process' ability to use the timestamp counter instruction */
950 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
951 #define SET_TSC_CTL(val) set_tsc_mode((val))
952
953 extern int get_tsc_mode(unsigned long adr);
954 extern int set_tsc_mode(unsigned int val);
955
956 #endif /* ASM_X86__PROCESSOR_H */
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