1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
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15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
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60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
64 * Please use this file (iwl-4965-hw.h) only for hardware-related definitions.
65 * Use iwl-4965-commands.h for uCode API definitions.
66 * Use iwl-4965.h for driver implementation definitions.
69 #ifndef __iwl_4965_hw_h__
70 #define __iwl_4965_hw_h__
73 * uCode queue management definitions ...
74 * Queue #4 is the command queue for 3945 and 4965; map it to Tx FIFO chnl 4.
75 * The first queue used for block-ack aggregation is #7 (4965 only).
76 * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7.
78 #define IWL_CMD_QUEUE_NUM 4
79 #define IWL_CMD_FIFO_NUM 4
80 #define IWL_BACK_QUEUE_FIRST_ID 7
83 #define IWL_CCK_RATES 4
84 #define IWL_OFDM_RATES 8
85 #define IWL_HT_RATES 16
86 #define IWL_MAX_RATES (IWL_CCK_RATES+IWL_OFDM_RATES+IWL_HT_RATES)
89 #define SHORT_SLOT_TIME 9
90 #define LONG_SLOT_TIME 20
93 #define IWL_RSSI_OFFSET 44
96 * EEPROM related constants, enums, and structures.
100 * EEPROM access time values:
102 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG,
103 * then clearing (with subsequent read/modify/write) CSR_EEPROM_REG bit
104 * CSR_EEPROM_REG_BIT_CMD (0x2).
105 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
106 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
107 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
109 #define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
110 #define IWL_EEPROM_ACCESS_DELAY 10 /* uSec */
113 * Regulatory channel usage flags in EEPROM struct iwl4965_eeprom_channel.flags.
115 * IBSS and/or AP operation is allowed *only* on those channels with
116 * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because
117 * RADAR detection is not supported by the 4965 driver, but is a
118 * requirement for establishing a new network for legal operation on channels
119 * requiring RADAR detection or restricting ACTIVE scanning.
121 * NOTE: "WIDE" flag does not indicate anything about "FAT" 40 MHz channels.
122 * It only indicates that 20 MHz channel use is supported; FAT channel
123 * usage is indicated by a separate set of regulatory flags for each
126 * NOTE: Using a channel inappropriately will result in a uCode error!
129 EEPROM_CHANNEL_VALID
= (1 << 0), /* usable for this SKU/geo */
130 EEPROM_CHANNEL_IBSS
= (1 << 1), /* usable as an IBSS channel */
132 EEPROM_CHANNEL_ACTIVE
= (1 << 3), /* active scanning allowed */
133 EEPROM_CHANNEL_RADAR
= (1 << 4), /* radar detection required */
134 EEPROM_CHANNEL_WIDE
= (1 << 5), /* 20 MHz channel okay */
135 EEPROM_CHANNEL_NARROW
= (1 << 6), /* 10 MHz channel (not used) */
136 EEPROM_CHANNEL_DFS
= (1 << 7), /* dynamic freq selection candidate */
139 /* SKU Capabilities */
140 #define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
141 #define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
143 /* *regulatory* channel data format in eeprom, one for each channel.
144 * There are separate entries for FAT (40 MHz) vs. normal (20 MHz) channels. */
145 struct iwl4965_eeprom_channel
{
146 u8 flags
; /* EEPROM_CHANNEL_* flags copied from EEPROM */
147 s8 max_power_avg
; /* max power (dBm) on this chnl, limit 31 */
148 } __attribute__ ((packed
));
150 /* 4965 has two radio transmitters (and 3 radio receivers) */
151 #define EEPROM_TX_POWER_TX_CHAINS (2)
153 /* 4965 has room for up to 8 sets of txpower calibration data */
154 #define EEPROM_TX_POWER_BANDS (8)
156 /* 4965 factory calibration measures txpower gain settings for
157 * each of 3 target output levels */
158 #define EEPROM_TX_POWER_MEASUREMENTS (3)
160 /* 4965 driver does not work with txpower calibration version < 5.
161 * Look for this in calib_version member of struct iwl4965_eeprom. */
162 #define EEPROM_TX_POWER_VERSION_NEW (5)
166 * 4965 factory calibration data for one txpower level, on one channel,
167 * measured on one of the 2 tx chains (radio transmitter and associated
168 * antenna). EEPROM contains:
170 * 1) Temperature (degrees Celsius) of device when measurement was made.
172 * 2) Gain table index used to achieve the target measurement power.
173 * This refers to the "well-known" gain tables (see iwl-4965-hw.h).
175 * 3) Actual measured output power, in half-dBm ("34" = 17 dBm).
177 * 4) RF power amplifier detector level measurement (not used).
179 struct iwl4965_eeprom_calib_measure
{
180 u8 temperature
; /* Device temperature (Celsius) */
181 u8 gain_idx
; /* Index into gain table */
182 u8 actual_pow
; /* Measured RF output power, half-dBm */
183 s8 pa_det
; /* Power amp detector level (not used) */
184 } __attribute__ ((packed
));
188 * 4965 measurement set for one channel. EEPROM contains:
190 * 1) Channel number measured
192 * 2) Measurements for each of 3 power levels for each of 2 radio transmitters
193 * (a.k.a. "tx chains") (6 measurements altogether)
195 struct iwl4965_eeprom_calib_ch_info
{
197 struct iwl4965_eeprom_calib_measure measurements
[EEPROM_TX_POWER_TX_CHAINS
]
198 [EEPROM_TX_POWER_MEASUREMENTS
];
199 } __attribute__ ((packed
));
202 * 4965 txpower subband info.
204 * For each frequency subband, EEPROM contains the following:
206 * 1) First and last channels within range of the subband. "0" values
207 * indicate that this sample set is not being used.
209 * 2) Sample measurement sets for 2 channels close to the range endpoints.
211 struct iwl4965_eeprom_calib_subband_info
{
212 u8 ch_from
; /* channel number of lowest channel in subband */
213 u8 ch_to
; /* channel number of highest channel in subband */
214 struct iwl4965_eeprom_calib_ch_info ch1
;
215 struct iwl4965_eeprom_calib_ch_info ch2
;
216 } __attribute__ ((packed
));
220 * 4965 txpower calibration info. EEPROM contains:
222 * 1) Factory-measured saturation power levels (maximum levels at which
223 * tx power amplifier can output a signal without too much distortion).
224 * There is one level for 2.4 GHz band and one for 5 GHz band. These
225 * values apply to all channels within each of the bands.
227 * 2) Factory-measured power supply voltage level. This is assumed to be
228 * constant (i.e. same value applies to all channels/bands) while the
229 * factory measurements are being made.
231 * 3) Up to 8 sets of factory-measured txpower calibration values.
232 * These are for different frequency ranges, since txpower gain
233 * characteristics of the analog radio circuitry vary with frequency.
235 * Not all sets need to be filled with data;
236 * struct iwl4965_eeprom_calib_subband_info contains range of channels
237 * (0 if unused) for each set of data.
239 struct iwl4965_eeprom_calib_info
{
240 u8 saturation_power24
; /* half-dBm (e.g. "34" = 17 dBm) */
241 u8 saturation_power52
; /* half-dBm */
242 s16 voltage
; /* signed */
243 struct iwl4965_eeprom_calib_subband_info band_info
[EEPROM_TX_POWER_BANDS
];
244 } __attribute__ ((packed
));
250 struct iwl4965_eeprom
{
252 #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
253 u16 device_id
; /* abs.ofs: 16 */
255 #define EEPROM_PMC (2*0x0A) /* 2 bytes */
256 u16 pmc
; /* abs.ofs: 20 */
258 #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
259 u8 mac_address
[6]; /* abs.ofs: 42 */
261 #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
262 u16 board_revision
; /* abs.ofs: 106 */
264 #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
265 u8 board_pba_number
[9]; /* abs.ofs: 119 */
267 #define EEPROM_VERSION (2*0x44) /* 2 bytes */
268 u16 version
; /* abs.ofs: 136 */
269 #define EEPROM_SKU_CAP (2*0x45) /* 1 bytes */
270 u8 sku_cap
; /* abs.ofs: 138 */
271 #define EEPROM_LEDS_MODE (2*0x45+1) /* 1 bytes */
272 u8 leds_mode
; /* abs.ofs: 139 */
273 #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
275 #define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */
276 u16 wowlan_mode
; /* abs.ofs: 142 */
277 #define EEPROM_LEDS_TIME_INTERVAL (2*0x48) /* 2 bytes */
278 u16 leds_time_interval
; /* abs.ofs: 144 */
279 #define EEPROM_LEDS_OFF_TIME (2*0x49) /* 1 bytes */
280 u8 leds_off_time
; /* abs.ofs: 146 */
281 #define EEPROM_LEDS_ON_TIME (2*0x49+1) /* 1 bytes */
282 u8 leds_on_time
; /* abs.ofs: 147 */
283 #define EEPROM_ALMGOR_M_VERSION (2*0x4A) /* 1 bytes */
284 u8 almgor_m_version
; /* abs.ofs: 148 */
285 #define EEPROM_ANTENNA_SWITCH_TYPE (2*0x4A+1) /* 1 bytes */
286 u8 antenna_switch_type
; /* abs.ofs: 149 */
288 #define EEPROM_4965_BOARD_REVISION (2*0x4F) /* 2 bytes */
289 u16 board_revision_4965
; /* abs.ofs: 158 */
291 #define EEPROM_4965_BOARD_PBA (2*0x56+1) /* 9 bytes */
292 u8 board_pba_number_4965
[9]; /* abs.ofs: 173 */
294 #define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */
295 u8 sku_id
[4]; /* abs.ofs: 192 */
298 * Per-channel regulatory data.
300 * Each channel that *might* be supported by 3945 or 4965 has a fixed location
301 * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
304 * Entries immediately below are for 20 MHz channel width. FAT (40 MHz)
305 * channels (only for 4965, not supported by 3945) appear later in the EEPROM.
307 * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
309 #define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */
310 u16 band_1_count
; /* abs.ofs: 196 */
311 #define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */
312 struct iwl4965_eeprom_channel band_1_channels
[14]; /* abs.ofs: 196 */
315 * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
316 * 5.0 GHz channels 7, 8, 11, 12, 16
317 * (4915-5080MHz) (none of these is ever supported)
319 #define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */
320 u16 band_2_count
; /* abs.ofs: 226 */
321 #define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */
322 struct iwl4965_eeprom_channel band_2_channels
[13]; /* abs.ofs: 228 */
325 * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
328 #define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */
329 u16 band_3_count
; /* abs.ofs: 254 */
330 #define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */
331 struct iwl4965_eeprom_channel band_3_channels
[12]; /* abs.ofs: 256 */
334 * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
337 #define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */
338 u16 band_4_count
; /* abs.ofs: 280 */
339 #define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */
340 struct iwl4965_eeprom_channel band_4_channels
[11]; /* abs.ofs: 282 */
343 * 5.7 GHz channels 145, 149, 153, 157, 161, 165
346 #define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */
347 u16 band_5_count
; /* abs.ofs: 304 */
348 #define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */
349 struct iwl4965_eeprom_channel band_5_channels
[6]; /* abs.ofs: 306 */
355 * 2.4 GHz FAT channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11)
357 * The channel listed is the center of the lower 20 MHz half of the channel.
358 * The overall center frequency is actually 2 channels (10 MHz) above that,
359 * and the upper half of each FAT channel is centered 4 channels (20 MHz) away
360 * from the lower half; e.g. the upper half of FAT channel 1 is channel 5,
361 * and the overall FAT channel width centers on channel 3.
363 * NOTE: The RXON command uses 20 MHz channel numbers to specify the
364 * control channel to which to tune. RXON also specifies whether the
365 * control channel is the upper or lower half of a FAT channel.
367 * NOTE: 4965 does not support FAT channels on 2.4 GHz.
369 #define EEPROM_REGULATORY_BAND_24_FAT_CHANNELS (2*0xA0) /* 14 bytes */
370 struct iwl4965_eeprom_channel band_24_channels
[7]; /* abs.ofs: 320 */
374 * 5.2 GHz FAT channels 36 (40), 44 (48), 52 (56), 60 (64),
375 * 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161)
377 #define EEPROM_REGULATORY_BAND_52_FAT_CHANNELS (2*0xA8) /* 22 bytes */
378 struct iwl4965_eeprom_channel band_52_channels
[11]; /* abs.ofs: 336 */
382 * 4965 driver requires txpower calibration format version 5 or greater.
383 * Driver does not work with txpower calibration version < 5.
384 * This value is simply a 16-bit number, no major/minor versions here.
386 #define EEPROM_CALIB_VERSION_OFFSET (2*0xB6) /* 2 bytes */
387 u16 calib_version
; /* abs.ofs: 364 */
389 u8 reserved14
[96]; /* abs.ofs: 368 */
392 * 4965 Txpower calibration data.
394 #define EEPROM_IWL_CALIB_TXPOWER_OFFSET (2*0xE8) /* 48 bytes */
395 struct iwl4965_eeprom_calib_info calib_info
; /* abs.ofs: 464 */
397 u8 reserved16
[140]; /* fill out to full 1024 byte block */
400 } __attribute__ ((packed
));
402 #define IWL_EEPROM_IMAGE_SIZE 1024
406 #include "iwl-4965-commands.h"
408 #define PCI_LINK_CTRL 0x0F0
409 #define PCI_POWER_SOURCE 0x0C8
410 #define PCI_REG_WUM8 0x0E8
411 #define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
413 #define TFD_QUEUE_SIZE_MAX (256)
415 #define IWL_NUM_SCAN_RATES (2)
417 #define IWL_DEFAULT_TX_RETRY 15
419 #define RX_QUEUE_SIZE 256
420 #define RX_QUEUE_MASK 255
421 #define RX_QUEUE_SIZE_LOG 8
423 #define TFD_TX_CMD_SLOTS 256
424 #define TFD_CMD_SLOTS 32
426 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl4965_cmd) - \
427 sizeof(struct iwl4965_cmd_meta))
430 * RX related structures and functions
432 #define RX_FREE_BUFFERS 64
433 #define RX_LOW_WATERMARK 8
435 /* Size of one Rx buffer in host DRAM */
436 #define IWL_RX_BUF_SIZE_4K (4 * 1024)
437 #define IWL_RX_BUF_SIZE_8K (8 * 1024)
439 /* Sizes and addresses for instruction and data memory (SRAM) in
440 * 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */
441 #define RTC_INST_LOWER_BOUND (0x000000)
442 #define KDR_RTC_INST_UPPER_BOUND (0x018000)
444 #define RTC_DATA_LOWER_BOUND (0x800000)
445 #define KDR_RTC_DATA_UPPER_BOUND (0x80A000)
447 #define KDR_RTC_INST_SIZE (KDR_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND)
448 #define KDR_RTC_DATA_SIZE (KDR_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND)
450 #define IWL_MAX_INST_SIZE KDR_RTC_INST_SIZE
451 #define IWL_MAX_DATA_SIZE KDR_RTC_DATA_SIZE
453 /* Size of uCode instruction memory in bootstrap state machine */
454 #define IWL_MAX_BSM_SIZE BSM_SRAM_SIZE
456 static inline int iwl4965_hw_valid_rtc_data_addr(u32 addr
)
458 return (addr
>= RTC_DATA_LOWER_BOUND
) &&
459 (addr
< KDR_RTC_DATA_UPPER_BOUND
);
462 /********************* START TEMPERATURE *************************************/
465 * 4965 temperature calculation.
467 * The driver must calculate the device temperature before calculating
468 * a txpower setting (amplifier gain is temperature dependent). The
469 * calculation uses 4 measurements, 3 of which (R1, R2, R3) are calibration
470 * values used for the life of the driver, and one of which (R4) is the
471 * real-time temperature indicator.
473 * uCode provides all 4 values to the driver via the "initialize alive"
474 * notification (see struct iwl4965_init_alive_resp). After the runtime uCode
475 * image loads, uCode updates the R4 value via statistics notifications
476 * (see STATISTICS_NOTIFICATION), which occur after each received beacon
477 * when associated, or can be requested via REPLY_STATISTICS_CMD.
479 * NOTE: uCode provides the R4 value as a 23-bit signed value. Driver
480 * must sign-extend to 32 bits before applying formula below.
484 * degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8
486 * NOTE: The basic formula is 259 * (R4-R2) / (R3-R1). The 97/100 is
487 * an additional correction, which should be centered around 0 degrees
488 * Celsius (273 degrees Kelvin). The 8 (3 percent of 273) compensates for
489 * centering the 97/100 correction around 0 degrees K.
491 * Add 273 to Kelvin value to find degrees Celsius, for comparing current
492 * temperature with factory-measured temperatures when calculating txpower
495 #define TEMPERATURE_CALIB_KELVIN_OFFSET 8
496 #define TEMPERATURE_CALIB_A_VAL 259
498 /* Limit range of calculated temperature to be between these Kelvin values */
499 #define IWL_TX_POWER_TEMPERATURE_MIN (263)
500 #define IWL_TX_POWER_TEMPERATURE_MAX (410)
502 #define IWL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \
503 (((t) < IWL_TX_POWER_TEMPERATURE_MIN) || \
504 ((t) > IWL_TX_POWER_TEMPERATURE_MAX))
506 /********************* END TEMPERATURE ***************************************/
508 /********************* START TXPOWER *****************************************/
511 * 4965 txpower calculations rely on information from three sources:
514 * 2) "initialize" alive notification
515 * 3) statistics notifications
517 * EEPROM data consists of:
519 * 1) Regulatory information (max txpower and channel usage flags) is provided
520 * separately for each channel that can possibly supported by 4965.
521 * 40 MHz wide (.11n fat) channels are listed separately from 20 MHz
524 * See struct iwl4965_eeprom_channel for format, and struct iwl4965_eeprom
525 * for locations in EEPROM.
527 * 2) Factory txpower calibration information is provided separately for
528 * sub-bands of contiguous channels. 2.4GHz has just one sub-band,
529 * but 5 GHz has several sub-bands.
531 * In addition, per-band (2.4 and 5 Ghz) saturation txpowers are provided.
533 * See struct iwl4965_eeprom_calib_info (and the tree of structures
534 * contained within it) for format, and struct iwl4965_eeprom for
535 * locations in EEPROM.
537 * "Initialization alive" notification (see struct iwl4965_init_alive_resp)
540 * 1) Temperature calculation parameters.
542 * 2) Power supply voltage measurement.
544 * 3) Tx gain compensation to balance 2 transmitters for MIMO use.
546 * Statistics notifications deliver:
548 * 1) Current values for temperature param R4.
552 * To calculate a txpower setting for a given desired target txpower, channel,
553 * modulation bit rate, and transmitter chain (4965 has 2 transmitters to
554 * support MIMO and transmit diversity), driver must do the following:
556 * 1) Compare desired txpower vs. (EEPROM) regulatory limit for this channel.
557 * Do not exceed regulatory limit; reduce target txpower if necessary.
559 * If setting up txpowers for MIMO rates (rate indexes 8-15, 24-31),
560 * 2 transmitters will be used simultaneously; driver must reduce the
561 * regulatory limit by 3 dB (half-power) for each transmitter, so the
562 * combined total output of the 2 transmitters is within regulatory limits.
565 * 2) Compare target txpower vs. (EEPROM) saturation txpower *reduced by
566 * backoff for this bit rate*. Do not exceed (saturation - backoff[rate]);
567 * reduce target txpower if necessary.
569 * Backoff values below are in 1/2 dB units (equivalent to steps in
570 * txpower gain tables):
572 * OFDM 6 - 36 MBit: 10 steps (5 dB)
573 * OFDM 48 MBit: 15 steps (7.5 dB)
574 * OFDM 54 MBit: 17 steps (8.5 dB)
575 * OFDM 60 MBit: 20 steps (10 dB)
576 * CCK all rates: 10 steps (5 dB)
578 * Backoff values apply to saturation txpower on a per-transmitter basis;
579 * when using MIMO (2 transmitters), each transmitter uses the same
580 * saturation level provided in EEPROM, and the same backoff values;
581 * no reduction (such as with regulatory txpower limits) is required.
583 * Saturation and Backoff values apply equally to 20 Mhz (legacy) channel
584 * widths and 40 Mhz (.11n fat) channel widths; there is no separate
585 * factory measurement for fat channels.
587 * The result of this step is the final target txpower. The rest of
588 * the steps figure out the proper settings for the device to achieve
589 * that target txpower.
592 * 3) Determine (EEPROM) calibration subband for the target channel, by
593 * comparing against first and last channels in each subband
594 * (see struct iwl4965_eeprom_calib_subband_info).
597 * 4) Linearly interpolate (EEPROM) factory calibration measurement sets,
598 * referencing the 2 factory-measured (sample) channels within the subband.
600 * Interpolation is based on difference between target channel's frequency
601 * and the sample channels' frequencies. Since channel numbers are based
602 * on frequency (5 MHz between each channel number), this is equivalent
603 * to interpolating based on channel number differences.
605 * Note that the sample channels may or may not be the channels at the
606 * edges of the subband. The target channel may be "outside" of the
607 * span of the sampled channels.
609 * Driver may choose the pair (for 2 Tx chains) of measurements (see
610 * struct iwl4965_eeprom_calib_ch_info) for which the actual measured
611 * txpower comes closest to the desired txpower. Usually, though,
612 * the middle set of measurements is closest to the regulatory limits,
613 * and is therefore a good choice for all txpower calculations (this
614 * assumes that high accuracy is needed for maximizing legal txpower,
615 * while lower txpower configurations do not need as much accuracy).
617 * Driver should interpolate both members of the chosen measurement pair,
618 * i.e. for both Tx chains (radio transmitters), unless the driver knows
619 * that only one of the chains will be used (e.g. only one tx antenna
620 * connected, but this should be unusual). The rate scaling algorithm
621 * switches antennas to find best performance, so both Tx chains will
622 * be used (although only one at a time) even for non-MIMO transmissions.
624 * Driver should interpolate factory values for temperature, gain table
625 * index, and actual power. The power amplifier detector values are
626 * not used by the driver.
628 * Sanity check: If the target channel happens to be one of the sample
629 * channels, the results should agree with the sample channel's
633 * 5) Find difference between desired txpower and (interpolated)
634 * factory-measured txpower. Using (interpolated) factory gain table index
635 * (shown elsewhere) as a starting point, adjust this index lower to
636 * increase txpower, or higher to decrease txpower, until the target
637 * txpower is reached. Each step in the gain table is 1/2 dB.
639 * For example, if factory measured txpower is 16 dBm, and target txpower
640 * is 13 dBm, add 6 steps to the factory gain index to reduce txpower
644 * 6) Find difference between current device temperature and (interpolated)
645 * factory-measured temperature for sub-band. Factory values are in
646 * degrees Celsius. To calculate current temperature, see comments for
647 * "4965 temperature calculation".
649 * If current temperature is higher than factory temperature, driver must
650 * increase gain (lower gain table index), and vice versa.
652 * Temperature affects gain differently for different channels:
654 * 2.4 GHz all channels: 3.5 degrees per half-dB step
655 * 5 GHz channels 34-43: 4.5 degrees per half-dB step
656 * 5 GHz channels >= 44: 4.0 degrees per half-dB step
658 * NOTE: Temperature can increase rapidly when transmitting, especially
659 * with heavy traffic at high txpowers. Driver should update
660 * temperature calculations often under these conditions to
661 * maintain strong txpower in the face of rising temperature.
664 * 7) Find difference between current power supply voltage indicator
665 * (from "initialize alive") and factory-measured power supply voltage
666 * indicator (EEPROM).
668 * If the current voltage is higher (indicator is lower) than factory
669 * voltage, gain should be reduced (gain table index increased) by:
671 * (eeprom - current) / 7
673 * If the current voltage is lower (indicator is higher) than factory
674 * voltage, gain should be increased (gain table index decreased) by:
676 * 2 * (current - eeprom) / 7
678 * If number of index steps in either direction turns out to be > 2,
679 * something is wrong ... just use 0.
681 * NOTE: Voltage compensation is independent of band/channel.
683 * NOTE: "Initialize" uCode measures current voltage, which is assumed
684 * to be constant after this initial measurement. Voltage
685 * compensation for txpower (number of steps in gain table)
686 * may be calculated once and used until the next uCode bootload.
689 * 8) If setting up txpowers for MIMO rates (rate indexes 8-15, 24-31),
690 * adjust txpower for each transmitter chain, so txpower is balanced
691 * between the two chains. There are 5 pairs of tx_atten[group][chain]
692 * values in "initialize alive", one pair for each of 5 channel ranges:
694 * Group 0: 5 GHz channel 34-43
695 * Group 1: 5 GHz channel 44-70
696 * Group 2: 5 GHz channel 71-124
697 * Group 3: 5 GHz channel 125-200
698 * Group 4: 2.4 GHz all channels
700 * Add the tx_atten[group][chain] value to the index for the target chain.
701 * The values are signed, but are in pairs of 0 and a non-negative number,
702 * so as to reduce gain (if necessary) of the "hotter" channel. This
703 * avoids any need to double-check for regulatory compliance after
707 * 9) If setting up for a CCK rate, lower the gain by adding a CCK compensation
708 * value to the index:
710 * Hardware rev B: 9 steps (4.5 dB)
711 * Hardware rev C: 5 steps (2.5 dB)
713 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
714 * bits [3:2], 1 = B, 2 = C.
716 * NOTE: This compensation is in addition to any saturation backoff that
717 * might have been applied in an earlier step.
720 * 10) Select the gain table, based on band (2.4 vs 5 GHz).
722 * Limit the adjusted index to stay within the table!
725 * 11) Read gain table entries for DSP and radio gain, place into appropriate
726 * location(s) in command (struct iwl4965_txpowertable_cmd).
729 /* Limit range of txpower output target to be between these values */
730 #define IWL_TX_POWER_TARGET_POWER_MIN (0) /* 0 dBm = 1 milliwatt */
731 #define IWL_TX_POWER_TARGET_POWER_MAX (16) /* 16 dBm */
734 * When MIMO is used (2 transmitters operating simultaneously), driver should
735 * limit each transmitter to deliver a max of 3 dB below the regulatory limit
736 * for the device. That is, use half power for each transmitter, so total
737 * txpower is within regulatory limits.
739 * The value "6" represents number of steps in gain table to reduce power 3 dB.
740 * Each step is 1/2 dB.
742 #define IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6)
745 * CCK gain compensation.
747 * When calculating txpowers for CCK, after making sure that the target power
748 * is within regulatory and saturation limits, driver must additionally
749 * back off gain by adding these values to the gain table index.
751 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
752 * bits [3:2], 1 = B, 2 = C.
754 #define IWL_TX_POWER_CCK_COMPENSATION_B_STEP (9)
755 #define IWL_TX_POWER_CCK_COMPENSATION_C_STEP (5)
758 * 4965 power supply voltage compensation for txpower
760 #define TX_POWER_IWL_VOLTAGE_CODES_PER_03V (7)
765 * The following tables contain pair of values for setting txpower, i.e.
766 * gain settings for the output of the device's digital signal processor (DSP),
767 * and for the analog gain structure of the transmitter.
769 * Each entry in the gain tables represents a step of 1/2 dB. Note that these
770 * are *relative* steps, not indications of absolute output power. Output
771 * power varies with temperature, voltage, and channel frequency, and also
772 * requires consideration of average power (to satisfy regulatory constraints),
773 * and peak power (to avoid distortion of the output signal).
775 * Each entry contains two values:
776 * 1) DSP gain (or sometimes called DSP attenuation). This is a fine-grained
777 * linear value that multiplies the output of the digital signal processor,
778 * before being sent to the analog radio.
779 * 2) Radio gain. This sets the analog gain of the radio Tx path.
780 * It is a coarser setting, and behaves in a logarithmic (dB) fashion.
782 * EEPROM contains factory calibration data for txpower. This maps actual
783 * measured txpower levels to gain settings in the "well known" tables
784 * below ("well-known" means here that both factory calibration *and* the
785 * driver work with the same table).
787 * There are separate tables for 2.4 GHz and 5 GHz bands. The 5 GHz table
788 * has an extension (into negative indexes), in case the driver needs to
789 * boost power setting for high device temperatures (higher than would be
790 * present during factory calibration). A 5 Ghz EEPROM index of "40"
791 * corresponds to the 49th entry in the table used by the driver.
793 #define MIN_TX_GAIN_INDEX (0) /* highest gain, lowest idx, 2.4 */
794 #define MIN_TX_GAIN_INDEX_52GHZ_EXT (-9) /* highest gain, lowest idx, 5 */
799 * Index Dsp gain Radio gain
800 * 0 110 0x3f (highest gain)
904 * Index Dsp gain Radio gain
905 * -9 123 0x3F (highest gain)
1017 * Sanity checks and default values for EEPROM regulatory levels.
1018 * If EEPROM values fall outside MIN/MAX range, use default values.
1020 * Regulatory limits refer to the maximum average txpower allowed by
1021 * regulatory agencies in the geographies in which the device is meant
1022 * to be operated. These limits are SKU-specific (i.e. geography-specific),
1023 * and channel-specific; each channel has an individual regulatory limit
1024 * listed in the EEPROM.
1026 * Units are in half-dBm (i.e. "34" means 17 dBm).
1028 #define IWL_TX_POWER_DEFAULT_REGULATORY_24 (34)
1029 #define IWL_TX_POWER_DEFAULT_REGULATORY_52 (34)
1030 #define IWL_TX_POWER_REGULATORY_MIN (0)
1031 #define IWL_TX_POWER_REGULATORY_MAX (34)
1034 * Sanity checks and default values for EEPROM saturation levels.
1035 * If EEPROM values fall outside MIN/MAX range, use default values.
1037 * Saturation is the highest level that the output power amplifier can produce
1038 * without significant clipping distortion. This is a "peak" power level.
1039 * Different types of modulation (i.e. various "rates", and OFDM vs. CCK)
1040 * require differing amounts of backoff, relative to their average power output,
1041 * in order to avoid clipping distortion.
1043 * Driver must make sure that it is violating neither the saturation limit,
1044 * nor the regulatory limit, when calculating Tx power settings for various
1047 * Units are in half-dBm (i.e. "38" means 19 dBm).
1049 #define IWL_TX_POWER_DEFAULT_SATURATION_24 (38)
1050 #define IWL_TX_POWER_DEFAULT_SATURATION_52 (38)
1051 #define IWL_TX_POWER_SATURATION_MIN (20)
1052 #define IWL_TX_POWER_SATURATION_MAX (50)
1055 * Channel groups used for Tx Attenuation calibration (MIMO tx channel balance)
1056 * and thermal Txpower calibration.
1058 * When calculating txpower, driver must compensate for current device
1059 * temperature; higher temperature requires higher gain. Driver must calculate
1060 * current temperature (see "4965 temperature calculation"), then compare vs.
1061 * factory calibration temperature in EEPROM; if current temperature is higher
1062 * than factory temperature, driver must *increase* gain by proportions shown
1063 * in table below. If current temperature is lower than factory, driver must
1066 * Different frequency ranges require different compensation, as shown below.
1068 /* Group 0, 5.2 GHz ch 34-43: 4.5 degrees per 1/2 dB. */
1069 #define CALIB_IWL_TX_ATTEN_GR1_FCH 34
1070 #define CALIB_IWL_TX_ATTEN_GR1_LCH 43
1072 /* Group 1, 5.3 GHz ch 44-70: 4.0 degrees per 1/2 dB. */
1073 #define CALIB_IWL_TX_ATTEN_GR2_FCH 44
1074 #define CALIB_IWL_TX_ATTEN_GR2_LCH 70
1076 /* Group 2, 5.5 GHz ch 71-124: 4.0 degrees per 1/2 dB. */
1077 #define CALIB_IWL_TX_ATTEN_GR3_FCH 71
1078 #define CALIB_IWL_TX_ATTEN_GR3_LCH 124
1080 /* Group 3, 5.7 GHz ch 125-200: 4.0 degrees per 1/2 dB. */
1081 #define CALIB_IWL_TX_ATTEN_GR4_FCH 125
1082 #define CALIB_IWL_TX_ATTEN_GR4_LCH 200
1084 /* Group 4, 2.4 GHz all channels: 3.5 degrees per 1/2 dB. */
1085 #define CALIB_IWL_TX_ATTEN_GR5_FCH 1
1086 #define CALIB_IWL_TX_ATTEN_GR5_LCH 20
1089 CALIB_CH_GROUP_1
= 0,
1090 CALIB_CH_GROUP_2
= 1,
1091 CALIB_CH_GROUP_3
= 2,
1092 CALIB_CH_GROUP_4
= 3,
1093 CALIB_CH_GROUP_5
= 4,
1097 /********************* END TXPOWER *****************************************/
1099 /****************************/
1100 /* Flow Handler Definitions */
1101 /****************************/
1104 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
1105 * Addresses are offsets from device's PCI hardware base address.
1107 #define FH_MEM_LOWER_BOUND (0x1000)
1108 #define FH_MEM_UPPER_BOUND (0x1EF0)
1111 * Keep-Warm (KW) buffer base address.
1113 * Driver must allocate a 4KByte buffer that is used by 4965 for keeping the
1114 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
1115 * DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host
1116 * from going into a power-savings mode that would cause higher DRAM latency,
1117 * and possible data over/under-runs, before all Tx/Rx is complete.
1119 * Driver loads IWL_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
1120 * of the buffer, which must be 4K aligned. Once this is set up, the 4965
1121 * automatically invokes keep-warm accesses when normal accesses might not
1122 * be sufficient to maintain fast DRAM response.
1125 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
1127 #define IWL_FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C)
1131 * TFD Circular Buffers Base (CBBC) addresses
1133 * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident
1134 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
1135 * (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04
1136 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
1137 * aligned (address bits 0-7 must be 0).
1139 * Bit fields in each pointer register:
1140 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
1142 #define FH_MEM_CBBC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0)
1143 #define FH_MEM_CBBC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10)
1145 /* Find TFD CB base pointer for given queue (range 0-15). */
1146 #define FH_MEM_CBBC_QUEUE(x) (FH_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
1150 * Rx SRAM Control and Status Registers (RSCSR)
1152 * These registers provide handshake between driver and 4965 for the Rx queue
1153 * (this queue handles *all* command responses, notifications, Rx data, etc.
1154 * sent from 4965 uCode to host driver). Unlike Tx, there is only one Rx
1155 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
1156 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
1157 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
1158 * mapping between RBDs and RBs.
1160 * Driver must allocate host DRAM memory for the following, and set the
1161 * physical address of each into 4965 registers:
1163 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
1164 * entries (although any power of 2, up to 4096, is selectable by driver).
1165 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
1166 * (typically 4K, although 8K or 16K are also selectable by driver).
1167 * Driver sets up RB size and number of RBDs in the CB via Rx config
1168 * register FH_MEM_RCSR_CHNL0_CONFIG_REG.
1170 * Bit fields within one RBD:
1171 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
1173 * Driver sets physical address [35:8] of base of RBD circular buffer
1174 * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
1176 * 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers
1177 * (RBs) have been filled, via a "write pointer", actually the index of
1178 * the RB's corresponding RBD within the circular buffer. Driver sets
1179 * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
1181 * Bit fields in lower dword of Rx status buffer (upper dword not used
1182 * by driver; see struct iwl4965_shared, val0):
1183 * 31-12: Not used by driver
1184 * 11- 0: Index of last filled Rx buffer descriptor
1185 * (4965 writes, driver reads this value)
1187 * As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must
1188 * enter pointers to these RBs into contiguous RBD circular buffer entries,
1189 * and update the 4965's "write" index register, FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
1191 * This "write" index corresponds to the *next* RBD that the driver will make
1192 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
1193 * the circular buffer. This value should initially be 0 (before preparing any
1194 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
1195 * wrap back to 0 at the end of the circular buffer (but don't wrap before
1196 * "read" index has advanced past 1! See below).
1197 * NOTE: 4965 EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
1199 * As the 4965 fills RBs (referenced from contiguous RBDs within the circular
1200 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
1201 * to tell the driver the index of the latest filled RBD. The driver must
1202 * read this "read" index from DRAM after receiving an Rx interrupt from 4965.
1204 * The driver must also internally keep track of a third index, which is the
1205 * next RBD to process. When receiving an Rx interrupt, driver should process
1206 * all filled but unprocessed RBs up to, but not including, the RB
1207 * corresponding to the "read" index. For example, if "read" index becomes "1",
1208 * driver may process the RB pointed to by RBD 0. Depending on volume of
1209 * traffic, there may be many RBs to process.
1211 * If read index == write index, 4965 thinks there is no room to put new data.
1212 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
1213 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
1214 * and "read" indexes; that is, make sure that there are no more than 254
1215 * buffers waiting to be filled.
1217 #define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0)
1218 #define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
1219 #define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND)
1222 * Physical base address of 8-byte Rx Status buffer.
1224 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
1226 #define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0)
1229 * Physical base address of Rx Buffer Descriptor Circular Buffer.
1231 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
1233 #define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004)
1236 * Rx write pointer (index, really!).
1238 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
1239 * NOTE: For 256-entry circular buffer, use only bits [7:0].
1241 #define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008)
1242 #define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
1246 * Rx Config/Status Registers (RCSR)
1247 * Rx Config Reg for channel 0 (only channel used)
1249 * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
1250 * normal operation (see bit fields).
1252 * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
1253 * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for
1254 * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
1257 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1258 * '10' operate normally
1260 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
1261 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
1263 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
1264 * '10' 12K, '11' 16K.
1266 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
1267 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
1268 * typical value 0x10 (about 1/2 msec)
1271 #define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
1272 #define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0)
1273 #define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND)
1275 #define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0)
1277 #define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MASK (0x00000FF0) /* bit 4-11 */
1278 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MASK (0x00001000) /* bit 12 */
1279 #define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MASK (0x00008000) /* bit 15 */
1280 #define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MASK (0x00030000) /* bits 16-17 */
1281 #define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MASK (0x00F00000) /* bits 20-23 */
1282 #define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MASK (0xC0000000) /* bits 30-31 */
1284 #define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT (20)
1285 #define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_BITSHIFT (4)
1286 #define RX_RB_TIMEOUT (0x10)
1288 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1289 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1290 #define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1292 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1293 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
1294 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
1295 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
1297 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1298 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
1302 * Rx Shared Status Registers (RSSR)
1304 * After stopping Rx DMA channel (writing 0 to FH_MEM_RCSR_CHNL0_CONFIG_REG),
1305 * driver must poll FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
1308 * 24: 1 = Channel 0 is idle
1310 * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV contain
1311 * default values that should not be altered by the driver.
1313 #define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40)
1314 #define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
1316 #define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND)
1317 #define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004)
1318 #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV (FH_MEM_RSSR_LOWER_BOUND + 0x008)
1320 #define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1324 * Transmit DMA Channel Control/Status Registers (TCSR)
1326 * 4965 has one configuration register for each of 8 Tx DMA/FIFO channels
1327 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
1328 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1330 * To use a Tx DMA channel, driver must initialize its
1331 * IWL_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
1333 * IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1334 * IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
1336 * All other bits should be 0.
1339 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1340 * '10' operate normally
1341 * 29- 4: Reserved, set to "0"
1342 * 3: Enable internal DMA requests (1, normal operation), disable (0)
1343 * 2- 0: Reserved, set to "0"
1345 #define IWL_FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
1346 #define IWL_FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60)
1348 /* Find Control/Status reg for given Tx DMA/FIFO channel */
1349 #define IWL_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1350 (IWL_FH_TCSR_LOWER_BOUND + 0x20 * _chnl)
1352 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
1353 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
1355 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1356 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1357 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1360 * Tx Shared Status Registers (TSSR)
1362 * After stopping Tx DMA channel (writing 0 to
1363 * IWL_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
1364 * IWL_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
1365 * (channel's buffers empty | no pending requests).
1368 * 31-24: 1 = Channel buffers empty (channel 7:0)
1369 * 23-16: 1 = No pending requests (channel 7:0)
1371 #define IWL_FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0)
1372 #define IWL_FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0)
1374 #define IWL_FH_TSSR_TX_STATUS_REG (IWL_FH_TSSR_LOWER_BOUND + 0x010)
1376 #define IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) \
1377 ((1 << (_chnl)) << 24)
1378 #define IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl) \
1379 ((1 << (_chnl)) << 16)
1381 #define IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) \
1382 (IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) | \
1383 IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl))
1386 /********************* START TX SCHEDULER *************************************/
1391 * The Tx Scheduler selects the next frame to be transmitted, chosing TFDs
1392 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
1393 * host DRAM. It steers each frame's Tx command (which contains the frame
1394 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
1395 * device. A queue maps to only one (selectable by driver) Tx DMA channel,
1396 * but one DMA channel may take input from several queues.
1398 * Tx DMA channels have dedicated purposes. For 4965, they are used as follows:
1400 * 0 -- EDCA BK (background) frames, lowest priority
1401 * 1 -- EDCA BE (best effort) frames, normal priority
1402 * 2 -- EDCA VI (video) frames, higher priority
1403 * 3 -- EDCA VO (voice) and management frames, highest priority
1404 * 4 -- Commands (e.g. RXON, etc.)
1405 * 5 -- HCCA short frames
1406 * 6 -- HCCA long frames
1407 * 7 -- not used by driver (device-internal only)
1409 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
1410 * In addition, driver can map queues 7-15 to Tx DMA/FIFO channels 0-3 to
1411 * support 11n aggregation via EDCA DMA channels.
1413 * The driver sets up each queue to work in one of two modes:
1415 * 1) Scheduler-Ack, in which the scheduler automatically supports a
1416 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue
1417 * contains TFDs for a unique combination of Recipient Address (RA)
1418 * and Traffic Identifier (TID), that is, traffic of a given
1419 * Quality-Of-Service (QOS) priority, destined for a single station.
1421 * In scheduler-ack mode, the scheduler keeps track of the Tx status of
1422 * each frame within the BA window, including whether it's been transmitted,
1423 * and whether it's been acknowledged by the receiving station. The device
1424 * automatically processes block-acks received from the receiving STA,
1425 * and reschedules un-acked frames to be retransmitted (successful
1426 * Tx completion may end up being out-of-order).
1428 * The driver must maintain the queue's Byte Count table in host DRAM
1429 * (struct iwl4965_sched_queue_byte_cnt_tbl) for this mode.
1430 * This mode does not support fragmentation.
1432 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
1433 * The device may automatically retry Tx, but will retry only one frame
1434 * at a time, until receiving ACK from receiving station, or reaching
1435 * retry limit and giving up.
1437 * The command queue (#4) must use this mode!
1438 * This mode does not require use of the Byte Count table in host DRAM.
1440 * Driver controls scheduler operation via 3 means:
1441 * 1) Scheduler registers
1442 * 2) Shared scheduler data base in internal 4956 SRAM
1443 * 3) Shared data in host DRAM
1447 * When loading, driver should allocate memory for:
1448 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.
1449 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory
1450 * (1024 bytes for each queue).
1452 * After receiving "Alive" response from uCode, driver must initialize
1453 * the scheduler (especially for queue #4, the command queue, otherwise
1454 * the driver can't issue commands!):
1458 * Max Tx window size is the max number of contiguous TFDs that the scheduler
1459 * can keep track of at one time when creating block-ack chains of frames.
1460 * Note that "64" matches the number of ack bits in a block-ack packet.
1461 * Driver should use SCD_WIN_SIZE and SCD_FRAME_LIMIT values to initialize
1462 * SCD_CONTEXT_QUEUE_OFFSET(x) values.
1464 #define SCD_WIN_SIZE 64
1465 #define SCD_FRAME_LIMIT 64
1467 /* SCD registers are internal, must be accessed via HBUS_TARG_PRPH regs */
1468 #define SCD_START_OFFSET 0xa02c00
1471 * 4965 tells driver SRAM address for internal scheduler structs via this reg.
1472 * Value is valid only after "Alive" response from uCode.
1474 #define SCD_SRAM_BASE_ADDR (SCD_START_OFFSET + 0x0)
1477 * Driver may need to update queue-empty bits after changing queue's
1478 * write and read pointers (indexes) during (re-)initialization (i.e. when
1479 * scheduler is not tracking what's happening).
1481 * 31-16: Write mask -- 1: update empty bit, 0: don't change empty bit
1482 * 15-00: Empty state, one for each queue -- 1: empty, 0: non-empty
1483 * NOTE: This register is not used by Linux driver.
1485 #define SCD_EMPTY_BITS (SCD_START_OFFSET + 0x4)
1488 * Physical base address of array of byte count (BC) circular buffers (CBs).
1489 * Each Tx queue has a BC CB in host DRAM to support Scheduler-ACK mode.
1490 * This register points to BC CB for queue 0, must be on 1024-byte boundary.
1491 * Others are spaced by 1024 bytes.
1492 * Each BC CB is 2 bytes * (256 + 64) = 740 bytes, followed by 384 bytes pad.
1493 * (Index into a queue's BC CB) = (index into queue's TFD CB) = (SSN & 0xff).
1495 * 25-00: Byte Count CB physical address [35:10], must be 1024-byte aligned.
1497 #define SCD_DRAM_BASE_ADDR (SCD_START_OFFSET + 0x10)
1500 * Enables any/all Tx DMA/FIFO channels.
1501 * Scheduler generates requests for only the active channels.
1502 * Set this to 0xff to enable all 8 channels (normal usage).
1504 * 7- 0: Enable (1), disable (0), one bit for each channel 0-7
1506 #define SCD_TXFACT (SCD_START_OFFSET + 0x1c)
1508 /* Mask to enable contiguous Tx DMA/FIFO channels between "lo" and "hi". */
1509 #define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \
1510 ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
1513 * Queue (x) Write Pointers (indexes, really!), one for each Tx queue.
1514 * Initialized and updated by driver as new TFDs are added to queue.
1515 * NOTE: If using Block Ack, index must correspond to frame's
1516 * Start Sequence Number; index = (SSN & 0xff)
1517 * NOTE: Alternative to HBUS_TARG_WRPTR, which is what Linux driver uses?
1519 #define SCD_QUEUE_WRPTR(x) (SCD_START_OFFSET + 0x24 + (x) * 4)
1522 * Queue (x) Read Pointers (indexes, really!), one for each Tx queue.
1523 * For FIFO mode, index indicates next frame to transmit.
1524 * For Scheduler-ACK mode, index indicates first frame in Tx window.
1525 * Initialized by driver, updated by scheduler.
1527 #define SCD_QUEUE_RDPTR(x) (SCD_START_OFFSET + 0x64 + (x) * 4)
1530 * Select which queues work in chain mode (1) vs. not (0).
1531 * Use chain mode to build chains of aggregated frames.
1534 * 15-00: Mode, one bit for each queue -- 1: Chain mode, 0: one-at-a-time
1535 * NOTE: If driver sets up queue for chain mode, it should be also set up
1536 * Scheduler-ACK mode as well, via SCD_QUEUE_STATUS_BITS(x).
1538 #define SCD_QUEUECHAIN_SEL (SCD_START_OFFSET + 0xd0)
1541 * Select which queues interrupt driver when scheduler increments
1542 * a queue's read pointer (index).
1545 * 15-00: Interrupt enable, one bit for each queue -- 1: enabled, 0: disabled
1546 * NOTE: This functionality is apparently a no-op; driver relies on interrupts
1547 * from Rx queue to read Tx command responses and update Tx queues.
1549 #define SCD_INTERRUPT_MASK (SCD_START_OFFSET + 0xe4)
1552 * Queue search status registers. One for each queue.
1553 * Sets up queue mode and assigns queue to Tx DMA channel.
1555 * 19-10: Write mask/enable bits for bits 0-9
1556 * 9: Driver should init to "0"
1557 * 8: Scheduler-ACK mode (1), non-Scheduler-ACK (i.e. FIFO) mode (0).
1558 * Driver should init to "1" for aggregation mode, or "0" otherwise.
1559 * 7-6: Driver should init to "0"
1560 * 5: Window Size Left; indicates whether scheduler can request
1561 * another TFD, based on window size, etc. Driver should init
1562 * this bit to "1" for aggregation mode, or "0" for non-agg.
1563 * 4-1: Tx FIFO to use (range 0-7).
1564 * 0: Queue is active (1), not active (0).
1565 * Other bits should be written as "0"
1567 * NOTE: If enabling Scheduler-ACK mode, chain mode should also be enabled
1568 * via SCD_QUEUECHAIN_SEL.
1570 #define SCD_QUEUE_STATUS_BITS(x) (SCD_START_OFFSET + 0x104 + (x) * 4)
1572 /* Bit field positions */
1573 #define SCD_QUEUE_STTS_REG_POS_ACTIVE (0)
1574 #define SCD_QUEUE_STTS_REG_POS_TXF (1)
1575 #define SCD_QUEUE_STTS_REG_POS_WSL (5)
1576 #define SCD_QUEUE_STTS_REG_POS_SCD_ACK (8)
1579 #define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10)
1580 #define SCD_QUEUE_STTS_REG_MSK (0x0007FC00)
1583 * 4965 internal SRAM structures for scheduler, shared with driver ...
1585 * Driver should clear and initialize the following areas after receiving
1586 * "Alive" response from 4965 uCode, i.e. after initial
1587 * uCode load, or after a uCode load done for error recovery:
1589 * SCD_CONTEXT_DATA_OFFSET (size 128 bytes)
1590 * SCD_TX_STTS_BITMAP_OFFSET (size 256 bytes)
1591 * SCD_TRANSLATE_TBL_OFFSET (size 32 bytes)
1593 * Driver accesses SRAM via HBUS_TARG_MEM_* registers.
1594 * Driver reads base address of this scheduler area from SCD_SRAM_BASE_ADDR.
1595 * All OFFSET values must be added to this base address.
1599 * Queue context. One 8-byte entry for each of 16 queues.
1601 * Driver should clear this entire area (size 0x80) to 0 after receiving
1602 * "Alive" notification from uCode. Additionally, driver should init
1603 * each queue's entry as follows:
1605 * LS Dword bit fields:
1606 * 0-06: Max Tx window size for Scheduler-ACK. Driver should init to 64.
1608 * MS Dword bit fields:
1609 * 16-22: Frame limit. Driver should init to 10 (0xa).
1611 * Driver should init all other bits to 0.
1613 * Init must be done after driver receives "Alive" response from 4965 uCode,
1614 * and when setting up queue for aggregation.
1616 #define SCD_CONTEXT_DATA_OFFSET 0x380
1617 #define SCD_CONTEXT_QUEUE_OFFSET(x) (SCD_CONTEXT_DATA_OFFSET + ((x) * 8))
1619 #define SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0)
1620 #define SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F)
1621 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
1622 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
1627 * Driver should clear this entire area (size 0x100) to 0 after receiving
1628 * "Alive" notification from uCode. Area is used only by device itself;
1629 * no other support (besides clearing) is required from driver.
1631 #define SCD_TX_STTS_BITMAP_OFFSET 0x400
1634 * RAxTID to queue translation mapping.
1636 * When queue is in Scheduler-ACK mode, frames placed in a that queue must be
1637 * for only one combination of receiver address (RA) and traffic ID (TID), i.e.
1638 * one QOS priority level destined for one station (for this wireless link,
1639 * not final destination). The SCD_TRANSLATE_TABLE area provides 16 16-bit
1640 * mappings, one for each of the 16 queues. If queue is not in Scheduler-ACK
1641 * mode, the device ignores the mapping value.
1643 * Bit fields, for each 16-bit map:
1644 * 15-9: Reserved, set to 0
1645 * 8-4: Index into device's station table for recipient station
1646 * 3-0: Traffic ID (tid), range 0-15
1648 * Driver should clear this entire area (size 32 bytes) to 0 after receiving
1649 * "Alive" notification from uCode. To update a 16-bit map value, driver
1650 * must read a dword-aligned value from device SRAM, replace the 16-bit map
1651 * value of interest, and write the dword value back into device SRAM.
1653 #define SCD_TRANSLATE_TBL_OFFSET 0x500
1655 /* Find translation table dword to read/write for given queue */
1656 #define SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \
1657 ((SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc)
1659 #define SCD_TXFIFO_POS_TID (0)
1660 #define SCD_TXFIFO_POS_RA (4)
1661 #define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
1663 /*********************** END TX SCHEDULER *************************************/
1665 static inline u8
iwl4965_hw_get_rate(__le32 rate_n_flags
)
1667 return le32_to_cpu(rate_n_flags
) & 0xFF;
1669 static inline u16
iwl4965_hw_get_rate_n_flags(__le32 rate_n_flags
)
1671 return le32_to_cpu(rate_n_flags
) & 0xFFFF;
1673 static inline __le32
iwl4965_hw_set_rate_n_flags(u8 rate
, u16 flags
)
1675 return cpu_to_le32(flags
|(u16
)rate
);
1682 * Most communication between driver and 4965 is via queues of data buffers.
1683 * For example, all commands that the driver issues to device's embedded
1684 * controller (uCode) are via the command queue (one of the Tx queues). All
1685 * uCode command responses/replies/notifications, including Rx frames, are
1686 * conveyed from uCode to driver via the Rx queue.
1688 * Most support for these queues, including handshake support, resides in
1689 * structures in host DRAM, shared between the driver and the device. When
1690 * allocating this memory, the driver must make sure that data written by
1691 * the host CPU updates DRAM immediately (and does not get "stuck" in CPU's
1692 * cache memory), so DRAM and cache are consistent, and the device can
1693 * immediately see changes made by the driver.
1695 * 4965 supports up to 16 DRAM-based Tx queues, and services these queues via
1696 * up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array
1697 * in DRAM containing 256 Transmit Frame Descriptors (TFDs).
1699 #define IWL4965_MAX_WIN_SIZE 64
1700 #define IWL4965_QUEUE_SIZE 256
1701 #define IWL4965_NUM_FIFOS 7
1702 #define IWL_MAX_NUM_QUEUES 16
1706 * struct iwl4965_tfd_frame_data
1708 * Describes up to 2 buffers containing (contiguous) portions of a Tx frame.
1709 * Each buffer must be on dword boundary.
1710 * Up to 10 iwl_tfd_frame_data structures, describing up to 20 buffers,
1711 * may be filled within a TFD (iwl_tfd_frame).
1713 * Bit fields in tb1_addr:
1714 * 31- 0: Tx buffer 1 address bits [31:0]
1716 * Bit fields in val1:
1717 * 31-16: Tx buffer 2 address bits [15:0]
1718 * 15- 4: Tx buffer 1 length (bytes)
1719 * 3- 0: Tx buffer 1 address bits [32:32]
1721 * Bit fields in val2:
1722 * 31-20: Tx buffer 2 length (bytes)
1723 * 19- 0: Tx buffer 2 address bits [35:16]
1725 struct iwl4965_tfd_frame_data
{
1729 /* __le32 ptb1_32_35:4; */
1730 #define IWL_tb1_addr_hi_POS 0
1731 #define IWL_tb1_addr_hi_LEN 4
1732 #define IWL_tb1_addr_hi_SYM val1
1733 /* __le32 tb_len1:12; */
1734 #define IWL_tb1_len_POS 4
1735 #define IWL_tb1_len_LEN 12
1736 #define IWL_tb1_len_SYM val1
1737 /* __le32 ptb2_0_15:16; */
1738 #define IWL_tb2_addr_lo16_POS 16
1739 #define IWL_tb2_addr_lo16_LEN 16
1740 #define IWL_tb2_addr_lo16_SYM val1
1743 /* __le32 ptb2_16_35:20; */
1744 #define IWL_tb2_addr_hi20_POS 0
1745 #define IWL_tb2_addr_hi20_LEN 20
1746 #define IWL_tb2_addr_hi20_SYM val2
1747 /* __le32 tb_len2:12; */
1748 #define IWL_tb2_len_POS 20
1749 #define IWL_tb2_len_LEN 12
1750 #define IWL_tb2_len_SYM val2
1751 } __attribute__ ((packed
));
1755 * struct iwl4965_tfd_frame
1757 * Transmit Frame Descriptor (TFD)
1759 * 4965 supports up to 16 Tx queues resident in host DRAM.
1760 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
1761 * Both driver and device share these circular buffers, each of which must be
1762 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes for 4965.
1764 * Driver must indicate the physical address of the base of each
1765 * circular buffer via the 4965's FH_MEM_CBBC_QUEUE registers.
1767 * Each TFD contains pointer/size information for up to 20 data buffers
1768 * in host DRAM. These buffers collectively contain the (one) frame described
1769 * by the TFD. Each buffer must be a single contiguous block of memory within
1770 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
1771 * of (4K - 4). The 4965 concatenates all of a TFD's buffers into a single
1772 * Tx frame, up to 8 KBytes in size.
1774 * Bit fields in the control dword (val0):
1775 * 31-30: # dwords (0-3) of padding required at end of frame for 16-byte bound
1777 * 28-24: # Transmit Buffer Descriptors in TFD
1780 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
1782 struct iwl4965_tfd_frame
{
1784 /* __le32 rsvd1:24; */
1785 /* __le32 num_tbs:5; */
1786 #define IWL_num_tbs_POS 24
1787 #define IWL_num_tbs_LEN 5
1788 #define IWL_num_tbs_SYM val0
1789 /* __le32 rsvd2:1; */
1790 /* __le32 padding:2; */
1791 struct iwl4965_tfd_frame_data pa
[10];
1793 } __attribute__ ((packed
));
1797 * struct iwl4965_queue_byte_cnt_entry
1799 * Byte Count Table Entry
1803 * 11- 0: total to-be-transmitted byte count of frame (does not include command)
1805 struct iwl4965_queue_byte_cnt_entry
{
1807 /* __le16 byte_cnt:12; */
1808 #define IWL_byte_cnt_POS 0
1809 #define IWL_byte_cnt_LEN 12
1810 #define IWL_byte_cnt_SYM val
1811 /* __le16 rsvd:4; */
1812 } __attribute__ ((packed
));
1816 * struct iwl4965_sched_queue_byte_cnt_tbl
1820 * Each Tx queue uses a byte-count table containing 320 entries:
1821 * one 16-bit entry for each of 256 TFDs, plus an additional 64 entries that
1822 * duplicate the first 64 entries (to avoid wrap-around within a Tx window;
1823 * max Tx window is 64 TFDs).
1825 * When driver sets up a new TFD, it must also enter the total byte count
1826 * of the frame to be transmitted into the corresponding entry in the byte
1827 * count table for the chosen Tx queue. If the TFD index is 0-63, the driver
1828 * must duplicate the byte count entry in corresponding index 256-319.
1830 * "dont_care" padding puts each byte count table on a 1024-byte boundary;
1831 * 4965 assumes tables are separated by 1024 bytes.
1833 struct iwl4965_sched_queue_byte_cnt_tbl
{
1834 struct iwl4965_queue_byte_cnt_entry tfd_offset
[IWL4965_QUEUE_SIZE
+
1835 IWL4965_MAX_WIN_SIZE
];
1837 (IWL4965_QUEUE_SIZE
+ IWL4965_MAX_WIN_SIZE
) *
1839 } __attribute__ ((packed
));
1843 * struct iwl4965_shared - handshake area for Tx and Rx
1845 * For convenience in allocating memory, this structure combines 2 areas of
1846 * DRAM which must be shared between driver and 4965. These do not need to
1847 * be combined, if better allocation would result from keeping them separate:
1849 * 1) The Tx byte count tables occupy 1024 bytes each (16 KBytes total for
1850 * 16 queues). Driver uses SCD_DRAM_BASE_ADDR to tell 4965 where to find
1851 * the first of these tables. 4965 assumes tables are 1024 bytes apart.
1853 * 2) The Rx status (val0 and val1) occupies only 8 bytes. Driver uses
1854 * FH_RSCSR_CHNL0_STTS_WPTR_REG to tell 4965 where to find this area.
1855 * Driver reads val0 to determine the latest Receive Buffer Descriptor (RBD)
1856 * that has been filled by the 4965.
1860 * 11- 0: Index of last filled Rx buffer descriptor (4965 writes, driver reads)
1865 struct iwl4965_shared
{
1866 struct iwl4965_sched_queue_byte_cnt_tbl
1867 queues_byte_cnt_tbls
[IWL_MAX_NUM_QUEUES
];
1870 /* __le32 rb_closed_stts_rb_num:12; */
1871 #define IWL_rb_closed_stts_rb_num_POS 0
1872 #define IWL_rb_closed_stts_rb_num_LEN 12
1873 #define IWL_rb_closed_stts_rb_num_SYM val0
1874 /* __le32 rsrv1:4; */
1875 /* __le32 rb_closed_stts_rx_frame_num:12; */
1876 #define IWL_rb_closed_stts_rx_frame_num_POS 16
1877 #define IWL_rb_closed_stts_rx_frame_num_LEN 12
1878 #define IWL_rb_closed_stts_rx_frame_num_SYM val0
1879 /* __le32 rsrv2:4; */
1882 /* __le32 frame_finished_stts_rb_num:12; */
1883 #define IWL_frame_finished_stts_rb_num_POS 0
1884 #define IWL_frame_finished_stts_rb_num_LEN 12
1885 #define IWL_frame_finished_stts_rb_num_SYM val1
1886 /* __le32 rsrv3:4; */
1887 /* __le32 frame_finished_stts_rx_frame_num:12; */
1888 #define IWL_frame_finished_stts_rx_frame_num_POS 16
1889 #define IWL_frame_finished_stts_rx_frame_num_LEN 12
1890 #define IWL_frame_finished_stts_rx_frame_num_SYM val1
1891 /* __le32 rsrv4:4; */
1893 __le32 padding1
; /* so that allocation will be aligned to 16B */
1895 } __attribute__ ((packed
));
1897 #endif /* __iwl4965_4965_hw_h__ */