arch/arm/mach-at91/gpio.c

   1 /*
   2  * linux/arch/arm/mach-at91/gpio.c
   3  *
   4  * Copyright (C) 2005 HP Labs
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/errno.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/seq_file.h>
  18 #include <linux/kernel.h>
  19 #include <linux/list.h>
  20 #include <linux/module.h>
  21
  22 #include <asm/io.h>
  23 #include <asm/hardware.h>
  24 #include <asm/arch/at91_pio.h>
  25 #include <asm/arch/gpio.h>
  26
  27 #include "generic.h"
  28
  29
  30 static struct at91_gpio_bank *gpio;
  31 static int gpio_banks;
  32
  33
  34 static inline void __iomem *pin_to_controller(unsigned pin)
  35 {
  36         void __iomem *sys_base = (void __iomem *) AT91_VA_BASE_SYS;
  37
  38         pin -= PIN_BASE;
  39         pin /= 32;
  40         if (likely(pin < gpio_banks))
  41                 return sys_base + gpio[pin].offset;
  42
  43         return NULL;
  44 }
  45
  46 static inline unsigned pin_to_mask(unsigned pin)
  47 {
  48         pin -= PIN_BASE;
  49         return 1 << (pin % 32);
  50 }
  51
  52
  53 /*--------------------------------------------------------------------------*/
  54
  55 /* Not all hardware capabilities are exposed through these calls; they
  56  * only encapsulate the most common features and modes.  (So if you
  57  * want to change signals in groups, do it directly.)
  58  *
  59  * Bootloaders will usually handle some of the pin multiplexing setup.
  60  * The intent is certainly that by the time Linux is fully booted, all
  61  * pins should have been fully initialized.  These setup calls should
  62  * only be used by board setup routines, or possibly in driver probe().
  63  *
  64  * For bootloaders doing all that setup, these calls could be inlined
  65  * as NOPs so Linux won't duplicate any setup code
  66  */
  67
  68
  69 /*
  70  * mux the pin to the "GPIO" peripheral role.
  71  */
  72 int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup)
  73 {
  74         void __iomem    *pio = pin_to_controller(pin);
  75         unsigned        mask = pin_to_mask(pin);
  76
  77         if (!pio)
  78                 return -EINVAL;
  79         __raw_writel(mask, pio + PIO_IDR);
  80         __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
  81         __raw_writel(mask, pio + PIO_PER);
  82         return 0;
  83 }
  84 EXPORT_SYMBOL(at91_set_GPIO_periph);
  85
  86
  87 /*
  88  * mux the pin to the "A" internal peripheral role.
  89  */
  90 int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
  91 {
  92         void __iomem    *pio = pin_to_controller(pin);
  93         unsigned        mask = pin_to_mask(pin);
  94
  95         if (!pio)
  96                 return -EINVAL;
  97
  98         __raw_writel(mask, pio + PIO_IDR);
  99         __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
 100         __raw_writel(mask, pio + PIO_ASR);
 101         __raw_writel(mask, pio + PIO_PDR);
 102         return 0;
 103 }
 104 EXPORT_SYMBOL(at91_set_A_periph);
 105
 106
 107 /*
 108  * mux the pin to the "B" internal peripheral role.
 109  */
 110 int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
 111 {
 112         void __iomem    *pio = pin_to_controller(pin);
 113         unsigned        mask = pin_to_mask(pin);
 114
 115         if (!pio)
 116                 return -EINVAL;
 117
 118         __raw_writel(mask, pio + PIO_IDR);
 119         __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
 120         __raw_writel(mask, pio + PIO_BSR);
 121         __raw_writel(mask, pio + PIO_PDR);
 122         return 0;
 123 }
 124 EXPORT_SYMBOL(at91_set_B_periph);
 125
 126
 127 /*
 128  * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
 129  * configure it for an input.
 130  */
 131 int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
 132 {
 133         void __iomem    *pio = pin_to_controller(pin);
 134         unsigned        mask = pin_to_mask(pin);
 135
 136         if (!pio)
 137                 return -EINVAL;
 138
 139         __raw_writel(mask, pio + PIO_IDR);
 140         __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
 141         __raw_writel(mask, pio + PIO_ODR);
 142         __raw_writel(mask, pio + PIO_PER);
 143         return 0;
 144 }
 145 EXPORT_SYMBOL(at91_set_gpio_input);
 146
 147
 148 /*
 149  * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
 150  * and configure it for an output.
 151  */
 152 int __init_or_module at91_set_gpio_output(unsigned pin, int value)
 153 {
 154         void __iomem    *pio = pin_to_controller(pin);
 155         unsigned        mask = pin_to_mask(pin);
 156
 157         if (!pio)
 158                 return -EINVAL;
 159
 160         __raw_writel(mask, pio + PIO_IDR);
 161         __raw_writel(mask, pio + PIO_PUDR);
 162         __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
 163         __raw_writel(mask, pio + PIO_OER);
 164         __raw_writel(mask, pio + PIO_PER);
 165         return 0;
 166 }
 167 EXPORT_SYMBOL(at91_set_gpio_output);
 168
 169
 170 /*
 171  * enable/disable the glitch filter; mostly used with IRQ handling.
 172  */
 173 int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
 174 {
 175         void __iomem    *pio = pin_to_controller(pin);
 176         unsigned        mask = pin_to_mask(pin);
 177
 178         if (!pio)
 179                 return -EINVAL;
 180         __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
 181         return 0;
 182 }
 183 EXPORT_SYMBOL(at91_set_deglitch);
 184
 185 /*
 186  * enable/disable the multi-driver; This is only valid for output and
 187  * allows the output pin to run as an open collector output.
 188  */
 189 int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
 190 {
 191         void __iomem    *pio = pin_to_controller(pin);
 192         unsigned        mask = pin_to_mask(pin);
 193
 194         if (!pio)
 195                 return -EINVAL;
 196
 197         __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
 198         return 0;
 199 }
 200 EXPORT_SYMBOL(at91_set_multi_drive);
 201
 202 /*--------------------------------------------------------------------------*/
 203
 204 /* new-style GPIO calls; these expect at91_set_GPIO_periph to have been
 205  * called, and maybe at91_set_multi_drive() for putout pins.
 206  */
 207
 208 int gpio_direction_input(unsigned pin)
 209 {
 210         void __iomem    *pio = pin_to_controller(pin);
 211         unsigned        mask = pin_to_mask(pin);
 212
 213         if (!pio || !(__raw_readl(pio + PIO_PSR) & mask))
 214                 return -EINVAL;
 215         __raw_writel(mask, pio + PIO_ODR);
 216         return 0;
 217 }
 218 EXPORT_SYMBOL(gpio_direction_input);
 219
 220 int gpio_direction_output(unsigned pin, int value)
 221 {
 222         void __iomem    *pio = pin_to_controller(pin);
 223         unsigned        mask = pin_to_mask(pin);
 224
 225         if (!pio || !(__raw_readl(pio + PIO_PSR) & mask))
 226                 return -EINVAL;
 227         __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
 228         __raw_writel(mask, pio + PIO_OER);
 229         return 0;
 230 }
 231 EXPORT_SYMBOL(gpio_direction_output);
 232
 233 /*--------------------------------------------------------------------------*/
 234
 235 /*
 236  * assuming the pin is muxed as a gpio output, set its value.
 237  */
 238 int at91_set_gpio_value(unsigned pin, int value)
 239 {
 240         void __iomem    *pio = pin_to_controller(pin);
 241         unsigned        mask = pin_to_mask(pin);
 242
 243         if (!pio)
 244                 return -EINVAL;
 245         __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
 246         return 0;
 247 }
 248 EXPORT_SYMBOL(at91_set_gpio_value);
 249
 250
 251 /*
 252  * read the pin's value (works even if it's not muxed as a gpio).
 253  */
 254 int at91_get_gpio_value(unsigned pin)
 255 {
 256         void __iomem    *pio = pin_to_controller(pin);
 257         unsigned        mask = pin_to_mask(pin);
 258         u32             pdsr;
 259
 260         if (!pio)
 261                 return -EINVAL;
 262         pdsr = __raw_readl(pio + PIO_PDSR);
 263         return (pdsr & mask) != 0;
 264 }
 265 EXPORT_SYMBOL(at91_get_gpio_value);
 266
 267 /*--------------------------------------------------------------------------*/
 268
 269 #ifdef CONFIG_PM
 270
 271 static u32 wakeups[MAX_GPIO_BANKS];
 272 static u32 backups[MAX_GPIO_BANKS];
 273
 274 static int gpio_irq_set_wake(unsigned pin, unsigned state)
 275 {
 276         unsigned        mask = pin_to_mask(pin);
 277         unsigned        bank = (pin - PIN_BASE) / 32;
 278
 279         if (unlikely(bank >= MAX_GPIO_BANKS))
 280                 return -EINVAL;
 281
 282         if (state)
 283                 wakeups[bank] |= mask;
 284         else
 285                 wakeups[bank] &= ~mask;
 286
 287         set_irq_wake(gpio[bank].id, state);
 288
 289         return 0;
 290 }
 291
 292 void at91_gpio_suspend(void)
 293 {
 294         int i;
 295
 296         for (i = 0; i < gpio_banks; i++) {
 297                 u32 pio = gpio[i].offset;
 298
 299                 backups[i] = at91_sys_read(pio + PIO_IMR);
 300                 at91_sys_write(pio + PIO_IDR, backups[i]);
 301                 at91_sys_write(pio + PIO_IER, wakeups[i]);
 302
 303                 if (!wakeups[i])
 304                         clk_disable(gpio[i].clock);
 305                 else {
 306 #ifdef CONFIG_PM_DEBUG
 307                         printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
 308 #endif
 309                 }
 310         }
 311 }
 312
 313 void at91_gpio_resume(void)
 314 {
 315         int i;
 316
 317         for (i = 0; i < gpio_banks; i++) {
 318                 u32 pio = gpio[i].offset;
 319
 320                 if (!wakeups[i])
 321                         clk_enable(gpio[i].clock);
 322
 323                 at91_sys_write(pio + PIO_IDR, wakeups[i]);
 324                 at91_sys_write(pio + PIO_IER, backups[i]);
 325         }
 326 }
 327
 328 #else
 329 #define gpio_irq_set_wake       NULL
 330 #endif
 331
 332
 333 /* Several AIC controller irqs are dispatched through this GPIO handler.
 334  * To use any AT91_PIN_* as an externally triggered IRQ, first call
 335  * at91_set_gpio_input() then maybe enable its glitch filter.
 336  * Then just request_irq() with the pin ID; it works like any ARM IRQ
 337  * handler, though it always triggers on rising and falling edges.
 338  *
 339  * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
 340  * configuring them with at91_set_a_periph() or at91_set_b_periph().
 341  * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
 342  */
 343
 344 static void gpio_irq_mask(unsigned pin)
 345 {
 346         void __iomem    *pio = pin_to_controller(pin);
 347         unsigned        mask = pin_to_mask(pin);
 348
 349         if (pio)
 350                 __raw_writel(mask, pio + PIO_IDR);
 351 }
 352
 353 static void gpio_irq_unmask(unsigned pin)
 354 {
 355         void __iomem    *pio = pin_to_controller(pin);
 356         unsigned        mask = pin_to_mask(pin);
 357
 358         if (pio)
 359                 __raw_writel(mask, pio + PIO_IER);
 360 }
 361
 362 static int gpio_irq_type(unsigned pin, unsigned type)
 363 {
 364         return (type == IRQT_BOTHEDGE) ? 0 : -EINVAL;
 365 }
 366
 367 static struct irq_chip gpio_irqchip = {
 368         .name           = "GPIO",
 369         .mask           = gpio_irq_mask,
 370         .unmask         = gpio_irq_unmask,
 371         .set_type       = gpio_irq_type,
 372         .set_wake       = gpio_irq_set_wake,
 373 };
 374
 375 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 376 {
 377         unsigned        pin;
 378         struct irq_desc *gpio;
 379         void __iomem    *pio;
 380         u32             isr;
 381
 382         pio = get_irq_chip_data(irq);
 383
 384         /* temporarily mask (level sensitive) parent IRQ */
 385         desc->chip->ack(irq);
 386         for (;;) {
 387                 /* reading ISR acks the pending (edge triggered) GPIO interrupt */
 388                 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
 389                 if (!isr)
 390                         break;
 391
 392                 pin = (unsigned) get_irq_data(irq);
 393                 gpio = &irq_desc[pin];
 394
 395                 while (isr) {
 396                         if (isr & 1) {
 397                                 if (unlikely(gpio->depth)) {
 398                                         /*
 399                                          * The core ARM interrupt handler lazily disables IRQs so
 400                                          * another IRQ must be generated before it actually gets
 401                                          * here to be disabled on the GPIO controller.
 402                                          */
 403                                         gpio_irq_mask(pin);
 404                                 }
 405                                 else
 406                                         desc_handle_irq(pin, gpio);
 407                         }
 408                         pin++;
 409                         gpio++;
 410                         isr >>= 1;
 411                 }
 412         }
 413         desc->chip->unmask(irq);
 414         /* now it may re-trigger */
 415 }
 416
 417 /*--------------------------------------------------------------------------*/
 418
 419 #ifdef CONFIG_DEBUG_FS
 420
 421 static int at91_gpio_show(struct seq_file *s, void *unused)
 422 {
 423         int bank, j;
 424
 425         /* print heading */
 426         seq_printf(s, "Pin\t");
 427         for (bank = 0; bank < gpio_banks; bank++) {
 428                 seq_printf(s, "PIO%c\t", 'A' + bank);
 429         };
 430         seq_printf(s, "\n\n");
 431
 432         /* print pin status */
 433         for (j = 0; j < 32; j++) {
 434                 seq_printf(s, "%i:\t", j);
 435
 436                 for (bank = 0; bank < gpio_banks; bank++) {
 437                         unsigned        pin  = PIN_BASE + (32 * bank) + j;
 438                         void __iomem    *pio = pin_to_controller(pin);
 439                         unsigned        mask = pin_to_mask(pin);
 440
 441                         if (__raw_readl(pio + PIO_PSR) & mask)
 442                                 seq_printf(s, "GPIO:%s", __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
 443                         else
 444                                 seq_printf(s, "%s", __raw_readl(pio + PIO_ABSR) & mask ? "B" : "A");
 445
 446                         seq_printf(s, "\t");
 447                 }
 448
 449                 seq_printf(s, "\n");
 450         }
 451
 452         return 0;
 453 }
 454
 455 static int at91_gpio_open(struct inode *inode, struct file *file)
 456 {
 457         return single_open(file, at91_gpio_show, NULL);
 458 }
 459
 460 static const struct file_operations at91_gpio_operations = {
 461         .open           = at91_gpio_open,
 462         .read           = seq_read,
 463         .llseek         = seq_lseek,
 464         .release        = single_release,
 465 };
 466
 467 static int __init at91_gpio_debugfs_init(void)
 468 {
 469         /* /sys/kernel/debug/at91_gpio */
 470         (void) debugfs_create_file("at91_gpio", S_IFREG | S_IRUGO, NULL, NULL, &at91_gpio_operations);
 471         return 0;
 472 }
 473 postcore_initcall(at91_gpio_debugfs_init);
 474
 475 #endif
 476
 477 /*--------------------------------------------------------------------------*/
 478
 479 /*
 480  * Called from the processor-specific init to enable GPIO interrupt support.
 481  */
 482 void __init at91_gpio_irq_setup(void)
 483 {
 484         unsigned        pioc, pin;
 485
 486         for (pioc = 0, pin = PIN_BASE;
 487                         pioc < gpio_banks;
 488                         pioc++) {
 489                 void __iomem    *controller;
 490                 unsigned        id = gpio[pioc].id;
 491                 unsigned        i;
 492
 493                 clk_enable(gpio[pioc].clock);   /* enable PIO controller's clock */
 494
 495                 controller = (void __iomem *) AT91_VA_BASE_SYS + gpio[pioc].offset;
 496                 __raw_writel(~0, controller + PIO_IDR);
 497
 498                 set_irq_data(id, (void *) pin);
 499                 set_irq_chip_data(id, controller);
 500
 501                 for (i = 0; i < 32; i++, pin++) {
 502                         /*
 503                          * Can use the "simple" and not "edge" handler since it's
 504                          * shorter, and the AIC handles interrupts sanely.
 505                          */
 506                         set_irq_chip(pin, &gpio_irqchip);
 507                         set_irq_handler(pin, handle_simple_irq);
 508                         set_irq_flags(pin, IRQF_VALID);
 509                 }
 510
 511                 set_irq_chained_handler(id, gpio_irq_handler);
 512         }
 513         pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
 514 }
 515
 516 /*
 517  * Called from the processor-specific init to enable GPIO pin support.
 518  */
 519 void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
 520 {
 521         BUG_ON(nr_banks > MAX_GPIO_BANKS);
 522
 523         gpio = data;
 524         gpio_banks = nr_banks;
 525 }