| blob | 60f0eab4ca8d77d084b19adcd3c0e02e8ecc242d |
1 /*
2 * MPC8568E MDS Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
13 /*
14 /memreserve/ 00000000 1000000;
15 */
17 / {
18 model = "MPC8568EMDS";
19 compatible = "MPC8568EMDS", "MPC85xxMDS";
20 #address-cells = <1>;
21 #size-cells = <1>;
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
27 PowerPC,8568@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <20>; // 32 bytes
31 i-cache-line-size = <20>; // 32 bytes
32 d-cache-size = <8000>; // L1, 32K
33 i-cache-size = <8000>; // L1, 32K
34 timebase-frequency = <0>;
35 bus-frequency = <0>;
36 clock-frequency = <0>;
37 };
38 };
40 memory {
41 device_type = "memory";
42 reg = <00000000 10000000>;
43 };
45 bcsr@f8000000 {
46 device_type = "board-control";
47 reg = <f8000000 8000>;
48 };
50 soc8568@e0000000 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 device_type = "soc";
54 ranges = <0 e0000000 00100000>;
55 reg = <e0000000 00001000>;
56 bus-frequency = <0>;
58 memory-controller@2000 {
59 compatible = "fsl,8568-memory-controller";
60 reg = <2000 1000>;
61 interrupt-parent = <&mpic>;
62 interrupts = <12 2>;
63 };
65 l2-cache-controller@20000 {
66 compatible = "fsl,8568-l2-cache-controller";
67 reg = <20000 1000>;
68 cache-line-size = <20>; // 32 bytes
69 cache-size = <80000>; // L2, 512K
70 interrupt-parent = <&mpic>;
71 interrupts = <10 2>;
72 };
74 i2c@3000 {
75 #address-cells = <1>;
76 #size-cells = <0>;
77 cell-index = <0>;
78 compatible = "fsl-i2c";
79 reg = <3000 100>;
80 interrupts = <2b 2>;
81 interrupt-parent = <&mpic>;
82 dfsrr;
84 rtc@68 {
85 compatible = "dallas,ds1374";
86 reg = <68>;
87 };
88 };
90 i2c@3100 {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 cell-index = <1>;
94 compatible = "fsl-i2c";
95 reg = <3100 100>;
96 interrupts = <2b 2>;
97 interrupt-parent = <&mpic>;
98 dfsrr;
99 };
101 mdio@24520 {
102 #address-cells = <1>;
103 #size-cells = <0>;
104 compatible = "fsl,gianfar-mdio";
105 reg = <24520 20>;
107 phy0: ethernet-phy@7 {
108 interrupt-parent = <&mpic>;
109 interrupts = <1 1>;
110 reg = <7>;
111 device_type = "ethernet-phy";
112 };
113 phy1: ethernet-phy@1 {
114 interrupt-parent = <&mpic>;
115 interrupts = <2 1>;
116 reg = <1>;
117 device_type = "ethernet-phy";
118 };
119 phy2: ethernet-phy@2 {
120 interrupt-parent = <&mpic>;
121 interrupts = <1 1>;
122 reg = <2>;
123 device_type = "ethernet-phy";
124 };
125 phy3: ethernet-phy@3 {
126 interrupt-parent = <&mpic>;
127 interrupts = <2 1>;
128 reg = <3>;
129 device_type = "ethernet-phy";
130 };
131 };
133 enet0: ethernet@24000 {
134 cell-index = <0>;
135 device_type = "network";
136 model = "eTSEC";
137 compatible = "gianfar";
138 reg = <24000 1000>;
139 local-mac-address = [ 00 00 00 00 00 00 ];
140 interrupts = <1d 2 1e 2 22 2>;
141 interrupt-parent = <&mpic>;
142 phy-handle = <&phy2>;
143 };
145 enet1: ethernet@25000 {
146 cell-index = <1>;
147 device_type = "network";
148 model = "eTSEC";
149 compatible = "gianfar";
150 reg = <25000 1000>;
151 local-mac-address = [ 00 00 00 00 00 00 ];
152 interrupts = <23 2 24 2 28 2>;
153 interrupt-parent = <&mpic>;
154 phy-handle = <&phy3>;
155 };
157 serial@4500 {
158 device_type = "serial";
159 compatible = "ns16550";
160 reg = <4500 100>;
161 clock-frequency = <0>;
162 interrupts = <2a 2>;
163 interrupt-parent = <&mpic>;
164 };
166 global-utilities@e0000 { //global utilities block
167 compatible = "fsl,mpc8548-guts";
168 reg = <e0000 1000>;
169 fsl,has-rstcr;
170 };
172 serial@4600 {
173 device_type = "serial";
174 compatible = "ns16550";
175 reg = <4600 100>;
176 clock-frequency = <0>;
177 interrupts = <2a 2>;
178 interrupt-parent = <&mpic>;
179 };
181 crypto@30000 {
182 device_type = "crypto";
183 model = "SEC2";
184 compatible = "talitos";
185 reg = <30000 f000>;
186 interrupts = <2d 2>;
187 interrupt-parent = <&mpic>;
188 num-channels = <4>;
189 channel-fifo-len = <18>;
190 exec-units-mask = <000000fe>;
191 descriptor-types-mask = <012b0ebf>;
192 };
194 mpic: pic@40000 {
195 clock-frequency = <0>;
196 interrupt-controller;
197 #address-cells = <0>;
198 #interrupt-cells = <2>;
199 reg = <40000 40000>;
200 compatible = "chrp,open-pic";
201 device_type = "open-pic";
202 big-endian;
203 };
205 par_io@e0100 {
206 reg = <e0100 100>;
207 device_type = "par_io";
208 num-ports = <7>;
210 pio1: ucc_pin@01 {
211 pio-map = <
212 /* port pin dir open_drain assignment has_irq */
213 4 0a 1 0 2 0 /* TxD0 */
214 4 09 1 0 2 0 /* TxD1 */
215 4 08 1 0 2 0 /* TxD2 */
216 4 07 1 0 2 0 /* TxD3 */
217 4 17 1 0 2 0 /* TxD4 */
218 4 16 1 0 2 0 /* TxD5 */
219 4 15 1 0 2 0 /* TxD6 */
220 4 14 1 0 2 0 /* TxD7 */
221 4 0f 2 0 2 0 /* RxD0 */
222 4 0e 2 0 2 0 /* RxD1 */
223 4 0d 2 0 2 0 /* RxD2 */
224 4 0c 2 0 2 0 /* RxD3 */
225 4 1d 2 0 2 0 /* RxD4 */
226 4 1c 2 0 2 0 /* RxD5 */
227 4 1b 2 0 2 0 /* RxD6 */
228 4 1a 2 0 2 0 /* RxD7 */
229 4 0b 1 0 2 0 /* TX_EN */
230 4 18 1 0 2 0 /* TX_ER */
231 4 10 2 0 2 0 /* RX_DV */
232 4 1e 2 0 2 0 /* RX_ER */
233 4 11 2 0 2 0 /* RX_CLK */
234 4 13 1 0 2 0 /* GTX_CLK */
235 1 1f 2 0 3 0>; /* GTX125 */
236 };
238 pio2: ucc_pin@02 {
239 pio-map = <
240 /* port pin dir open_drain assignment has_irq */
241 5 0a 1 0 2 0 /* TxD0 */
242 5 09 1 0 2 0 /* TxD1 */
243 5 08 1 0 2 0 /* TxD2 */
244 5 07 1 0 2 0 /* TxD3 */
245 5 17 1 0 2 0 /* TxD4 */
246 5 16 1 0 2 0 /* TxD5 */
247 5 15 1 0 2 0 /* TxD6 */
248 5 14 1 0 2 0 /* TxD7 */
249 5 0f 2 0 2 0 /* RxD0 */
250 5 0e 2 0 2 0 /* RxD1 */
251 5 0d 2 0 2 0 /* RxD2 */
252 5 0c 2 0 2 0 /* RxD3 */
253 5 1d 2 0 2 0 /* RxD4 */
254 5 1c 2 0 2 0 /* RxD5 */
255 5 1b 2 0 2 0 /* RxD6 */
256 5 1a 2 0 2 0 /* RxD7 */
257 5 0b 1 0 2 0 /* TX_EN */
258 5 18 1 0 2 0 /* TX_ER */
259 5 10 2 0 2 0 /* RX_DV */
260 5 1e 2 0 2 0 /* RX_ER */
261 5 11 2 0 2 0 /* RX_CLK */
262 5 13 1 0 2 0 /* GTX_CLK */
263 1 1f 2 0 3 0 /* GTX125 */
264 4 06 3 0 2 0 /* MDIO */
265 4 05 1 0 2 0>; /* MDC */
266 };
267 };
268 };
270 qe@e0080000 {
271 #address-cells = <1>;
272 #size-cells = <1>;
273 device_type = "qe";
274 model = "QE";
275 ranges = <0 e0080000 00040000>;
276 reg = <e0080000 480>;
277 brg-frequency = <0>;
278 bus-frequency = <179A7B00>;
280 muram@10000 {
281 device_type = "muram";
282 ranges = <0 00010000 0000c000>;
284 data-only@0{
285 reg = <0 c000>;
286 };
287 };
289 spi@4c0 {
290 device_type = "spi";
291 compatible = "fsl_spi";
292 reg = <4c0 40>;
293 interrupts = <2>;
294 interrupt-parent = <&qeic>;
295 mode = "cpu";
296 };
298 spi@500 {
299 device_type = "spi";
300 compatible = "fsl_spi";
301 reg = <500 40>;
302 interrupts = <1>;
303 interrupt-parent = <&qeic>;
304 mode = "cpu";
305 };
307 enet2: ucc@2000 {
308 device_type = "network";
309 compatible = "ucc_geth";
310 model = "UCC";
311 cell-index = <1>;
312 device-id = <1>;
313 reg = <2000 200>;
314 interrupts = <20>;
315 interrupt-parent = <&qeic>;
316 local-mac-address = [ 00 00 00 00 00 00 ];
317 rx-clock = <0>;
318 tx-clock = <20>;
319 pio-handle = <&pio1>;
320 phy-handle = <&phy0>;
321 phy-connection-type = "rgmii-id";
322 };
324 enet3: ucc@3000 {
325 device_type = "network";
326 compatible = "ucc_geth";
327 model = "UCC";
328 cell-index = <2>;
329 device-id = <2>;
330 reg = <3000 200>;
331 interrupts = <21>;
332 interrupt-parent = <&qeic>;
333 local-mac-address = [ 00 00 00 00 00 00 ];
334 rx-clock = <0>;
335 tx-clock = <20>;
336 pio-handle = <&pio2>;
337 phy-handle = <&phy1>;
338 phy-connection-type = "rgmii-id";
339 };
341 mdio@2120 {
342 #address-cells = <1>;
343 #size-cells = <0>;
344 reg = <2120 18>;
345 compatible = "ucc_geth_phy";
347 /* These are the same PHYs as on
348 * gianfar's MDIO bus */
349 qe_phy0: ethernet-phy@07 {
350 interrupt-parent = <&mpic>;
351 interrupts = <1 1>;
352 reg = <7>;
353 device_type = "ethernet-phy";
354 };
355 qe_phy1: ethernet-phy@01 {
356 interrupt-parent = <&mpic>;
357 interrupts = <2 1>;
358 reg = <1>;
359 device_type = "ethernet-phy";
360 };
361 qe_phy2: ethernet-phy@02 {
362 interrupt-parent = <&mpic>;
363 interrupts = <1 1>;
364 reg = <2>;
365 device_type = "ethernet-phy";
366 };
367 qe_phy3: ethernet-phy@03 {
368 interrupt-parent = <&mpic>;
369 interrupts = <2 1>;
370 reg = <3>;
371 device_type = "ethernet-phy";
372 };
373 };
375 qeic: qeic@80 {
376 interrupt-controller;
377 device_type = "qeic";
378 #address-cells = <0>;
379 #interrupt-cells = <1>;
380 reg = <80 80>;
381 big-endian;
382 interrupts = <2e 2 2e 2>; //high:30 low:30
383 interrupt-parent = <&mpic>;
384 };
386 };
388 pci@e0008000 {
389 interrupt-map-mask = <f800 0 0 7>;
390 interrupt-map = <
391 /* IDSEL 0x12 AD18 */
392 9000 0 0 1 &mpic 5 1
393 9000 0 0 2 &mpic 6 1
394 9000 0 0 3 &mpic 7 1
395 9000 0 0 4 &mpic 4 1
397 /* IDSEL 0x13 AD19 */
398 9800 0 0 1 &mpic 6 1
399 9800 0 0 2 &mpic 7 1
400 9800 0 0 3 &mpic 4 1
401 9800 0 0 4 &mpic 5 1>;
403 interrupt-parent = <&mpic>;
404 interrupts = <18 2>;
405 bus-range = <0 ff>;
406 ranges = <02000000 0 80000000 80000000 0 20000000
407 01000000 0 00000000 e2000000 0 00800000>;
408 clock-frequency = <3f940aa>;
409 #interrupt-cells = <1>;
410 #size-cells = <2>;
411 #address-cells = <3>;
412 reg = <e0008000 1000>;
413 compatible = "fsl,mpc8540-pci";
414 device_type = "pci";
415 };
417 /* PCI Express */
418 pcie@e000a000 {
419 interrupt-map-mask = <f800 0 0 7>;
420 interrupt-map = <
422 /* IDSEL 0x0 (PEX) */
423 00000 0 0 1 &mpic 0 1
424 00000 0 0 2 &mpic 1 1
425 00000 0 0 3 &mpic 2 1
426 00000 0 0 4 &mpic 3 1>;
428 interrupt-parent = <&mpic>;
429 interrupts = <1a 2>;
430 bus-range = <0 ff>;
431 ranges = <02000000 0 a0000000 a0000000 0 10000000
432 01000000 0 00000000 e2800000 0 00800000>;
433 clock-frequency = <1fca055>;
434 #interrupt-cells = <1>;
435 #size-cells = <2>;
436 #address-cells = <3>;
437 reg = <e000a000 1000>;
438 compatible = "fsl,mpc8548-pcie";
439 device_type = "pci";
440 pcie@0 {
441 reg = <0 0 0 0 0>;
442 #size-cells = <2>;
443 #address-cells = <3>;
444 device_type = "pci";
445 ranges = <02000000 0 a0000000
446 02000000 0 a0000000
447 0 10000000
449 01000000 0 00000000
450 01000000 0 00000000
451 0 00800000>;
452 };
453 };
454 };