2 * linux/drivers/ide/pci/cs5530.c Version 0.7 Sept 10, 2002
4 * Copyright (C) 2000 Andre Hedrick <andre@linux-ide.org>
5 * Ditto of GNU General Public License.
7 * Copyright (C) 2000 Mark Lord <mlord@pobox.com>
8 * May be copied or modified under the terms of the GNU General Public License
10 * Development of this chipset driver was funded
11 * by the nice folks at National Semiconductor.
14 * CS5530 documentation available from National Semiconductor.
17 #include <linux/module.h>
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/timer.h>
23 #include <linux/ioport.h>
24 #include <linux/blkdev.h>
25 #include <linux/hdreg.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/ide.h>
34 * cs5530_xfer_set_mode - set a new transfer mode at the drive
35 * @drive: drive to tune
38 * Logging wrapper to the IDE driver speed configuration. This can
39 * probably go away now.
42 static int cs5530_set_xfer_mode (ide_drive_t
*drive
, u8 mode
)
44 printk(KERN_DEBUG
"%s: cs5530_set_xfer_mode(%s)\n",
45 drive
->name
, ide_xfer_verbose(mode
));
46 return (ide_config_drive_speed(drive
, mode
));
50 * Here are the standard PIO mode 0-4 timings for each "format".
51 * Format-0 uses fast data reg timings, with slower command reg timings.
52 * Format-1 uses fast timings for all registers, but won't work with all drives.
54 static unsigned int cs5530_pio_timings
[2][5] = {
55 {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
56 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
60 * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
62 #define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
63 #define CS5530_BASEREG(hwif) (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
66 * cs5530_tuneproc - select/set PIO modes
68 * cs5530_tuneproc() handles selection/setting of PIO modes
69 * for both the chipset and drive.
71 * The ide_init_cs5530() routine guarantees that all drives
72 * will have valid default PIO timings set up before we get here.
75 static void cs5530_tuneproc (ide_drive_t
*drive
, u8 pio
) /* pio=255 means "autotune" */
77 ide_hwif_t
*hwif
= HWIF(drive
);
79 unsigned long basereg
= CS5530_BASEREG(hwif
);
80 static u8 modes
[5] = { XFER_PIO_0
, XFER_PIO_1
, XFER_PIO_2
, XFER_PIO_3
, XFER_PIO_4
};
82 pio
= ide_get_best_pio_mode(drive
, pio
, 4, NULL
);
83 if (!cs5530_set_xfer_mode(drive
, modes
[pio
])) {
84 format
= (hwif
->INL(basereg
+4) >> 31) & 1;
85 hwif
->OUTL(cs5530_pio_timings
[format
][pio
],
86 basereg
+(drive
->select
.b
.unit
<<3));
91 * cs5530_config_dma - select/set DMA and UDMA modes
92 * @drive: drive to tune
94 * cs5530_config_dma() handles selection/setting of DMA/UDMA modes
95 * for both the chipset and drive. The CS5530 has limitations about
96 * mixing DMA/UDMA on the same cable.
99 static int cs5530_config_dma (ide_drive_t
*drive
)
101 int udma_ok
= 1, mode
= 0;
102 ide_hwif_t
*hwif
= HWIF(drive
);
103 int unit
= drive
->select
.b
.unit
;
104 ide_drive_t
*mate
= &hwif
->drives
[unit
^1];
105 struct hd_driveid
*id
= drive
->id
;
106 unsigned int reg
, timings
;
107 unsigned long basereg
;
110 * Default to DMA-off in case we run into trouble here.
112 hwif
->ide_dma_off_quietly(drive
);
113 /* turn off DMA while we fiddle */
114 hwif
->ide_dma_host_off(drive
);
115 /* clear DMA_capable bit */
118 * The CS5530 specifies that two drives sharing a cable cannot
119 * mix UDMA/MDMA. It has to be one or the other, for the pair,
120 * though different timings can still be chosen for each drive.
121 * We could set the appropriate timing bits on the fly,
122 * but that might be a bit confusing. So, for now we statically
123 * handle this requirement by looking at our mate drive to see
124 * what it is capable of, before choosing a mode for our own drive.
126 * Note: This relies on the fact we never fail from UDMA to MWDMA_2
127 * but instead drop to PIO
130 struct hd_driveid
*mateid
= mate
->id
;
131 if (mateid
&& (mateid
->capability
& 1) &&
132 !__ide_dma_bad_drive(mate
)) {
133 if ((mateid
->field_valid
& 4) &&
134 (mateid
->dma_ultra
& 7))
136 else if ((mateid
->field_valid
& 2) &&
137 (mateid
->dma_mword
& 7))
145 * Now see what the current drive is capable of,
146 * selecting UDMA only if the mate said it was ok.
148 if (id
&& (id
->capability
& 1) && drive
->autodma
&&
149 !__ide_dma_bad_drive(drive
)) {
150 if (udma_ok
&& (id
->field_valid
& 4) && (id
->dma_ultra
& 7)) {
151 if (id
->dma_ultra
& 4)
153 else if (id
->dma_ultra
& 2)
155 else if (id
->dma_ultra
& 1)
158 if (!mode
&& (id
->field_valid
& 2) && (id
->dma_mword
& 7)) {
159 if (id
->dma_mword
& 4)
160 mode
= XFER_MW_DMA_2
;
161 else if (id
->dma_mword
& 2)
162 mode
= XFER_MW_DMA_1
;
163 else if (id
->dma_mword
& 1)
164 mode
= XFER_MW_DMA_0
;
169 * Tell the drive to switch to the new mode; abort on failure.
171 if (!mode
|| cs5530_set_xfer_mode(drive
, mode
))
172 return 1; /* failure */
175 * Now tune the chipset to match the drive:
178 case XFER_UDMA_0
: timings
= 0x00921250; break;
179 case XFER_UDMA_1
: timings
= 0x00911140; break;
180 case XFER_UDMA_2
: timings
= 0x00911030; break;
181 case XFER_MW_DMA_0
: timings
= 0x00077771; break;
182 case XFER_MW_DMA_1
: timings
= 0x00012121; break;
183 case XFER_MW_DMA_2
: timings
= 0x00002020; break;
185 printk(KERN_ERR
"%s: cs5530_config_dma: huh? mode=%02x\n",
187 return 1; /* failure */
189 basereg
= CS5530_BASEREG(hwif
);
190 reg
= hwif
->INL(basereg
+4); /* get drive0 config register */
191 timings
|= reg
& 0x80000000; /* preserve PIO format bit */
192 if (unit
== 0) { /* are we configuring drive0? */
193 hwif
->OUTL(timings
, basereg
+4); /* write drive0 config register */
195 if (timings
& 0x00100000)
196 reg
|= 0x00100000; /* enable UDMA timings for both drives */
198 reg
&= ~0x00100000; /* disable UDMA timings for both drives */
199 hwif
->OUTL(reg
, basereg
+4); /* write drive0 config register */
200 hwif
->OUTL(timings
, basereg
+12); /* write drive1 config register */
202 (void) hwif
->ide_dma_host_on(drive
);
203 /* set DMA_capable bit */
206 * Finally, turn DMA on in software, and exit.
208 return hwif
->ide_dma_on(drive
); /* success */
212 * init_chipset_5530 - set up 5530 bridge
216 * Initialize the cs5530 bridge for reliable IDE DMA operation.
219 static unsigned int __devinit
init_chipset_cs5530 (struct pci_dev
*dev
, const char *name
)
221 struct pci_dev
*master_0
= NULL
, *cs5530_0
= NULL
;
225 while ((dev
= pci_get_device(PCI_VENDOR_ID_CYRIX
, PCI_ANY_ID
, dev
)) != NULL
) {
226 switch (dev
->device
) {
227 case PCI_DEVICE_ID_CYRIX_PCI_MASTER
:
228 master_0
= pci_dev_get(dev
);
230 case PCI_DEVICE_ID_CYRIX_5530_LEGACY
:
231 cs5530_0
= pci_dev_get(dev
);
236 printk(KERN_ERR
"%s: unable to locate PCI MASTER function\n", name
);
240 printk(KERN_ERR
"%s: unable to locate CS5530 LEGACY function\n", name
);
244 spin_lock_irqsave(&ide_lock
, flags
);
245 /* all CPUs (there should only be one CPU with this chipset) */
248 * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
249 * --> OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
252 pci_set_master(cs5530_0
);
253 pci_set_mwi(cs5530_0
);
256 * Set PCI CacheLineSize to 16-bytes:
257 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
260 pci_write_config_byte(cs5530_0
, PCI_CACHE_LINE_SIZE
, 0x04);
263 * Disable trapping of UDMA register accesses (Win98 hack):
264 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
267 pci_write_config_word(cs5530_0
, 0xd0, 0x5006);
270 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
271 * The other settings are what is necessary to get the register
272 * into a sane state for IDE DMA operation.
275 pci_write_config_byte(master_0
, 0x40, 0x1e);
278 * Set max PCI burst size (16-bytes seems to work best):
279 * 16bytes: set bit-1 at 0x41 (reg value of 0x16)
280 * all others: clear bit-1 at 0x41, and do:
281 * 128bytes: OR 0x00 at 0x41
282 * 256bytes: OR 0x04 at 0x41
283 * 512bytes: OR 0x08 at 0x41
284 * 1024bytes: OR 0x0c at 0x41
287 pci_write_config_byte(master_0
, 0x41, 0x14);
290 * These settings are necessary to get the chip
291 * into a sane state for IDE DMA operation.
294 pci_write_config_byte(master_0
, 0x42, 0x00);
295 pci_write_config_byte(master_0
, 0x43, 0xc1);
297 spin_unlock_irqrestore(&ide_lock
, flags
);
300 pci_dev_put(master_0
);
301 pci_dev_put(cs5530_0
);
306 * init_hwif_cs5530 - initialise an IDE channel
307 * @hwif: IDE to initialize
309 * This gets invoked by the IDE driver once for each channel. It
310 * performs channel-specific pre-initialization before drive probing.
313 static void __devinit
init_hwif_cs5530 (ide_hwif_t
*hwif
)
315 unsigned long basereg
;
320 hwif
->serialized
= hwif
->mate
->serialized
= 1;
322 hwif
->tuneproc
= &cs5530_tuneproc
;
323 basereg
= CS5530_BASEREG(hwif
);
324 d0_timings
= hwif
->INL(basereg
+0);
325 if (CS5530_BAD_PIO(d0_timings
)) {
326 /* PIO timings not initialized? */
327 hwif
->OUTL(cs5530_pio_timings
[(d0_timings
>>31)&1][0], basereg
+0);
328 if (!hwif
->drives
[0].autotune
)
329 hwif
->drives
[0].autotune
= 1;
330 /* needs autotuning later */
332 if (CS5530_BAD_PIO(hwif
->INL(basereg
+8))) {
333 /* PIO timings not initialized? */
334 hwif
->OUTL(cs5530_pio_timings
[(d0_timings
>>31)&1][0], basereg
+8);
335 if (!hwif
->drives
[1].autotune
)
336 hwif
->drives
[1].autotune
= 1;
337 /* needs autotuning later */
341 hwif
->ultra_mask
= 0x07;
342 hwif
->mwdma_mask
= 0x07;
344 hwif
->ide_dma_check
= &cs5530_config_dma
;
347 hwif
->drives
[0].autodma
= hwif
->autodma
;
348 hwif
->drives
[1].autodma
= hwif
->autodma
;
351 static ide_pci_device_t cs5530_chipset __devinitdata
= {
353 .init_chipset
= init_chipset_cs5530
,
354 .init_hwif
= init_hwif_cs5530
,
357 .bootable
= ON_BOARD
,
360 static int __devinit
cs5530_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
362 return ide_setup_pci_device(dev
, &cs5530_chipset
);
365 static struct pci_device_id cs5530_pci_tbl
[] = {
366 { PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_5530_IDE
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
369 MODULE_DEVICE_TABLE(pci
, cs5530_pci_tbl
);
371 static struct pci_driver driver
= {
372 .name
= "CS5530 IDE",
373 .id_table
= cs5530_pci_tbl
,
374 .probe
= cs5530_init_one
,
377 static int __init
cs5530_ide_init(void)
379 return ide_pci_register_driver(&driver
);
382 module_init(cs5530_ide_init
);
384 MODULE_AUTHOR("Mark Lord");
385 MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
386 MODULE_LICENSE("GPL");